URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/VHDL
- from Rev 289 to Rev 290
- ↔ Reverse comparison
Rev 289 → Rev 290
/Open8_cfg.vhd
28,6 → 28,7
constant RTI_Ignores_GP_Flags : boolean := TRUE; |
constant Supervisor_Mode : boolean := TRUE; |
constant Unsigned_Index_Offsets : boolean := TRUE; |
constant Rotate_Ignores_Carry : boolean := TRUE; |
constant Default_Int_Mask : DATA_TYPE := x"00"; |
|
-- System Memory Map |
/o8_cpu.vhd
108,6 → 108,12
-- : Setting this generic to TRUE will switch to unsigned offsets, |
-- : switching the range to 0 to 255 instead. |
-- : |
-- : Rotate_Ignores_Carry alters the ROL and ROR instructions to |
-- : not rotate through, or alter, the carry bit. When enabled, |
-- : ROL performs Rn <= Rn<<1 and ROR performs Rn <= 1>>Rn. Note |
-- : that unlike the original instructions, the C bit is not |
-- : altered. |
-- : |
-- : Default_Interrupt_Mask sets the intial/reset value of the |
-- : interrupt mask. To remain true to the original core, which |
-- : had no interrupt mask, this should be set to x"FF". Otherwise |
266,6 → 272,9
-- flag used to alter the RSP instruction, making it |
-- a constant instead (PSR_GP4). This eliminated the |
-- need to expose an internal constant externally |
-- Seth Henry 05/01/21 Added the Rotate_Ignores_Carry generic, which |
-- alters the ROR and ROL instructions to behave more |
-- like expected by not rotating through the C flag |
|
library ieee; |
use ieee.std_logic_1164.all; |
289,6 → 298,7
RTI_Ignores_GP_Flags : boolean := false; -- RTI sets all flags |
Supervisor_Mode : boolean := false; -- I bit is restricted |
Unsigned_Index_Offsets : boolean := false; -- Offsets are signed |
Rotate_Ignores_Carry : boolean := false; -- Rotate thru Carry |
Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints |
Clock_Frequency : real -- Clock Frequency |
); |
1559,18 → 1569,30
Flags(PSR_N) <= Temp(7); |
Regfile(0) <= Temp(7 downto 0); |
|
when ALU_ROL => -- Rn = Rn<<1,C : Flags N,C,Z |
Temp := Regfile(Index) & Flags(PSR_C); |
when ALU_ROL => -- Varies based on config |
if( Rotate_Ignores_Carry )then |
-- Rn = Rn<<1 : Flags N,Z |
Temp(7 downto 0) := Regfile(Index)(6 downto 0) & Regfile(Index)(7); |
else |
-- Rn = Rn<<1,C : Flags N,C,Z |
Temp := Regfile(Index) & Flags(PSR_C); |
Flags(PSR_C) <= Temp(8); |
end if; |
Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0)); |
Flags(PSR_C) <= Temp(8); |
Flags(PSR_N) <= Temp(7); |
Regfile(Index) <= Temp(7 downto 0); |
|
when ALU_ROR => -- Rn = C,Rn>>1 : Flags N,C,Z |
Temp := Regfile(Index)(0) & Flags(PSR_C) & |
when ALU_ROR => -- Varies based on config |
if( Rotate_Ignores_Carry )then |
-- Rn = Rn>>1 : Flags N,Z |
Temp(7 downto 0) := Regfile(Index)(0) & Regfile(Index)(7 downto 1); |
else |
-- Rn = C,Rn>>1 : Flags N,C,Z |
Temp := Regfile(Index)(0) & Flags(PSR_C) & |
Regfile(Index)(7 downto 1); |
Flags(PSR_C) <= Temp(8); |
end if; |
Flags(PSR_Z) <= nor_reduce(Temp(7 downto 0)); |
Flags(PSR_C) <= Temp(8); |
Flags(PSR_N) <= Temp(7); |
Regfile(Index) <= Temp(7 downto 0); |
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