OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/VHDL
    from Rev 290 to Rev 292
    ↔ Reverse comparison
  •

Rev 290 → Rev 292

/o8_trig_delay.vhd
23,7 → 23,7
--
-- VHDL Entity: o8_trig_delay
-- Description: Programmable delay timer with time-base selection. Allows both
-- they delay after triggering and pulse width to be set by
-- the delay after triggering and pulse width to be set by
-- software. Output may either be routed to a pin or used to
-- trigger an interrupt.
--
35,27 → 35,31
-- 0x3 AAAAAAAA Pulse Width Byte 0 (RW)
-- 0x4 AAAAAAAA Pulse Width Byte 1 (RW)
-- 0x5 AAAAAAAA Pulse Width Byte 2 (RW)
-- 0x6 EDCBAA-- Timer Configuration (RW*)
-- A: Interrupt Select
-- 00 - Disabled
-- 01 - Interrupt on trigger event
-- 0x6 FEDCBBA- Timer Configuration (RW*)
-- A: Global Interrupt Enable
-- B: Interrupt Select
-- 00 - Interrupt on trigger input (pre-arm check)
-- 01 - Interrupt on trigger event (post-arm check)
-- 10 - Interrupt on delay done
-- 11 - Interrupt on pulse done
-- B: Trigger Edge
-- C: Trigger Edge
-- 0 - Trigger on falling edge
-- 1 - Trigger on rising edge
-- C: Automatic Re-Arm (enabled if 1)
-- D: Time base locked (okay if 1) (read-only)
-- E: Time base source
-- D: Automatic Re-Arm (enabled if 1)
-- E: Time base locked (okay if 1) (read-only)
-- F: Time base source
-- 0 - Use the internal uSec_Tick pulse
-- 1 - Use an external clock source
-- 0x7 DCBA---- Timer Control (RW*)
-- A: Current output level (read-only)
-- B: Clear/Re-Arm on '1' (one-shot)
-- 0x7 FEDCB--A Timer Control (RW*)
-- A: External Trigger Input State (read-only)
-- B: Issue Internal Trigger (one-shot)
-- Returns '0' on read
-- C: Current output level (read-only)
-- D: Clear/Re-Arm on '1' (one-shot)
-- Trigger event status on read
-- C: Disable/Safe Trigger (one-shot)
-- E: Disable/Safe Trigger (one-shot)
-- Returns '0' on read
-- D: Enable/Arm Trigger (one-shot)
-- F: Enable/Arm Trigger (one-shot)
-- Trigger armed status on read
--
-- Revision History
63,6 → 67,12
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/14/20 Design start
-- Seth Henry 05/18/20 Added write qualification input
-- Seth Henry 05/27/21 Added internal trigger function
-- Seth Henry 05/27/21 Moved the arming logic to later in the trigger to
-- allow premature trigger detection
-- Seth Henry 06/15/21 Added a global interrupt enable and modified the
-- interrupt to use either the pre- or post-arm
-- trigger input
 
library ieee;
use ieee.std_logic_1164.all;
81,6 → 91,7
Default_Auto_ReArm : std_logic := '0';
Default_Trigger_Edge : std_logic := '1';
Default_Int_Source : std_logic_vector(1 downto 0) := "00";
Default_Int_Enable : std_logic := '0';
Address : ADDRESS_TYPE
);
port(
134,7 → 145,11
signal Auto_ReArm : std_logic := '0';
signal Trigger_Edge : std_logic := '0';
signal Interrupt_Select : std_logic_vector(1 downto 0);
signal Interrupt_Enable : std_logic := '0';
 
signal Interrupt_Src : std_logic := '0';
 
signal Int_Trig : std_logic := '0';
signal Arm_Timer : std_logic := '0';
signal Safe_Timer : std_logic := '0';
signal Clear_Trigd : std_logic := '0';
149,9 → 164,11
signal Ext_Trig_SR : std_logic_vector(3 downto 0) := "0000";
signal Trig_RE : std_logic := '0';
signal Trig_FE : std_logic := '0';
signal Delay_Trig : std_logic := '0';
signal Trigger_In : std_logic := '0';
signal Trigger_Armed : std_logic := '0';
signal Trigger_Event : std_logic := '0';
signal Trigger_Event_q : std_logic := '0';
signal Delay_Trig : std_logic := '0';
 
-- Delay Timer signals
signal Delay_Pending : std_logic := '0';
187,6 → 204,8
Auto_ReArm <= Default_Auto_ReArm;
Trigger_Edge <= Default_Trigger_Edge;
Interrupt_Select <= Default_Int_Source;
Interrupt_Enable <= Default_Int_Enable;
Int_Trig <= '0';
Arm_Timer <= '0';
Safe_Timer <= '0';
Clear_Trigd <= '0';
197,6 → 216,7
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
Int_Trig <= '0';
Arm_Timer <= '0';
Safe_Timer <= '0';
Clear_Trigd <= '0';
223,11 → 243,13
Auto_ReArm <= Wr_Data_q(5);
Trigger_Edge <= Wr_Data_q(4);
Interrupt_Select <= Wr_Data_q(3 downto 2);
Interrupt_Enable <= Wr_Data_q(1);
 
when "111" =>
Arm_Timer <= Wr_Data_q(7);
Safe_Timer <= Wr_Data_q(6);
Clear_Trigd <= Wr_Data_q(5);
Int_Trig <= Wr_Data_q(3);
when others => null;
end case;
end if;
262,7 → 284,8
'0' & -- Bit 6
Trigger_Event & -- Bit 5
Pulse_Out & -- Bit 4
"0000"; -- Bits 3:0
"000" & -- Bits 3:1
Ext_Trig_SR(3); -- Bit 0
when others => null;
end case;
end if;
269,17 → 292,19
 
case( Interrupt_Select )is
when "00" =>
Interrupt <= '0';
Interrupt_Src <= Trigger_In;
when "01" =>
Interrupt <= Delay_Trig;
Interrupt_Src <= Delay_Trig;
when "10" =>
Interrupt <= Width_Trig;
Interrupt_Src <= Width_Trig;
when "11" =>
Interrupt <= Pulse_Done;
Interrupt_Src <= Pulse_Done;
when others =>
null;
end case;
 
Interrupt <= Interrupt_Src and Interrupt_Enable;
 
end if;
end process;
 
310,9 → 335,11
Ext_Trig_SR <= (others => '0');
Trig_RE <= '0';
Trig_FE <= '0';
Delay_Trig <= '0';
Trigger_In <= '0';
Trigger_Armed <= '0';
Trigger_Event <= '0';
Trigger_Event_q <= '0';
Delay_Trig <= '0';
elsif( rising_edge(Clock) )then
Ext_Trig_SR <= Ext_Trig_SR(2 downto 0) & Ext_Trig;
 
319,9 → 346,10
Trig_RE <= Ext_Trig_SR(2) and not Ext_Trig_SR(3);
Trig_FE <= Ext_Trig_SR(3) and not Ext_Trig_SR(2);
 
Delay_Trig <= ((Trig_FE and not Trigger_Edge) or
(Trig_RE and Trigger_Edge)) and
Trigger_Armed and (not Trigger_Event);
Trigger_In <= ((Trig_FE and not Trigger_Edge) or
(Trig_RE and Trigger_Edge) or
Int_Trig
);
 
if( Arm_Timer = '1' )then
Trigger_Armed <= '1';
329,12 → 357,15
Trigger_Armed <= '0';
end if;
 
if( Delay_Trig = '1' )then
Trigger_Event <= '1';
if( Trigger_In = '1' )then
Trigger_Event <= Trigger_Armed;
elsif( Clear_Trigd = '1' or Auto_ReArm = '1' )then
Trigger_Event <= '0';
end if;
 
-- Trigger on rising edge only
Trigger_Event_q <= Trigger_Event;
Delay_Trig <= Trigger_Event and (not Trigger_Event_q);
end if;
end process;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.