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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk/gnu/binutils/include/opcode
    from Rev 149 to Rev 161
    ↔ Reverse comparison
  •

Rev 149 → Rev 161

/bfin.h
41,18 → 41,24
#define M_IH 11
#define M_IU 12
 
static inline int is_macmod_pmove(int x)
static inline int is_macmod_pmove (int x)
{
return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_S2RND)
|| (x == M_ISS2) || (x == M_IU);
}
 
static inline int is_macmod_hmove(int x)
static inline int is_macmod_hmove (int x)
{
return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_IU) || (x == M_T)
|| (x == M_TFU) || (x == M_S2RND) || (x == M_ISS2) || (x == M_IH);
}
 
static inline int is_macmod_signed (int x)
{
return (x == 0) || (x == M_IS) || (x == M_T) || (x == M_S2RND)
|| (x == M_ISS2) || (x == M_IH) || (x == M_W32);
}
 
/* dsp32mac
+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
| 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
/avr.h
68,8 → 68,7
#define AVR_ISA_AVR6 (AVR_ISA_1200 | AVR_ISA_LPM | AVR_ISA_LPMX | \
AVR_ISA_SRAM | AVR_ISA_MEGA | AVR_ISA_MUL | \
AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \
AVR_ISA_SPM | AVR_ISA_BRK | AVR_ISA_EIND | \
AVR_ISA_MOVW)
AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW)
 
#define REGISTER_P(x) ((x) == 'r' \
|| (x) == 'd' \
/ChangeLog
1,3 → 1,217
2011-08-09 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
 
* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
(INSN_ASE_MASK): Add the MCU bit.
(INSN_MCU): New macro.
(M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
 
2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
 
* mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
(INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
(INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
(INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
(INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
(INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
(INSN2_READ_GPR_MMN): Likewise.
(INSN2_READ_FPR_D): Change the bit used.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
(INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
(INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
(INSN2_COND_BRANCH): Likewise.
(INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
(INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
(INSN2_MOD_GPR_MN): Likewise.
 
2011-08-05 David S. Miller <davem@davemloft.net>
 
* sparc.h: Document new format codes '4', '5', and '('.
(OPF_LOW4, RS3): New macros.
 
2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
 
* mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
order of flags documented.
 
2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
 
* mips.h: Clarify the description of microMIPS instruction
manipulation macros.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
 
2011-07-24 Chao-ying Fu <fu@mips.com>
Maciej W. Rozycki <macro@codesourcery.com>
 
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
(OP_MASK_CODE10, OP_SH_CODE10): Likewise.
(OP_MASK_TRAP, OP_SH_TRAP): Likewise.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
(OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
(OP_MASK_RS3, OP_SH_RS3): Likewise.
(OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
(OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
(OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
(OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
(OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
(OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
(OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
(OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
(OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
(OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
(OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
(OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
(OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
(OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
(INSN_WRITE_GPR_S): New macro.
(INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
(INSN2_READ_FPR_D): Likewise.
(INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
(INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
(INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
(INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
(INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
(INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
(INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
(INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
(CPU_MICROMIPS): New macro.
(M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
(M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
(M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
(M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
(M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
(M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
(M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
(M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
(M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
(M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
(M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
(M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
(M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
(MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
(MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
(MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
(MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
(MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
(MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
(MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
(MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
(MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
(MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
(MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
(MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
(MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
(MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
(MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
(MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
(MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
(MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
(MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
(MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
(MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
(MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
(MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
(MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
(MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
(MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
(MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
(MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
(MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
(MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
(MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
(MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
(MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
(MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
(MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
(MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
(MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
(MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
(MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
(MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
(MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
(MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
(MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
(MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
(MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
(MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
(MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
(MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
(MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
(MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
(MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
(MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
(MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
(MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
(MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
(MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
(MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
(MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
(MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
(MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
(MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
(MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
(MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
(MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
(MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
(MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
(MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
(MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
(MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
(MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
(MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
(MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
(MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
(MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
(MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
(MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
(MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
(micromips_opcodes): New declaration.
(bfd_micromips_num_opcodes): Likewise.
 
2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
 
* mips.h (INSN_TRAP): Rename to...
(INSN_NO_DELAY_SLOT): ... this.
(INSN_SYNC): Remove macro.
 
2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
 
* avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
a duplicate of AVR_ISA_SPM.
 
2011-07-01 Nick Clifton <nickc@redhat.com>
 
* avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
 
2011-06-18 Robin Getz <robin.getz@analog.com>
 
* bfin.h (is_macmod_signed): New func
 
2011-06-18 Mike Frysinger <vapier@gentoo.org>
 
* bfin.h (is_macmod_pmove): Add missing space before func args.
(is_macmod_hmove): Likewise.
 
2011-06-13 Walter Lee <walt@tilera.com>
 
* tilegx.h: New file.
/mips.h
91,6 → 91,10
#define OP_SH_CODE20 6
#define OP_MASK_SHAMT 0x1f
#define OP_SH_SHAMT 6
#define OP_MASK_EXTLSB OP_MASK_SHAMT
#define OP_SH_EXTLSB OP_SH_SHAMT
#define OP_MASK_STYPE OP_MASK_SHAMT
#define OP_SH_STYPE OP_SH_SHAMT
#define OP_MASK_FD 0x1f
#define OP_SH_FD 6
#define OP_MASK_TARGET 0x3ffffff
183,6 → 187,12
#define OP_SH_MTACC_D 13
#define OP_MASK_MTACC_D 0x3
 
/* MIPS MCU ASE */
#define OP_MASK_3BITPOS 0x7
#define OP_SH_3BITPOS 12
#define OP_MASK_OFFSET12 0xfff
#define OP_SH_OFFSET12 0
 
#define OP_OP_COP0 0x10
#define OP_OP_COP1 0x11
#define OP_OP_COP2 0x12
238,6 → 248,84
#define OP_SH_FZ 0
#define OP_MASK_FZ 0x1f
 
/* Every MICROMIPSOP_X definition requires a corresponding OP_X
definition, and vice versa. This simplifies various parts
of the operand handling in GAS. The fields below only exist
in the microMIPS encoding, so define each one to have an empty
range. */
#define OP_MASK_CODE10 0
#define OP_SH_CODE10 0
#define OP_MASK_TRAP 0
#define OP_SH_TRAP 0
#define OP_MASK_OFFSET10 0
#define OP_SH_OFFSET10 0
#define OP_MASK_RS3 0
#define OP_SH_RS3 0
#define OP_MASK_MB 0
#define OP_SH_MB 0
#define OP_MASK_MC 0
#define OP_SH_MC 0
#define OP_MASK_MD 0
#define OP_SH_MD 0
#define OP_MASK_ME 0
#define OP_SH_ME 0
#define OP_MASK_MF 0
#define OP_SH_MF 0
#define OP_MASK_MG 0
#define OP_SH_MG 0
#define OP_MASK_MH 0
#define OP_SH_MH 0
#define OP_MASK_MI 0
#define OP_SH_MI 0
#define OP_MASK_MJ 0
#define OP_SH_MJ 0
#define OP_MASK_ML 0
#define OP_SH_ML 0
#define OP_MASK_MM 0
#define OP_SH_MM 0
#define OP_MASK_MN 0
#define OP_SH_MN 0
#define OP_MASK_MP 0
#define OP_SH_MP 0
#define OP_MASK_MQ 0
#define OP_SH_MQ 0
#define OP_MASK_IMMA 0
#define OP_SH_IMMA 0
#define OP_MASK_IMMB 0
#define OP_SH_IMMB 0
#define OP_MASK_IMMC 0
#define OP_SH_IMMC 0
#define OP_MASK_IMMF 0
#define OP_SH_IMMF 0
#define OP_MASK_IMMG 0
#define OP_SH_IMMG 0
#define OP_MASK_IMMH 0
#define OP_SH_IMMH 0
#define OP_MASK_IMMI 0
#define OP_SH_IMMI 0
#define OP_MASK_IMMJ 0
#define OP_SH_IMMJ 0
#define OP_MASK_IMML 0
#define OP_SH_IMML 0
#define OP_MASK_IMMM 0
#define OP_SH_IMMM 0
#define OP_MASK_IMMN 0
#define OP_SH_IMMN 0
#define OP_MASK_IMMO 0
#define OP_SH_IMMO 0
#define OP_MASK_IMMP 0
#define OP_SH_IMMP 0
#define OP_MASK_IMMQ 0
#define OP_SH_IMMQ 0
#define OP_MASK_IMMU 0
#define OP_SH_IMMU 0
#define OP_MASK_IMMW 0
#define OP_SH_IMMW 0
#define OP_MASK_IMMX 0
#define OP_SH_IMMX 0
#define OP_MASK_IMMY 0
#define OP_SH_IMMY 0
 
/* This structure holds information for a particular instruction. */
 
struct mips_opcode
305,7 → 393,8
"z" must be zero register
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
"+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
LSB (OP_*_SHAMT).
LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
microMIPS compatibility).
Enforces: 0 <= pos < 32.
"+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
388,6 → 477,10
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 
MCU ASE usage:
"~" 12 bit offset (OP_*_OFFSET12)
"\" 3 bit position for aset and aclr (OP_*_3BITPOS)
 
UDI immediates:
"+1" UDI immediate bits 6-10
"+2" UDI immediate bits 6-15
423,7 → 516,7
 
Characters used so far, for quick reference when adding more:
"1234567890"
"%[]<>(),+:'@!$*&"
"%[]<>(),+:'@!$*&\~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefghijklopqrstuvwxz"
 
489,8 → 582,9
#define INSN_WRITE_HI 0x01000000
/* Modifies the LO register. */
#define INSN_WRITE_LO 0x02000000
/* Takes a trap (easier to keep out of delay slot). */
#define INSN_TRAP 0x04000000
/* Not to be placed in a branch delay slot, either architecturally
or for ease of handling (such as with instructions that take a trap). */
#define INSN_NO_DELAY_SLOT 0x04000000
/* Instruction stores value into memory. */
#define INSN_STORE_MEMORY 0x08000000
/* Instruction uses single precision floating point. */
499,8 → 593,8
#define FP_D 0x20000000
/* Instruction is part of the tx39's integer multiply family. */
#define INSN_MULT 0x40000000
/* Instruction synchronize shared memory. */
#define INSN_SYNC 0x80000000
/* Modifies the general purpose register in MICROMIPSOP_*_RS. */
#define INSN_WRITE_GPR_S 0x80000000
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
534,6 → 628,51
#define INSN2_READ_GPR_D 0x00000200
 
 
/* Instruction has a branch delay slot that requires a 16-bit instruction. */
#define INSN2_BRANCH_DELAY_16BIT 0x00000400
/* Instruction has a branch delay slot that requires a 32-bit instruction. */
#define INSN2_BRANCH_DELAY_32BIT 0x00000800
/* Reads the floating point register in MICROMIPSOP_*_FD. */
#define INSN2_READ_FPR_D 0x00001000
/* Modifies the general purpose register in MICROMIPSOP_*_MB. */
#define INSN2_WRITE_GPR_MB 0x00002000
/* Reads the general purpose register in MICROMIPSOP_*_MC. */
#define INSN2_READ_GPR_MC 0x00004000
/* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */
#define INSN2_MOD_GPR_MD 0x00008000
/* Reads the general purpose register in MICROMIPSOP_*_ME. */
#define INSN2_READ_GPR_ME 0x00010000
/* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */
#define INSN2_MOD_GPR_MF 0x00020000
/* Reads the general purpose register in MICROMIPSOP_*_MG. */
#define INSN2_READ_GPR_MG 0x00040000
/* Reads the general purpose register in MICROMIPSOP_*_MJ. */
#define INSN2_READ_GPR_MJ 0x00080000
/* Modifies the general purpose register in MICROMIPSOP_*_MJ. */
#define INSN2_WRITE_GPR_MJ 0x00100000
/* Reads the general purpose register in MICROMIPSOP_*_MP. */
#define INSN2_READ_GPR_MP 0x00200000
/* Modifies the general purpose register in MICROMIPSOP_*_MP. */
#define INSN2_WRITE_GPR_MP 0x00400000
/* Reads the general purpose register in MICROMIPSOP_*_MQ. */
#define INSN2_READ_GPR_MQ 0x00800000
/* Reads/Writes the stack pointer ($29). */
#define INSN2_MOD_SP 0x01000000
/* Reads the RA ($31) register. */
#define INSN2_READ_GPR_31 0x02000000
/* Reads the global pointer ($28). */
#define INSN2_READ_GP 0x04000000
/* Reads the program counter ($pc). */
#define INSN2_READ_PC 0x08000000
/* Is an unconditional branch insn. */
#define INSN2_UNCOND_BRANCH 0x10000000
/* Is a conditional branch insn. */
#define INSN2_COND_BRANCH 0x20000000
/* Modifies the general purpose registers in MICROMIPSOP_*_MH/I. */
#define INSN2_WRITE_GPR_MHI 0x40000000
/* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */
#define INSN2_READ_GPR_MMN 0x80000000
 
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
specifies the base ISA level(s). The remainder of a 32-bit
580,7 → 719,7
#define INSN_OCTEON 0x00000800
 
/* Masks used for MIPS-defined ASEs. */
#define INSN_ASE_MASK 0x3c00f000
#define INSN_ASE_MASK 0x3c00f010
 
/* DSP ASE */
#define INSN_DSP 0x00001000
629,6 → 768,9
/* RMI Xlr instruction */
#define INSN_XLR 0x00000020
 
/* MCU (MicroController) ASE */
#define INSN_MCU 0x00000010
 
/* MIPS ISA defines, use instead of hardcoding ISA level. */
 
#define ISA_UNKNOWN 0 /* Gas internal use. */
731,12 → 873,21
enum
{
M_ABS,
M_ACLR_AB,
M_ACLR_OB,
M_ADD_I,
M_ADDU_I,
M_AND_I,
M_ASET_AB,
M_ASET_OB,
M_BALIGN,
M_BC1FL,
M_BC1TL,
M_BC2FL,
M_BC2TL,
M_BEQ,
M_BEQ_I,
M_BEQL,
M_BEQL_I,
M_BGE,
M_BGEL,
746,6 → 897,9
M_BGEUL,
M_BGEU_I,
M_BGEUL_I,
M_BGEZ,
M_BGEZL,
M_BGEZALL,
M_BGT,
M_BGTL,
M_BGT_I,
754,6 → 908,8
M_BGTUL,
M_BGTU_I,
M_BGTUL_I,
M_BGTZ,
M_BGTZL,
M_BLE,
M_BLEL,
M_BLE_I,
762,6 → 918,8
M_BLEUL,
M_BLEU_I,
M_BLEUL_I,
M_BLEZ,
M_BLEZL,
M_BLT,
M_BLTL,
M_BLT_I,
770,10 → 928,15
M_BLTUL,
M_BLTU_I,
M_BLTUL_I,
M_BLTZ,
M_BLTZL,
M_BLTZALL,
M_BNE,
M_BNEL,
M_BNE_I,
M_BNEL_I,
M_CACHE_AB,
M_CACHE_OB,
M_DABS,
M_DADD_I,
M_DADDU_I,
807,6 → 970,9
M_JAL_1,
M_JAL_2,
M_JAL_A,
M_JALS_1,
M_JALS_2,
M_JALS_A,
M_L_DOB,
M_L_DAB,
M_LA_AB,
820,9 → 986,16
M_LD_AB,
M_LDC1_AB,
M_LDC2_AB,
M_LDC2_OB,
M_LDC3_AB,
M_LDL_AB,
M_LDL_OB,
M_LDM_AB,
M_LDM_OB,
M_LDP_AB,
M_LDP_OB,
M_LDR_AB,
M_LDR_OB,
M_LH_A,
M_LH_AB,
M_LHU_A,
833,7 → 1006,9
M_LI_S,
M_LI_SS,
M_LL_AB,
M_LL_OB,
M_LLD_AB,
M_LLD_OB,
M_LS_A,
M_LW_A,
M_LW_AB,
843,13 → 1018,21
M_LWC1_AB,
M_LWC2_A,
M_LWC2_AB,
M_LWC2_OB,
M_LWC3_A,
M_LWC3_AB,
M_LWL_A,
M_LWL_AB,
M_LWL_OB,
M_LWM_AB,
M_LWM_OB,
M_LWP_AB,
M_LWP_OB,
M_LWR_A,
M_LWR_AB,
M_LWR_OB,
M_LWU_AB,
M_LWU_OB,
M_MSGSND,
M_MSGLD,
M_MSGLD_T,
865,6 → 1048,7
M_NOR_I,
M_OR_I,
M_PREF_AB,
M_PREF_OB,
M_REM_3,
M_REM_3I,
M_REMU_3,
882,15 → 1066,24
M_S_DAB,
M_S_S,
M_SC_AB,
M_SC_OB,
M_SCD_AB,
M_SCD_OB,
M_SD_A,
M_SD_OB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
M_SDC2_OB,
M_SDC3_AB,
M_SDL_AB,
M_SDL_OB,
M_SDM_AB,
M_SDM_OB,
M_SDP_AB,
M_SDP_OB,
M_SDR_AB,
M_SDR_OB,
M_SEQ,
M_SEQ_I,
M_SGE,
921,12 → 1114,19
M_SWC1_AB,
M_SWC2_A,
M_SWC2_AB,
M_SWC2_OB,
M_SWC3_A,
M_SWC3_AB,
M_SWL_A,
M_SWL_AB,
M_SWL_OB,
M_SWM_AB,
M_SWM_OB,
M_SWP_AB,
M_SWP_OB,
M_SWR_A,
M_SWR_AB,
M_SWR_OB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
1132,6 → 1332,9
 
/* The following flags have the same value for the mips16 opcode
table:
 
INSN_ISA3
 
INSN_UNCOND_BRANCH_DELAY
INSN_COND_BRANCH_DELAY
INSN_COND_BRANCH_LIKELY (never used)
1140,12 → 1343,383
INSN_WRITE_HI
INSN_WRITE_LO
INSN_TRAP
INSN_ISA3
FP_D (never used)
*/
 
extern const struct mips_opcode mips16_opcodes[];
extern const int bfd_mips16_num_opcodes;
 
/* These are the bit masks and shift counts used for the different fields
in the microMIPS instruction formats. No masks are provided for the
fixed portions of an instruction, since they are not needed. */
 
#define MICROMIPSOP_MASK_IMMEDIATE 0xffff
#define MICROMIPSOP_SH_IMMEDIATE 0
#define MICROMIPSOP_MASK_DELTA 0xffff
#define MICROMIPSOP_SH_DELTA 0
#define MICROMIPSOP_MASK_CODE10 0x3ff
#define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
#define MICROMIPSOP_MASK_TRAP 0xf
#define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
#define MICROMIPSOP_MASK_SHAMT 0x1f
#define MICROMIPSOP_SH_SHAMT 11
#define MICROMIPSOP_MASK_TARGET 0x3ffffff
#define MICROMIPSOP_SH_TARGET 0
#define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
#define MICROMIPSOP_SH_EXTLSB 6
#define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
#define MICROMIPSOP_SH_EXTMSBD 11
#define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
#define MICROMIPSOP_SH_INSMSB 11
#define MICROMIPSOP_MASK_CODE 0x3ff
#define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
#define MICROMIPSOP_MASK_CODE2 0x3ff
#define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
#define MICROMIPSOP_MASK_CACHE 0x1f
#define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
#define MICROMIPSOP_MASK_SEL 0x7
#define MICROMIPSOP_SH_SEL 11
#define MICROMIPSOP_MASK_OFFSET12 0xfff
#define MICROMIPSOP_SH_OFFSET12 0
#define MICROMIPSOP_MASK_3BITPOS 0x7
#define MICROMIPSOP_SH_3BITPOS 21
#define MICROMIPSOP_MASK_STYPE 0x1f
#define MICROMIPSOP_SH_STYPE 16
#define MICROMIPSOP_MASK_OFFSET10 0x3ff
#define MICROMIPSOP_SH_OFFSET10 6
#define MICROMIPSOP_MASK_RS 0x1f
#define MICROMIPSOP_SH_RS 16
#define MICROMIPSOP_MASK_RT 0x1f
#define MICROMIPSOP_SH_RT 21
#define MICROMIPSOP_MASK_RD 0x1f
#define MICROMIPSOP_SH_RD 11
#define MICROMIPSOP_MASK_FS 0x1f
#define MICROMIPSOP_SH_FS 16
#define MICROMIPSOP_MASK_FT 0x1f
#define MICROMIPSOP_SH_FT 21
#define MICROMIPSOP_MASK_FD 0x1f
#define MICROMIPSOP_SH_FD 11
#define MICROMIPSOP_MASK_FR 0x1f
#define MICROMIPSOP_SH_FR 6
#define MICROMIPSOP_MASK_RS3 0x1f
#define MICROMIPSOP_SH_RS3 6
#define MICROMIPSOP_MASK_PREFX 0x1f
#define MICROMIPSOP_SH_PREFX 11
#define MICROMIPSOP_MASK_BCC 0x7
#define MICROMIPSOP_SH_BCC 18
#define MICROMIPSOP_MASK_CCC 0x7
#define MICROMIPSOP_SH_CCC 13
#define MICROMIPSOP_MASK_COPZ 0x7fffff
#define MICROMIPSOP_SH_COPZ 3
 
#define MICROMIPSOP_MASK_MB 0x7
#define MICROMIPSOP_SH_MB 23
#define MICROMIPSOP_MASK_MC 0x7
#define MICROMIPSOP_SH_MC 4
#define MICROMIPSOP_MASK_MD 0x7
#define MICROMIPSOP_SH_MD 7
#define MICROMIPSOP_MASK_ME 0x7
#define MICROMIPSOP_SH_ME 1
#define MICROMIPSOP_MASK_MF 0x7
#define MICROMIPSOP_SH_MF 3
#define MICROMIPSOP_MASK_MG 0x7
#define MICROMIPSOP_SH_MG 0
#define MICROMIPSOP_MASK_MH 0x7
#define MICROMIPSOP_SH_MH 7
#define MICROMIPSOP_MASK_MI 0x7
#define MICROMIPSOP_SH_MI 7
#define MICROMIPSOP_MASK_MJ 0x1f
#define MICROMIPSOP_SH_MJ 0
#define MICROMIPSOP_MASK_ML 0x7
#define MICROMIPSOP_SH_ML 4
#define MICROMIPSOP_MASK_MM 0x7
#define MICROMIPSOP_SH_MM 1
#define MICROMIPSOP_MASK_MN 0x7
#define MICROMIPSOP_SH_MN 4
#define MICROMIPSOP_MASK_MP 0x1f
#define MICROMIPSOP_SH_MP 5
#define MICROMIPSOP_MASK_MQ 0x7
#define MICROMIPSOP_SH_MQ 7
 
#define MICROMIPSOP_MASK_IMMA 0x7f
#define MICROMIPSOP_SH_IMMA 0
#define MICROMIPSOP_MASK_IMMB 0x7
#define MICROMIPSOP_SH_IMMB 1
#define MICROMIPSOP_MASK_IMMC 0xf
#define MICROMIPSOP_SH_IMMC 0
#define MICROMIPSOP_MASK_IMMD 0x3ff
#define MICROMIPSOP_SH_IMMD 0
#define MICROMIPSOP_MASK_IMME 0x7f
#define MICROMIPSOP_SH_IMME 0
#define MICROMIPSOP_MASK_IMMF 0xf
#define MICROMIPSOP_SH_IMMF 0
#define MICROMIPSOP_MASK_IMMG 0xf
#define MICROMIPSOP_SH_IMMG 0
#define MICROMIPSOP_MASK_IMMH 0xf
#define MICROMIPSOP_SH_IMMH 0
#define MICROMIPSOP_MASK_IMMI 0x7f
#define MICROMIPSOP_SH_IMMI 0
#define MICROMIPSOP_MASK_IMMJ 0xf
#define MICROMIPSOP_SH_IMMJ 0
#define MICROMIPSOP_MASK_IMML 0xf
#define MICROMIPSOP_SH_IMML 0
#define MICROMIPSOP_MASK_IMMM 0x7
#define MICROMIPSOP_SH_IMMM 1
#define MICROMIPSOP_MASK_IMMN 0x3
#define MICROMIPSOP_SH_IMMN 4
#define MICROMIPSOP_MASK_IMMO 0xf
#define MICROMIPSOP_SH_IMMO 0
#define MICROMIPSOP_MASK_IMMP 0x1f
#define MICROMIPSOP_SH_IMMP 0
#define MICROMIPSOP_MASK_IMMQ 0x7fffff
#define MICROMIPSOP_SH_IMMQ 0
#define MICROMIPSOP_MASK_IMMU 0x1f
#define MICROMIPSOP_SH_IMMU 0
#define MICROMIPSOP_MASK_IMMW 0x3f
#define MICROMIPSOP_SH_IMMW 1
#define MICROMIPSOP_MASK_IMMX 0xf
#define MICROMIPSOP_SH_IMMX 1
#define MICROMIPSOP_MASK_IMMY 0x1ff
#define MICROMIPSOP_SH_IMMY 1
 
/* Placeholders for fields that only exist in the traditional 32-bit
instruction encoding; see the comment above for details. */
#define MICROMIPSOP_MASK_CODE20 0
#define MICROMIPSOP_SH_CODE20 0
#define MICROMIPSOP_MASK_PERFREG 0
#define MICROMIPSOP_SH_PERFREG 0
#define MICROMIPSOP_MASK_CODE19 0
#define MICROMIPSOP_SH_CODE19 0
#define MICROMIPSOP_MASK_ALN 0
#define MICROMIPSOP_SH_ALN 0
#define MICROMIPSOP_MASK_VECBYTE 0
#define MICROMIPSOP_SH_VECBYTE 0
#define MICROMIPSOP_MASK_VECALIGN 0
#define MICROMIPSOP_SH_VECALIGN 0
#define MICROMIPSOP_MASK_DSPACC 0
#define MICROMIPSOP_SH_DSPACC 0
#define MICROMIPSOP_MASK_DSPACC_S 0
#define MICROMIPSOP_SH_DSPACC_S 0
#define MICROMIPSOP_MASK_DSPSFT 0
#define MICROMIPSOP_SH_DSPSFT 0
#define MICROMIPSOP_MASK_DSPSFT_7 0
#define MICROMIPSOP_SH_DSPSFT_7 0
#define MICROMIPSOP_MASK_SA3 0
#define MICROMIPSOP_SH_SA3 0
#define MICROMIPSOP_MASK_SA4 0
#define MICROMIPSOP_SH_SA4 0
#define MICROMIPSOP_MASK_IMM8 0
#define MICROMIPSOP_SH_IMM8 0
#define MICROMIPSOP_MASK_IMM10 0
#define MICROMIPSOP_SH_IMM10 0
#define MICROMIPSOP_MASK_WRDSP 0
#define MICROMIPSOP_SH_WRDSP 0
#define MICROMIPSOP_MASK_RDDSP 0
#define MICROMIPSOP_SH_RDDSP 0
#define MICROMIPSOP_MASK_BP 0
#define MICROMIPSOP_SH_BP 0
#define MICROMIPSOP_MASK_MT_U 0
#define MICROMIPSOP_SH_MT_U 0
#define MICROMIPSOP_MASK_MT_H 0
#define MICROMIPSOP_SH_MT_H 0
#define MICROMIPSOP_MASK_MTACC_T 0
#define MICROMIPSOP_SH_MTACC_T 0
#define MICROMIPSOP_MASK_MTACC_D 0
#define MICROMIPSOP_SH_MTACC_D 0
#define MICROMIPSOP_MASK_BBITIND 0
#define MICROMIPSOP_SH_BBITIND 0
#define MICROMIPSOP_MASK_CINSPOS 0
#define MICROMIPSOP_SH_CINSPOS 0
#define MICROMIPSOP_MASK_CINSLM1 0
#define MICROMIPSOP_SH_CINSLM1 0
#define MICROMIPSOP_MASK_SEQI 0
#define MICROMIPSOP_SH_SEQI 0
#define MICROMIPSOP_SH_OFFSET_A 0
#define MICROMIPSOP_MASK_OFFSET_A 0
#define MICROMIPSOP_SH_OFFSET_B 0
#define MICROMIPSOP_MASK_OFFSET_B 0
#define MICROMIPSOP_SH_OFFSET_C 0
#define MICROMIPSOP_MASK_OFFSET_C 0
#define MICROMIPSOP_SH_RZ 0
#define MICROMIPSOP_MASK_RZ 0
#define MICROMIPSOP_SH_FZ 0
#define MICROMIPSOP_MASK_FZ 0
 
/* These are the characters which may appears in the args field of a microMIPS
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
string are ignored when assembling, and written into the output
when disassembling.
 
The followings are for 16-bit microMIPS instructions.
 
"ma" must be $28
"mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
The same register used as both source and target.
"md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
"me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
The same register used as both source and target.
"mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
"mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
"mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
"mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
("mh" and "mi" form a valid 3-bit register pair)
"mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
"ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
"mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
"mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
"mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
"mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
"mr" must be program counter
"ms" must be $29
"mt" must be the same as the previous register
"mx" must be the same as the destination register
"my" must be $31
"mz" must be $0
 
"mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
"mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
"mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
32768, 65535) (MICROMIPSOP_*_IMMC)
"mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
"mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
"mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
"mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
"mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
"mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
"mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
"mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
"mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
"mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
"mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
"mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
"mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
"mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
"mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
"mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
"mZ" must be zero
 
In most cases 32-bit microMIPS instructions use the same characters
as MIPS (with ADDIUPC being a notable exception, but there are some
others too).
 
"." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
"1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
"<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32
(MICROMIPSOP_*_SHAMT)
"\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
"|" 4-bit trap code (MICROMIPSOP_*_TRAP)
"~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
"a" 26-bit target address (MICROMIPSOP_*_TARGET)
"b" 5-bit base register (MICROMIPSOP_*_RS)
"c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
"d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
"h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
"i" 16 bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
"j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
"k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
"n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
"o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
"p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
"q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
"r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
"s" 5-bit source register specifier (MICROMIPSOP_*_RS)
"t" 5-bit target register (MICROMIPSOP_*_RT)
"u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
"v" 5-bit same register used as both source and destination
(MICROMIPSOP_*_RS)
"w" 5-bit same register used as both target and destination
(MICROMIPSOP_*_RT)
"y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
"z" must be zero register
"C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
"B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
"K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
 
"+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
LSB (MICROMIPSOP_*_EXTLSB).
Enforces: 0 <= pos < 32.
"+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
"+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 0 < (pos+size) <= 32.
(Also used by DEXT w/ different limits, but limits for
that are checked by the M_DEXT macro.)
"+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
Enforces: 32 <= pos < 64.
"+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
"+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
"+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
 
PC-relative addition (ADDIUPC) instruction:
"mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
"mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
 
Floating point instructions:
"D" 5-bit destination register (MICROMIPSOP_*_FD)
"M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
"N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
"R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
"S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
"T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
"V" 5-bit same register used as floating source and destination or target
(MICROMIPSOP_*_FS)
 
Coprocessor instructions:
"E" 5-bit target register (MICROMIPSOP_*_RT)
"G" 5-bit destination register (MICROMIPSOP_*_RD)
"H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
"+D" combined destination register ("G") and sel ("H") for CP0 ops,
for pretty-printing in disassembly only
 
Macro instructions:
"A" general 32 bit expression
"I" 32-bit immediate (value placed in imm_expr).
"+I" 32-bit immediate (value placed in imm2_expr).
"F" 64-bit floating point constant in .rdata
"L" 64-bit floating point constant in .lit8
"f" 32-bit floating point constant
"l" 32-bit floating point constant in .lit4
 
Other:
"()" parens surrounding optional value
"," separates operands
"+" start of extension sequence
"m" start of microMIPS extension sequence
 
Characters used so far, for quick reference when adding more:
"1234567890"
"<>(),+.\|~"
"ABCDEFGHI KLMN RST V "
"abcd f hijklmnopqrstuvw yz"
 
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
""
""
"ABCDEFGHI"
""
 
Extension character sequences used so far ("m" followed by the
following), for quick reference when adding more:
""
""
" BCDEFGHIJ LMNOPQ U WXYZ"
" bcdefghij lmn pq st xyz"
*/
 
extern const struct mips_opcode micromips_opcodes[];
extern const int bfd_micromips_num_opcodes;
 
/* A NOP insn impemented as "or at,at,zero".
Used to implement -mfix-loongson2f. */
#define LOONGSON2F_NOP_INSN 0x00200825
/sparc.h
131,6 → 131,8
f frs2 floating point register.
B frs2 floating point register (double/even).
R frs2 floating point register (quad/multiple of 4).
4 frs3 floating point register.
5 frs3 floating point register (doube/even).
g frsd floating point register.
H frsd floating point register (double/even).
J frsd floating point register (quad/multiple of 4).
187,15 → 189,14
0 32/64 bit immediate for set or setx (v9) insns
_ Ancillary state register in rd (v9a)
/ Ancillary state register in rs1 (v9a)
( entire floating point state register (%efsr). */
 
The following chars are unused: (note: ,[] are used as punctuation)
[45]. */
 
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
207,6 → 208,7
#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */
#define ASI_RS2(x) (SIMM13 (x))
#define MEMBAR(x) ((x) & 0x7f)
#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */

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