URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc/trunk/gnu/binutils/include/opcode
- from Rev 163 to Rev 166
- ↔ Reverse comparison
Rev 163 → Rev 166
/i386.h
76,6 → 76,8
#define SS_PREFIX_OPCODE 0x36 |
#define REPNE_PREFIX_OPCODE 0xf2 |
#define REPE_PREFIX_OPCODE 0xf3 |
#define XACQUIRE_PREFIX_OPCODE 0xf2 |
#define XRELEASE_PREFIX_OPCODE 0xf3 |
|
#define TWO_BYTE_OPCODE_ESCAPE 0x0f |
#define NOP_OPCODE (char) 0x90 |
/tilegx.h
34,6 → 34,8
TILEGX_OPC_BPT, |
TILEGX_OPC_INFO, |
TILEGX_OPC_INFOL, |
TILEGX_OPC_LD4S_TLS, |
TILEGX_OPC_LD_TLS, |
TILEGX_OPC_MOVE, |
TILEGX_OPC_MOVEI, |
TILEGX_OPC_MOVELI, |
/tilepro.h
36,6 → 36,8
TILEPRO_OPC_INFOL, |
TILEPRO_OPC_J, |
TILEPRO_OPC_JAL, |
TILEPRO_OPC_LW_TLS, |
TILEPRO_OPC_LW_TLS_SN, |
TILEPRO_OPC_MOVE, |
TILEPRO_OPC_MOVE_SN, |
TILEPRO_OPC_MOVEI, |
/crx.h
1,5 → 1,5
/* crx.h -- Header file for CRX opcode and register tables. |
Copyright 2004, 2010 Free Software Foundation, Inc. |
Copyright 2004, 2010, 2012 Free Software Foundation, Inc. |
Contributed by Tomer Levi, NSC, Israel. |
Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. |
Updates, BFDizing, GNUifying and ELF support by Tomer Levi. |
384,7 → 384,7
#define NUMTRAPS crx_num_traps |
|
/* cst4 operand mapping. */ |
extern const long cst4_map[]; |
extern const int cst4_map[]; |
extern const int cst4_maps; |
|
/* Table of instructions with no operands. */ |
/ChangeLog
1,3 → 1,35
2012-02-27 Alan Modra <amodra@gmail.com> |
|
* crx.h (cst4_map): Update declaration. |
|
2012-02-25 Walter Lee <walt@tilera.com> |
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* tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS, |
TILEGX_OPC_LD_TLS. |
* tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS, |
TILEPRO_OPC_LW_TLS_SN. |
|
2012-02-08 H.J. Lu <hongjiu.lu@intel.com> |
|
* i386.h (XACQUIRE_PREFIX_OPCODE): New. |
(XRELEASE_PREFIX_OPCODE): Likewise. |
|
2011-12-08 Andrew Pinski <apinski@cavium.com> |
Adam Nemet <anemet@caviumnetworks.com> |
|
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. |
(INSN_OCTEON2): New macro. |
(CPU_OCTEON2): New macro. |
(OPCODE_IS_MEMBER): Add Octeon2. |
|
2011-11-29 Andrew Pinski <apinski@cavium.com> |
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* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. |
(INSN_OCTEONP): New macro. |
(CPU_OCTEONP): New macro. |
(OPCODE_IS_MEMBER): Add Octeon+. |
(M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. |
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2011-11-01 DJ Delorie <dj@redhat.com> |
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* rl78.h: New file. |
/mips.h
713,10 → 713,12
{ 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; |
|
/* Masks used for Chip specific instructions. */ |
#define INSN_CHIP_MASK 0xc3ff0c20 |
#define INSN_CHIP_MASK 0xc3ff0f20 |
|
/* Cavium Networks Octeon instructions. */ |
#define INSN_OCTEON 0x00000800 |
#define INSN_OCTEONP 0x00000200 |
#define INSN_OCTEON2 0x00000100 |
|
/* Masks used for MIPS-defined ASEs. */ |
#define INSN_ASE_MASK 0x3c00f010 |
823,6 → 825,8
#define CPU_LOONGSON_2F 3002 |
#define CPU_LOONGSON_3A 3003 |
#define CPU_OCTEON 6501 |
#define CPU_OCTEONP 6601 |
#define CPU_OCTEON2 6502 |
#define CPU_XLR 887682 /* decimal 'XLR' */ |
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/* Test for membership in an ISA including chip specific ISAs. INSN |
859,6 → 863,10
&& ((insn)->membership & INSN_LOONGSON_3A) != 0) \ |
|| (cpu == CPU_OCTEON \ |
&& ((insn)->membership & INSN_OCTEON) != 0) \ |
|| (cpu == CPU_OCTEONP \ |
&& ((insn)->membership & INSN_OCTEONP) != 0) \ |
|| (cpu == CPU_OCTEON2 \ |
&& ((insn)->membership & INSN_OCTEON2) != 0) \ |
|| (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ |
|| 0) /* Please keep this term for easier source merging. */ |
|
1065,6 → 1073,10
M_S_DOB, |
M_S_DAB, |
M_S_S, |
M_SAA_AB, |
M_SAA_OB, |
M_SAAD_AB, |
M_SAAD_OB, |
M_SC_AB, |
M_SC_OB, |
M_SCD_AB, |