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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
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/open8_urisc/trunk/gnu/binutils
- from Rev 87 to Rev 88
- ↔ Reverse comparison
Rev 87 → Rev 88
/gas/testsuite/gas/mcore/allinsn.s
0,0 → 1,146
.data |
foodata: .word 42 |
.text |
footext: |
|
.macro test insn text="" |
.export \insn |
\insn: |
\insn \text |
.endm |
|
test abs r0 |
test addc "r1,r2" // A double forward slash starts a line comment |
test addi "r3, 1" # So does a hash |
test addu "r4, r5" // White space between operands should be ignored |
test and "r6,r7" ; test andi "r8,2" // A semicolon seperates statements |
test andn "r9, r10" |
test asr "r11, R12" // Uppercase R is allowed as a register prefix |
test asrc "r13" |
test asri "r14,0x1f" |
test bclri "r15,0" |
test bf footext |
test bgeni "sp, 7" // r0 can also be refered to as 'sp' |
test BGENI "r0, 8" // Officially upper case or mixed case |
test BGENi "r0, 31" // mnemonics should not be allowed, but we relax this... |
test bgenr "r1, r2" |
test bkpt |
test bmaski "r3,8" |
test BMASKI "r3,0x1f" |
test br . // Dot means the current address |
test brev r4 |
test bseti "r5,30" |
test bsr footext |
test bt footext |
test btsti "r6, 27" |
test clrc |
test clrf r7 |
test clrt r8 |
test cmphs "r9,r10" |
test cmplt "r11,r12" |
test cmplei "r11, 14" |
test cmplti "r13,32" |
test cmpne "r14, r15" |
test cmpnei "r0,0" |
test decf r1 |
test decgt r2 |
test declt r3 |
test decne r4 |
test dect r5 |
test divs "r6,r1" |
test divu "r8, r1" |
test doze |
test ff1 r10 |
test incf r11 |
test inct r12 |
test ixh "r13,r14" |
test ixw "r15,r0" |
test jbf footext |
test jbr fooloop |
test jbsr footext |
test jbt fooloop |
test jmp r1 |
test jmpi footext |
test jsr r2 |
test jsri footext |
test ld.b "r3,(r4,0)" |
test ld.h "r5 , ( r6, 2)" |
test ld.w "r7, (r8, 0x4)" |
test ldb "r9,(r10,0xf)" |
test ldh "r11, (r12, 30)" |
test ld "r13, (r14, 20)" |
test ldw "r13, (r14, 60)" |
test ldm "r2-r15,(r0)" |
.export fooloop |
fooloop: |
test ldq "r4-r7,(r1)" |
test loopt "r8, fooloop" |
test LRW "r9, [foolit]" |
test lrw "r9, 0x4321" // PC rel indirect |
.global foolit |
foolit: |
.word 0x1234 |
test lsl "r10,r11" |
test lslc r12 |
.literals // Dump literals table |
test lsli "r13,31" |
test lsr "r14,r15" |
test lsrc r0 |
test lsri "r1,1" |
test mclri "r4, 64" |
test mfcr "r2, cr0" |
test mov "r3,r4" |
test movf "r5, r6" |
test movi "r7, 127" |
test movt "r8, r9" |
test mtcr "r10, psr" |
test mult "r11, r12" |
test mvc r13 |
test mvcv r14 |
test neg r2 |
test not r15 |
test or "r0,r1" |
test rfi |
test rolc "r6, 1" |
test rori "r9, 6" |
test rotlc "r6, 1" |
test rotli "r2, 10" |
test rotri "r9, 6" |
test rsub "r3, r4" |
test rsubi "r5, 0x0" |
test rte |
test rts |
test setc |
test sextb r6 |
test sexth r7 |
test st.b "r8, (r9, 0)" |
test st.h "r10, (r11, 2)" |
test st.w "r12, (r13, 4)" |
test stb "r14, (r15, 15)" |
test sth "r0, (r1, 30)" |
test stw "r2, (r3, 0x3c)" |
test st "r4, (r5, 0)" |
test stm "r14 - r15 , (r0)" |
test stop |
test stq "r4 - r7 , (r1)" |
test subc "r7, r13" |
test subi "r14, 32" |
test subu "r9, r3" |
test sync |
test tstlt r5 |
test tstne r7 |
test trap 2 |
test tst "r14, r14" |
test tstnbz r2 |
test wait |
test xor "r15,r0" |
test xsr r11 |
test xtrb0 "r1, r1" |
test xtrb1 "r1, r2" |
test xtrb2 "r1, r0" |
test xtrb3 "r1, r13" |
test zextb r8 |
test zexth r4 |
clrc // These two instructions pad the object file |
clrc // out to a 16 byte boundary. |
|
/gas/testsuite/gas/mcore/allinsn.d
0,0 → 1,398
#as: |
#objdump: -drz |
#name: allinsn |
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.*: +file format .* |
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Disassembly of section \.text: |
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0+000 <abs>: |
0: 01e0 abs r0 |
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0+002 <addc>: |
2: 0621 addc r1, r2 |
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0+004 <addi>: |
4: 2003 addi r3, 1 |
|
0+006 <addu>: |
6: 1c54 addu r4, r5 |
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0+008 <and>: |
8: 1676 and r6, r7 |
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0+00a <andi>: |
a: 2e28 andi r8, 2 |
|
0+00c <andn>: |
c: 1fa9 andn r9, r10 |
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0+00e <asr>: |
e: 1acb asr r11, r12 |
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0+010 <asrc>: |
10: 3a0d asrc r13 |
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0+012 <asri>: |
12: 3bfe asri r14, 31 |
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0+014 <bclri>: |
14: 300f bclri r15, 0 |
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0+016 <bf>: |
16: eff4 bf 0x.*0 |
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0+018 <bgeni>: |
18: 3270 bgeni r0, 7 |
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0+01a <BGENI>: |
1a: 3280 bgeni r0, 8 |
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0+01c <BGENi>: |
1c: 33f0 bgeni r0, 31 |
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0+01e <bgenr>: |
1e: 1321 bgenr r1, r2 |
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0+020 <bkpt>: |
20: 0000 bkpt |
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0+022 <bmaski>: |
22: 2c83 bmaski r3, 8 |
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0+024 <BMASKI>: |
24: 2df3 bmaski r3, 31 |
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0+026 <br>: |
26: f7ff br 0x.*26 |
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0+028 <brev>: |
28: 00f4 brev r4 |
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0+02a <bseti>: |
2a: 35e5 bseti r5, 30 |
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0+02c <bsr>: |
2c: ffe9 bsr 0x.*0.* |
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0+02e <bt>: |
2e: e7e8 bt 0x.*0 |
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0+030 <btsti>: |
30: 37b6 btsti r6, 27 |
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0+032 <clrc>: |
32: 0f00 cmpne r0, r0 |
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0+034 <clrf>: |
34: 01d7 clrf r7 |
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0+036 <clrt>: |
36: 01c8 clrt r8 |
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0+038 <cmphs>: |
38: 0ca9 cmphs r9, r10 |
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0+03a <cmplt>: |
3a: 0dcb cmplt r11, r12 |
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0+03c <cmplei>: |
3c: 22eb cmplti r11, 15 |
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0+03e <cmplti>: |
3e: 23fd cmplti r13, 32 |
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0+040 <cmpne>: |
40: 0ffe cmpne r14, r15 |
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0+042 <cmpnei>: |
42: 2a00 cmpnei r0, 0 |
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0+044 <decf>: |
44: 0091 decf r1 |
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0+046 <decgt>: |
46: 01a2 decgt r2 |
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0+048 <declt>: |
48: 0183 declt r3 |
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0+04a <decne>: |
4a: 01b4 decne r4 |
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0+04c <dect>: |
4c: 0085 dect r5 |
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0+04e <divs>: |
4e: 3216 divs r6, r1 |
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0+050 <divu>: |
50: 2c18 divu r8, r1 |
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0+052 <doze>: |
52: 0006 doze |
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0+054 <ff1>: |
54: 00ea ff1 r10 |
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0+056 <incf>: |
56: 00bb incf r11 |
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0+058 <inct>: |
58: 00ac inct r12 |
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0+05a <ixh>: |
5a: 1ded ixh r13, r14 |
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0+05c <ixw>: |
5c: 150f ixw r15, r0 |
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0+05e <jbf>: |
5e: efd0 bf 0x.*0 |
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0+060 <jbr>: |
60: f00e br 0x7e |
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0+062 <jbsr>: |
62: 7f0a jsri 0x0 // from address pool at 0x8c |
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0+064 <jbt>: |
64: e00c bt 0x7e |
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0+066 <jmp>: |
66: 00c1 jmp r1 |
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0+068 <jmpi>: |
68: 7009 jmpi 0x0 // from address pool at 0x8c |
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0+06a <jsr>: |
6a: 00d2 jsr r2 |
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0+06c <jsri>: |
6c: 7f08 jsri 0x0 // from address pool at 0x8c |
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0+06e <ld\.b>: |
6e: a304 ldb r3, \(r4, 0\) |
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0+070 <ld\.h>: |
70: c516 ldh r5, \(r6, 2\) |
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0+072 <ld\.w>: |
72: 8718 ld r7, \(r8, 4\) |
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0+074 <ldb>: |
74: a9fa ldb r9, \(r10, 15\) |
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0+076 <ldh>: |
76: cbfc ldh r11, \(r12, 30\) |
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0+078 <ld>: |
78: 8d5e ld r13, \(r14, 20\) |
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0+07a <ldw>: |
7a: 8dfe ld r13, \(r14, 60\) |
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0+07c <ldm>: |
7c: 0062 ldm r2-r15, \(r0\) |
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0+07e <fooloop>: |
7e: 0041 ldq r4-r7, \(r1\) |
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0+080 <loopt>: |
80: 048e loopt r8, 0x64 |
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0+082 <LRW>: |
82: 7901 lrw r9, 0x3C0C1BBA |
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0+084 <lrw>: |
84: 7903 lrw r9, 0x4321 |
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0+086 <foolit>: |
86: 1234 mov r4, r3 |
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0+088 <lsl>: |
88: 1bba lsl r10, r11 |
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0+08a <lslc>: |
8a: 3c0c lslc r12 |
8c: 0000 bkpt |
8c: ADDR32 \.text |
8e: 0000 bkpt |
90: 4321 \.short 0x4321 |
92: 0000 bkpt |
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0+094 <lsli>: |
94: 3dfd lsli r13, 31 |
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0+096 <lsr>: |
96: 0bfe lsr r14, r15 |
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0+098 <lsrc>: |
98: 3e00 lsrc r0 |
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0+09a <lsri>: |
9a: 3e11 lsri r1, 1 |
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0+09c <mclri>: |
9c: 3064 bclri r4, 6 |
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0+09e <mfcr>: |
9e: 1002 mfcr r2, psr |
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0+0a0 <mov>: |
a0: 1243 mov r3, r4 |
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0+0a2 <movf>: |
a2: 0a65 movf r5, r6 |
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0+0a4 <movi>: |
a4: 67f7 movi r7, 127 |
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0+0a6 <movt>: |
a6: 0298 movt r8, r9 |
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0+0a8 <mtcr>: |
a8: 180a mtcr r10, psr |
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0+0aa <mult>: |
aa: 03cb mult r11, r12 |
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0+0ac <mvc>: |
ac: 002d mvc r13 |
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0+0ae <mvcv>: |
ae: 003e mvcv r14 |
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0+0b0 <neg>: |
b0: 2802 rsubi r2, 0 |
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0+0b2 <not>: |
b2: 01ff not r15 |
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0+0b4 <or>: |
b4: 1e10 or r0, r1 |
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0+0b6 <rfi>: |
b6: 0003 rfi |
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0+0b8 <rolc>: |
b8: 0666 addc r6, r6 |
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0+0ba <rori>: |
ba: 39a9 rotli r9, 26 |
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0+0bc <rotlc>: |
bc: 0666 addc r6, r6 |
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0+0be <rotli>: |
be: 38a2 rotli r2, 10 |
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0+0c0 <rotri>: |
c0: 39a9 rotli r9, 26 |
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0+0c2 <rsub>: |
c2: 1443 rsub r3, r4 |
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0+0c4 <rsubi>: |
c4: 2805 rsubi r5, 0 |
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0+0c6 <rte>: |
c6: 0002 rte |
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0+0c8 <rts>: |
c8: 00cf jmp r15 |
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0+0ca <setc>: |
ca: 0c00 cmphs r0, r0 |
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0+0cc <sextb>: |
cc: 0156 sextb r6 |
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0+0ce <sexth>: |
ce: 0177 sexth r7 |
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0+0d0 <st\.b>: |
d0: b809 stb r8, \(r9, 0\) |
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0+0d2 <st\.h>: |
d2: da1b sth r10, \(r11, 2\) |
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0+0d4 <st\.w>: |
d4: 9c1d st r12, \(r13, 4\) |
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0+0d6 <stb>: |
d6: beff stb r14, \(r15, 15\) |
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0+0d8 <sth>: |
d8: d0f1 sth r0, \(r1, 30\) |
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0+0da <stw>: |
da: 92f3 st r2, \(r3, 60\) |
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0+0dc <st>: |
dc: 9405 st r4, \(r5, 0\) |
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0+0de <stm>: |
de: 007e stm r14-r15, \(r0\) |
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0+0e0 <stop>: |
e0: 0004 stop |
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0+0e2 <stq>: |
e2: 0051 stq r4-r7, \(r1\) |
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0+0e4 <subc>: |
e4: 07d7 subc r7, r13 |
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0+0e6 <subi>: |
e6: 25fe subi r14, 32 |
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0+0e8 <subu>: |
e8: 0539 subu r9, r3 |
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0+0ea <sync>: |
ea: 0001 sync |
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0+0ec <tstlt>: |
ec: 37f5 btsti r5, 31 |
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0+0ee <tstne>: |
ee: 2a07 cmpnei r7, 0 |
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0+0f0 <trap>: |
f0: 000a trap 2 |
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0+0f2 <tst>: |
f2: 0eee tst r14, r14 |
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0+0f4 <tstnbz>: |
f4: 0192 tstnbz r2 |
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0+0f6 <wait>: |
f6: 0005 wait |
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0+0f8 <xor>: |
f8: 170f xor r15, r0 |
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0+0fa <xsr>: |
fa: 380b xsr r11 |
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0+0fc <xtrb0>: |
fc: 0131 xtrb0 r1, r1 |
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0+0fe <xtrb1>: |
fe: 0122 xtrb1 r1, r2 |
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0+0100 <xtrb2>: |
100: 0110 xtrb2 r1, r0 |
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0+0102 <xtrb3>: |
102: 010d xtrb3 r1, r13 |
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0+0104 <zextb>: |
104: 0148 zextb r8 |
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0+0106 <zexth>: |
106: 0164 zexth r4 |
108: 0f00 cmpne r0, r0 |
10a: 0f00 cmpne r0, r0 |
/gas/testsuite/gas/mcore/allinsn.exp
0,0 → 1,5
# M*Core assembler testsuite. |
|
if [istarget mcore-*-*] { |
run_dump_test "allinsn" |
} |