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Rev 178 → Rev 179

/binutils/gas/doc/Makefile.am
0,0 → 1,119
## Process this file with automake to generate Makefile.in
 
AUTOMAKE_OPTIONS = 1.8 cygnus
 
# What version of the manual you want; "all" includes everything
CONFIG=all
 
# Options to extract the man page from as.texinfo
MANCONF = -Dman
 
TEXI2POD = perl $(BASEDIR)/etc/texi2pod.pl $(AM_MAKEINFOFLAGS)
 
POD2MAN = pod2man --center="GNU Development Tools" \
--release="binutils-$(VERSION)" --section=1
 
man_MANS = as.1
 
info_TEXINFOS = as.texinfo
as_TEXINFOS = asconfig.texi $(CPU_DOCS)
 
AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
-I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc
TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty" \
-I "$(top_srcdir)/../bfd/doc" -I ../../bfd/doc
 
asconfig.texi: $(CONFIG).texi
rm -f asconfig.texi
cp $(srcdir)/$(CONFIG).texi ./asconfig.texi
chmod u+w ./asconfig.texi
 
CPU_DOCS = \
c-alpha.texi \
c-arc.texi \
c-arm.texi \
c-avr.texi \
c-bfin.texi \
c-cr16.texi \
c-cris.texi \
c-d10v.texi \
c-epiphany.texi \
c-h8300.texi \
c-hppa.texi \
c-i370.texi \
c-i386.texi \
c-i860.texi \
c-i960.texi \
c-ip2k.texi \
c-lm32.texi \
c-m32c.texi \
c-m32r.texi \
c-m68hc11.texi \
c-m68k.texi \
c-microblaze.texi \
c-mips.texi \
c-mmix.texi \
c-mt.texi \
c-msp430.texi \
c-ns32k.texi \
c-pdp11.texi \
c-pj.texi \
c-ppc.texi \
c-rl78.texi \
c-rx.texi \
c-s390.texi \
c-score.texi \
c-sh.texi \
c-sh64.texi \
c-sparc.texi \
c-tic54x.texi \
c-tic6x.texi \
c-tilegx.texi \
c-tilepro.texi \
c-vax.texi \
c-v850.texi \
c-xstormy16.texi \
c-xtensa.texi \
c-z80.texi \
c-z8k.texi
 
# We want install to imply install-info as per GNU standards, despite the
# cygnus option.
install-data-local: install-info
 
# This one isn't ready for prime time yet. Not even a little bit.
 
noinst_TEXINFOS = internals.texi
 
MAINTAINERCLEANFILES = asconfig.texi
 
BASEDIR = $(srcdir)/../..
BFDDIR = $(BASEDIR)/bfd
 
CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in
 
# Maintenance
 
# We need it for the taz target in ../../Makefile.in.
info-local: $(MANS)
 
# Build the man page from the texinfo file
# The sed command removes the no-adjust Nroff command so that
# the man output looks standard.
as.1: $(srcdir)/as.texinfo asconfig.texi $(CPU_DOCS)
touch $@
-$(TEXI2POD) $(MANCONF) < $(srcdir)/as.texinfo > as.pod
-($(POD2MAN) as.pod | \
sed -e '/^.if n .na/d' > $@.T$$$$ && \
mv -f $@.T$$$$ $@) || \
(rm -f $@.T$$$$ && exit 1)
rm -f as.pod
 
MAINTAINERCLEANFILES += as.info
 
# Automake 1.9 will only build info files in the objdir if they are
# mentioned in DISTCLEANFILES. It doesn't have to be unconditional,
# though, so we use a bogus condition.
if GENINSRC_NEVER
DISTCLEANFILES = as.info
endif
/binutils/gas/doc/c-alpha.texi
0,0 → 1,487
@c Copyright 2002, 2003, 2005, 2009, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c man end
 
@ifset GENERIC
@page
@node Alpha-Dependent
@chapter Alpha Dependent Features
@end ifset
 
@ifclear GENERIC
@node Machine Dependencies
@chapter Alpha Dependent Features
@end ifclear
 
@cindex Alpha support
@menu
* Alpha Notes:: Notes
* Alpha Options:: Options
* Alpha Syntax:: Syntax
* Alpha Floating Point:: Floating Point
* Alpha Directives:: Alpha Machine Directives
* Alpha Opcodes:: Opcodes
@end menu
 
@node Alpha Notes
@section Notes
@cindex Alpha notes
@cindex notes for Alpha
 
The documentation here is primarily for the ELF object format.
@code{@value{AS}} also supports the ECOFF and EVAX formats, but
features specific to these formats are not yet documented.
 
@node Alpha Options
@section Options
@cindex Alpha options
@cindex options for Alpha
 
@c man begin OPTIONS
@table @gcctabopt
@cindex @code{-m@var{cpu}} command line option, Alpha
@item -m@var{cpu}
This option specifies the target processor. If an attempt is made to
assemble an instruction which will not execute on the target processor,
the assembler may either expand the instruction as a macro or issue an
error message. This option is equivalent to the @code{.arch} directive.
 
The following processor names are recognized:
@code{21064},
@code{21064a},
@code{21066},
@code{21068},
@code{21164},
@code{21164a},
@code{21164pc},
@code{21264},
@code{21264a},
@code{21264b},
@code{ev4},
@code{ev5},
@code{lca45},
@code{ev5},
@code{ev56},
@code{pca56},
@code{ev6},
@code{ev67},
@code{ev68}.
The special name @code{all} may be used to allow the assembler to accept
instructions valid for any Alpha processor.
 
In order to support existing practice in OSF/1 with respect to @code{.arch},
and existing practice within @command{MILO} (the Linux ARC bootloader), the
numbered processor names (e.g.@: 21064) enable the processor-specific PALcode
instructions, while the ``electro-vlasic'' names (e.g.@: @code{ev4}) do not.
 
@cindex @code{-mdebug} command line option, Alpha
@cindex @code{-no-mdebug} command line option, Alpha
@item -mdebug
@itemx -no-mdebug
Enables or disables the generation of @code{.mdebug} encapsulation for
stabs directives and procedure descriptors. The default is to automatically
enable @code{.mdebug} when the first stabs directive is seen.
 
@cindex @code{-relax} command line option, Alpha
@item -relax
This option forces all relocations to be put into the object file, instead
of saving space and resolving some relocations at assembly time. Note that
this option does not propagate all symbol arithmetic into the object file,
because not all symbol arithmetic can be represented. However, the option
can still be useful in specific applications.
 
@cindex @code{-replace} command line option, Alpha
@cindex @code{-noreplace} command line option, Alpha
@item -replace
@itemx -noreplace
Enables or disables the optimization of procedure calls, both at assemblage
and at link time. These options are only available for VMS targets and
@code{-replace} is the default. See section 1.4.1 of the OpenVMS Linker
Utility Manual.
 
@cindex @code{-g} command line option, Alpha
@item -g
This option is used when the compiler generates debug information. When
@command{gcc} is using @command{mips-tfile} to generate debug
information for ECOFF, local labels must be passed through to the object
file. Otherwise this option has no effect.
 
@cindex @code{-G} command line option, Alpha
@item -G@var{size}
A local common symbol larger than @var{size} is placed in @code{.bss},
while smaller symbols are placed in @code{.sbss}.
 
@cindex @code{-F} command line option, Alpha
@cindex @code{-32addr} command line option, Alpha
@item -F
@itemx -32addr
These options are ignored for backward compatibility.
@end table
@c man end
 
@cindex Alpha Syntax
@node Alpha Syntax
@section Syntax
The assembler syntax closely follow the Alpha Reference Manual;
assembler directives and general syntax closely follow the OSF/1 and
OpenVMS syntax, with a few differences for ELF.
 
@menu
* Alpha-Chars:: Special Characters
* Alpha-Regs:: Register Names
* Alpha-Relocs:: Relocations
@end menu
 
@node Alpha-Chars
@subsection Special Characters
 
@cindex line comment character, Alpha
@cindex Alpha line comment character
@samp{#} is the line comment character. Note that if @samp{#} is the
first character on a line then it can also be a logical line number
directive (@pxref{Comments}) or a preprocessor control
command (@pxref{Preprocessing}).
 
@cindex line separator, Alpha
@cindex statement separator, Alpha
@cindex Alpha line separator
@samp{;} can be used instead of a newline to separate statements.
 
@node Alpha-Regs
@subsection Register Names
@cindex Alpha registers
@cindex register names, Alpha
 
The 32 integer registers are referred to as @samp{$@var{n}} or
@samp{$r@var{n}}. In addition, registers 15, 28, 29, and 30 may
be referred to by the symbols @samp{$fp}, @samp{$at}, @samp{$gp},
and @samp{$sp} respectively.
 
The 32 floating-point registers are referred to as @samp{$f@var{n}}.
 
@node Alpha-Relocs
@subsection Relocations
@cindex Alpha relocations
@cindex relocations, Alpha
 
Some of these relocations are available for ECOFF, but mostly
only for ELF. They are modeled after the relocation format
introduced in Digital Unix 4.0, but there are additions.
 
The format is @samp{!@var{tag}} or @samp{!@var{tag}!@var{number}}
where @var{tag} is the name of the relocation. In some cases
@var{number} is used to relate specific instructions.
 
The relocation is placed at the end of the instruction like so:
 
@example
ldah $0,a($29) !gprelhigh
lda $0,a($0) !gprellow
ldq $1,b($29) !literal!100
ldl $2,0($1) !lituse_base!100
@end example
 
@table @code
@item !literal
@itemx !literal!@var{N}
Used with an @code{ldq} instruction to load the address of a symbol
from the GOT.
 
A sequence number @var{N} is optional, and if present is used to pair
@code{lituse} relocations with this @code{literal} relocation. The
@code{lituse} relocations are used by the linker to optimize the code
based on the final location of the symbol.
 
Note that these optimizations are dependent on the data flow of the
program. Therefore, if @emph{any} @code{lituse} is paired with a
@code{literal} relocation, then @emph{all} uses of the register set by
the @code{literal} instruction must also be marked with @code{lituse}
relocations. This is because the original @code{literal} instruction
may be deleted or transformed into another instruction.
 
Also note that there may be a one-to-many relationship between
@code{literal} and @code{lituse}, but not a many-to-one. That is, if
there are two code paths that load up the same address and feed the
value to a single use, then the use may not use a @code{lituse}
relocation.
 
@item !lituse_base!@var{N}
Used with any memory format instruction (e.g.@: @code{ldl}) to indicate
that the literal is used for an address load. The offset field of the
instruction must be zero. During relaxation, the code may be altered
to use a gp-relative load.
 
@item !lituse_jsr!@var{N}
Used with a register branch format instruction (e.g.@: @code{jsr}) to
indicate that the literal is used for a call. During relaxation, the
code may be altered to use a direct branch (e.g.@: @code{bsr}).
 
@item !lituse_jsrdirect!@var{N}
Similar to @code{lituse_jsr}, but also that this call cannot be vectored
through a PLT entry. This is useful for functions with special calling
conventions which do not allow the normal call-clobbered registers to be
clobbered.
 
@item !lituse_bytoff!@var{N}
Used with a byte mask instruction (e.g.@: @code{extbl}) to indicate
that only the low 3 bits of the address are relevant. During relaxation,
the code may be altered to use an immediate instead of a register shift.
 
@item !lituse_addr!@var{N}
Used with any other instruction to indicate that the original address
is in fact used, and the original @code{ldq} instruction may not be
altered or deleted. This is useful in conjunction with @code{lituse_jsr}
to test whether a weak symbol is defined.
 
@example
ldq $27,foo($29) !literal!1
beq $27,is_undef !lituse_addr!1
jsr $26,($27),foo !lituse_jsr!1
@end example
 
@item !lituse_tlsgd!@var{N}
Used with a register branch format instruction to indicate that the
literal is the call to @code{__tls_get_addr} used to compute the
address of the thread-local storage variable whose descriptor was
loaded with @code{!tlsgd!@var{N}}.
 
@item !lituse_tlsldm!@var{N}
Used with a register branch format instruction to indicate that the
literal is the call to @code{__tls_get_addr} used to compute the
address of the base of the thread-local storage block for the current
module. The descriptor for the module must have been loaded with
@code{!tlsldm!@var{N}}.
 
@item !gpdisp!@var{N}
Used with @code{ldah} and @code{lda} to load the GP from the current
address, a-la the @code{ldgp} macro. The source register for the
@code{ldah} instruction must contain the address of the @code{ldah}
instruction. There must be exactly one @code{lda} instruction paired
with the @code{ldah} instruction, though it may appear anywhere in
the instruction stream. The immediate operands must be zero.
 
@example
bsr $26,foo
ldah $29,0($26) !gpdisp!1
lda $29,0($29) !gpdisp!1
@end example
 
@item !gprelhigh
Used with an @code{ldah} instruction to add the high 16 bits of a
32-bit displacement from the GP.
 
@item !gprellow
Used with any memory format instruction to add the low 16 bits of a
32-bit displacement from the GP.
 
@item !gprel
Used with any memory format instruction to add a 16-bit displacement
from the GP.
 
@item !samegp
Used with any branch format instruction to skip the GP load at the
target address. The referenced symbol must have the same GP as the
source object file, and it must be declared to either not use @code{$27}
or perform a standard GP load in the first two instructions via the
@code{.prologue} directive.
 
@item !tlsgd
@itemx !tlsgd!@var{N}
Used with an @code{lda} instruction to load the address of a TLS
descriptor for a symbol in the GOT.
 
The sequence number @var{N} is optional, and if present it used to
pair the descriptor load with both the @code{literal} loading the
address of the @code{__tls_get_addr} function and the @code{lituse_tlsgd}
marking the call to that function.
 
For proper relaxation, both the @code{tlsgd}, @code{literal} and
@code{lituse} relocations must be in the same extended basic block.
That is, the relocation with the lowest address must be executed
first at runtime.
 
@item !tlsldm
@itemx !tlsldm!@var{N}
Used with an @code{lda} instruction to load the address of a TLS
descriptor for the current module in the GOT.
 
Similar in other respects to @code{tlsgd}.
 
@item !gotdtprel
Used with an @code{ldq} instruction to load the offset of the TLS
symbol within its module's thread-local storage block. Also known
as the dynamic thread pointer offset or dtp-relative offset.
 
@item !dtprelhi
@itemx !dtprello
@itemx !dtprel
Like @code{gprel} relocations except they compute dtp-relative offsets.
 
@item !gottprel
Used with an @code{ldq} instruction to load the offset of the TLS
symbol from the thread pointer. Also known as the tp-relative offset.
 
@item !tprelhi
@itemx !tprello
@itemx !tprel
Like @code{gprel} relocations except they compute tp-relative offsets.
@end table
 
@node Alpha Floating Point
@section Floating Point
@cindex floating point, Alpha (@sc{ieee})
@cindex Alpha floating point (@sc{ieee})
The Alpha family uses both @sc{ieee} and VAX floating-point numbers.
 
@node Alpha Directives
@section Alpha Assembler Directives
 
@command{@value{AS}} for the Alpha supports many additional directives for
compatibility with the native assembler. This section describes them only
briefly.
 
@cindex Alpha-only directives
These are the additional directives in @code{@value{AS}} for the Alpha:
 
@table @code
@item .arch @var{cpu}
Specifies the target processor. This is equivalent to the
@option{-m@var{cpu}} command-line option. @xref{Alpha Options, Options},
for a list of values for @var{cpu}.
 
@item .ent @var{function}[, @var{n}]
Mark the beginning of @var{function}. An optional number may follow for
compatibility with the OSF/1 assembler, but is ignored. When generating
@code{.mdebug} information, this will create a procedure descriptor for
the function. In ELF, it will mark the symbol as a function a-la the
generic @code{.type} directive.
 
@item .end @var{function}
Mark the end of @var{function}. In ELF, it will set the size of the symbol
a-la the generic @code{.size} directive.
 
@item .mask @var{mask}, @var{offset}
Indicate which of the integer registers are saved in the current
function's stack frame. @var{mask} is interpreted a bit mask in which
bit @var{n} set indicates that register @var{n} is saved. The registers
are saved in a block located @var{offset} bytes from the @dfn{canonical
frame address} (CFA) which is the value of the stack pointer on entry to
the function. The registers are saved sequentially, except that the
return address register (normally @code{$26}) is saved first.
 
This and the other directives that describe the stack frame are
currently only used when generating @code{.mdebug} information. They
may in the future be used to generate DWARF2 @code{.debug_frame} unwind
information for hand written assembly.
 
@item .fmask @var{mask}, @var{offset}
Indicate which of the floating-point registers are saved in the current
stack frame. The @var{mask} and @var{offset} parameters are interpreted
as with @code{.mask}.
 
@item .frame @var{framereg}, @var{frameoffset}, @var{retreg}[, @var{argoffset}]
Describes the shape of the stack frame. The frame pointer in use is
@var{framereg}; normally this is either @code{$fp} or @code{$sp}. The
frame pointer is @var{frameoffset} bytes below the CFA. The return
address is initially located in @var{retreg} until it is saved as
indicated in @code{.mask}. For compatibility with OSF/1 an optional
@var{argoffset} parameter is accepted and ignored. It is believed to
indicate the offset from the CFA to the saved argument registers.
 
@item .prologue @var{n}
Indicate that the stack frame is set up and all registers have been
spilled. The argument @var{n} indicates whether and how the function
uses the incoming @dfn{procedure vector} (the address of the called
function) in @code{$27}. 0 indicates that @code{$27} is not used; 1
indicates that the first two instructions of the function use @code{$27}
to perform a load of the GP register; 2 indicates that @code{$27} is
used in some non-standard way and so the linker cannot elide the load of
the procedure vector during relaxation.
 
@item .usepv @var{function}, @var{which}
Used to indicate the use of the @code{$27} register, similar to
@code{.prologue}, but without the other semantics of needing to
be inside an open @code{.ent}/@code{.end} block.
 
The @var{which} argument should be either @code{no}, indicating that
@code{$27} is not used, or @code{std}, indicating that the first two
instructions of the function perform a GP load.
 
One might use this directive instead of @code{.prologue} if you are
also using dwarf2 CFI directives.
 
@item .gprel32 @var{expression}
Computes the difference between the address in @var{expression} and the
GP for the current object file, and stores it in 4 bytes. In addition
to being smaller than a full 8 byte address, this also does not require
a dynamic relocation when used in a shared library.
 
@item .t_floating @var{expression}
Stores @var{expression} as an @sc{ieee} double precision value.
 
@item .s_floating @var{expression}
Stores @var{expression} as an @sc{ieee} single precision value.
 
@item .f_floating @var{expression}
Stores @var{expression} as a VAX F format value.
 
@item .g_floating @var{expression}
Stores @var{expression} as a VAX G format value.
 
@item .d_floating @var{expression}
Stores @var{expression} as a VAX D format value.
 
@item .set @var{feature}
Enables or disables various assembler features. Using the positive
name of the feature enables while using @samp{no@var{feature}} disables.
 
@table @code
@item at
Indicates that macro expansions may clobber the @dfn{assembler
temporary} (@code{$at} or @code{$28}) register. Some macros may not be
expanded without this and will generate an error message if @code{noat}
is in effect. When @code{at} is in effect, a warning will be generated
if @code{$at} is used by the programmer.
 
@item macro
Enables the expansion of macro instructions. Note that variants of real
instructions, such as @code{br label} vs @code{br $31,label} are
considered alternate forms and not macros.
 
@item move
@itemx reorder
@itemx volatile
These control whether and how the assembler may re-order instructions.
Accepted for compatibility with the OSF/1 assembler, but @command{@value{AS}}
does not do instruction scheduling, so these features are ignored.
@end table
@end table
 
The following directives are recognized for compatibility with the OSF/1
assembler but are ignored.
 
@example
.proc .aproc
.reguse .livereg
.option .aent
.ugen .eflag
.alias .noalias
@end example
 
@node Alpha Opcodes
@section Opcodes
For detailed information on the Alpha machine instruction set, see the
@c Attempt to work around a very overfull hbox.
@iftex
Alpha Architecture Handbook located at
@smallfonts
@example
ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf
@end example
@textfonts
@end iftex
@ifnottex
@uref{ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf,Alpha Architecture Handbook}.
@end ifnottex
/binutils/gas/doc/c-arc.texi
0,0 → 1,340
@c Copyright 2000, 2001, 2005, 2006, 2007, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@ifset GENERIC
@page
@node ARC-Dependent
@chapter ARC Dependent Features
@end ifset
 
@ifclear GENERIC
@node Machine Dependencies
@chapter ARC Dependent Features
@end ifclear
 
@set ARC_CORE_DEFAULT 6
 
@cindex ARC support
@menu
* ARC Options:: Options
* ARC Syntax:: Syntax
* ARC Floating Point:: Floating Point
* ARC Directives:: ARC Machine Directives
* ARC Opcodes:: Opcodes
@end menu
 
 
@node ARC Options
@section Options
@cindex ARC options (none)
@cindex options for ARC (none)
 
@table @code
 
@cindex @code{-marc[5|6|7|8]} command line option, ARC
@item -marc[5|6|7|8]
This option selects the core processor variant. Using
@code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which
is also the default.
 
@table @code
 
@cindex @code{arc5} arc5, ARC
@item arc5
Base instruction set.
 
@cindex @code{arc6} arc6, ARC
@item arc6
Jump-and-link (jl) instruction. No requirement of an instruction between
setting flags and conditional jump. For example:
 
@smallexample
mov.f r0,r1
beq foo
@end smallexample
 
@cindex @code{arc7} arc7, ARC
@item arc7
Break (brk) and sleep (sleep) instructions.
 
@cindex @code{arc8} arc8, ARC
@item arc8
Software interrupt (swi) instruction.
 
@end table
 
Note: the @code{.option} directive can to be used to select a core
variant from within assembly code.
 
@cindex @code{-EB} command line option, ARC
@item -EB
This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
 
@cindex @code{-EL} command line option, ARC
@item -EL
This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor - this is the
default.
 
@end table
 
@node ARC Syntax
@section Syntax
@menu
* ARC-Chars:: Special Characters
* ARC-Regs:: Register Names
@end menu
 
@node ARC-Chars
@subsection Special Characters
 
@cindex line comment character, ARC
@cindex ARC line comment character
The presence of a @samp{#} on a line indicates the start of a comment
that extends to the end of the current line. Note that if a line
starts with a @samp{#} character then it can also be a logical line
number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, ARC
@cindex statement separator, ARC
@cindex ARC line separator
The ARC assembler does not support a line separator character.
 
@node ARC-Regs
@subsection Register Names
 
@cindex ARC register names
@cindex register names, ARC
*TODO*
 
 
@node ARC Floating Point
@section Floating Point
 
@cindex floating point, ARC (@sc{ieee})
@cindex ARC floating point (@sc{ieee})
The ARC core does not currently have hardware floating point
support. Software floating point support is provided by @code{GCC}
and uses @sc{ieee} floating-point numbers.
 
 
@node ARC Directives
@section ARC Machine Directives
 
@cindex machine directives, ARC
@cindex ARC machine directives
The ARC version of @code{@value{AS}} supports the following additional
machine directives:
 
@table @code
 
@cindex @code{2byte} directive, ARC
@item .2byte @var{expressions}
*TODO*
 
@cindex @code{3byte} directive, ARC
@item .3byte @var{expressions}
*TODO*
 
@cindex @code{4byte} directive, ARC
@item .4byte @var{expressions}
*TODO*
 
@cindex @code{extAuxRegister} directive, ARC
@item .extAuxRegister @var{name},@var{address},@var{mode}
The ARCtangent A4 has extensible auxiliary register space. The
auxiliary registers can be defined in the assembler source code by
using this directive. The first parameter is the @var{name} of the
new auxiallry register. The second parameter is the @var{address} of
the register in the auxiliary register memory map for the variant of
the ARC. The third parameter specifies the @var{mode} in which the
register can be operated is and it can be one of:
 
@table @code
@item r (readonly)
@item w (write only)
@item r|w (read or write)
@end table
 
For example:
 
@smallexample
.extAuxRegister mulhi,0x12,w
@end smallexample
 
This specifies an extension auxiliary register called @emph{mulhi}
which is at address 0x12 in the memory space and which is only
writable.
 
@cindex @code{extCondCode} directive, ARC
@item .extCondCode @var{suffix},@var{value}
The condition codes on the ARCtangent A4 are extensible and can be
specified by means of this assembler directive. They are specified
by the suffix and the value for the condition code. They can be used to
specify extra condition codes with any values. For example:
 
@smallexample
.extCondCode is_busy,0x14
add.is_busy r1,r2,r3
bis_busy _main
@end smallexample
 
@cindex @code{extCoreRegister} directive, ARC
@item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut}
Specifies an extension core register @var{name} for the application.
This allows a register @var{name} with a valid @var{regnum} between 0
and 60, with the following as valid values for @var{mode}
 
@table @samp
@item @emph{r} (readonly)
@item @emph{w} (write only)
@item @emph{r|w} (read or write)
@end table
 
 
The other parameter gives a description of the register having a
@var{shortcut} in the pipeline. The valid values are:
 
@table @code
@item can_shortcut
@item cannot_shortcut
@end table
 
For example:
 
@smallexample
.extCoreRegister mlo,57,r,can_shortcut
@end smallexample
 
This defines an extension core register mlo with the value 57 which
can shortcut the pipeline.
 
@cindex @code{extInstruction} directive, ARC
@item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass}
The ARCtangent A4 allows the user to specify extension instructions.
The extension instructions are not macros. The assembler creates
encodings for use of these instructions according to the specification
by the user. The parameters are:
 
@table @bullet
@item @var{name}
Name of the extension instruction
 
@item @var{opcode}
Opcode to be used. (Bits 27:31 in the encoding). Valid values
0x10-0x1f or 0x03
 
@item @var{subopcode}
Subopcode to be used. Valid values are from 0x09-0x3f. However the
correct value also depends on @var{syntaxclass}
 
@item @var{suffixclass}
Determines the kinds of suffixes to be allowed. Valid values are
@code{SUFFIX_NONE}, @code{SUFFIX_COND},
@code{SUFFIX_FLAG} which indicates the absence or presence of
conditional suffixes and flag setting by the extension instruction.
It is also possible to specify that an instruction sets the flags and
is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
 
@item @var{syntaxclass}
Determines the syntax class for the instruction. It can have the
following values:
 
@table @code
@item @code{SYNTAX_2OP}:
2 Operand Instruction
@item @code{SYNTAX_3OP}:
3 Operand Instruction
@end table
 
In addition there could be modifiers for the syntax class as described
below:
 
@itemize @minus
Syntax Class Modifiers are:
 
@item @code{OP1_MUST_BE_IMM}:
Modifies syntax class SYNTAX_3OP, specifying that the first operand
of a three-operand instruction must be an immediate (i.e., the result
is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with
SYNTAX_3OP as given in the example below. This could usually be used
to set the flags using specific instructions and not retain results.
 
@item @code{OP1_IMM_IMPLIED}:
Modifies syntax class SYNTAX_20P, it specifies that there is an
implied immediate destination operand which does not appear in the
syntax. For example, if the source code contains an instruction like:
 
@smallexample
inst r1,r2
@end smallexample
 
it really means that the first argument is an implied immediate (that
is, the result is discarded). This is the same as though the source
code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it
with SYNTAX_20P.
 
@end itemize
@end table
 
For example, defining 64-bit multiplier with immediate operands:
 
@smallexample
.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
SYNTAX_3OP|OP1_MUST_BE_IMM
@end smallexample
 
The above specifies an extension instruction called mp64 which has 3 operands,
sets the flags, can be used with a condition code, for which the
first operand is an immediate. (Equivalent to discarding the result
of the operation).
 
@smallexample
.extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
@end smallexample
 
This describes a 2 operand instruction with an implicit first
immediate operand. The result of this operation would be discarded.
 
@cindex @code{half} directive, ARC
@item .half @var{expressions}
*TODO*
 
@cindex @code{long} directive, ARC
@item .long @var{expressions}
*TODO*
 
@cindex @code{option} directive, ARC
@item .option @var{arc|arc5|arc6|arc7|arc8}
The @code{.option} directive must be followed by the desired core
version. Again @code{arc} is an alias for
@code{arc@value{ARC_CORE_DEFAULT}}.
 
Note: the @code{.option} directive overrides the command line option
@code{-marc}; a warning is emitted when the version is not consistent
between the two - even for the implicit default core version
(arc@value{ARC_CORE_DEFAULT}).
 
@cindex @code{short} directive, ARC
@item .short @var{expressions}
*TODO*
 
@cindex @code{word} directive, ARC
@item .word @var{expressions}
*TODO*
 
@end table
 
 
@node ARC Opcodes
@section Opcodes
 
@cindex ARC opcodes
@cindex opcodes for ARC
 
For information on the ARC instruction set, see @cite{ARC Programmers
Reference Manual}, ARC International (www.arc.com)
/binutils/gas/doc/c-arm.texi
0,0 → 1,1179
@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
@c 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@ifset GENERIC
@page
@node ARM-Dependent
@chapter ARM Dependent Features
@end ifset
 
@ifclear GENERIC
@node Machine Dependencies
@chapter ARM Dependent Features
@end ifclear
 
@cindex ARM support
@cindex Thumb support
@menu
* ARM Options:: Options
* ARM Syntax:: Syntax
* ARM Floating Point:: Floating Point
* ARM Directives:: ARM Machine Directives
* ARM Opcodes:: Opcodes
* ARM Mapping Symbols:: Mapping Symbols
* ARM Unwinding Tutorial:: Unwinding
@end menu
 
@node ARM Options
@section Options
@cindex ARM options (none)
@cindex options for ARM (none)
 
@table @code
 
@cindex @code{-mcpu=} command line option, ARM
@item -mcpu=@var{processor}[+@var{extension}@dots{}]
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
@code{arm1},
@code{arm2},
@code{arm250},
@code{arm3},
@code{arm6},
@code{arm60},
@code{arm600},
@code{arm610},
@code{arm620},
@code{arm7},
@code{arm7m},
@code{arm7d},
@code{arm7dm},
@code{arm7di},
@code{arm7dmi},
@code{arm70},
@code{arm700},
@code{arm700i},
@code{arm710},
@code{arm710t},
@code{arm720},
@code{arm720t},
@code{arm740t},
@code{arm710c},
@code{arm7100},
@code{arm7500},
@code{arm7500fe},
@code{arm7t},
@code{arm7tdmi},
@code{arm7tdmi-s},
@code{arm8},
@code{arm810},
@code{strongarm},
@code{strongarm1},
@code{strongarm110},
@code{strongarm1100},
@code{strongarm1110},
@code{arm9},
@code{arm920},
@code{arm920t},
@code{arm922t},
@code{arm940t},
@code{arm9tdmi},
@code{fa526} (Faraday FA526 processor),
@code{fa626} (Faraday FA626 processor),
@code{arm9e},
@code{arm926e},
@code{arm926ej-s},
@code{arm946e-r0},
@code{arm946e},
@code{arm946e-s},
@code{arm966e-r0},
@code{arm966e},
@code{arm966e-s},
@code{arm968e-s},
@code{arm10t},
@code{arm10tdmi},
@code{arm10e},
@code{arm1020},
@code{arm1020t},
@code{arm1020e},
@code{arm1022e},
@code{arm1026ej-s},
@code{fa606te} (Faraday FA606TE processor),
@code{fa616te} (Faraday FA616TE processor),
@code{fa626te} (Faraday FA626TE processor),
@code{fmp626} (Faraday FMP626 processor),
@code{fa726te} (Faraday FA726TE processor),
@code{arm1136j-s},
@code{arm1136jf-s},
@code{arm1156t2-s},
@code{arm1156t2f-s},
@code{arm1176jz-s},
@code{arm1176jzf-s},
@code{mpcore},
@code{mpcorenovfp},
@code{cortex-a5},
@code{cortex-a7},
@code{cortex-a8},
@code{cortex-a9},
@code{cortex-a15},
@code{cortex-r4},
@code{cortex-r4f},
@code{cortex-m4},
@code{cortex-m3},
@code{cortex-m1},
@code{cortex-m0},
@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
@code{i80200} (Intel XScale processor)
@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
and
@code{xscale}.
The special name @code{all} may be used to allow the
assembler to accept instructions valid for any ARM processor.
 
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
is equivalent to specifying @code{-mcpu=ep9312}.
 
Multiple extensions may be specified, separated by a @code{+}. The
extensions should be specified in ascending alphabetical order.
 
Some extensions may be restricted to particular architectures; this is
documented in the list of extensions below.
 
Extension mnemonics may also be removed from those the assembler accepts.
This is done be prepending @code{no} to the option that adds the extension.
Extensions that are removed should be listed after all extensions which have
been added, again in ascending alphabetical order. For example,
@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
 
 
The following extensions are currently supported:
@code{idiv}, (Integer Divide Extensions for v7-A and v7-R architectures),
@code{iwmmxt},
@code{iwmmxt2},
@code{maverick},
@code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
@code{os} (Operating System for v6M architecture),
@code{sec} (Security Extensions for v6K and v7-A architectures),
@code{virt} (Virtualization Extensions for v7-A architecture, implies
@code{idiv}),
and
@code{xscale}.
 
@cindex @code{-march=} command line option, ARM
@item -march=@var{architecture}[+@var{extension}@dots{}]
This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
will not execute on the target architecture. The following architecture
names are recognized:
@code{armv1},
@code{armv2},
@code{armv2a},
@code{armv2s},
@code{armv3},
@code{armv3m},
@code{armv4},
@code{armv4xm},
@code{armv4t},
@code{armv4txm},
@code{armv5},
@code{armv5t},
@code{armv5txm},
@code{armv5te},
@code{armv5texp},
@code{armv6},
@code{armv6j},
@code{armv6k},
@code{armv6z},
@code{armv6zk},
@code{armv6-m},
@code{armv6s-m},
@code{armv7},
@code{armv7-a},
@code{armv7-r},
@code{armv7-m},
@code{armv7e-m},
@code{iwmmxt}
and
@code{xscale}.
If both @code{-mcpu} and
@code{-march} are specified, the assembler will use
the setting for @code{-mcpu}.
 
The architecture option can be extended with the same instruction set
extension options as the @code{-mcpu} option.
 
@cindex @code{-mfpu=} command line option, ARM
@item -mfpu=@var{floating-point-format}
 
This option specifies the floating point format to assemble for. The
assembler will issue an error message if an attempt is made to assemble
an instruction which will not execute on the target floating point unit.
The following format options are recognized:
@code{softfpa},
@code{fpe},
@code{fpe2},
@code{fpe3},
@code{fpa},
@code{fpa10},
@code{fpa11},
@code{arm7500fe},
@code{softvfp},
@code{softvfp+vfp},
@code{vfp},
@code{vfp10},
@code{vfp10-r0},
@code{vfp9},
@code{vfpxd},
@code{vfpv2},
@code{vfpv3},
@code{vfpv3-fp16},
@code{vfpv3-d16},
@code{vfpv3-d16-fp16},
@code{vfpv3xd},
@code{vfpv3xd-d16},
@code{vfpv4},
@code{vfpv4-d16},
@code{fpv4-sp-d16},
@code{arm1020t},
@code{arm1020e},
@code{arm1136jf-s},
@code{maverick},
@code{neon},
and
@code{neon-vfpv4}.
 
In addition to determining which instructions are assembled, this option
also affects the way in which the @code{.double} assembler directive behaves
when assembling little-endian code.
 
The default is dependent on the processor selected. For Architecture 5 or
later, the default is to assembler for VFP instructions; for earlier
architectures the default is to assemble for FPA instructions.
 
@cindex @code{-mthumb} command line option, ARM
@item -mthumb
This option specifies that the assembler should start assembling Thumb
instructions; that is, it should behave as though the file starts with a
@code{.code 16} directive.
 
@cindex @code{-mthumb-interwork} command line option, ARM
@item -mthumb-interwork
This option specifies that the output generated by the assembler should
be marked as supporting interworking.
 
@cindex @code{-mimplicit-it} command line option, ARM
@item -mimplicit-it=never
@itemx -mimplicit-it=always
@itemx -mimplicit-it=arm
@itemx -mimplicit-it=thumb
The @code{-mimplicit-it} option controls the behavior of the assembler when
conditional instructions are not enclosed in IT blocks.
There are four possible behaviors.
If @code{never} is specified, such constructs cause a warning in ARM
code and an error in Thumb-2 code.
If @code{always} is specified, such constructs are accepted in both
ARM and Thumb-2 code, where the IT instruction is added implicitly.
If @code{arm} is specified, such constructs are accepted in ARM code
and cause an error in Thumb-2 code.
If @code{thumb} is specified, such constructs cause a warning in ARM
code and are accepted in Thumb-2 code. If you omit this option, the
behavior is equivalent to @code{-mimplicit-it=arm}.
 
@cindex @code{-mapcs-26} command line option, ARM
@cindex @code{-mapcs-32} command line option, ARM
@item -mapcs-26
@itemx -mapcs-32
These options specify that the output generated by the assembler should
be marked as supporting the indicated version of the Arm Procedure.
Calling Standard.
 
@cindex @code{-matpcs} command line option, ARM
@item -matpcs
This option specifies that the output generated by the assembler should
be marked as supporting the Arm/Thumb Procedure Calling Standard. If
enabled this option will cause the assembler to create an empty
debugging section in the object file called .arm.atpcs. Debuggers can
use this to determine the ABI being used by.
 
@cindex @code{-mapcs-float} command line option, ARM
@item -mapcs-float
This indicates the floating point variant of the APCS should be
used. In this variant floating point arguments are passed in FP
registers rather than integer registers.
 
@cindex @code{-mapcs-reentrant} command line option, ARM
@item -mapcs-reentrant
This indicates that the reentrant variant of the APCS should be used.
This variant supports position independent code.
 
@cindex @code{-mfloat-abi=} command line option, ARM
@item -mfloat-abi=@var{abi}
This option specifies that the output generated by the assembler should be
marked as using specified floating point ABI.
The following values are recognized:
@code{soft},
@code{softfp}
and
@code{hard}.
 
@cindex @code{-eabi=} command line option, ARM
@item -meabi=@var{ver}
This option specifies which EABI version the produced object files should
conform to.
The following values are recognized:
@code{gnu},
@code{4}
and
@code{5}.
 
@cindex @code{-EB} command line option, ARM
@item -EB
This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
 
@cindex @code{-EL} command line option, ARM
@item -EL
This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.
 
@cindex @code{-k} command line option, ARM
@cindex PIC code generation for ARM
@item -k
This option specifies that the output of the assembler should be marked
as position-independent code (PIC).
 
@cindex @code{--fix-v4bx} command line option, ARM
@item --fix-v4bx
Allow @code{BX} instructions in ARMv4 code. This is intended for use with
the linker option of the same name.
 
@cindex @code{-mwarn-deprecated} command line option, ARM
@item -mwarn-deprecated
@itemx -mno-warn-deprecated
Enable or disable warnings about using deprecated options or
features. The default is to warn.
 
@end table
 
 
@node ARM Syntax
@section Syntax
@menu
* ARM-Instruction-Set:: Instruction Set
* ARM-Chars:: Special Characters
* ARM-Regs:: Register Names
* ARM-Relocations:: Relocations
* ARM-Neon-Alignment:: NEON Alignment Specifiers
@end menu
 
@node ARM-Instruction-Set
@subsection Instruction Set Syntax
Two slightly different syntaxes are support for ARM and THUMB
instructions. The default, @code{divided}, uses the old style where
ARM and THUMB instructions had their own, separate syntaxes. The new,
@code{unified} syntax, which can be selected via the @code{.syntax}
directive, and has the following main features:
 
@table @bullet
@item
Immediate operands do not require a @code{#} prefix.
 
@item
The @code{IT} instruction may appear, and if it does it is validated
against subsequent conditional affixes. In ARM mode it does not
generate machine code, in THUMB mode it does.
 
@item
For ARM instructions the conditional affixes always appear at the end
of the instruction. For THUMB instructions conditional affixes can be
used, but only inside the scope of an @code{IT} instruction.
 
@item
All of the instructions new to the V6T2 architecture (and later) are
available. (Only a few such instructions can be written in the
@code{divided} syntax).
 
@item
The @code{.N} and @code{.W} suffixes are recognized and honored.
 
@item
All instructions set the flags if and only if they have an @code{s}
affix.
@end table
 
@node ARM-Chars
@subsection Special Characters
 
@cindex line comment character, ARM
@cindex ARM line comment character
The presence of a @samp{@@} anywhere on a line indicates the start of
a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, ARM
@cindex statement separator, ARM
@cindex ARM line separator
The @samp{;} character can be used instead of a newline to separate
statements.
 
@cindex immediate character, ARM
@cindex ARM immediate character
Either @samp{#} or @samp{$} can be used to indicate immediate operands.
 
@cindex identifiers, ARM
@cindex ARM identifiers
*TODO* Explain about /data modifier on symbols.
 
@node ARM-Regs
@subsection Register Names
 
@cindex ARM register names
@cindex register names, ARM
*TODO* Explain about ARM register naming, and the predefined names.
 
@node ARM-Neon-Alignment
@subsection NEON Alignment Specifiers
 
@cindex alignment for NEON instructions
Some NEON load/store instructions allow an optional address
alignment qualifier.
The ARM documentation specifies that this is indicated by
@samp{@@ @var{align}}. However GAS already interprets
the @samp{@@} character as a "line comment" start,
so @samp{: @var{align}} is used instead. For example:
 
@smallexample
vld1.8 @{q0@}, [r0, :128]
@end smallexample
 
@node ARM Floating Point
@section Floating Point
 
@cindex floating point, ARM (@sc{ieee})
@cindex ARM floating point (@sc{ieee})
The ARM family uses @sc{ieee} floating-point numbers.
 
@node ARM-Relocations
@subsection ARM relocation generation
 
@cindex data relocations, ARM
@cindex ARM data relocations
Specific data relocations can be generated by putting the relocation name
in parentheses after the symbol name. For example:
 
@smallexample
.word foo(TARGET1)
@end smallexample
 
This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
@var{foo}.
The following relocations are supported:
@code{GOT},
@code{GOTOFF},
@code{TARGET1},
@code{TARGET2},
@code{SBREL},
@code{TLSGD},
@code{TLSLDM},
@code{TLSLDO},
@code{TLSDESC},
@code{TLSCALL},
@code{GOTTPOFF},
@code{GOT_PREL}
and
@code{TPOFF}.
 
For compatibility with older toolchains the assembler also accepts
@code{(PLT)} after branch targets. On legacy targets this will
generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
targets it will encode either the @samp{R_ARM_CALL} or
@samp{R_ARM_JUMP24} relocation, as appropriate.
 
@cindex MOVW and MOVT relocations, ARM
Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
respectively. For example to load the 32-bit address of foo into r0:
 
@smallexample
MOVW r0, #:lower16:foo
MOVT r0, #:upper16:foo
@end smallexample
 
@node ARM Directives
@section ARM Machine Directives
 
@cindex machine directives, ARM
@cindex ARM machine directives
@table @code
 
@c AAAAAAAAAAAAAAAAAAAAAAAAA
 
@cindex @code{.2byte} directive, ARM
@cindex @code{.4byte} directive, ARM
@cindex @code{.8byte} directive, ARM
@item .2byte @var{expression} [, @var{expression}]*
@itemx .4byte @var{expression} [, @var{expression}]*
@itemx .8byte @var{expression} [, @var{expression}]*
These directives write 2, 4 or 8 byte values to the output section.
 
@cindex @code{.align} directive, ARM
@item .align @var{expression} [, @var{expression}]
This is the generic @var{.align} directive. For the ARM however if the
first argument is zero (ie no alignment is needed) the assembler will
behave as if the argument had been 2 (ie pad to the next four byte
boundary). This is for compatibility with ARM's own assembler.
 
@cindex @code{.arch} directive, ARM
@item .arch @var{name}
Select the target architecture. Valid values for @var{name} are the same as
for the @option{-march} commandline option.
 
Specifying @code{.arch} clears any previously selected architecture
extensions.
 
@cindex @code{.arch_extension} directive, ARM
@item .arch_extension @var{name}
Add or remove an architecture extension to the target architecture. Valid
values for @var{name} are the same as those accepted as architectural
extensions by the @option{-mcpu} commandline option.
 
@code{.arch_extension} may be used multiple times to add or remove extensions
incrementally to the architecture being compiled for.
 
@cindex @code{.arm} directive, ARM
@item .arm
This performs the same action as @var{.code 32}.
 
@anchor{arm_pad}
@cindex @code{.pad} directive, ARM
@item .pad #@var{count}
Generate unwinder annotations for a stack adjustment of @var{count} bytes.
A positive value indicates the function prologue allocated stack space by
decrementing the stack pointer.
 
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
 
@cindex @code{.bss} directive, ARM
@item .bss
This directive switches to the @code{.bss} section.
 
@c CCCCCCCCCCCCCCCCCCCCCCCCCC
 
@cindex @code{.cantunwind} directive, ARM
@item .cantunwind
Prevents unwinding through the current function. No personality routine
or exception table data is required or permitted.
 
@cindex @code{.code} directive, ARM
@item .code @code{[16|32]}
This directive selects the instruction set being generated. The value 16
selects Thumb, with the value 32 selecting ARM.
 
@cindex @code{.cpu} directive, ARM
@item .cpu @var{name}
Select the target processor. Valid values for @var{name} are the same as
for the @option{-mcpu} commandline option.
 
Specifying @code{.cpu} clears any previously selected architecture
extensions.
 
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
 
@cindex @code{.dn} and @code{.qn} directives, ARM
@item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
@itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
 
The @code{dn} and @code{qn} directives are used to create typed
and/or indexed register aliases for use in Advanced SIMD Extension
(Neon) instructions. The former should be used to create aliases
of double-precision registers, and the latter to create aliases of
quad-precision registers.
 
If these directives are used to create typed aliases, those aliases can
be used in Neon instructions instead of writing types after the mnemonic
or after each operand. For example:
 
@smallexample
x .dn d2.f32
y .dn d3.f32
z .dn d4.f32[1]
vmul x,y,z
@end smallexample
 
This is equivalent to writing the following:
 
@smallexample
vmul.f32 d2,d3,d4[1]
@end smallexample
 
Aliases created using @code{dn} or @code{qn} can be destroyed using
@code{unreq}.
 
@c EEEEEEEEEEEEEEEEEEEEEEEEEE
 
@cindex @code{.eabi_attribute} directive, ARM
@item .eabi_attribute @var{tag}, @var{value}
Set the EABI object attribute @var{tag} to @var{value}.
 
The @var{tag} is either an attribute number, or one of the following:
@code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
@code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
@code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
@code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
@code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
@code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
@code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
@code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
@code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
@code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
@code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
@code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
@code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
@code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
@code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
@code{Tag_MPextension_use}, @code{Tag_DIV_use},
@code{Tag_nodefaults}, @code{Tag_also_compatible_with},
@code{Tag_conformance}, @code{Tag_T2EE_use},
@code{Tag_Virtualization_use}
 
The @var{value} is either a @code{number}, @code{"string"}, or
@code{number, "string"} depending on the tag.
 
Note - the following legacy values are also accepted by @var{tag}:
@code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
@code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
 
@cindex @code{.even} directive, ARM
@item .even
This directive aligns to an even-numbered address.
 
@cindex @code{.extend} directive, ARM
@cindex @code{.ldouble} directive, ARM
@item .extend @var{expression} [, @var{expression}]*
@itemx .ldouble @var{expression} [, @var{expression}]*
These directives write 12byte long double floating-point values to the
output section. These are not compatible with current ARM processors
or ABIs.
 
@c FFFFFFFFFFFFFFFFFFFFFFFFFF
 
@anchor{arm_fnend}
@cindex @code{.fnend} directive, ARM
@item .fnend
Marks the end of a function with an unwind table entry. The unwind index
table entry is created when this directive is processed.
 
If no personality routine has been specified then standard personality
routine 0 or 1 will be used, depending on the number of unwind opcodes
required.
 
@anchor{arm_fnstart}
@cindex @code{.fnstart} directive, ARM
@item .fnstart
Marks the start of a function with an unwind table entry.
 
@cindex @code{.force_thumb} directive, ARM
@item .force_thumb
This directive forces the selection of Thumb instructions, even if the
target processor does not support those instructions
 
@cindex @code{.fpu} directive, ARM
@item .fpu @var{name}
Select the floating-point unit to assemble for. Valid values for @var{name}
are the same as for the @option{-mfpu} commandline option.
 
@c GGGGGGGGGGGGGGGGGGGGGGGGGG
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
 
@cindex @code{.handlerdata} directive, ARM
@item .handlerdata
Marks the end of the current function, and the start of the exception table
entry for that function. Anything between this directive and the
@code{.fnend} directive will be added to the exception table entry.
 
Must be preceded by a @code{.personality} or @code{.personalityindex}
directive.
 
@c IIIIIIIIIIIIIIIIIIIIIIIIII
 
@cindex @code{.inst} directive, ARM
@item .inst @var{opcode} [ , @dots{} ]
@itemx .inst.n @var{opcode} [ , @dots{} ]
@itemx .inst.w @var{opcode} [ , @dots{} ]
Generates the instruction corresponding to the numerical value @var{opcode}.
@code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
specified explicitly, overriding the normal encoding rules.
 
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
@c LLLLLLLLLLLLLLLLLLLLLLLLLL
 
@item .ldouble @var{expression} [, @var{expression}]*
See @code{.extend}.
 
@cindex @code{.ltorg} directive, ARM
@item .ltorg
This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
@code{GAS} maintains a separate literal pool for each section and each
sub-section. The @code{.ltorg} directive will only affect the literal
pool of the current section and sub-section. At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.
 
Note - older versions of @code{GAS} would dump the current literal
pool any time a section change occurred. This is no longer done, since
it prevents accurate control of the placement of literal pools.
 
@c MMMMMMMMMMMMMMMMMMMMMMMMMM
 
@cindex @code{.movsp} directive, ARM
@item .movsp @var{reg} [, #@var{offset}]
Tell the unwinder that @var{reg} contains an offset from the current
stack pointer. If @var{offset} is not specified then it is assumed to be
zero.
 
@c NNNNNNNNNNNNNNNNNNNNNNNNNN
@c OOOOOOOOOOOOOOOOOOOOOOOOOO
 
@cindex @code{.object_arch} directive, ARM
@item .object_arch @var{name}
Override the architecture recorded in the EABI object attribute section.
Valid values for @var{name} are the same as for the @code{.arch} directive.
Typically this is useful when code uses runtime detection of CPU features.
 
@c PPPPPPPPPPPPPPPPPPPPPPPPPP
 
@cindex @code{.packed} directive, ARM
@item .packed @var{expression} [, @var{expression}]*
This directive writes 12-byte packed floating-point values to the
output section. These are not compatible with current ARM processors
or ABIs.
 
@cindex @code{.pad} directive, ARM
@item .pad #@var{count}
Generate unwinder annotations for a stack adjustment of @var{count} bytes.
A positive value indicates the function prologue allocated stack space by
decrementing the stack pointer.
 
@cindex @code{.personality} directive, ARM
@item .personality @var{name}
Sets the personality routine for the current function to @var{name}.
 
@cindex @code{.personalityindex} directive, ARM
@item .personalityindex @var{index}
Sets the personality routine for the current function to the EABI standard
routine number @var{index}
 
@cindex @code{.pool} directive, ARM
@item .pool
This is a synonym for .ltorg.
 
@c QQQQQQQQQQQQQQQQQQQQQQQQQQ
@c RRRRRRRRRRRRRRRRRRRRRRRRRR
 
@cindex @code{.req} directive, ARM
@item @var{name} .req @var{register name}
This creates an alias for @var{register name} called @var{name}. For
example:
 
@smallexample
foo .req r0
@end smallexample
 
@c SSSSSSSSSSSSSSSSSSSSSSSSSS
 
@anchor{arm_save}
@cindex @code{.save} directive, ARM
@item .save @var{reglist}
Generate unwinder annotations to restore the registers in @var{reglist}.
The format of @var{reglist} is the same as the corresponding store-multiple
instruction.
 
@smallexample
@exdent @emph{core registers}
.save @{r4, r5, r6, lr@}
stmfd sp!, @{r4, r5, r6, lr@}
@exdent @emph{FPA registers}
.save f4, 2
sfmfd f4, 2, [sp]!
@exdent @emph{VFP registers}
.save @{d8, d9, d10@}
fstmdx sp!, @{d8, d9, d10@}
@exdent @emph{iWMMXt registers}
.save @{wr10, wr11@}
wstrd wr11, [sp, #-8]!
wstrd wr10, [sp, #-8]!
or
.save wr11
wstrd wr11, [sp, #-8]!
.save wr10
wstrd wr10, [sp, #-8]!
@end smallexample
 
@anchor{arm_setfp}
@cindex @code{.setfp} directive, ARM
@item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
Make all unwinder annotations relative to a frame pointer. Without this
the unwinder will use offsets from the stack pointer.
 
The syntax of this directive is the same as the @code{add} or @code{mov}
instruction used to set the frame pointer. @var{spreg} must be either
@code{sp} or mentioned in a previous @code{.movsp} directive.
 
@smallexample
.movsp ip
mov ip, sp
@dots{}
.setfp fp, ip, #4
add fp, ip, #4
@end smallexample
 
@cindex @code{.secrel32} directive, ARM
@item .secrel32 @var{expression} [, @var{expression}]*
This directive emits relocations that evaluate to the section-relative
offset of each expression's symbol. This directive is only supported
for PE targets.
 
@cindex @code{.syntax} directive, ARM
@item .syntax [@code{unified} | @code{divided}]
This directive sets the Instruction Set Syntax as described in the
@ref{ARM-Instruction-Set} section.
 
@c TTTTTTTTTTTTTTTTTTTTTTTTTT
 
@cindex @code{.thumb} directive, ARM
@item .thumb
This performs the same action as @var{.code 16}.
 
@cindex @code{.thumb_func} directive, ARM
@item .thumb_func
This directive specifies that the following symbol is the name of a
Thumb encoded function. This information is necessary in order to allow
the assembler and linker to generate correct code for interworking
between Arm and Thumb instructions and should be used even if
interworking is not going to be performed. The presence of this
directive also implies @code{.thumb}
 
This directive is not neccessary when generating EABI objects. On these
targets the encoding is implicit when generating Thumb code.
 
@cindex @code{.thumb_set} directive, ARM
@item .thumb_set
This performs the equivalent of a @code{.set} directive in that it
creates a symbol which is an alias for another symbol (possibly not yet
defined). This directive also has the added property in that it marks
the aliased symbol as being a thumb function entry point, in the same
way that the @code{.thumb_func} directive does.
 
@cindex @code{.tlsdescseq} directive, ARM
@item .tlsdescseq @var{tls-variable}
This directive is used to annotate parts of an inlined TLS descriptor
trampoline. Normally the trampoline is provided by the linker, and
this directive is not needed.
 
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
 
@cindex @code{.unreq} directive, ARM
@item .unreq @var{alias-name}
This undefines a register alias which was previously defined using the
@code{req}, @code{dn} or @code{qn} directives. For example:
 
@smallexample
foo .req r0
.unreq foo
@end smallexample
 
An error occurs if the name is undefined. Note - this pseudo op can
be used to delete builtin in register name aliases (eg 'r0'). This
should only be done if it is really necessary.
 
@cindex @code{.unwind_raw} directive, ARM
@item .unwind_raw @var{offset}, @var{byte1}, @dots{}
Insert one of more arbitary unwind opcode bytes, which are known to adjust
the stack pointer by @var{offset} bytes.
 
For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
@code{.save @{r0@}}
 
@c VVVVVVVVVVVVVVVVVVVVVVVVVV
 
@cindex @code{.vsave} directive, ARM
@item .vsave @var{vfp-reglist}
Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
using FLDMD. Also works for VFPv3 registers
that are to be restored using VLDM.
The format of @var{vfp-reglist} is the same as the corresponding store-multiple
instruction.
 
@smallexample
@exdent @emph{VFP registers}
.vsave @{d8, d9, d10@}
fstmdd sp!, @{d8, d9, d10@}
@exdent @emph{VFPv3 registers}
.vsave @{d15, d16, d17@}
vstm sp!, @{d15, d16, d17@}
@end smallexample
 
Since FLDMX and FSTMX are now deprecated, this directive should be
used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
 
@c WWWWWWWWWWWWWWWWWWWWWWWWWW
@c XXXXXXXXXXXXXXXXXXXXXXXXXX
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
 
@end table
 
@node ARM Opcodes
@section Opcodes
 
@cindex ARM opcodes
@cindex opcodes for ARM
@code{@value{AS}} implements all the standard ARM opcodes. It also
implements several pseudo opcodes, including several synthetic load
instructions.
 
@table @code
 
@cindex @code{NOP} pseudo op, ARM
@item NOP
@smallexample
nop
@end smallexample
 
This pseudo op will always evaluate to a legal ARM instruction that does
nothing. Currently it will evaluate to MOV r0, r0.
 
@cindex @code{LDR reg,=<label>} pseudo op, ARM
@item LDR
@smallexample
ldr <register> , = <expression>
@end smallexample
 
If expression evaluates to a numeric constant then a MOV or MVN
instruction will be used in place of the LDR instruction, if the
constant can be generated by either of these instructions. Otherwise
the constant will be placed into the nearest literal pool (if it not
already there) and a PC relative LDR instruction will be generated.
 
@cindex @code{ADR reg,<label>} pseudo op, ARM
@item ADR
@smallexample
adr <register> <label>
@end smallexample
 
This instruction will load the address of @var{label} into the indicated
register. The instruction will evaluate to a PC relative ADD or SUB
instruction depending upon where the label is located. If the label is
out of range, or if it is not defined in the same file (and section) as
the ADR instruction, then an error will be generated. This instruction
will not make use of the literal pool.
 
@cindex @code{ADRL reg,<label>} pseudo op, ARM
@item ADRL
@smallexample
adrl <register> <label>
@end smallexample
 
This instruction will load the address of @var{label} into the indicated
register. The instruction will evaluate to one or two PC relative ADD
or SUB instructions depending upon where the label is located. If a
second instruction is not needed a NOP instruction will be generated in
its place, so that this instruction is always 8 bytes long.
 
If the label is out of range, or if it is not defined in the same file
(and section) as the ADRL instruction, then an error will be generated.
This instruction will not make use of the literal pool.
 
@end table
 
For information on the ARM or Thumb instruction sets, see @cite{ARM
Software Development Toolkit Reference Manual}, Advanced RISC Machines
Ltd.
 
@node ARM Mapping Symbols
@section Mapping Symbols
 
The ARM ELF specification requires that special symbols be inserted
into object files to mark certain features:
 
@table @code
 
@cindex @code{$a}
@item $a
At the start of a region of code containing ARM instructions.
 
@cindex @code{$t}
@item $t
At the start of a region of code containing THUMB instructions.
 
@cindex @code{$d}
@item $d
At the start of a region of data.
 
@end table
 
The assembler will automatically insert these symbols for you - there
is no need to code them yourself. Support for tagging symbols ($b,
$f, $p and $m) which is also mentioned in the current ARM ELF
specification is not implemented. This is because they have been
dropped from the new EABI and so tools cannot rely upon their
presence.
 
@node ARM Unwinding Tutorial
@section Unwinding
 
The ABI for the ARM Architecture specifies a standard format for
exception unwind information. This information is used when an
exception is thrown to determine where control should be transferred.
In particular, the unwind information is used to determine which
function called the function that threw the exception, and which
function called that one, and so forth. This information is also used
to restore the values of callee-saved registers in the function
catching the exception.
 
If you are writing functions in assembly code, and those functions
call other functions that throw exceptions, you must use assembly
pseudo ops to ensure that appropriate exception unwind information is
generated. Otherwise, if one of the functions called by your assembly
code throws an exception, the run-time library will be unable to
unwind the stack through your assembly code and your program will not
behave correctly.
 
To illustrate the use of these pseudo ops, we will examine the code
that G++ generates for the following C++ input:
 
@verbatim
void callee (int *);
 
int
caller ()
{
int i;
callee (&i);
return i;
}
@end verbatim
 
This example does not show how to throw or catch an exception from
assembly code. That is a much more complex operation and should
always be done in a high-level language, such as C++, that directly
supports exceptions.
 
The code generated by one particular version of G++ when compiling the
example above is:
 
@verbatim
_Z6callerv:
.fnstart
.LFB2:
@ Function supports interworking.
@ args = 0, pretend = 0, frame = 8
@ frame_needed = 1, uses_anonymous_args = 0
stmfd sp!, {fp, lr}
.save {fp, lr}
.LCFI0:
.setfp fp, sp, #4
add fp, sp, #4
.LCFI1:
.pad #8
sub sp, sp, #8
.LCFI2:
sub r3, fp, #8
mov r0, r3
bl _Z6calleePi
ldr r3, [fp, #-8]
mov r0, r3
sub sp, fp, #4
ldmfd sp!, {fp, lr}
bx lr
.LFE2:
.fnend
@end verbatim
 
Of course, the sequence of instructions varies based on the options
you pass to GCC and on the version of GCC in use. The exact
instructions are not important since we are focusing on the pseudo ops
that are used to generate unwind information.
 
An important assumption made by the unwinder is that the stack frame
does not change during the body of the function. In particular, since
we assume that the assembly code does not itself throw an exception,
the only point where an exception can be thrown is from a call, such
as the @code{bl} instruction above. At each call site, the same saved
registers (including @code{lr}, which indicates the return address)
must be located in the same locations relative to the frame pointer.
 
The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
op appears immediately before the first instruction of the function
while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
op appears immediately after the last instruction of the function.
These pseudo ops specify the range of the function.
 
Only the order of the other pseudos ops (e.g., @code{.setfp} or
@code{.pad}) matters; their exact locations are irrelevant. In the
example above, the compiler emits the pseudo ops with particular
instructions. That makes it easier to understand the code, but it is
not required for correctness. It would work just as well to emit all
of the pseudo ops other than @code{.fnend} in the same order, but
immediately after @code{.fnstart}.
 
The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
indicates registers that have been saved to the stack so that they can
be restored before the function returns. The argument to the
@code{.save} pseudo op is a list of registers to save. If a register
is ``callee-saved'' (as specified by the ABI) and is modified by the
function you are writing, then your code must save the value before it
is modified and restore the original value before the function
returns. If an exception is thrown, the run-time library restores the
values of these registers from their locations on the stack before
returning control to the exception handler. (Of course, if an
exception is not thrown, the function that contains the @code{.save}
pseudo op restores these registers in the function epilogue, as is
done with the @code{ldmfd} instruction above.)
 
You do not have to save callee-saved registers at the very beginning
of the function and you do not need to use the @code{.save} pseudo op
immediately following the point at which the registers are saved.
However, if you modify a callee-saved register, you must save it on
the stack before modifying it and before calling any functions which
might throw an exception. And, you must use the @code{.save} pseudo
op to indicate that you have done so.
 
The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
modification of the stack pointer that does not save any registers.
The argument is the number of bytes (in decimal) that are subtracted
from the stack pointer. (On ARM CPUs, the stack grows downwards, so
subtracting from the stack pointer increases the size of the stack.)
 
The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
indicates the register that contains the frame pointer. The first
argument is the register that is set, which is typically @code{fp}.
The second argument indicates the register from which the frame
pointer takes its value. The third argument, if present, is the value
(in decimal) added to the register specified by the second argument to
compute the value of the frame pointer. You should not modify the
frame pointer in the body of the function.
 
If you do not use a frame pointer, then you should not use the
@code{.setfp} pseudo op. If you do not use a frame pointer, then you
should avoid modifying the stack pointer outside of the function
prologue. Otherwise, the run-time library will be unable to find
saved registers when it is unwinding the stack.
 
The pseudo ops described above are sufficient for writing assembly
code that calls functions which may throw exceptions. If you need to
know more about the object-file format used to represent unwind
information, you may consult the @cite{Exception Handling ABI for the
ARM Architecture} available from @uref{http://infocenter.arm.com}.
/binutils/gas/doc/c-avr.texi
0,0 → 1,413
@c Copyright 2006, 2007, 2008, 2009, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@ifset GENERIC
@page
@node AVR-Dependent
@chapter AVR Dependent Features
@end ifset
 
@ifclear GENERIC
@node Machine Dependencies
@chapter AVR Dependent Features
@end ifclear
 
@cindex AVR support
@menu
* AVR Options:: Options
* AVR Syntax:: Syntax
* AVR Opcodes:: Opcodes
@end menu
 
@node AVR Options
@section Options
@cindex AVR options (none)
@cindex options for AVR (none)
 
@table @code
 
@cindex @code{-mmcu=} command line option, AVR
@item -mmcu=@var{mcu}
Specify ATMEL AVR instruction set or MCU type.
 
Instruction set avr1 is for the minimal AVR core, not supported by the C
compiler, only for assembler programs (MCU types: at90s1200,
attiny11, attiny12, attiny15, attiny28).
 
Instruction set avr2 (default) is for the classic AVR core with up to
8K program memory space (MCU types: at90s2313, at90s2323, at90s2333, at90s2343,
attiny22, attiny26, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534,
at90s8535).
 
Instruction set avr25 is for the classic AVR core with up to 8K program memory
space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313,
attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84,
attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461,
attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88,
at86rf401, ata6289).
 
Instruction set avr3 is for the classic AVR core with up to 128K program
memory space (MCU types: at43usb355, at76c711).
 
Instruction set avr31 is for the classic AVR core with exactly 128K program
memory space (MCU types: atmega103, at43usb320).
 
Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP
instructions (MCU types: attiny167, at90usb82, at90usb162, atmega8u2,
atmega16u2, atmega32u2).
 
Instruction set avr4 is for the enhanced AVR core with up to 8K program
memory space (MCU types: atmega48, atmega48a, atmega48p, atmega8, atmega88,
atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1,
at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81).
 
Instruction set avr5 is for the enhanced AVR core with up to 128K program
memory space (MCU types: atmega16, atmega16a, atmega161, atmega162, atmega163,
atmega164a, atmega164p, atmega165, atmega165a, atmega165p, atmega168,
atmega168a, atmega168p, atmega169, atmega169a, atmega169p, atmega169pa,
atmega32, atmega323, atmega324a, atmega324p, atmega325, atmega325a, atmega325p,
atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, atmega3290,
atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega640,
atmega644, atmega644a, atmega644p, atmega644pa, atmega645, atmega645a,
atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a,
atmega649p, atmega6490, atmega6490a, atmega6490p, atmega16hva, atmega16hva2,
atmega16hvb, atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve,
at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, atmega32c1,
atmega64c1, atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4,
atmega32u6, at90usb646, at90usb647, at94k, at90scr100).
 
Instruction set avr51 is for the enhanced AVR core with exactly 128K program
memory space (MCU types: atmega128, atmega1280, atmega1281, atmega1284p,
atmega128rfa1, at90can128, at90usb1286, at90usb1287, m3000).
 
Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types:
atmega2560, atmega2561).
 
Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program
memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16d4,
atxmega16x1, atxmega32a4, atxmega32d4, atxmega32x1).
 
Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program
memory space and greater than 64K data space (MCU types: none).
 
Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program
memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3).
 
Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program
memory space and greater than 64K data space (MCU types: atxmega64a1,
atxmega64a1u).
 
Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program
memory space and less than 64K data space (MCU types: atxmega128a3,
atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3,
atxmega256a3b, atxmega256a3bu, atxmega192d3).
 
Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program
memory space and greater than 64K data space (MCU types: atxmega128a1,
atxmega128a1u).
 
@cindex @code{-mall-opcodes} command line option, AVR
@item -mall-opcodes
Accept all AVR opcodes, even if not supported by @code{-mmcu}.
 
@cindex @code{-mno-skip-bug} command line option, AVR
@item -mno-skip-bug
This option disable warnings for skipping two-word instructions.
 
@cindex @code{-mno-wrap} command line option, AVR
@item -mno-wrap
This option reject @code{rjmp/rcall} instructions with 8K wrap-around.
 
@end table
 
 
@node AVR Syntax
@section Syntax
@menu
* AVR-Chars:: Special Characters
* AVR-Regs:: Register Names
* AVR-Modifiers:: Relocatable Expression Modifiers
@end menu
 
@node AVR-Chars
@subsection Special Characters
 
@cindex line comment character, AVR
@cindex AVR line comment character
 
The presence of a @samp{;} anywhere on a line indicates the start of a
comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line, the whole line
is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, AVR
@cindex statement separator, AVR
@cindex AVR line separator
 
The @samp{$} character can be used instead of a newline to separate
statements.
 
@node AVR-Regs
@subsection Register Names
 
@cindex AVR register names
@cindex register names, AVR
 
The AVR has 32 x 8-bit general purpose working registers @samp{r0},
@samp{r1}, ... @samp{r31}.
Six of the 32 registers can be used as three 16-bit indirect address
register pointers for Data Space addressing. One of the these address
pointers can also be used as an address pointer for look up tables in
Flash program memory. These added function registers are the 16-bit
@samp{X}, @samp{Y} and @samp{Z} - registers.
 
@smallexample
X = @r{r26:r27}
Y = @r{r28:r29}
Z = @r{r30:r31}
@end smallexample
 
@node AVR-Modifiers
@subsection Relocatable Expression Modifiers
 
@cindex AVR modifiers
@cindex syntax, AVR
 
The assembler supports several modifiers when using relocatable addresses
in AVR instruction operands. The general syntax is the following:
 
@smallexample
modifier(relocatable-expression)
@end smallexample
 
@table @code
@cindex symbol modifiers
 
@item lo8
 
This modifier allows you to use bits 0 through 7 of
an address expression as 8 bit relocatable expression.
 
@item hi8
 
This modifier allows you to use bits 7 through 15 of an address expression
as 8 bit relocatable expression. This is useful with, for example, the
AVR @samp{ldi} instruction and @samp{lo8} modifier.
 
For example
 
@smallexample
ldi r26, lo8(sym+10)
ldi r27, hi8(sym+10)
@end smallexample
 
@item hh8
 
This modifier allows you to use bits 16 through 23 of
an address expression as 8 bit relocatable expression.
Also, can be useful for loading 32 bit constants.
 
@item hlo8
 
Synonym of @samp{hh8}.
 
@item hhi8
 
This modifier allows you to use bits 24 through 31 of
an expression as 8 bit expression. This is useful with, for example, the
AVR @samp{ldi} instruction and @samp{lo8}, @samp{hi8}, @samp{hlo8},
@samp{hhi8}, modifier.
 
For example
 
@smallexample
ldi r26, lo8(285774925)
ldi r27, hi8(285774925)
ldi r28, hlo8(285774925)
ldi r29, hhi8(285774925)
; r29,r28,r27,r26 = 285774925
@end smallexample
 
@item pm_lo8
 
This modifier allows you to use bits 0 through 7 of
an address expression as 8 bit relocatable expression.
This modifier useful for addressing data or code from
Flash/Program memory. The using of @samp{pm_lo8} similar
to @samp{lo8}.
 
@item pm_hi8
 
This modifier allows you to use bits 8 through 15 of
an address expression as 8 bit relocatable expression.
This modifier useful for addressing data or code from
Flash/Program memory.
 
@item pm_hh8
 
This modifier allows you to use bits 15 through 23 of
an address expression as 8 bit relocatable expression.
This modifier useful for addressing data or code from
Flash/Program memory.
 
@end table
 
@node AVR Opcodes
@section Opcodes
 
@cindex AVR opcode summary
@cindex opcode summary, AVR
@cindex mnemonics, AVR
@cindex instruction summary, AVR
For detailed information on the AVR machine instruction set, see
@url{www.atmel.com/products/AVR}.
 
@code{@value{AS}} implements all the standard AVR opcodes.
The following table summarizes the AVR opcodes, and their arguments.
 
@smallexample
@i{Legend:}
r @r{any register}
d @r{`ldi' register (r16-r31)}
v @r{`movw' even register (r0, r2, ..., r28, r30)}
a @r{`fmul' register (r16-r23)}
w @r{`adiw' register (r24,r26,r28,r30)}
e @r{pointer registers (X,Y,Z)}
b @r{base pointer register and displacement ([YZ]+disp)}
z @r{Z pointer register (for [e]lpm Rd,Z[+])}
M @r{immediate value from 0 to 255}
n @r{immediate value from 0 to 255 ( n = ~M ). Relocation impossible}
s @r{immediate value from 0 to 7}
P @r{Port address value from 0 to 63. (in, out)}
p @r{Port address value from 0 to 31. (cbi, sbi, sbic, sbis)}
K @r{immediate value from 0 to 63 (used in `adiw', `sbiw')}
i @r{immediate value}
l @r{signed pc relative offset from -64 to 63}
L @r{signed pc relative offset from -2048 to 2047}
h @r{absolute code address (call, jmp)}
S @r{immediate value from 0 to 7 (S = s << 4)}
? @r{use this opcode entry if no parameters, else use next opcode entry}
 
1001010010001000 clc
1001010011011000 clh
1001010011111000 cli
1001010010101000 cln
1001010011001000 cls
1001010011101000 clt
1001010010111000 clv
1001010010011000 clz
1001010000001000 sec
1001010001011000 seh
1001010001111000 sei
1001010000101000 sen
1001010001001000 ses
1001010001101000 set
1001010000111000 sev
1001010000011000 sez
100101001SSS1000 bclr S
100101000SSS1000 bset S
1001010100001001 icall
1001010000001001 ijmp
1001010111001000 lpm ?
1001000ddddd010+ lpm r,z
1001010111011000 elpm ?
1001000ddddd011+ elpm r,z
0000000000000000 nop
1001010100001000 ret
1001010100011000 reti
1001010110001000 sleep
1001010110011000 break
1001010110101000 wdr
1001010111101000 spm
000111rdddddrrrr adc r,r
000011rdddddrrrr add r,r
001000rdddddrrrr and r,r
000101rdddddrrrr cp r,r
000001rdddddrrrr cpc r,r
000100rdddddrrrr cpse r,r
001001rdddddrrrr eor r,r
001011rdddddrrrr mov r,r
100111rdddddrrrr mul r,r
001010rdddddrrrr or r,r
000010rdddddrrrr sbc r,r
000110rdddddrrrr sub r,r
001001rdddddrrrr clr r
000011rdddddrrrr lsl r
000111rdddddrrrr rol r
001000rdddddrrrr tst r
0111KKKKddddKKKK andi d,M
0111KKKKddddKKKK cbr d,n
1110KKKKddddKKKK ldi d,M
11101111dddd1111 ser d
0110KKKKddddKKKK ori d,M
0110KKKKddddKKKK sbr d,M
0011KKKKddddKKKK cpi d,M
0100KKKKddddKKKK sbci d,M
0101KKKKddddKKKK subi d,M
1111110rrrrr0sss sbrc r,s
1111111rrrrr0sss sbrs r,s
1111100ddddd0sss bld r,s
1111101ddddd0sss bst r,s
10110PPdddddPPPP in r,P
10111PPrrrrrPPPP out P,r
10010110KKddKKKK adiw w,K
10010111KKddKKKK sbiw w,K
10011000pppppsss cbi p,s
10011010pppppsss sbi p,s
10011001pppppsss sbic p,s
10011011pppppsss sbis p,s
111101lllllll000 brcc l
111100lllllll000 brcs l
111100lllllll001 breq l
111101lllllll100 brge l
111101lllllll101 brhc l
111100lllllll101 brhs l
111101lllllll111 brid l
111100lllllll111 brie l
111100lllllll000 brlo l
111100lllllll100 brlt l
111100lllllll010 brmi l
111101lllllll001 brne l
111101lllllll010 brpl l
111101lllllll000 brsh l
111101lllllll110 brtc l
111100lllllll110 brts l
111101lllllll011 brvc l
111100lllllll011 brvs l
111101lllllllsss brbc s,l
111100lllllllsss brbs s,l
1101LLLLLLLLLLLL rcall L
1100LLLLLLLLLLLL rjmp L
1001010hhhhh111h call h
1001010hhhhh110h jmp h
1001010rrrrr0101 asr r
1001010rrrrr0000 com r
1001010rrrrr1010 dec r
1001010rrrrr0011 inc r
1001010rrrrr0110 lsr r
1001010rrrrr0001 neg r
1001000rrrrr1111 pop r
1001001rrrrr1111 push r
1001010rrrrr0111 ror r
1001010rrrrr0010 swap r
00000001ddddrrrr movw v,v
00000010ddddrrrr muls d,d
000000110ddd0rrr mulsu a,a
000000110ddd1rrr fmul a,a
000000111ddd0rrr fmuls a,a
000000111ddd1rrr fmulsu a,a
1001001ddddd0000 sts i,r
1001000ddddd0000 lds r,i
10o0oo0dddddbooo ldd r,b
100!000dddddee-+ ld r,e
10o0oo1rrrrrbooo std b,r
100!001rrrrree-+ st e,r
1001010100011001 eicall
1001010000011001 eijmp
@end smallexample
/binutils/gas/doc/c-bfin.texi
0,0 → 1,274
@c Copyright 2005, 2006, 2009, 2010, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c man end
 
@ifset GENERIC
@page
@node Blackfin-Dependent
@chapter Blackfin Dependent Features
@end ifset
 
@ifclear GENERIC
@node Machine Dependencies
@chapter Blackfin Dependent Features
@end ifclear
 
@cindex Blackfin support
@menu
* Blackfin Options:: Blackfin Options
* Blackfin Syntax:: Blackfin Syntax
* Blackfin Directives:: Blackfin Directives
@end menu
 
@node Blackfin Options
@section Options
@cindex Blackfin options (none)
@cindex options for Blackfin (none)
 
@c man begin OPTIONS
@table @gcctabopt
 
@cindex @code{-mcpu=} command line option, Blackfin
@item -mcpu=@var{processor}@r{[}-@var{sirevision}@r{]}
This option specifies the target processor. The optional @var{sirevision}
is not used in assembler. It's here such that GCC can easily pass down its
@code{-mcpu=} option. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
@code{bf504},
@code{bf506},
@code{bf512},
@code{bf514},
@code{bf516},
@code{bf518},
@code{bf522},
@code{bf523},
@code{bf524},
@code{bf525},
@code{bf526},
@code{bf527},
@code{bf531},
@code{bf532},
@code{bf533},
@code{bf534},
@code{bf535} (not implemented yet),
@code{bf536},
@code{bf537},
@code{bf538},
@code{bf539},
@code{bf542},
@code{bf542m},
@code{bf544},
@code{bf544m},
@code{bf547},
@code{bf547m},
@code{bf548},
@code{bf548m},
@code{bf549},
@code{bf549m},
@code{bf561},
and
@code{bf592}.
 
@cindex @code{-mfdpic} command line option, Blackfin
@item -mfdpic
Assemble for the FDPIC ABI.
 
@cindex @code{-mno-fdpic} command line option, Blackfin
@cindex @code{-mnopic} command line option, Blackfin
@item -mno-fdpic
@itemx -mnopic
Disable -mfdpic.
@end table
@c man end
 
@node Blackfin Syntax
@section Syntax
@cindex Blackfin syntax
@cindex syntax, Blackfin
 
@table @code
@item Special Characters
Assembler input is free format and may appear anywhere on the line.
One instruction may extend across multiple lines or more than one
instruction may appear on the same line. White space (space, tab,
comments or newline) may appear anywhere between tokens. A token must
not have embedded spaces. Tokens include numbers, register names,
keywords, user identifiers, and also some multicharacter special
symbols like "+=", "/*" or "||".
 
Comments are introduced by the @samp{#} character and extend to the
end of the current line. If the @samp{#} appears as the first
character of a line, the whole line is treated as a comment, but in
this case the line can also be a logical line number directive
(@pxref{Comments}) or a preprocessor control command
(@pxref{Preprocessing}).
 
@item Instruction Delimiting
A semicolon must terminate every instruction. Sometimes a complete
instruction will consist of more than one operation. There are two
cases where this occurs. The first is when two general operations
are combined. Normally a comma separates the different parts, as in
 
@smallexample
a0= r3.h * r2.l, a1 = r3.l * r2.h ;
@end smallexample
 
The second case occurs when a general instruction is combined with one
or two memory references for joint issue. The latter portions are
set off by a "||" token.
 
@smallexample
a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
@end smallexample
 
Multiple instructions can occur on the same line. Each must be
terminated by a semicolon character.
 
@item Register Names
 
The assembler treats register names and instruction keywords in a case
insensitive manner. User identifiers are case sensitive. Thus, R3.l,
R3.L, r3.l and r3.L are all equivalent input to the assembler.
 
Register names are reserved and may not be used as program identifiers.
 
Some operations (such as "Move Register") require a register pair.
Register pairs are always data registers and are denoted using a colon,
eg., R3:2. The larger number must be written firsts. Note that the
hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
 
Some instructions (such as --SP (Push Multiple)) require a group of
adjacent registers. Adjacent registers are denoted in the syntax by
the range enclosed in parentheses and separated by a colon, eg., (R7:3).
Again, the larger number appears first.
 
Portions of a particular register may be individually specified. This
is written with a dot (".") following the register name and then a
letter denoting the desired portion. For 32-bit registers, ".H"
denotes the most significant ("High") portion. ".L" denotes the
least-significant portion. The subdivisions of the 40-bit registers
are described later.
 
@item Accumulators
The set of 40-bit registers A1 and A0 that normally contain data that
is being manipulated. Each accumulator can be accessed in four ways.
 
@table @code
@item one 40-bit register
The register will be referred to as A1 or A0.
@item one 32-bit register
The registers are designated as A1.W or A0.W.
@item two 16-bit registers
The registers are designated as A1.H, A1.L, A0.H or A0.L.
@item one 8-bit register
The registers are designated as A1.X or A0.X for the bits that
extend beyond bit 31.
@end table
 
@item Data Registers
The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
normally contain data for manipulation. These are abbreviated as
D-register or Dreg. Data registers can be accessed as 32-bit registers
or as two independent 16-bit registers. The least significant 16 bits
of each register is called the "low" half and is designated with ".L"
following the register name. The most significant 16 bits are called
the "high" half and is designated with ".H" following the name.
 
@smallexample
R7.L, r2.h, r4.L, R0.H
@end smallexample
 
@item Pointer Registers
The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
normally contain byte addresses of data structures. These are
abbreviated as P-register or Preg.
 
@smallexample
p2, p5, fp, sp
@end smallexample
 
@item Stack Pointer SP
The stack pointer contains the 32-bit address of the last occupied
byte location in the stack. The stack grows by decrementing the
stack pointer.
 
@item Frame Pointer FP
The frame pointer contains the 32-bit address of the previous frame
pointer in the stack. It is located at the top of a frame.
 
@item Loop Top
LT0 and LT1. These registers contain the 32-bit address of the top of
a zero overhead loop.
 
@item Loop Count
LC0 and LC1. These registers contain the 32-bit counter of the zero
overhead loop executions.
 
@item Loop Bottom
LB0 and LB1. These registers contain the 32-bit address of the bottom
of a zero overhead loop.
 
@item Index Registers
The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
addresses of data structures. Abbreviated I-register or Ireg.
 
@item Modify Registers
The set of 32-bit registers (M0, M1, M2, M3) that normally contain
offset values that are added and subtracted to one of the index
registers. Abbreviated as Mreg.
 
@item Length Registers
The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
length in bytes of the circular buffer. Abbreviated as Lreg. Clear
the Lreg to disable circular addressing for the corresponding Ireg.
 
@item Base Registers
The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
base address in bytes of the circular buffer. Abbreviated as Breg.
 
@item Floating Point
The Blackfin family has no hardware floating point but the .float
directive generates ieee floating point numbers for use with software
floating point libraries.
 
@item Blackfin Opcodes
For detailed information on the Blackfin machine instruction set, see
the Blackfin(r) Processor Instruction Set Reference.
 
@end table
 
@node Blackfin Directives
@section Directives
@cindex Blackfin directives
@cindex directives, Blackfin
 
The following directives are provided for compatibility with the VDSP assembler.
 
@table @code
@item .byte2
Initializes a two byte data object.
 
This maps to the @code{.short} directive.
@item .byte4
Initializes a four byte data object.
 
This maps to the @code{.int} directive.
@item .db
Initializes a single byte data object.
 
This directive is a synonym for @code{.byte}.
@item .dw
Initializes a two byte data object.
 
This directive is a synonym for @code{.byte2}.
@item .dd
Initializes a four byte data object.
 
This directive is a synonym for @code{.byte4}.
@item .var
Define and initialize a 32 bit data object.
@end table
/binutils/gas/doc/c-cr16.texi
0,0 → 1,117
@c Copyright 2007, 2008, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@ifset GENERIC
@page
@node CR16-Dependent
@chapter CR16 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter CR16 Dependent Features
@end ifclear
 
@cindex CR16 support
@menu
* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers
* CR16 Syntax:: Syntax for the CR16
@end menu
 
@node CR16 Operand Qualifiers
@section CR16 Operand Qualifiers
@cindex CR16 Operand Qualifiers
 
The National Semiconductor CR16 target of @code{@value{AS}} has a few machine dependent operand qualifiers.
 
Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The @code{@@} is required. CR16 architecture uses one of the following expression qualifiers:
 
@table @code
@item s
- @code{Specifies expression operand type as small}
@item m
- @code{Specifies expression operand type as medium}
@item l
- @code{Specifies expression operand type as large}
@item c
- @code{Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.}
@item got/GOT
- @code{Specifies the CR16 Assembler generates a relocation entry for the operand, offset from Global Offset Table. The linker uses this relocation entry to update the operand address at link time}
@item cgot/cGOT
- @code{Specifies the CompactRISC Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.}
@end table
 
CR16 target operand qualifiers and its size (in bits):
 
@table @samp
@item Immediate Operand
- s ---- 4 bits
@item
- m ---- 16 bits, for movb and movw instructions.
@item
- m ---- 20 bits, movd instructions.
@item
- l ---- 32 bits
 
@item Absolute Operand
- s ---- Illegal specifier for this operand.
@item
- m ---- 20 bits, movd instructions.
 
@item Displacement Operand
- s ---- 8 bits
@item
- m ---- 16 bits
@item
- l ---- 24 bits
@end table
 
For example:
@example
1 @code{movw $_myfun@@c,r1}
 
This loads the address of _myfun, shifted right by 1, into r1.
 
2 @code{movd $_myfun@@c,(r2,r1)}
 
This loads the address of _myfun, shifted right by 1, into register-pair r2-r1.
3 @code{_myfun_ptr:}
@code{.long _myfun@@c}
@code{loadd _myfun_ptr, (r1,r0)}
@code{jal (r1,r0)}
 
This .long directive, the address of _myfunc, shifted right by 1 at link time.
 
4 @code{loadd _data1@@GOT(r12), (r1,r0)}
 
This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1.
 
5 @code{loadd _myfunc@@cGOT(r12), (r1,r0)}
 
This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.
@end example
 
@node CR16 Syntax
@section CR16 Syntax
@menu
* CR16-Chars:: Special Characters
@end menu
 
@node CR16-Chars
@subsection Special Characters
 
@cindex line comment character, CR16
@cindex CR16 line comment character
The presence of a @samp{#} on a line indicates the start of a comment
that extends to the end of the current line. If the @samp{#} appears
as the first character of a line, the whole line is treated as a
comment, but in this case the line can also be a logical line number
directive (@pxref{Comments}) or a preprocessor control command
(@pxref{Preprocessing}).
 
@cindex line separator, CR16
@cindex statement separator, CR16
@cindex CR16 line separator
The @samp{;} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-cris.texi
0,0 → 1,411
@c Copyright 2002, 2004 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c CRIS description contributed by Axis Communications.
@ifset GENERIC
@page
@node CRIS-Dependent
@chapter CRIS Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter CRIS Dependent Features
@end ifclear
 
@cindex CRIS support
@menu
* CRIS-Opts:: Command-line Options
* CRIS-Expand:: Instruction expansion
* CRIS-Symbols:: Symbols
* CRIS-Syntax:: Syntax
@end menu
 
@node CRIS-Opts
@section Command-line Options
 
@cindex options, CRIS
@cindex CRIS options
The CRIS version of @code{@value{AS}} has these
machine-dependent command-line options.
 
@cindex @option{--emulation=criself} command line option, CRIS
@cindex @option{--emulation=crisaout} command line option, CRIS
@cindex CRIS @option{--emulation=criself} command line option
@cindex CRIS @option{--emulation=crisaout} command line option
 
The format of the generated object files can be either ELF or
a.out, specified by the command-line options
@option{--emulation=crisaout} and @option{--emulation=criself}.
The default is ELF (criself), unless @code{@value{AS}} has been
configured specifically for a.out by using the configuration
name @code{cris-axis-aout}.
 
@cindex @option{--underscore} command line option, CRIS
@cindex @option{--no-underscore} command line option, CRIS
@cindex CRIS @option{--underscore} command line option
@cindex CRIS @option{--no-underscore} command line option
There are two different link-incompatible ELF object file
variants for CRIS, for use in environments where symbols are
expected to be prefixed by a leading @samp{_} character and for
environments without such a symbol prefix. The variant used for
GNU/Linux port has no symbol prefix. Which variant to produce
is specified by either of the options @option{--underscore} and
@option{--no-underscore}. The default is @option{--underscore}.
Since symbols in CRIS a.out objects are expected to have a
@samp{_} prefix, specifying @option{--no-underscore} when
generating a.out objects is an error. Besides the object format
difference, the effect of this option is to parse register names
differently (@pxref{crisnous}). The @option{--no-underscore}
option makes a @samp{$} register prefix mandatory.
 
@cindex @option{--pic} command line option, CRIS
@cindex CRIS @option{--pic} command line option
@cindex Position-independent code, CRIS
@cindex CRIS position-independent code
The option @option{--pic} must be passed to @code{@value{AS}} in
order to recognize the symbol syntax used for ELF (SVR4 PIC)
position-independent-code (@pxref{crispic}). This will also
affect expansion of instructions. The expansion with
@option{--pic} will use PC-relative rather than (slightly
faster) absolute addresses in those expansions. This option is only
valid when generating ELF format object files.
 
@cindex @option{--march=@var{architecture}} command line option, CRIS
@cindex CRIS @option{--march=@var{architecture}} command line option
@cindex Architecture variant option, CRIS
@cindex CRIS architecture variant option
The option @option{--march=@var{architecture}}
@anchor{march-option}specifies the recognized instruction set
and recognized register names. It also controls the
architecture type of the object file. Valid values for
@var{architecture} are:
@table @code
 
@item v0_v10
All instructions and register names for any architecture variant
in the set v0@dots{}v10 are recognized. This is the
default if the target is configured as cris-*.
 
@item v10
Only instructions and register names for CRIS v10 (as found in
ETRAX 100 LX) are recognized. This is the default if the target
is configured as crisv10-*.
 
@item v32
Only instructions and register names for CRIS v32 (code name
Guinness) are recognized. This is the default if the target is
configured as crisv32-*. This value implies
@option{--no-mul-bug-abort}. (A subsequent
@option{--mul-bug-abort} will turn it back on.)
 
@item common_v10_v32
Only instructions with register names and addressing modes with
opcodes common to the v10 and v32 are recognized.
@end table
 
@cindex @option{-N} command line option, CRIS
@cindex CRIS @option{-N} command line option
When @option{-N} is specified, @code{@value{AS}} will emit a
warning when a 16-bit branch instruction is expanded into a
32-bit multiple-instruction construct (@pxref{CRIS-Expand}).
 
@cindex @option{--no-mul-bug-abort} command line option, CRIS
@cindex @option{--mul-bug-abort} command line option, CRIS
@cindex CRIS @option{--no-mul-bug-abort} command line option
@cindex CRIS @option{--mul-bug-abort} command line option
 
Some versions of the CRIS v10, for example in the Etrax 100 LX,
contain a bug that causes destabilizing memory accesses when a
multiply instruction is executed with certain values in the
first operand just before a cache-miss. When the
@option{--mul-bug-abort} command line option is active (the
default value), @code{@value{AS}} will refuse to assemble a file
containing a multiply instruction at a dangerous offset, one
that could be the last on a cache-line, or is in a section with
insufficient alignment. This placement checking does not catch
any case where the multiply instruction is dangerously placed
because it is located in a delay-slot. The
@option{--mul-bug-abort} command line option turns off the
checking.
 
@node CRIS-Expand
@section Instruction expansion
 
@cindex instruction expansion, CRIS
@cindex CRIS instruction expansion
@code{@value{AS}} will silently choose an instruction that fits
the operand size for @samp{[register+constant]} operands. For
example, the offset @code{127} in @code{move.d [r3+127],r4} fits
in an instruction using a signed-byte offset. Similarly,
@code{move.d [r2+32767],r1} will generate an instruction using a
16-bit offset. For symbolic expressions and constants that do
not fit in 16 bits including the sign bit, a 32-bit offset is
generated.
 
For branches, @code{@value{AS}} will expand from a 16-bit branch
instruction into a sequence of instructions that can reach a
full 32-bit address. Since this does not correspond to a single
instruction, such expansions can optionally be warned about.
@xref{CRIS-Opts}.
 
If the operand is found to fit the range, a @code{lapc} mnemonic
will translate to a @code{lapcq} instruction. Use @code{lapc.d}
to force the 32-bit @code{lapc} instruction.
 
Similarly, the @code{addo} mnemonic will translate to the
shortest fitting instruction of @code{addoq}, @code{addo.w} and
@code{addo.d}, when used with a operand that is a constant known
at assembly time.
 
@node CRIS-Symbols
@section Symbols
@cindex Symbols, built-in, CRIS
@cindex Symbols, CRIS, built-in
@cindex CRIS built-in symbols
@cindex Built-in symbols, CRIS
 
Some symbols are defined by the assembler. They're intended to
be used in conditional assembly, for example:
@smallexample
.if ..asm.arch.cris.v32
@var{code for CRIS v32}
.elseif ..asm.arch.cris.common_v10_v32
@var{code common to CRIS v32 and CRIS v10}
.elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
@var{code for v10}
.else
.error "Code needs to be added here."
.endif
@end smallexample
 
These symbols are defined in the assembler, reflecting
command-line options, either when specified or the default.
They are always defined, to 0 or 1.
@table @code
 
@item ..asm.arch.cris.any_v0_v10
This symbol is non-zero when @option{--march=v0_v10} is specified
or the default.
 
@item ..asm.arch.cris.common_v10_v32
Set according to the option @option{--march=common_v10_v32}.
 
@item ..asm.arch.cris.v10
Reflects the option @option{--march=v10}.
 
@item ..asm.arch.cris.v32
Corresponds to @option{--march=v10}.
@end table
 
Speaking of symbols, when a symbol is used in code, it can have
a suffix modifying its value for use in position-independent
code. @xref{CRIS-Pic}.
 
@node CRIS-Syntax
@section Syntax
 
There are different aspects of the CRIS assembly syntax.
 
@menu
* CRIS-Chars:: Special Characters
* CRIS-Pic:: Position-Independent Code Symbols
* CRIS-Regs:: Register Names
* CRIS-Pseudos:: Assembler Directives
@end menu
 
@node CRIS-Chars
@subsection Special Characters
@cindex line comment characters, CRIS
@cindex CRIS line comment characters
 
The character @samp{#} is a line comment character. It starts a
comment if and only if it is placed at the beginning of a line.
 
A @samp{;} character starts a comment anywhere on the line,
causing all characters up to the end of the line to be ignored.
 
A @samp{@@} character is handled as a line separator equivalent
to a logical new-line character (except in a comment), so
separate instructions can be specified on a single line.
 
@node CRIS-Pic
@subsection Symbols in position-independent code
@cindex Symbols in position-independent code, CRIS
@cindex CRIS symbols in position-independent code
@cindex Position-independent code, symbols in, CRIS
 
When generating @anchor{crispic}position-independent code (SVR4
PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu
shared libraries, symbol
suffixes are used to specify what kind of run-time symbol lookup
will be used, expressed in the object as different
@emph{relocation types}. Usually, all absolute symbol values
must be located in a table, the @emph{global offset table},
leaving the code position-independent; independent of values of
global symbols and independent of the address of the code. The
suffix modifies the value of the symbol, into for example an
index into the global offset table where the real symbol value
is entered, or a PC-relative value, or a value relative to the
start of the global offset table. All symbol suffixes start
with the character @samp{:} (omitted in the list below). Every
symbol use in code or a read-only section must therefore have a
PIC suffix to enable a useful shared library to be created.
Usually, these constructs must not be used with an additive
constant offset as is usually allowed, i.e.@: no 4 as in
@code{symbol + 4} is allowed. This restriction is checked at
link-time, not at assembly-time.
 
@table @code
@item GOT
 
Attaching this suffix to a symbol in an instruction causes the
symbol to be entered into the global offset table. The value is
a 32-bit index for that symbol into the global offset table.
The name of the corresponding relocation is
@samp{R_CRIS_32_GOT}. Example: @code{move.d
[$r0+extsym:GOT],$r9}
 
@item GOT16
 
Same as for @samp{GOT}, but the value is a 16-bit index into the
global offset table. The corresponding relocation is
@samp{R_CRIS_16_GOT}. Example: @code{move.d
[$r0+asymbol:GOT16],$r10}
 
@item PLT
 
This suffix is used for function symbols. It causes a
@emph{procedure linkage table}, an array of code stubs, to be
created at the time the shared object is created or linked
against, together with a global offset table entry. The value
is a pc-relative offset to the corresponding stub code in the
procedure linkage table. This arrangement causes the run-time
symbol resolver to be called to look up and set the value of the
symbol the first time the function is called (at latest;
depending environment variables). It is only safe to leave the
symbol unresolved this way if all references are function calls.
The name of the relocation is @samp{R_CRIS_32_PLT_PCREL}.
Example: @code{add.d fnname:PLT,$pc}
 
@item PLTG
 
Like PLT, but the value is relative to the beginning of the
global offset table. The relocation is
@samp{R_CRIS_32_PLT_GOTREL}. Example: @code{move.d
fnname:PLTG,$r3}
 
@item GOTPLT
 
Similar to @samp{PLT}, but the value of the symbol is a 32-bit
index into the global offset table. This is somewhat of a mix
between the effect of the @samp{GOT} and the @samp{PLT} suffix;
the difference to @samp{GOT} is that there will be a procedure
linkage table entry created, and that the symbol is assumed to
be a function entry and will be resolved by the run-time
resolver as with @samp{PLT}. The relocation is
@samp{R_CRIS_32_GOTPLT}. Example: @code{jsr
[$r0+fnname:GOTPLT]}
 
@item GOTPLT16
 
A variant of @samp{GOTPLT} giving a 16-bit value. Its
relocation name is @samp{R_CRIS_16_GOTPLT}. Example: @code{jsr
[$r0+fnname:GOTPLT16]}
 
@item GOTOFF
 
This suffix must only be attached to a local symbol, but may be
used in an expression adding an offset. The value is the
address of the symbol relative to the start of the global offset
table. The relocation name is @samp{R_CRIS_32_GOTREL}.
Example: @code{move.d [$r0+localsym:GOTOFF],r3}
@end table
 
@node CRIS-Regs
@subsection Register names
@cindex register names, CRIS
@cindex CRIS register names
 
A @samp{$} character may always prefix a general or special
register name in an instruction operand but is mandatory when
the option @option{--no-underscore} is specified or when the
@code{.syntax register_prefix} directive is in effect
(@pxref{crisnous}). Register names are case-insensitive.
 
@node CRIS-Pseudos
@subsection Assembler Directives
@cindex assembler directives, CRIS
@cindex pseudo-ops, CRIS
@cindex CRIS assembler directives
@cindex CRIS pseudo-ops
 
There are a few CRIS-specific pseudo-directives in addition to
the generic ones. @xref{Pseudo Ops}. Constants emitted by
pseudo-directives are in little-endian order for CRIS. There is
no support for floating-point-specific directives for CRIS.
 
@table @code
@item .dword EXPRESSIONS
@cindex assembler directive .dword, CRIS
@cindex pseudo-op .dword, CRIS
@cindex CRIS assembler directive .dword
@cindex CRIS pseudo-op .dword
 
The @code{.dword} directive is a synonym for @code{.int},
expecting zero or more EXPRESSIONS, separated by commas. For
each expression, a 32-bit little-endian constant is emitted.
 
@item .syntax ARGUMENT
@cindex assembler directive .syntax, CRIS
@cindex pseudo-op .syntax, CRIS
@cindex CRIS assembler directive .syntax
@cindex CRIS pseudo-op .syntax
The @code{.syntax} directive takes as @var{ARGUMENT} one of the
following case-sensitive choices.
 
@table @code
@item no_register_prefix
 
The @code{.syntax no_register_prefix} @anchor{crisnous}directive
makes a @samp{$} character prefix on all registers optional. It
overrides a previous setting, including the corresponding effect
of the option @option{--no-underscore}. If this directive is
used when ordinary symbols do not have a @samp{_} character
prefix, care must be taken to avoid ambiguities whether an
operand is a register or a symbol; using symbols with names the
same as general or special registers then invoke undefined
behavior.
 
@item register_prefix
 
This directive makes a @samp{$} character prefix on all
registers mandatory. It overrides a previous setting, including
the corresponding effect of the option @option{--underscore}.
 
@item leading_underscore
 
This is an assertion directive, emitting an error if the
@option{--no-underscore} option is in effect.
 
@item no_leading_underscore
 
This is the opposite of the @code{.syntax leading_underscore}
directive and emits an error if the option @option{--underscore}
is in effect.
@end table
 
@item .arch ARGUMENT
@cindex assembler directive .arch, CRIS
@cindex pseudo-op .arch, CRIS
@cindex CRIS assembler directive .arch
@cindex CRIS pseudo-op .arch
This is an assertion directive, giving an error if the specified
@var{ARGUMENT} is not the same as the specified or default value
for the @option{--march=@var{architecture}} option
(@pxref{march-option}).
 
@c If you compare with md_pseudo_table, you see that we don't
@c document ".file" and ".loc" here. This is because we're just
@c wrapping the corresponding ELF function and emitting an error for
@c a.out.
@end table
/binutils/gas/doc/c-d10v.texi
0,0 → 1,264
@c Copyright 1996, 2000, 2002 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node D10V-Dependent
@chapter D10V Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter D10V Dependent Features
@end ifclear
 
@cindex D10V support
@menu
* D10V-Opts:: D10V Options
* D10V-Syntax:: Syntax
* D10V-Float:: Floating Point
* D10V-Opcodes:: Opcodes
@end menu
 
@node D10V-Opts
@section D10V Options
@cindex options, D10V
@cindex D10V options
The Mitsubishi D10V version of @code{@value{AS}} has a few machine
dependent options.
 
@table @samp
@item -O
The D10V can often execute two sub-instructions in parallel. When this option
is used, @code{@value{AS}} will attempt to optimize its output by detecting when
instructions can be executed in parallel.
@item --nowarnswap
To optimize execution performance, @code{@value{AS}} will sometimes swap the
order of instructions. Normally this generates a warning. When this option
is used, no warning will be generated when instructions are swapped.
@item --gstabs-packing
@itemx --no-gstabs-packing
@code{@value{AS}} packs adjacent short instructions into a single packed
instruction. @samp{--no-gstabs-packing} turns instruction packing off if
@samp{--gstabs} is specified as well; @samp{--gstabs-packing} (the
default) turns instruction packing on even when @samp{--gstabs} is
specified.
@end table
 
@node D10V-Syntax
@section Syntax
@cindex D10V syntax
@cindex syntax, D10V
 
The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual.
The differences are detailed below.
 
@menu
* D10V-Size:: Size Modifiers
* D10V-Subs:: Sub-Instructions
* D10V-Chars:: Special Characters
* D10V-Regs:: Register Names
* D10V-Addressing:: Addressing Modes
* D10V-Word:: @@WORD Modifier
@end menu
 
 
@node D10V-Size
@subsection Size Modifiers
@cindex D10V size modifiers
@cindex size modifiers, D10V
The D10V version of @code{@value{AS}} uses the instruction names in the D10V
Architecture Manual. However, the names in the manual are sometimes ambiguous.
There are instruction names that can assemble to a short or long form opcode.
How does the assembler pick the correct form? @code{@value{AS}} will always pick the
smallest form if it can. When dealing with a symbol that is not defined yet when a
line is being assembled, it will always use the long form. If you need to force the
assembler to use either the short or long form of the instruction, you can append
either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
an assembly program and you want to do a branch to a symbol that is defined later
in your program, you can write @samp{bra.s foo}.
Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
have both short and long forms.
 
@node D10V-Subs
@subsection Sub-Instructions
@cindex D10V sub-instructions
@cindex sub-instructions, D10V
The D10V assembler takes as input a series of instructions, either one-per-line,
or in the special two-per-line format described in the next section. Some of these
instructions will be short-form or sub-instructions. These sub-instructions can be packed
into a single instruction. The assembler will do this automatically. It will also detect
when it should not pack instructions. For example, when a label is defined, the next
instruction will never be packaged with the previous one. Whenever a branch and link
instruction is called, it will not be packaged with the next instruction so the return
address will be valid. Nops are automatically inserted when necessary.
 
If you do not want the assembler automatically making these decisions, you can control
the packaging and execution type (parallel or sequential) with the special execution
symbols described in the next section.
 
@node D10V-Chars
@subsection Special Characters
@cindex line comment character, D10V
@cindex D10V line comment character
A semicolon (@samp{;}) can be used anywhere on a line to start a
comment that extends to the end of the line.
 
If a @samp{#} appears as the first character of a line, the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex sub-instruction ordering, D10V
@cindex D10V sub-instruction ordering
Sub-instructions may be executed in order, in reverse-order, or in parallel.
Instructions listed in the standard one-per-line format will be executed sequentially.
To specify the executing order, use the following symbols:
@table @samp
@item ->
Sequential with instruction on the left first.
@item <-
Sequential with instruction on the right first.
@item ||
Parallel
@end table
The D10V syntax allows either one instruction per line, one instruction per line with
the execution symbol, or two instructions per line. For example
@table @code
@item abs a1 -> abs r0
Execute these sequentially. The instruction on the right is in the right
container and is executed second.
@item abs r0 <- abs a1
Execute these reverse-sequentially. The instruction on the right is in the right
container, and is executed first.
@item ld2w r2,@@r8+ || mac a0,r0,r7
Execute these in parallel.
@item ld2w r2,@@r8+ ||
@itemx mac a0,r0,r7
Two-line format. Execute these in parallel.
@item ld2w r2,@@r8+
@itemx mac a0,r0,r7
Two-line format. Execute these sequentially. Assembler will
put them in the proper containers.
@item ld2w r2,@@r8+ ->
@itemx mac a0,r0,r7
Two-line format. Execute these sequentially. Same as above but
second instruction will always go into right container.
@end table
@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
Since @samp{$} has no special meaning, you may use it in symbol names.
 
@node D10V-Regs
@subsection Register Names
@cindex D10V registers
@cindex registers, D10V
You can use the predefined symbols @samp{r0} through @samp{r15} to refer to the D10V
registers. You can also use @samp{sp} as an alias for @samp{r15}. The accumulators
are @samp{a0} and @samp{a1}. There are special register-pair names that may
optionally be used in opcodes that require even-numbered registers. Register names are
not case sensitive.
 
Register Pairs
@table @code
@item r0-r1
@item r2-r3
@item r4-r5
@item r6-r7
@item r8-r9
@item r10-r11
@item r12-r13
@item r14-r15
@end table
 
The D10V also has predefined symbols for these control registers and status bits:
@table @code
@item psw
Processor Status Word
@item bpsw
Backup Processor Status Word
@item pc
Program Counter
@item bpc
Backup Program Counter
@item rpt_c
Repeat Count
@item rpt_s
Repeat Start address
@item rpt_e
Repeat End address
@item mod_s
Modulo Start address
@item mod_e
Modulo End address
@item iba
Instruction Break Address
@item f0
Flag 0
@item f1
Flag 1
@item c
Carry flag
@end table
@node D10V-Addressing
@subsection Addressing Modes
@cindex addressing modes, D10V
@cindex D10V addressing modes
@code{@value{AS}} understands the following addressing modes for the D10V.
@code{R@var{n}} in the following refers to any of the numbered
registers, but @emph{not} the control registers.
@table @code
@item R@var{n}
Register direct
@item @@R@var{n}
Register indirect
@item @@R@var{n}+
Register indirect with post-increment
@item @@R@var{n}-
Register indirect with post-decrement
@item @@-SP
Register indirect with pre-decrement
@item @@(@var{disp}, R@var{n})
Register indirect with displacement
@item @var{addr}
PC relative address (for branch or rep).
@item #@var{imm}
Immediate data (the @samp{#} is optional and ignored)
@end table
 
@node D10V-Word
@subsection @@WORD Modifier
@cindex D10V @@word modifier
@cindex @@word modifier, D10V
Any symbol followed by @code{@@word} will be replaced by the symbol's value
shifted right by 2. This is used in situations such as loading a register
with the address of a function (or any other code fragment). For example, if
you want to load a register with the location of the function @code{main} then
jump to that function, you could do it as follows:
@smallexample
@group
ldi r2, main@@word
jmp r2
@end group
@end smallexample
 
@node D10V-Float
@section Floating Point
@cindex floating point, D10V
@cindex D10V floating point
The D10V has no hardware floating point, but the @code{.float} and @code{.double}
directives generates @sc{ieee} floating-point numbers for compatibility
with other development tools.
 
@node D10V-Opcodes
@section Opcodes
@cindex D10V opcode summary
@cindex opcode summary, D10V
@cindex mnemonics, D10V
@cindex instruction summary, D10V
For detailed information on the D10V machine instruction set, see
@cite{D10V Architecture: A VLIW Microprocessor for Multimedia Applications}
(Mitsubishi Electric Corp.).
@code{@value{AS}} implements all the standard D10V opcodes. The only changes are those
described in the section on size modifiers
 
/binutils/gas/doc/c-d30v.texi
0,0 → 1,299
@c Copyright (C) 1997, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node D30V-Dependent
@chapter D30V Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter D30V Dependent Features
@end ifclear
 
@cindex D30V support
@menu
* D30V-Opts:: D30V Options
* D30V-Syntax:: Syntax
* D30V-Float:: Floating Point
* D30V-Opcodes:: Opcodes
@end menu
 
@node D30V-Opts
@section D30V Options
@cindex options, D30V
@cindex D30V options
The Mitsubishi D30V version of @code{@value{AS}} has a few machine
dependent options.
 
@table @samp
@item -O
The D30V can often execute two sub-instructions in parallel. When this option
is used, @code{@value{AS}} will attempt to optimize its output by detecting when
instructions can be executed in parallel.
 
@item -n
When this option is used, @code{@value{AS}} will issue a warning every
time it adds a nop instruction.
 
@item -N
When this option is used, @code{@value{AS}} will issue a warning if it
needs to insert a nop after a 32-bit multiply before a load or 16-bit
multiply instruction.
@end table
 
@node D30V-Syntax
@section Syntax
@cindex D30V syntax
@cindex syntax, D30V
 
The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual.
The differences are detailed below.
 
@menu
* D30V-Size:: Size Modifiers
* D30V-Subs:: Sub-Instructions
* D30V-Chars:: Special Characters
* D30V-Guarded:: Guarded Execution
* D30V-Regs:: Register Names
* D30V-Addressing:: Addressing Modes
@end menu
 
 
@node D30V-Size
@subsection Size Modifiers
@cindex D30V size modifiers
@cindex size modifiers, D30V
The D30V version of @code{@value{AS}} uses the instruction names in the D30V
Architecture Manual. However, the names in the manual are sometimes ambiguous.
There are instruction names that can assemble to a short or long form opcode.
How does the assembler pick the correct form? @code{@value{AS}} will always pick the
smallest form if it can. When dealing with a symbol that is not defined yet when a
line is being assembled, it will always use the long form. If you need to force the
assembler to use either the short or long form of the instruction, you can append
either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing
an assembly program and you want to do a branch to a symbol that is defined later
in your program, you can write @samp{bra.s foo}.
Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which
have both short and long forms.
 
@node D30V-Subs
@subsection Sub-Instructions
@cindex D30V sub-instructions
@cindex sub-instructions, D30V
The D30V assembler takes as input a series of instructions, either one-per-line,
or in the special two-per-line format described in the next section. Some of these
instructions will be short-form or sub-instructions. These sub-instructions can be packed
into a single instruction. The assembler will do this automatically. It will also detect
when it should not pack instructions. For example, when a label is defined, the next
instruction will never be packaged with the previous one. Whenever a branch and link
instruction is called, it will not be packaged with the next instruction so the return
address will be valid. Nops are automatically inserted when necessary.
 
If you do not want the assembler automatically making these decisions, you can control
the packaging and execution type (parallel or sequential) with the special execution
symbols described in the next section.
 
@node D30V-Chars
@subsection Special Characters
@cindex line comment character, D30V
@cindex D30V line comment character
A semicolon (@samp{;}) can be used anywhere on a line to start a
comment that extends to the end of the line.
 
If a @samp{#} appears as the first character of a line, the whole line
is treated as a comment, but in this case the line could also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex sub-instruction ordering, D30V
@cindex D30V sub-instruction ordering
Sub-instructions may be executed in order, in reverse-order, or in parallel.
Instructions listed in the standard one-per-line format will be executed
sequentially unless you use the @samp{-O} option.
 
To specify the executing order, use the following symbols:
@table @samp
@item ->
Sequential with instruction on the left first.
 
@item <-
Sequential with instruction on the right first.
 
@item ||
Parallel
@end table
 
The D30V syntax allows either one instruction per line, one instruction per line with
the execution symbol, or two instructions per line. For example
@table @code
@item abs r2,r3 -> abs r4,r5
Execute these sequentially. The instruction on the right is in the right
container and is executed second.
 
@item abs r2,r3 <- abs r4,r5
Execute these reverse-sequentially. The instruction on the right is in the right
container, and is executed first.
 
@item abs r2,r3 || abs r4,r5
Execute these in parallel.
 
@item ldw r2,@@(r3,r4) ||
@itemx mulx r6,r8,r9
Two-line format. Execute these in parallel.
 
@item mulx a0,r8,r9
@itemx stw r2,@@(r3,r4)
Two-line format. Execute these sequentially unless @samp{-O} option is
used. If the @samp{-O} option is used, the assembler will determine if
the instructions could be done in parallel (the above two instructions
can be done in parallel), and if so, emit them as parallel instructions.
The assembler will put them in the proper containers. In the above
example, the assembler will put the @samp{stw} instruction in left
container and the @samp{mulx} instruction in the right container.
 
@item stw r2,@@(r3,r4) ->
@itemx mulx a0,r8,r9
Two-line format. Execute the @samp{stw} instruction followed by the
@samp{mulx} instruction sequentially. The first instruction goes in the
left container and the second instruction goes into right container.
The assembler will give an error if the machine ordering constraints are
violated.
 
@item stw r2,@@(r3,r4) <-
@itemx mulx a0,r8,r9
Same as previous example, except that the @samp{mulx} instruction is
executed before the @samp{stw} instruction.
@end table
 
@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
Since @samp{$} has no special meaning, you may use it in symbol names.
 
@node D30V-Guarded
@subsection Guarded Execution
@cindex D30V Guarded Execution
@code{@value{AS}} supports the full range of guarded execution
directives for each instruction. Just append the directive after the
instruction proper. The directives are:
 
@table @samp
@item /tx
Execute the instruction if flag f0 is true.
@item /fx
Execute the instruction if flag f0 is false.
@item /xt
Execute the instruction if flag f1 is true.
@item /xf
Execute the instruction if flag f1 is false.
@item /tt
Execute the instruction if both flags f0 and f1 are true.
@item /tf
Execute the instruction if flag f0 is true and flag f1 is false.
@end table
 
@node D30V-Regs
@subsection Register Names
@cindex D30V registers
@cindex registers, D30V
You can use the predefined symbols @samp{r0} through @samp{r63} to refer
to the D30V registers. You can also use @samp{sp} as an alias for
@samp{r63} and @samp{link} as an alias for @samp{r62}. The accumulators
are @samp{a0} and @samp{a1}.
 
The D30V also has predefined symbols for these control registers and status bits:
@table @code
@item psw
Processor Status Word
@item bpsw
Backup Processor Status Word
@item pc
Program Counter
@item bpc
Backup Program Counter
@item rpt_c
Repeat Count
@item rpt_s
Repeat Start address
@item rpt_e
Repeat End address
@item mod_s
Modulo Start address
@item mod_e
Modulo End address
@item iba
Instruction Break Address
@item f0
Flag 0
@item f1
Flag 1
@item f2
Flag 2
@item f3
Flag 3
@item f4
Flag 4
@item f5
Flag 5
@item f6
Flag 6
@item f7
Flag 7
@item s
Same as flag 4 (saturation flag)
@item v
Same as flag 5 (overflow flag)
@item va
Same as flag 6 (sticky overflow flag)
@item c
Same as flag 7 (carry/borrow flag)
@item b
Same as flag 7 (carry/borrow flag)
@end table
@node D30V-Addressing
@subsection Addressing Modes
@cindex addressing modes, D30V
@cindex D30V addressing modes
@code{@value{AS}} understands the following addressing modes for the D30V.
@code{R@var{n}} in the following refers to any of the numbered
registers, but @emph{not} the control registers.
@table @code
@item R@var{n}
Register direct
@item @@R@var{n}
Register indirect
@item @@R@var{n}+
Register indirect with post-increment
@item @@R@var{n}-
Register indirect with post-decrement
@item @@-SP
Register indirect with pre-decrement
@item @@(@var{disp}, R@var{n})
Register indirect with displacement
@item @var{addr}
PC relative address (for branch or rep).
@item #@var{imm}
Immediate data (the @samp{#} is optional and ignored)
@end table
 
@node D30V-Float
@section Floating Point
@cindex floating point, D30V
@cindex D30V floating point
The D30V has no hardware floating point, but the @code{.float} and @code{.double}
directives generates @sc{ieee} floating-point numbers for compatibility
with other development tools.
 
@node D30V-Opcodes
@section Opcodes
@cindex D30V opcode summary
@cindex opcode summary, D30V
@cindex mnemonics, D30V
@cindex instruction summary, D30V
For detailed information on the D30V machine instruction set, see
@cite{D30V Architecture: A VLIW Microprocessor for Multimedia Applications}
(Mitsubishi Electric Corp.).
@code{@value{AS}} implements all the standard D30V opcodes. The only changes are those
described in the section on size modifiers
 
/binutils/gas/doc/c-h8300.texi
0,0 → 1,363
@c Copyright (C) 1991, 1992, 1993, 1994, 1995, 2003, 2008, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@end ifset
@node H8/300-Dependent
@chapter H8/300 Dependent Features
 
@cindex H8/300 support
@menu
* H8/300 Options:: Options
* H8/300 Syntax:: Syntax
* H8/300 Floating Point:: Floating Point
* H8/300 Directives:: H8/300 Machine Directives
* H8/300 Opcodes:: Opcodes
@end menu
 
@node H8/300 Options
@section Options
 
@cindex H8/300 options
@cindex options, H8/300
The Renesas H8/300 version of @code{@value{AS}} has one
machine-dependent option:
 
@table @code
@item -h-tick-hex
Support H'00 style hex constants in addition to 0x00 style.
 
@end table
 
@node H8/300 Syntax
@section Syntax
@menu
* H8/300-Chars:: Special Characters
* H8/300-Regs:: Register Names
* H8/300-Addressing:: Addressing Modes
@end menu
 
@node H8/300-Chars
@subsection Special Characters
 
@cindex line comment character, H8/300
@cindex H8/300 line comment character
@samp{;} is the line comment character.
 
@cindex line separator, H8/300
@cindex statement separator, H8/300
@cindex H8/300 line separator
@samp{$} can be used instead of a newline to separate statements.
Therefore @emph{you may not use @samp{$} in symbol names} on the H8/300.
 
@node H8/300-Regs
@subsection Register Names
 
@cindex H8/300 registers
@cindex register names, H8/300
You can use predefined symbols of the form @samp{r@var{n}h} and
@samp{r@var{n}l} to refer to the H8/300 registers as sixteen 8-bit
general-purpose registers. @var{n} is a digit from @samp{0} to
@samp{7}); for instance, both @samp{r0h} and @samp{r7l} are valid
register names.
 
You can also use the eight predefined symbols @samp{r@var{n}} to refer
to the H8/300 registers as 16-bit registers (you must use this form for
addressing).
 
On the H8/300H, you can also use the eight predefined symbols
@samp{er@var{n}} (@samp{er0} @dots{} @samp{er7}) to refer to the 32-bit
general purpose registers.
 
The two control registers are called @code{pc} (program counter; a
16-bit register, except on the H8/300H where it is 24 bits) and
@code{ccr} (condition code register; an 8-bit register). @code{r7} is
used as the stack pointer, and can also be called @code{sp}.
 
@node H8/300-Addressing
@subsection Addressing Modes
 
@cindex addressing modes, H8/300
@cindex H8/300 addressing modes
@value{AS} understands the following addressing modes for the H8/300:
@table @code
@item r@var{n}
Register direct
 
@item @@r@var{n}
Register indirect
 
@need 1200
@item @@(@var{d}, r@var{n})
@itemx @@(@var{d}:16, r@var{n})
@itemx @@(@var{d}:24, r@var{n})
Register indirect: 16-bit or 24-bit displacement @var{d} from register
@var{n}. (24-bit displacements are only meaningful on the H8/300H.)
 
@item @@r@var{n}+
Register indirect with post-increment
 
@item @@-r@var{n}
Register indirect with pre-decrement
 
@item @code{@@}@var{aa}
@itemx @code{@@}@var{aa}:8
@itemx @code{@@}@var{aa}:16
@itemx @code{@@}@var{aa}:24
Absolute address @code{aa}. (The address size @samp{:24} only makes
sense on the H8/300H.)
 
@item #@var{xx}
@itemx #@var{xx}:8
@itemx #@var{xx}:16
@itemx #@var{xx}:32
Immediate data @var{xx}. You may specify the @samp{:8}, @samp{:16}, or
@samp{:32} for clarity, if you wish; but @code{@value{AS}} neither
requires this nor uses it---the data size required is taken from
context.
 
@item @code{@@}@code{@@}@var{aa}
@itemx @code{@@}@code{@@}@var{aa}:8
Memory indirect. You may specify the @samp{:8} for clarity, if you
wish; but @code{@value{AS}} neither requires this nor uses it.
@end table
 
@node H8/300 Floating Point
@section Floating Point
 
@cindex floating point, H8/300 (@sc{ieee})
@cindex H8/300 floating point (@sc{ieee})
The H8/300 family has no hardware floating point, but the @code{.float}
directive generates @sc{ieee} floating-point numbers for compatibility
with other development tools.
 
@page
@node H8/300 Directives
@section H8/300 Machine Directives
 
@cindex H8/300 machine directives (none)
@cindex machine directives, H8/300 (none)
@cindex @code{word} directive, H8/300
@cindex @code{int} directive, H8/300
@code{@value{AS}} has the following machine-dependent directives for
the H8/300:
 
@table @code
@cindex H8/300H, assembling for
@item .h8300h
Recognize and emit additional instructions for the H8/300H variant, and
also make @code{.int} emit 32-bit numbers rather than the usual (16-bit)
for the H8/300 family.
 
@item .h8300s
Recognize and emit additional instructions for the H8S variant, and
also make @code{.int} emit 32-bit numbers rather than the usual (16-bit)
for the H8/300 family.
 
@item .h8300hn
Recognize and emit additional instructions for the H8/300H variant in
normal mode, and also make @code{.int} emit 32-bit numbers rather than
the usual (16-bit) for the H8/300 family.
 
@item .h8300sn
Recognize and emit additional instructions for the H8S variant in
normal mode, and also make @code{.int} emit 32-bit numbers rather than
the usual (16-bit) for the H8/300 family.
@end table
 
On the H8/300 family (including the H8/300H) @samp{.word} directives
generate 16-bit numbers.
 
@node H8/300 Opcodes
@section Opcodes
 
@cindex H8/300 opcode summary
@cindex opcode summary, H8/300
@cindex mnemonics, H8/300
@cindex instruction summary, H8/300
For detailed information on the H8/300 machine instruction set, see
@cite{H8/300 Series Programming Manual}. For information specific to
the H8/300H, see @cite{H8/300H Series Programming Manual} (Renesas).
 
@code{@value{AS}} implements all the standard H8/300 opcodes. No additional
pseudo-instructions are needed on this family.
 
@ifset SMALL
@c this table, due to the multi-col faking and hardcoded order, looks silly
@c except in smallbook. See comments below "@set SMALL" near top of this file.
 
The following table summarizes the H8/300 opcodes, and their arguments.
Entries marked @samp{*} are opcodes used only on the H8/300H.
 
@smallexample
@c Using @group seems to use the normal baselineskip, not the smallexample
@c baselineskip; looks approx doublespaced.
@i{Legend:}
Rs @r{source register}
Rd @r{destination register}
abs @r{absolute address}
imm @r{immediate data}
disp:N @r{N-bit displacement from a register}
pcrel:N @r{N-bit displacement relative to program counter}
 
add.b #imm,rd * andc #imm,ccr
add.b rs,rd band #imm,rd
add.w rs,rd band #imm,@@rd
* add.w #imm,rd band #imm,@@abs:8
* add.l rs,rd bra pcrel:8
* add.l #imm,rd * bra pcrel:16
adds #imm,rd bt pcrel:8
addx #imm,rd * bt pcrel:16
addx rs,rd brn pcrel:8
and.b #imm,rd * brn pcrel:16
and.b rs,rd bf pcrel:8
* and.w rs,rd * bf pcrel:16
* and.w #imm,rd bhi pcrel:8
* and.l #imm,rd * bhi pcrel:16
* and.l rs,rd bls pcrel:8
@page
* bls pcrel:16 bld #imm,rd
bcc pcrel:8 bld #imm,@@rd
* bcc pcrel:16 bld #imm,@@abs:8
bhs pcrel:8 bnot #imm,rd
* bhs pcrel:16 bnot #imm,@@rd
bcs pcrel:8 bnot #imm,@@abs:8
* bcs pcrel:16 bnot rs,rd
blo pcrel:8 bnot rs,@@rd
* blo pcrel:16 bnot rs,@@abs:8
bne pcrel:8 bor #imm,rd
* bne pcrel:16 bor #imm,@@rd
beq pcrel:8 bor #imm,@@abs:8
* beq pcrel:16 bset #imm,rd
bvc pcrel:8 bset #imm,@@rd
* bvc pcrel:16 bset #imm,@@abs:8
bvs pcrel:8 bset rs,rd
* bvs pcrel:16 bset rs,@@rd
bpl pcrel:8 bset rs,@@abs:8
* bpl pcrel:16 bsr pcrel:8
bmi pcrel:8 bsr pcrel:16
* bmi pcrel:16 bst #imm,rd
bge pcrel:8 bst #imm,@@rd
* bge pcrel:16 bst #imm,@@abs:8
blt pcrel:8 btst #imm,rd
* blt pcrel:16 btst #imm,@@rd
bgt pcrel:8 btst #imm,@@abs:8
* bgt pcrel:16 btst rs,rd
ble pcrel:8 btst rs,@@rd
* ble pcrel:16 btst rs,@@abs:8
bclr #imm,rd bxor #imm,rd
bclr #imm,@@rd bxor #imm,@@rd
bclr #imm,@@abs:8 bxor #imm,@@abs:8
bclr rs,rd cmp.b #imm,rd
bclr rs,@@rd cmp.b rs,rd
bclr rs,@@abs:8 cmp.w rs,rd
biand #imm,rd cmp.w rs,rd
biand #imm,@@rd * cmp.w #imm,rd
biand #imm,@@abs:8 * cmp.l #imm,rd
bild #imm,rd * cmp.l rs,rd
bild #imm,@@rd daa rs
bild #imm,@@abs:8 das rs
bior #imm,rd dec.b rs
bior #imm,@@rd * dec.w #imm,rd
bior #imm,@@abs:8 * dec.l #imm,rd
bist #imm,rd divxu.b rs,rd
bist #imm,@@rd * divxu.w rs,rd
bist #imm,@@abs:8 * divxs.b rs,rd
bixor #imm,rd * divxs.w rs,rd
bixor #imm,@@rd eepmov
bixor #imm,@@abs:8 * eepmovw
@page
* exts.w rd mov.w rs,@@abs:16
* exts.l rd * mov.l #imm,rd
* extu.w rd * mov.l rs,rd
* extu.l rd * mov.l @@rs,rd
inc rs * mov.l @@(disp:16,rs),rd
* inc.w #imm,rd * mov.l @@(disp:24,rs),rd
* inc.l #imm,rd * mov.l @@rs+,rd
jmp @@rs * mov.l @@abs:16,rd
jmp abs * mov.l @@abs:24,rd
jmp @@@@abs:8 * mov.l rs,@@rd
jsr @@rs * mov.l rs,@@(disp:16,rd)
jsr abs * mov.l rs,@@(disp:24,rd)
jsr @@@@abs:8 * mov.l rs,@@-rd
ldc #imm,ccr * mov.l rs,@@abs:16
ldc rs,ccr * mov.l rs,@@abs:24
* ldc @@abs:16,ccr movfpe @@abs:16,rd
* ldc @@abs:24,ccr movtpe rs,@@abs:16
* ldc @@(disp:16,rs),ccr mulxu.b rs,rd
* ldc @@(disp:24,rs),ccr * mulxu.w rs,rd
* ldc @@rs+,ccr * mulxs.b rs,rd
* ldc @@rs,ccr * mulxs.w rs,rd
* mov.b @@(disp:24,rs),rd neg.b rs
* mov.b rs,@@(disp:24,rd) * neg.w rs
mov.b @@abs:16,rd * neg.l rs
mov.b rs,rd nop
mov.b @@abs:8,rd not.b rs
mov.b rs,@@abs:8 * not.w rs
mov.b rs,rd * not.l rs
mov.b #imm,rd or.b #imm,rd
mov.b @@rs,rd or.b rs,rd
mov.b @@(disp:16,rs),rd * or.w #imm,rd
mov.b @@rs+,rd * or.w rs,rd
mov.b @@abs:8,rd * or.l #imm,rd
mov.b rs,@@rd * or.l rs,rd
mov.b rs,@@(disp:16,rd) orc #imm,ccr
mov.b rs,@@-rd pop.w rs
mov.b rs,@@abs:8 * pop.l rs
mov.w rs,@@rd push.w rs
* mov.w @@(disp:24,rs),rd * push.l rs
* mov.w rs,@@(disp:24,rd) rotl.b rs
* mov.w @@abs:24,rd * rotl.w rs
* mov.w rs,@@abs:24 * rotl.l rs
mov.w rs,rd rotr.b rs
mov.w #imm,rd * rotr.w rs
mov.w @@rs,rd * rotr.l rs
mov.w @@(disp:16,rs),rd rotxl.b rs
mov.w @@rs+,rd * rotxl.w rs
mov.w @@abs:16,rd * rotxl.l rs
mov.w rs,@@(disp:16,rd) rotxr.b rs
mov.w rs,@@-rd * rotxr.w rs
@page
* rotxr.l rs * stc ccr,@@(disp:24,rd)
bpt * stc ccr,@@-rd
rte * stc ccr,@@abs:16
rts * stc ccr,@@abs:24
shal.b rs sub.b rs,rd
* shal.w rs sub.w rs,rd
* shal.l rs * sub.w #imm,rd
shar.b rs * sub.l rs,rd
* shar.w rs * sub.l #imm,rd
* shar.l rs subs #imm,rd
shll.b rs subx #imm,rd
* shll.w rs subx rs,rd
* shll.l rs * trapa #imm
shlr.b rs xor #imm,rd
* shlr.w rs xor rs,rd
* shlr.l rs * xor.w #imm,rd
sleep * xor.w rs,rd
stc ccr,rd * xor.l #imm,rd
* stc ccr,@@rs * xor.l rs,rd
* stc ccr,@@(disp:16,rd) xorc #imm,ccr
@end smallexample
@end ifset
 
@cindex size suffixes, H8/300
@cindex H8/300 size suffixes
Four H8/300 instructions (@code{add}, @code{cmp}, @code{mov},
@code{sub}) are defined with variants using the suffixes @samp{.b},
@samp{.w}, and @samp{.l} to specify the size of a memory operand.
@code{@value{AS}} supports these suffixes, but does not require them;
since one of the operands is always a register, @code{@value{AS}} can
deduce the correct size.
 
For example, since @code{r0} refers to a 16-bit register,
@example
mov r0,@@foo
@exdent is equivalent to
mov.w r0,@@foo
@end example
 
If you use the size suffixes, @code{@value{AS}} issues a warning when
the suffix and the register size do not match.
/binutils/gas/doc/c-hppa.texi
0,0 → 1,301
@c Copyright 1991, 1992, 1993, 1994, 1995, 1998, 2004, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node HPPA-Dependent
@chapter HPPA Dependent Features
 
@cindex support
@menu
* HPPA Notes:: Notes
* HPPA Options:: Options
* HPPA Syntax:: Syntax
* HPPA Floating Point:: Floating Point
* HPPA Directives:: HPPA Machine Directives
* HPPA Opcodes:: Opcodes
@end menu
 
@node HPPA Notes
@section Notes
As a back end for @sc{gnu} @sc{cc} @code{@value{AS}} has been throughly tested and should
work extremely well. We have tested it only minimally on hand written assembly
code and no one has tested it much on the assembly output from the HP
compilers.
 
The format of the debugging sections has changed since the original
@code{@value{AS}} port (version 1.3X) was released; therefore,
you must rebuild all HPPA objects and libraries with the new
assembler so that you can debug the final executable.
 
The HPPA @code{@value{AS}} port generates a small subset of the relocations
available in the SOM and ELF object file formats. Additional relocation
support will be added as it becomes necessary.
 
@node HPPA Options
@section Options
@code{@value{AS}} has no machine-dependent command-line options for the HPPA.
 
@cindex HPPA Syntax
@node HPPA Syntax
@section Syntax
The assembler syntax closely follows the HPPA instruction set
reference manual; assembler directives and general syntax closely follow the
HPPA assembly language reference manual, with a few noteworthy differences.
 
First, a colon may immediately follow a label definition. This is
simply for compatibility with how most assembly language programmers
write code.
 
Some obscure expression parsing problems may affect hand written code which
uses the @code{spop} instructions, or code which makes significant
use of the @code{!} line separator.
 
@code{@value{AS}} is much less forgiving about missing arguments and other
similar oversights than the HP assembler. @code{@value{AS}} notifies you
of missing arguments as syntax errors; this is regarded as a feature, not a
bug.
 
Finally, @code{@value{AS}} allows you to use an external symbol without
explicitly importing the symbol. @emph{Warning:} in the future this will be
an error for HPPA targets.
 
Special characters for HPPA targets include:
 
@samp{;} is the line comment character.
 
@samp{!} can be used instead of a newline to separate statements.
 
Since @samp{$} has no special meaning, you may use it in symbol names.
 
@node HPPA Floating Point
@section Floating Point
@cindex floating point, HPPA (@sc{ieee})
@cindex HPPA floating point (@sc{ieee})
The HPPA family uses @sc{ieee} floating-point numbers.
 
@node HPPA Directives
@section HPPA Assembler Directives
 
@code{@value{AS}} for the HPPA supports many additional directives for
compatibility with the native assembler. This section describes them only
briefly. For detailed information on HPPA-specific assembler directives, see
@cite{HP9000 Series 800 Assembly Language Reference Manual} (HP 92432-90001).
 
@cindex HPPA directives not supported
@code{@value{AS}} does @emph{not} support the following assembler directives
described in the HP manual:
 
@example
.endm .liston
.enter .locct
.leave .macro
.listoff
@end example
 
@cindex @code{.param} on HPPA
Beyond those implemented for compatibility, @code{@value{AS}} supports one
additional assembler directive for the HPPA: @code{.param}. It conveys
register argument locations for static functions. Its syntax closely follows
the @code{.export} directive.
 
@cindex HPPA-only directives
These are the additional directives in @code{@value{AS}} for the HPPA:
 
@table @code
@item .block @var{n}
@itemx .blockz @var{n}
Reserve @var{n} bytes of storage, and initialize them to zero.
 
@item .call
Mark the beginning of a procedure call. Only the special case with @emph{no
arguments} is allowed.
 
@item .callinfo [ @var{param}=@var{value}, @dots{} ] [ @var{flag}, @dots{} ]
Specify a number of parameters and flags that define the environment for a
procedure.
 
@var{param} may be any of @samp{frame} (frame size), @samp{entry_gr} (end of
general register range), @samp{entry_fr} (end of float register range),
@samp{entry_sr} (end of space register range).
 
The values for @var{flag} are @samp{calls} or @samp{caller} (proc has
subroutines), @samp{no_calls} (proc does not call subroutines), @samp{save_rp}
(preserve return pointer), @samp{save_sp} (proc preserves stack pointer),
@samp{no_unwind} (do not unwind this proc), @samp{hpux_int} (proc is interrupt
routine).
 
@item .code
Assemble into the standard section called @samp{$TEXT$}, subsection
@samp{$CODE$}.
 
@ifset SOM
@item .copyright "@var{string}"
In the SOM object format, insert @var{string} into the object code, marked as a
copyright string.
@end ifset
 
@ifset ELF
@item .copyright "@var{string}"
In the ELF object format, insert @var{string} into the object code, marked as a
version string.
@end ifset
 
@item .enter
Not yet supported; the assembler rejects programs containing this directive.
 
@item .entry
Mark the beginning of a procedure.
 
@item .exit
Mark the end of a procedure.
 
@item .export @var{name} [ ,@var{typ} ] [ ,@var{param}=@var{r} ]
Make a procedure @var{name} available to callers. @var{typ}, if present, must
be one of @samp{absolute}, @samp{code} (ELF only, not SOM), @samp{data},
@samp{entry}, @samp{data}, @samp{entry}, @samp{millicode}, @samp{plabel},
@samp{pri_prog}, or @samp{sec_prog}.
 
@var{param}, if present, provides either relocation information for the
procedure arguments and result, or a privilege level. @var{param} may be
@samp{argw@var{n}} (where @var{n} ranges from @code{0} to @code{3}, and
indicates one of four one-word arguments); @samp{rtnval} (the procedure's
result); or @samp{priv_lev} (privilege level). For arguments or the result,
@var{r} specifies how to relocate, and must be one of @samp{no} (not
relocatable), @samp{gr} (argument is in general register), @samp{fr} (in
floating point register), or @samp{fu} (upper half of float register).
For @samp{priv_lev}, @var{r} is an integer.
 
@item .half @var{n}
Define a two-byte integer constant @var{n}; synonym for the portable
@code{@value{AS}} directive @code{.short}.
 
@item .import @var{name} [ ,@var{typ} ]
Converse of @code{.export}; make a procedure available to call. The arguments
use the same conventions as the first two arguments for @code{.export}.
 
@item .label @var{name}
Define @var{name} as a label for the current assembly location.
 
@item .leave
Not yet supported; the assembler rejects programs containing this directive.
 
@item .origin @var{lc}
Advance location counter to @var{lc}. Synonym for the @code{@value{AS}}
portable directive @code{.org}.
 
@item .param @var{name} [ ,@var{typ} ] [ ,@var{param}=@var{r} ]
@c Not in HP manual; @sc{gnu} HPPA extension
Similar to @code{.export}, but used for static procedures.
 
@item .proc
Use preceding the first statement of a procedure.
 
@item .procend
Use following the last statement of a procedure.
 
@item @var{label} .reg @var{expr}
@c ?? Not in HP manual (Jan 1988 vn)
Synonym for @code{.equ}; define @var{label} with the absolute expression
@var{expr} as its value.
 
@item .space @var{secname} [ ,@var{params} ]
Switch to section @var{secname}, creating a new section by that name if
necessary. You may only use @var{params} when creating a new section, not
when switching to an existing one. @var{secname} may identify a section by
number rather than by name.
 
If specified, the list @var{params} declares attributes of the section,
identified by keywords. The keywords recognized are @samp{spnum=@var{exp}}
(identify this section by the number @var{exp}, an absolute expression),
@samp{sort=@var{exp}} (order sections according to this sort key when linking;
@var{exp} is an absolute expression), @samp{unloadable} (section contains no
loadable data), @samp{notdefined} (this section defined elsewhere), and
@samp{private} (data in this section not available to other programs).
 
@item .spnum @var{secnam}
@c ?? Not in HP manual (Jan 1988)
Allocate four bytes of storage, and initialize them with the section number of
the section named @var{secnam}. (You can define the section number with the
HPPA @code{.space} directive.)
 
@cindex @code{string} directive on HPPA
@item .string "@var{str}"
Copy the characters in the string @var{str} to the object file.
@xref{Strings,,Strings}, for information on escape sequences you can use in
@code{@value{AS}} strings.
 
@emph{Warning!} The HPPA version of @code{.string} differs from the
usual @code{@value{AS}} definition: it does @emph{not} write a zero byte
after copying @var{str}.
 
@item .stringz "@var{str}"
Like @code{.string}, but appends a zero byte after copying @var{str} to object
file.
 
@item .subspa @var{name} [ ,@var{params} ]
@itemx .nsubspa @var{name} [ ,@var{params} ]
Similar to @code{.space}, but selects a subsection @var{name} within the
current section. You may only specify @var{params} when you create a
subsection (in the first instance of @code{.subspa} for this @var{name}).
 
If specified, the list @var{params} declares attributes of the subsection,
identified by keywords. The keywords recognized are @samp{quad=@var{expr}}
(``quadrant'' for this subsection), @samp{align=@var{expr}} (alignment for
beginning of this subsection; a power of two), @samp{access=@var{expr}} (value
for ``access rights'' field), @samp{sort=@var{expr}} (sorting order for this
subspace in link), @samp{code_only} (subsection contains only code),
@samp{unloadable} (subsection cannot be loaded into memory), @samp{comdat}
(subsection is comdat), @samp{common} (subsection is common block),
@samp{dup_comm} (subsection may have duplicate names), or @samp{zero}
(subsection is all zeros, do not write in object file).
 
@code{.nsubspa} always creates a new subspace with the given name, even
if one with the same name already exists.
 
@samp{comdat}, @samp{common} and @samp{dup_comm} can be used to implement
various flavors of one-only support when using the SOM linker. The SOM
linker only supports specific combinations of these flags. The details
are not documented. A brief description is provided here.
 
@samp{comdat} provides a form of linkonce support. It is useful for
both code and data subspaces. A @samp{comdat} subspace has a key symbol
marked by the @samp{is_comdat} flag or @samp{ST_COMDAT}. Only the first
subspace for any given key is selected. The key symbol becomes universal
in shared links. This is similar to the behavior of @samp{secondary_def}
symbols.
 
@samp{common} provides Fortran named common support. It is only useful
for data subspaces. Symbols with the flag @samp{is_common} retain this
flag in shared links. Referencing a @samp{is_common} symbol in a shared
library from outside the library doesn't work. Thus, @samp{is_common}
symbols must be output whenever they are needed.
 
@samp{common} and @samp{dup_comm} together provide Cobol common support.
The subspaces in this case must all be the same length. Otherwise, this
support is similar to the Fortran common support.
 
@samp{dup_comm} by itself provides a type of one-only support for code.
Only the first @samp{dup_comm} subspace is selected. There is a rather
complex algorithm to compare subspaces. Code symbols marked with the
@samp{dup_common} flag are hidden. This support was intended for "C++
duplicate inlines".
 
A simplified technique is used to mark the flags of symbols based on
the flags of their subspace. A symbol with the scope SS_UNIVERSAL and
type ST_ENTRY, ST_CODE or ST_DATA is marked with the corresponding
settings of @samp{comdat}, @samp{common} and @samp{dup_comm} from the
subspace, respectively. This avoids having to introduce additional
directives to mark these symbols. The HP assembler sets @samp{is_common}
from @samp{common}. However, it doesn't set the @samp{dup_common} from
@samp{dup_comm}. It doesn't have @samp{comdat} support.
 
@item .version "@var{str}"
Write @var{str} as version identifier in object code.
@end table
 
@node HPPA Opcodes
@section Opcodes
For detailed information on the HPPA machine instruction set, see
@cite{PA-RISC Architecture and Instruction Set Reference Manual}
(HP 09740-90039).
/binutils/gas/doc/c-i370.texi
0,0 → 1,200
@c Copyright 2000, 2002 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node ESA/390-Dependent
@chapter ESA/390 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter ESA/390 Dependent Features
@end ifclear
 
@cindex i370 support
@cindex ESA/390 support
 
@menu
* ESA/390 Notes:: Notes
* ESA/390 Options:: Options
* ESA/390 Syntax:: Syntax
* ESA/390 Floating Point:: Floating Point
* ESA/390 Directives:: ESA/390 Machine Directives
* ESA/390 Opcodes:: Opcodes
@end menu
 
@node ESA/390 Notes
@section Notes
The ESA/390 @code{@value{AS}} port is currently intended to be a back-end
for the @sc{gnu} @sc{cc} compiler. It is not HLASM compatible, although
it does support a subset of some of the HLASM directives. The only
supported binary file format is ELF; none of the usual MVS/VM/OE/USS
object file formats, such as ESD or XSD, are supported.
 
When used with the @sc{gnu} @sc{cc} compiler, the ESA/390 @code{@value{AS}}
will produce correct, fully relocated, functional binaries, and has been
used to compile and execute large projects. However, many aspects should
still be considered experimental; these include shared library support,
dynamically loadable objects, and any relocation other than the 31-bit
relocation.
 
@node ESA/390 Options
@section Options
@code{@value{AS}} has no machine-dependent command-line options for the ESA/390.
 
@cindex ESA/390 Syntax
@node ESA/390 Syntax
@section Syntax
The opcode/operand syntax follows the ESA/390 Principles of Operation
manual; assembler directives and general syntax are loosely based on the
prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives
are @emph{not} supported for the most part, with the exception of those
described herein.
 
A leading dot in front of directives is optional, and the case of
directives is ignored; thus for example, .using and USING have the same
effect.
 
A colon may immediately follow a label definition. This is
simply for compatibility with how most assembly language programmers
write code.
 
@samp{#} is the line comment character.
 
@samp{;} can be used instead of a newline to separate statements.
 
Since @samp{$} has no special meaning, you may use it in symbol names.
 
Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6.
By using thesse symbolic names, @code{@value{AS}} can detect simple
syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca
for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
for r3 and rpgt or r.pgt for r4.
 
@samp{*} is the current location counter. Unlike @samp{.} it is always
relative to the last USING directive. Note that this means that
expressions cannot use multiplication, as any occurrence of @samp{*}
will be interpreted as a location counter.
 
All labels are relative to the last USING. Thus, branches to a label
always imply the use of base+displacement.
 
Many of the usual forms of address constants / address literals
are supported. Thus,
@example
.using *,r3
L r15,=A(some_routine)
LM r6,r7,=V(some_longlong_extern)
A r1,=F'12'
AH r0,=H'42'
ME r6,=E'3.1416'
MD r6,=D'3.14159265358979'
O r6,=XL4'cacad0d0'
.ltorg
@end example
should all behave as expected: that is, an entry in the literal
pool will be created (or reused if it already exists), and the
instruction operands will be the displacement into the literal pool
using the current base register (as last declared with the @code{.using}
directive).
 
@node ESA/390 Floating Point
@section Floating Point
@cindex floating point, ESA/390 (@sc{ieee})
@cindex ESA/390 floating point (@sc{ieee})
The assembler generates only @sc{ieee} floating-point numbers. The older
floating point formats are not supported.
 
 
@node ESA/390 Directives
@section ESA/390 Assembler Directives
 
@code{@value{AS}} for the ESA/390 supports all of the standard ELF/SVR4
assembler directives that are documented in the main part of this
documentation. Several additional directives are supported in order
to implement the ESA/390 addressing model. The most important of these
are @code{.using} and @code{.ltorg}
 
@cindex ESA/390-only directives
These are the additional directives in @code{@value{AS}} for the ESA/390:
 
@table @code
@item .dc
A small subset of the usual DC directive is supported.
 
@item .drop @var{regno}
Stop using @var{regno} as the base register. The @var{regno} must
have been previously declared with a @code{.using} directive in the
same section as the current section.
 
@item .ebcdic @var{string}
Emit the EBCDIC equivalent of the indicated string. The emitted string
will be null terminated. Note that the directives @code{.string} etc. emit
ascii strings by default.
 
@item EQU
The standard HLASM-style EQU directive is not supported; however, the
standard @code{@value{AS}} directive .equ can be used to the same effect.
 
@item .ltorg
Dump the literal pool accumulated so far; begin a new literal pool.
The literal pool will be written in the current section; in order to
generate correct assembly, a @code{.using} must have been previously
specified in the same section.
 
@item .using @var{expr},@var{regno}
Use @var{regno} as the base register for all subsequent RX, RS, and SS form
instructions. The @var{expr} will be evaluated to obtain the base address;
usually, @var{expr} will merely be @samp{*}.
 
This assembler allows two @code{.using} directives to be simultaneously
outstanding, one in the @code{.text} section, and one in another section
(typically, the @code{.data} section). This feature allows
dynamically loaded objects to be implemented in a relatively
straightforward way. A @code{.using} directive must always be specified
in the @code{.text} section; this will specify the base register that
will be used for branches in the @code{.text} section. A second
@code{.using} may be specified in another section; this will specify
the base register that is used for non-label address literals.
When a second @code{.using} is specified, then the subsequent
@code{.ltorg} must be put in the same section; otherwise an error will
result.
 
Thus, for example, the following code uses @code{r3} to address branch
targets and @code{r4} to address the literal pool, which has been written
to the @code{.data} section. The is, the constants @code{=A(some_routine)},
@code{=H'42'} and @code{=E'3.1416'} will all appear in the @code{.data}
section.
 
@example
.data
.using LITPOOL,r4
.text
BASR r3,0
.using *,r3
B START
.long LITPOOL
START:
L r4,4(,r3)
L r15,=A(some_routine)
LTR r15,r15
BNE LABEL
AH r0,=H'42'
LABEL:
ME r6,=E'3.1416'
.data
LITPOOL:
.ltorg
@end example
 
 
Note that this dual-@code{.using} directive semantics extends
and is not compatible with HLASM semantics. Note that this assembler
directive does not support the full range of HLASM semantics.
 
@end table
 
@node ESA/390 Opcodes
@section Opcodes
For detailed information on the ESA/390 machine instruction set, see
@cite{ESA/390 Principles of Operation} (IBM Publication Number DZ9AR004).
/binutils/gas/doc/c-i860.texi
0,0 → 1,197
@c Copyright 2000, 2003, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node i860-Dependent
@chapter Intel i860 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter Intel i860 Dependent Features
@end ifclear
 
@ignore
@c FIXME: This is basically a stub for i860. There is tons more information
that I will add later (jle@cygnus.com).
@end ignore
 
@cindex i860 support
@menu
* Notes-i860:: i860 Notes
* Options-i860:: i860 Command-line Options
* Directives-i860:: i860 Machine Directives
* Opcodes for i860:: i860 Opcodes
* Syntax of i860:: i860 Syntax
@end menu
 
@node Notes-i860
@section i860 Notes
This is a fairly complete i860 assembler which is compatible with the
UNIX System V/860 Release 4 assembler. However, it does not currently
support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}).
 
Like the SVR4/860 assembler, the output object format is ELF32. Currently,
this is the only supported object format. If there is sufficient interest,
other formats such as COFF may be implemented.
 
Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
being the default. One difference is that AT&T syntax requires the '%'
prefix on register names while Intel syntax does not. Another difference
is in the specification of relocatable expressions. The Intel syntax
is @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha}
(and similarly for the "l" and "h" selectors).
@node Options-i860
@section i860 Command-line Options
@subsection SVR4 compatibility options
@table @code
@item -V
Print assembler version.
@item -Qy
Ignored.
@item -Qn
Ignored.
@end table
@subsection Other options
@table @code
@item -EL
Select little endian output (this is the default).
@item -EB
Select big endian output. Note that the i860 always reads instructions
as little endian data, so this option only effects data and not
instructions.
@item -mwarn-expand
Emit a warning message if any pseudo-instruction expansions occurred.
For example, a @code{or} instruction with an immediate larger than 16-bits
will be expanded into two instructions. This is a very undesirable feature to
rely on, so this flag can help detect any code where it happens. One
use of it, for instance, has been to find and eliminate any place
where @code{gcc} may emit these pseudo-instructions.
@item -mxp
Enable support for the i860XP instructions and control registers. By default,
this option is disabled so that only the base instruction set (i.e., i860XR)
is supported.
@item -mintel-syntax
The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the
Intel syntax.
@end table
 
@node Directives-i860
@section i860 Machine Directives
 
@cindex machine directives, i860
@cindex i860 machine directives
 
@table @code
@cindex @code{dual} directive, i860
@item .dual
Enter dual instruction mode. While this directive is supported, the
preferred way to use dual instruction mode is to explicitly code
the dual bit with the @code{d.} prefix.
@end table
 
@table @code
@cindex @code{enddual} directive, i860
@item .enddual
Exit dual instruction mode. While this directive is supported, the
preferred way to use dual instruction mode is to explicitly code
the dual bit with the @code{d.} prefix.
@end table
 
@table @code
@cindex @code{atmp} directive, i860
@item .atmp
Change the temporary register used when expanding pseudo operations. The
default register is @code{r31}.
@end table
 
The @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode.
 
Both syntaxes allow for the standard @code{.align} directive. However,
the Intel syntax additionally allows keywords for the alignment
parameter: "@code{.align type}", where `type' is one of @code{.short}, @code{.long},
@code{.quad}, @code{.single}, @code{.double} representing alignments of 2, 4,
16, 4, and 8, respectively.
 
@node Opcodes for i860
@section i860 Opcodes
 
@cindex opcodes, i860
@cindex i860 opcodes
All of the Intel i860XR and i860XP machine instructions are supported. Please see
either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information.
@subsection Other instruction support (pseudo-instructions)
For compatibility with some other i860 assemblers, a number of
pseudo-instructions are supported. While these are supported, they are
a very undesirable feature that should be avoided -- in particular, when
they result in an expansion to multiple actual i860 instructions. Below
are the pseudo-instructions that result in expansions.
@itemize @bullet
@item Load large immediate into general register:
 
The pseudo-instruction @code{mov imm,%rn} (where the immediate does
not fit within a signed 16-bit field) will be expanded into:
@smallexample
orh large_imm@@h,%r0,%rn
or large_imm@@l,%rn,%rn
@end smallexample
@item Load/store with relocatable address expression:
 
For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn}
will be expanded into:
@smallexample
orh addr_exp@@ha,%rx,%r31
ld.l addr_exp@@l(%r31),%rn
@end smallexample
 
The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well.
@item Signed large immediate with add/subtract:
 
If any of the arithmetic operations @code{adds, addu, subs, subu} are used
with an immediate larger than 16-bits (signed), then they will be expanded.
For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to:
@smallexample
orh large_imm@@h,%r0,%r31
or large_imm@@l,%r31,%r31
adds %r31,%rx,%rn
@end smallexample
@item Unsigned large immediate with logical operations:
 
Logical operations (@code{or, andnot, or, xor}) also result in expansions.
The pseudo-instruction @code{or large_imm,%rx,%rn} results in:
@smallexample
orh large_imm@@h,%rx,%r31
or large_imm@@l,%r31,%rn
@end smallexample
 
Similarly for the others, except for @code{and} which expands to:
@smallexample
andnot (-1 - large_imm)@@h,%rx,%r31
andnot (-1 - large_imm)@@l,%r31,%rn
@end smallexample
@end itemize
 
@node Syntax of i860
@section i860 Syntax
@menu
* i860-Chars:: Special Characters
@end menu
 
@node i860-Chars
@subsection Special Characters
 
@cindex line comment character, i860
@cindex i860 line comment character
The presence of a @samp{#} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, i860
@cindex statement separator, i860
@cindex i860 line separator
The @samp{;} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-i960.texi
0,0 → 1,325
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 2002, 2006, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node i960-Dependent
@chapter Intel 80960 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter Intel 80960 Dependent Features
@end ifclear
 
@cindex i960 support
@menu
* Options-i960:: i960 Command-line Options
* Floating Point-i960:: Floating Point
* Directives-i960:: i960 Machine Directives
* Opcodes for i960:: i960 Opcodes
* Syntax of i960:: i960 Syntax
@end menu
 
@c FIXME! Add Syntax sec with discussion of bitfields here, at least so
@c long as they're not turned on for other machines than 960.
 
@node Options-i960
 
@section i960 Command-line Options
 
@cindex i960 options
@cindex options, i960
@table @code
 
@cindex i960 architecture options
@cindex architecture options, i960
@cindex @code{-A} options, i960
@item -ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC
Select the 80960 architecture. Instructions or features not supported
by the selected architecture cause fatal errors.
 
@samp{-ACA} is equivalent to @samp{-ACA_A}; @samp{-AKC} is equivalent to
@samp{-AMC}. Synonyms are provided for compatibility with other tools.
 
If you do not specify any of these options, @code{@value{AS}} generates code
for any instruction or feature that is supported by @emph{some} version of the
960 (even if this means mixing architectures!). In principle,
@code{@value{AS}} attempts to deduce the minimal sufficient processor type if
none is specified; depending on the object code format, the processor type may
be recorded in the object file. If it is critical that the @code{@value{AS}}
output match a specific architecture, specify that architecture explicitly.
 
@cindex @code{-b} option, i960
@cindex branch recording, i960
@cindex i960 branch recording
@item -b
Add code to collect information about conditional branches taken, for
later optimization using branch prediction bits. (The conditional branch
instructions have branch prediction bits in the CA, CB, and CC
architectures.) If @var{BR} represents a conditional branch instruction,
the following represents the code generated by the assembler when
@samp{-b} is specified:
 
@smallexample
call @var{increment routine}
.word 0 # pre-counter
Label: @var{BR}
call @var{increment routine}
.word 0 # post-counter
@end smallexample
 
The counter following a branch records the number of times that branch
was @emph{not} taken; the difference between the two counters is the
number of times the branch @emph{was} taken.
 
@cindex @code{gbr960}, i960 postprocessor
@cindex branch statistics table, i960
A table of every such @code{Label} is also generated, so that the
external postprocessor @code{gbr960} (supplied by Intel) can locate all
the counters. This table is always labeled @samp{__BRANCH_TABLE__};
this is a local symbol to permit collecting statistics for many separate
object files. The table is word aligned, and begins with a two-word
header. The first word, initialized to 0, is used in maintaining linked
lists of branch tables. The second word is a count of the number of
entries in the table, which follow immediately: each is a word, pointing
to one of the labels illustrated above.
 
@c TEXI2ROFF-KILL
@ifinfo
@c END TEXI2ROFF-KILL
@example
+------------+------------+------------+ ... +------------+
| | | | | |
| *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N |
| | | | | |
+------------+------------+------------+ ... +------------+
 
__BRANCH_TABLE__ layout
@end example
@c TEXI2ROFF-KILL
@end ifinfo
@need 2000
@tex
\vskip 1pc
\line{\leftskip=0pt\hskip\tableindent
\boxit{2cm}{\tt *NEXT}\boxit{2cm}{\tt COUNT: \it N}\boxit{2cm}{\tt
*BRLAB 1}\ibox{1cm}{\quad\dots}\boxit{2cm}{\tt *BRLAB \it N}\hfil}
\centerline{\it {\tt \_\_BRANCH\_TABLE\_\_} layout}
@end tex
@c END TEXI2ROFF-KILL
 
The first word of the header is used to locate multiple branch tables,
since each object file may contain one. Normally the links are
maintained with a call to an initialization routine, placed at the
beginning of each function in the file. The @sc{gnu} C compiler
generates these calls automatically when you give it a @samp{-b} option.
For further details, see the documentation of @samp{gbr960}.
 
@cindex @code{-no-relax} option, i960
@item -no-relax
Normally, Compare-and-Branch instructions with targets that require
displacements greater than 13 bits (or that have external targets) are
replaced with the corresponding compare (or @samp{chkbit}) and branch
instructions. You can use the @samp{-no-relax} option to specify that
@code{@value{AS}} should generate errors instead, if the target displacement
is larger than 13 bits.
 
This option does not affect the Compare-and-Jump instructions; the code
emitted for them is @emph{always} adjusted when necessary (depending on
displacement size), regardless of whether you use @samp{-no-relax}.
@end table
 
@node Floating Point-i960
@section Floating Point
 
@cindex floating point, i960 (@sc{ieee})
@cindex i960 floating point (@sc{ieee})
@code{@value{AS}} generates @sc{ieee} floating-point numbers for the directives
@samp{.float}, @samp{.double}, @samp{.extended}, and @samp{.single}.
 
@node Directives-i960
@section i960 Machine Directives
 
@cindex machine directives, i960
@cindex i960 machine directives
 
@table @code
@cindex @code{bss} directive, i960
@item .bss @var{symbol}, @var{length}, @var{align}
Reserve @var{length} bytes in the bss section for a local @var{symbol},
aligned to the power of two specified by @var{align}. @var{length} and
@var{align} must be positive absolute expressions. This directive
differs from @samp{.lcomm} only in that it permits you to specify
an alignment. @xref{Lcomm,,@code{.lcomm}}.
@end table
 
@table @code
@cindex @code{extended} directive, i960
@item .extended @var{flonums}
@code{.extended} expects zero or more flonums, separated by commas; for
each flonum, @samp{.extended} emits an @sc{ieee} extended-format (80-bit)
floating-point number.
 
@cindex @code{leafproc} directive, i960
@item .leafproc @var{call-lab}, @var{bal-lab}
You can use the @samp{.leafproc} directive in conjunction with the
optimized @code{callj} instruction to enable faster calls of leaf
procedures. If a procedure is known to call no other procedures, you
may define an entry point that skips procedure prolog code (and that does
not depend on system-supplied saved context), and declare it as the
@var{bal-lab} using @samp{.leafproc}. If the procedure also has an
entry point that goes through the normal prolog, you can specify that
entry point as @var{call-lab}.
 
A @samp{.leafproc} declaration is meant for use in conjunction with the
optimized call instruction @samp{callj}; the directive records the data
needed later to choose between converting the @samp{callj} into a
@code{bal} or a @code{call}.
 
@var{call-lab} is optional; if only one argument is present, or if the
two arguments are identical, the single argument is assumed to be the
@code{bal} entry point.
 
@cindex @code{sysproc} directive, i960
@item .sysproc @var{name}, @var{index}
The @samp{.sysproc} directive defines a name for a system procedure.
After you define it using @samp{.sysproc}, you can use @var{name} to
refer to the system procedure identified by @var{index} when calling
procedures with the optimized call instruction @samp{callj}.
 
Both arguments are required; @var{index} must be between 0 and 31
(inclusive).
@end table
 
@node Opcodes for i960
@section i960 Opcodes
 
@cindex opcodes, i960
@cindex i960 opcodes
All Intel 960 machine instructions are supported;
@pxref{Options-i960,,i960 Command-line Options} for a discussion of
selecting the instruction subset for a particular 960
architecture.@refill
 
Some opcodes are processed beyond simply emitting a single corresponding
instruction: @samp{callj}, and Compare-and-Branch or Compare-and-Jump
instructions with target displacements larger than 13 bits.
 
@menu
* callj-i960:: @code{callj}
* Compare-and-branch-i960:: Compare-and-Branch
@end menu
 
@node callj-i960
@subsection @code{callj}
 
@cindex @code{callj}, i960 pseudo-opcode
@cindex i960 @code{callj} pseudo-opcode
You can write @code{callj} to have the assembler or the linker determine
the most appropriate form of subroutine call: @samp{call},
@samp{bal}, or @samp{calls}. If the assembly source contains
enough information---a @samp{.leafproc} or @samp{.sysproc} directive
defining the operand---then @code{@value{AS}} translates the
@code{callj}; if not, it simply emits the @code{callj}, leaving it
for the linker to resolve.
 
@node Compare-and-branch-i960
@subsection Compare-and-Branch
 
@cindex i960 compare/branch instructions
@cindex compare/branch instructions, i960
The 960 architectures provide combined Compare-and-Branch instructions
that permit you to store the branch target in the lower 13 bits of the
instruction word itself. However, if you specify a branch target far
enough away that its address won't fit in 13 bits, the assembler can
either issue an error, or convert your Compare-and-Branch instruction
into separate instructions to do the compare and the branch.
 
@cindex compare and jump expansions, i960
@cindex i960 compare and jump expansions
Whether @code{@value{AS}} gives an error or expands the instruction depends
on two choices you can make: whether you use the @samp{-no-relax} option,
and whether you use a ``Compare and Branch'' instruction or a ``Compare
and Jump'' instruction. The ``Jump'' instructions are @emph{always}
expanded if necessary; the ``Branch'' instructions are expanded when
necessary @emph{unless} you specify @code{-no-relax}---in which case
@code{@value{AS}} gives an error instead.
 
These are the Compare-and-Branch instructions, their ``Jump'' variants,
and the instruction pairs they may expand into:
 
@c TEXI2ROFF-KILL
@ifinfo
@c END TEXI2ROFF-KILL
@example
Compare and
Branch Jump Expanded to
------ ------ ------------
bbc chkbit; bno
bbs chkbit; bo
cmpibe cmpije cmpi; be
cmpibg cmpijg cmpi; bg
cmpibge cmpijge cmpi; bge
cmpibl cmpijl cmpi; bl
cmpible cmpijle cmpi; ble
cmpibno cmpijno cmpi; bno
cmpibne cmpijne cmpi; bne
cmpibo cmpijo cmpi; bo
cmpobe cmpoje cmpo; be
cmpobg cmpojg cmpo; bg
cmpobge cmpojge cmpo; bge
cmpobl cmpojl cmpo; bl
cmpoble cmpojle cmpo; ble
cmpobne cmpojne cmpo; bne
@end example
@c TEXI2ROFF-KILL
@end ifinfo
@tex
\hskip\tableindent
\halign{\hfil {\tt #}\quad&\hfil {\tt #}\qquad&{\tt #}\hfil\cr
\omit{\hfil\it Compare and\hfil}\span\omit&\cr
{\it Branch}&{\it Jump}&{\it Expanded to}\cr
bbc& & chkbit; bno\cr
bbs& & chkbit; bo\cr
cmpibe& cmpije& cmpi; be\cr
cmpibg& cmpijg& cmpi; bg\cr
cmpibge& cmpijge& cmpi; bge\cr
cmpibl& cmpijl& cmpi; bl\cr
cmpible& cmpijle& cmpi; ble\cr
cmpibno& cmpijno& cmpi; bno\cr
cmpibne& cmpijne& cmpi; bne\cr
cmpibo& cmpijo& cmpi; bo\cr
cmpobe& cmpoje& cmpo; be\cr
cmpobg& cmpojg& cmpo; bg\cr
cmpobge& cmpojge& cmpo; bge\cr
cmpobl& cmpojl& cmpo; bl\cr
cmpoble& cmpojle& cmpo; ble\cr
cmpobne& cmpojne& cmpo; bne\cr}
@end tex
@c END TEXI2ROFF-KILL
 
@node Syntax of i960
@section Syntax for the i960
@menu
* i960-Chars:: Special Characters
@end menu
 
@node i960-Chars
@subsection Special Characters
 
@cindex line comment character, i960
@cindex i960 line comment character
The presence of a @samp{#} on a line indicates the start of a comment
that extends to the end of the current line.
 
If a @samp{#} appears as the first character of a line, the whole line
is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a
preprocessor control command (@pxref{Preprocessing}).
 
@cindex line separator, i960
@cindex statement separator, i960
@cindex i960 line separator
The @samp{;} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-ia64.texi
0,0 → 1,202
@c Copyright 2002, 2003, 2005
@c Free Software Foundation, Inc.
@c Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@ifset GENERIC
@page
@node IA-64-Dependent
@chapter IA-64 Dependent Features
@end ifset
 
@ifclear GENERIC
@node Machine Dependencies
@chapter IA-64 Dependent Features
@end ifclear
 
@cindex IA-64 support
@menu
* IA-64 Options:: Options
* IA-64 Syntax:: Syntax
@c * IA-64 Floating Point:: Floating Point // to be written
@c * IA-64 Directives:: IA-64 Machine Directives // to be written
* IA-64 Opcodes:: Opcodes
@end menu
 
@node IA-64 Options
@section Options
@cindex IA-64 options
@cindex options for IA-64
 
@table @option
@cindex @code{-mconstant-gp} command line option, IA-64
 
@item -mconstant-gp
This option instructs the assembler to mark the resulting object file
as using the ``constant GP'' model. With this model, it is assumed
that the entire program uses a single global pointer (GP) value. Note
that this option does not in any fashion affect the machine code
emitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP
flag in the ELF file header.
 
@item -mauto-pic
This option instructs the assembler to mark the resulting object file
as using the ``constant GP without function descriptor'' data model.
This model is like the ``constant GP'' model, except that it
additionally does away with function descriptors. What this means is
that the address of a function refers directly to the function's code
entry-point. Normally, such an address would refer to a function
descriptor, which contains both the code entry-point and the GP-value
needed by the function. Note that this option does not in any fashion
affect the machine code emitted by the assembler. All it does is
turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.
 
@item -milp32
@itemx -milp64
@itemx -mlp64
@itemx -mp64
These options select the data model. The assembler defaults to @code{-mlp64}
(LP64 data model).
 
@item -mle
@itemx -mbe
These options select the byte order. The @code{-mle} option selects little-endian
byte order (default) and @code{-mbe} selects big-endian byte order. Note that
IA-64 machine code always uses little-endian byte order.
 
@item -mtune=itanium1
@itemx -mtune=itanium2
Tune for a particular IA-64 CPU, @var{itanium1} or @var{itanium2}. The
default is @var{itanium2}.
 
@item -munwind-check=warning
@itemx -munwind-check=error
These options control what the assembler will do when performing
consistency checks on unwind directives. @code{-munwind-check=warning}
will make the assembler issue a warning when an unwind directive check
fails. This is the default. @code{-munwind-check=error} will make the
assembler issue an error when an unwind directive check fails.
 
@item -mhint.b=ok
@itemx -mhint.b=warning
@itemx -mhint.b=error
These options control what the assembler will do when the @samp{hint.b}
instruction is used. @code{-mhint.b=ok} will make the assembler accept
@samp{hint.b}. @code{-mint.b=warning} will make the assembler issue a
warning when @samp{hint.b} is used. @code{-mhint.b=error} will make
the assembler treat @samp{hint.b} as an error, which is the default.
 
@item -x
@itemx -xexplicit
These options turn on dependency violation checking.
 
@item -xauto
This option instructs the assembler to automatically insert stop bits where necessary
to remove dependency violations. This is the default mode.
 
@item -xnone
This option turns off dependency violation checking.
 
@item -xdebug
This turns on debug output intended to help tracking down bugs in the dependency
violation checker.
 
@item -xdebugn
This is a shortcut for -xnone -xdebug.
 
@item -xdebugx
This is a shortcut for -xexplicit -xdebug.
 
@end table
 
@cindex IA-64 Syntax
@node IA-64 Syntax
@section Syntax
The assembler syntax closely follows the IA-64 Assembly Language
Reference Guide.
 
@menu
* IA-64-Chars:: Special Characters
* IA-64-Regs:: Register Names
* IA-64-Bits:: Bit Names
* IA-64-Relocs:: Relocations
@end menu
 
@node IA-64-Chars
@subsection Special Characters
 
@cindex line comment character, IA-64
@cindex IA-64 line comment character
@samp{//} is the line comment token.
 
@cindex line separator, IA-64
@cindex statement separator, IA-64
@cindex IA-64 line separator
@samp{;} can be used instead of a newline to separate statements.
 
@node IA-64-Regs
@subsection Register Names
@cindex IA-64 registers
@cindex register names, IA-64
 
The 128 integer registers are referred to as @samp{r@var{n}}.
The 128 floating-point registers are referred to as @samp{f@var{n}}.
The 128 application registers are referred to as @samp{ar@var{n}}.
The 128 control registers are referred to as @samp{cr@var{n}}.
The 64 one-bit predicate registers are referred to as @samp{p@var{n}}.
The 8 branch registers are referred to as @samp{b@var{n}}.
In addition, the assembler defines a number of aliases:
@samp{gp} (@samp{r1}), @samp{sp} (@samp{r12}), @samp{rp} (@samp{b0}),
@samp{ret0} (@samp{r8}), @samp{ret1} (@samp{r9}), @samp{ret2} (@samp{r10}),
@samp{ret3} (@samp{r9}), @samp{farg@var{n}} (@samp{f8+@var{n}}), and
@samp{fret@var{n}} (@samp{f8+@var{n}}).
 
For convenience, the assembler also defines aliases for all named application
and control registers. For example, @samp{ar.bsp} refers to the register
backing store pointer (@samp{ar17}). Similarly, @samp{cr.eoi} refers to
the end-of-interrupt register (@samp{cr67}).
 
@node IA-64-Bits
@subsection IA-64 Processor-Status-Register (PSR) Bit Names
@cindex IA-64 Processor-status-Register bit names
@cindex PSR bits
@cindex bit names, IA-64
 
The assembler defines bit masks for each of the bits in the IA-64
processor status register. For example, @samp{psr.ic} corresponds to
a value of 0x2000. These masks are primarily intended for use with
the @samp{ssm}/@samp{sum} and @samp{rsm}/@samp{rum}
instructions, but they can be used anywhere else where an integer
constant is expected.
 
@node IA-64-Relocs
@subsection Relocations
@cindex IA-64 relocations
 
In addition to the standard IA-64 relocations, the following relocations are
implemented by @code{@value{AS}}:
 
@table @code
@item @@slotcount(@var{V})
Convert the address offset @var{V} into a slot count. This pseudo
function is available only on VMS. The expression @var{V} must be
known at assembly time: it can't reference undefined symbols or symbols in
different sections.
@end table
 
@node IA-64 Opcodes
@section Opcodes
For detailed information on the IA-64 machine instruction set, see the
@c Attempt to work around a very overfull hbox.
@iftex
IA-64 Assembly Language Reference Guide available at
@smallfonts
@example
http://developer.intel.com/design/itanium/arch_spec.htm
@end example
@textfonts
@end iftex
@ifnottex
@uref{http://developer.intel.com/design/itanium/arch_spec.htm,IA-64 Architecture Handbook}.
@end ifnottex
/binutils/gas/doc/c-ip2k.texi
0,0 → 1,71
@c Copyright 2002, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node IP2K-Dependent
@chapter IP2K Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter IP2K Dependent Features
@end ifclear
 
@cindex IP2K support
@menu
* IP2K-Opts:: IP2K Options
* IP2K-Syntax:: IP2K Syntax
@end menu
 
@node IP2K-Opts
@section IP2K Options
 
@cindex options, IP2K
@cindex IP2K options
 
The Ubicom IP2K version of @code{@value{AS}} has a few machine
dependent options:
 
@table @code
@item -mip2022ext
@cindex @samp{-mip2022ext} option, IP2022
@cindex architecture options, IP2022
@cindex IP2K architecture options
@code{@value{AS}} can assemble the extended IP2022 instructions, but
it will only do so if this is specifically allowed via this command
line option.
 
@item -mip2022
@cindex @samp{-mip2022} option, IP2K
@cindex architecture options, IP2K
@cindex IP2K architecture options
This option restores the assembler's default behaviour of not
permitting the extended IP2022 instructions to be assembled.
 
@end table
 
@node IP2K-Syntax
@section IP2K Syntax
@menu
* IP2K-Chars:: Special Characters
@end menu
 
@node IP2K-Chars
@subsection Special Characters
 
@cindex line comment character, IP2K
@cindex IP2K line comment character
The presence of a @samp{;} on a line indicates the start of a comment
that extends to the end of the current line.
 
If a @samp{#} appears as the first character of a line, the whole line
is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, IP2K
@cindex statement separator, IP2K
@cindex IP2K line separator
The IP2K assembler does not currently support a line separator
character.
/binutils/gas/doc/c-lm32.texi
0,0 → 1,233
@c Copyright 2008, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@ifset GENERIC
@page
@node LM32-Dependent
@chapter LM32 Dependent Features
@end ifset
 
@ifclear GENERIC
@node Machine Dependencies
 
@end ifclear
 
@cindex LM32 support
@menu
* LM32 Options:: Options
* LM32 Syntax:: Syntax
* LM32 Opcodes:: Opcodes
@end menu
 
@node LM32 Options
@section Options
@cindex LM32 options (none)
@cindex options for LM32 (none)
 
@table @code
 
@cindex @code{-mmultiply-enabled} command line option, LM32
@item -mmultiply-enabled
Enable multiply instructions.
 
@cindex @code{-mdivide-enabled} command line option, LM32
@item -mdivide-enabled
Enable divide instructions.
 
@cindex @code{-mbarrel-shift-enabled} command line option, LM32
@item -mbarrel-shift-enabled
Enable barrel-shift instructions.
 
@cindex @code{-msign-extend-enabled} command line option, LM32
@item -msign-extend-enabled
Enable sign extend instructions.
 
@cindex @code{-muser-enabled} command line option, LM32
@item -muser-enabled
Enable user defined instructions.
 
@cindex @code{-micache-enabled} command line option, LM32
@item -micache-enabled
Enable instruction cache related CSRs.
 
@cindex @code{-mdcache-enabled} command line option, LM32
@item -mdcache-enabled
Enable data cache related CSRs.
 
@cindex @code{-mbreak-enabled} command line option, LM32
@item -mbreak-enabled
Enable break instructions.
 
@cindex @code{-mall-enabled} command line option, LM32
@item -mall-enabled
Enable all instructions and CSRs.
 
@end table
 
 
@node LM32 Syntax
@section Syntax
@menu
* LM32-Regs:: Register Names
* LM32-Modifiers:: Relocatable Expression Modifiers
* LM32-Chars:: Special Characters
@end menu
 
@node LM32-Regs
@subsection Register Names
 
@cindex LM32 register names
@cindex register names, LM32
 
LM32 has 32 x 32-bit general purpose registers @samp{r0},
@samp{r1}, ... @samp{r31}.
 
The following aliases are defined: @samp{gp} - @samp{r26},
@samp{fp} - @samp{r27}, @samp{sp} - @samp{r28},
@samp{ra} - @samp{r29}, @samp{ea} - @samp{r30},
@samp{ba} - @samp{r31}.
 
LM32 has the following Control and Status Registers (CSRs).
 
@table @code
@item IE
Interrupt enable.
@item IM
Interrupt mask.
@item IP
Interrupt pending.
@item ICC
Instruction cache control.
@item DCC
Data cache control.
@item CC
Cycle counter.
@item CFG
Configuration.
@item EBA
Exception base address.
@item DC
Debug control.
@item DEBA
Debug exception base address.
@item JTX
JTAG transmit.
@item JRX
JTAG receive.
@item BP0
Breakpoint 0.
@item BP1
Breakpoint 1.
@item BP2
Breakpoint 2.
@item BP3
Breakpoint 3.
@item WP0
Watchpoint 0.
@item WP1
Watchpoint 1.
@item WP2
Watchpoint 2.
@item WP3
Watchpoint 3.
@end table
 
@node LM32-Modifiers
@subsection Relocatable Expression Modifiers
 
@cindex LM32 modifiers
@cindex syntax, LM32
 
The assembler supports several modifiers when using relocatable addresses
in LM32 instruction operands. The general syntax is the following:
 
@smallexample
modifier(relocatable-expression)
@end smallexample
 
@table @code
@cindex symbol modifiers
 
@item lo
 
This modifier allows you to use bits 0 through 15 of
an address expression as 16 bit relocatable expression.
 
@item hi
 
This modifier allows you to use bits 16 through 23 of an address expression
as 16 bit relocatable expression.
 
For example
 
@smallexample
ori r4, r4, lo(sym+10)
orhi r4, r4, hi(sym+10)
@end smallexample
 
@item gp
 
This modified creates a 16-bit relocatable expression that is
the offset of the symbol from the global pointer.
 
@smallexample
mva r4, gp(sym)
@end smallexample
 
@item got
 
This modifier places a symbol in the GOT and creates a 16-bit
relocatable expression that is the offset into the GOT of this
symbol.
 
@smallexample
lw r4, (gp+got(sym))
@end smallexample
 
@item gotofflo16
 
This modifier allows you to use the bits 0 through 15 of an
address which is an offset from the GOT.
 
@item gotoffhi16
 
This modifier allows you to use the bits 16 through 31 of an
address which is an offset from the GOT.
 
@smallexample
orhi r4, r4, gotoffhi16(lsym)
addi r4, r4, gotofflo16(lsym)
@end smallexample
 
@end table
 
@node LM32-Chars
@subsection Special Characters
 
@cindex line comment character, LM32
@cindex LM32 line comment character
The presence of a @samp{#} on a line indicates the start of a comment
that extends to the end of the current line. Note that if a line
starts with a @samp{#} character then it can also be a logical line
number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, LM32
@cindex statement separator, LM32
@cindex LM32 line separator
A semicolon (@samp{;}) can be used to separate multiple statements on
the same line.
 
@node LM32 Opcodes
@section Opcodes
 
@cindex LM32 opcode summary
@cindex opcode summary, LM32
@cindex mnemonics, LM32
@cindex instruction summary, LM32
For detailed information on the LM32 machine instruction set, see
@url{http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/}.
 
@code{@value{AS}} implements all the standard LM32 opcodes.
/binutils/gas/doc/c-m32c.texi
0,0 → 1,149
@c Copyright 2005, 2008
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node M32C-Dependent
@chapter M32C Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter M32C Dependent Features
@end ifclear
@cindex M32C support
 
@code{@value{AS}} can assemble code for several different members of
the Renesas M32C family. Normally the default is to assemble code for
the M16C microprocessor. The @code{-m32c} option may be used to
change the default to the M32C microprocessor.
 
@menu
* M32C-Opts:: M32C Options
* M32C-Syntax:: M32C Syntax
@end menu
@node M32C-Opts
@section M32C Options
@cindex options, M32C
@cindex M32C options
The Renesas M32C version of @code{@value{AS}} has these
machine-dependent options:
@table @code
@item -m32c
@cindex @samp{-m32c} option, M32C
@cindex architecture options, M32C
@cindex M32C architecture option
Assemble M32C instructions.
@item -m16c
@cindex @samp{-m16c} option, M16C
@cindex architecture options, M16C
@cindex M16C architecture option
Assemble M16C instructions (default).
 
@item -relax
Enable support for link-time relaxations.
 
@item -h-tick-hex
Support H'00 style hex constants in addition to 0x00 style.
 
@end table
 
@node M32C-Syntax
@section M32C Syntax
@menu
* M32C-Modifiers:: Symbolic Operand Modifiers
* M32C-Chars:: Special Characters
@end menu
 
@node M32C-Modifiers
@subsection Symbolic Operand Modifiers
 
@cindex M32C modifiers
@cindex modifiers, M32C
 
The assembler supports several modifiers when using symbol addresses
in M32C instruction operands. The general syntax is the following:
 
@smallexample
%modifier(symbol)
@end smallexample
 
@table @code
@cindex symbol modifiers
 
@item %dsp8
@itemx %dsp16
 
These modifiers override the assembler's assumptions about how big a
symbol's address is. Normally, when it sees an operand like
@samp{sym[a0]} it assumes @samp{sym} may require the widest
displacement field (16 bits for @samp{-m16c}, 24 bits for
@samp{-m32c}). These modifiers tell it to assume the address will fit
in an 8 or 16 bit (respectively) unsigned displacement. Note that, of
course, if it doesn't actually fit you will get linker errors. Example:
 
@smallexample
mov.w %dsp8(sym)[a0],r1
mov.b #0,%dsp8(sym)[a0]
@end smallexample
 
@item %hi8
 
This modifier allows you to load bits 16 through 23 of a 24 bit
address into an 8 bit register. This is useful with, for example, the
M16C @samp{smovf} instruction, which expects a 20 bit address in
@samp{r1h} and @samp{a0}. Example:
 
@smallexample
mov.b #%hi8(sym),r1h
mov.w #%lo16(sym),a0
smovf.b
@end smallexample
 
@item %lo16
 
Likewise, this modifier allows you to load bits 0 through 15 of a 24
bit address into a 16 bit register.
 
@item %hi16
 
This modifier allows you to load bits 16 through 31 of a 32 bit
address into a 16 bit register. While the M32C family only has 24
bits of address space, it does support addresses in pairs of 16 bit
registers (like @samp{a1a0} for the @samp{lde} instruction). This
modifier is for loading the upper half in such cases. Example:
 
@smallexample
mov.w #%hi16(sym),a1
mov.w #%lo16(sym),a0
@dots{}
lde.w [a1a0],r1
@end smallexample
 
@end table
 
@node M32C-Chars
@subsection Special Characters
 
@cindex line comment character, M32C
@cindex M32C line comment character
The presence of a @samp{;} character on a line indicates the start of
a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line, the whole line
is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a
preprocessor control command (@pxref{Preprocessing}).
 
@cindex line separator, M32C
@cindex statement separator, M32C
@cindex M32C line separator
The @samp{|} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-m32r.texi
0,0 → 1,358
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
@c 2000, 2003, 2004, 2006
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node M32R-Dependent
@chapter M32R Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter M32R Dependent Features
@end ifclear
 
@cindex M32R support
@menu
* M32R-Opts:: M32R Options
* M32R-Directives:: M32R Directives
* M32R-Warnings:: M32R Warnings
@end menu
 
@node M32R-Opts
@section M32R Options
 
@cindex options, M32R
@cindex M32R options
 
The Renease M32R version of @code{@value{AS}} has a few machine
dependent options:
 
@table @code
 
@item -m32rx
@cindex @samp{-m32rx} option, M32RX
@cindex architecture options, M32RX
@cindex M32R architecture options
@code{@value{AS}} can assemble code for several different members of the
Renesas M32R family. Normally the default is to assemble code for
the M32R microprocessor. This option may be used to change the default
to the M32RX microprocessor, which adds some more instructions to the
basic M32R instruction set, and some additional parameters to some of
the original instructions.
 
@item -m32r2
@cindex @samp{-m32rx} option, M32R2
@cindex architecture options, M32R2
@cindex M32R architecture options
This option changes the target processor to the the M32R2
microprocessor.
 
@item -m32r
@cindex @samp{-m32r} option, M32R
@cindex architecture options, M32R
@cindex M32R architecture options
This option can be used to restore the assembler's default behaviour of
assembling for the M32R microprocessor. This can be useful if the
default has been changed by a previous command line option.
 
@item -little
@cindex @code{-little} option, M32R
This option tells the assembler to produce little-endian code and
data. The default is dependent upon how the toolchain was
configured.
 
@item -EL
@cindex @code{-EL} option, M32R
This is a synonym for @emph{-little}.
 
@item -big
@cindex @code{-big} option, M32R
This option tells the assembler to produce big-endian code and
data.
 
@item -EB
@cindex @code{-EB} option, M32R
This is a synonum for @emph{-big}.
 
@item -KPIC
@cindex @code{-KPIC} option, M32R
@cindex PIC code generation for M32R
This option specifies that the output of the assembler should be
marked as position-independent code (PIC).
 
@item -parallel
@cindex @code{-parallel} option, M32RX
This option tells the assembler to attempts to combine two sequential
instructions into a single, parallel instruction, where it is legal to
do so.
 
@item -no-parallel
@cindex @code{-no-parallel} option, M32RX
This option disables a previously enabled @emph{-parallel} option.
 
@item -no-bitinst
@cindex @samp{-no-bitinst}, M32R2
This option disables the support for the extended bit-field
instructions provided by the M32R2. If this support needs to be
re-enabled the @emph{-bitinst} switch can be used to restore it.
 
@item -O
@cindex @code{-O} option, M32RX
This option tells the assembler to attempt to optimize the
instructions that it produces. This includes filling delay slots and
converting sequential instructions into parallel ones. This option
implies @emph{-parallel}.
 
@item -warn-explicit-parallel-conflicts
@cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX
Instructs @code{@value{AS}} to produce warning messages when
questionable parallel instructions are encountered. This option is
enabled by default, but @code{@value{GCC}} disables it when it invokes
@code{@value{AS}} directly. Questionable instructions are those whose
behaviour would be different if they were executed sequentially. For
example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a
different result from @samp{mv r1, r2 \n mv r3, r1} since the former
moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
and r3.
 
@item -Wp
@cindex @samp{-Wp} option, M32RX
This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts}
option.
 
@item -no-warn-explicit-parallel-conflicts
@cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX
Instructs @code{@value{AS}} not to produce warning messages when
questionable parallel instructions are encountered.
 
@item -Wnp
@cindex @samp{-Wnp} option, M32RX
This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts}
option.
 
@item -ignore-parallel-conflicts
@cindex @samp{-ignore-parallel-conflicts} option, M32RX
This option tells the assembler's to stop checking parallel
instructions for constraint violations. This ability is provided for
hardware vendors testing chip designs and should not be used under
normal circumstances.
 
@item -no-ignore-parallel-conflicts
@cindex @samp{-no-ignore-parallel-conflicts} option, M32RX
This option restores the assembler's default behaviour of checking
parallel instructions to detect constraint violations.
 
@item -Ip
@cindex @samp{-Ip} option, M32RX
This is a shorter synonym for the @emph{-ignore-parallel-conflicts}
option.
 
@item -nIp
@cindex @samp{-nIp} option, M32RX
This is a shorter synonym for the @emph{-no-ignore-parallel-conflicts}
option.
 
@item -warn-unmatched-high
@cindex @samp{-warn-unmatched-high} option, M32R
This option tells the assembler to produce a warning message if a
@code{.high} pseudo op is encountered without a matching @code{.low}
pseudo op. The presence of such an unmatched pseudo op usually
indicates a programming error.
 
@item -no-warn-unmatched-high
@cindex @samp{-no-warn-unmatched-high} option, M32R
Disables a previously enabled @emph{-warn-unmatched-high} option.
 
@item -Wuh
@cindex @samp{-Wuh} option, M32RX
This is a shorter synonym for the @emph{-warn-unmatched-high} option.
 
@item -Wnuh
@cindex @samp{-Wnuh} option, M32RX
This is a shorter synonym for the @emph{-no-warn-unmatched-high} option.
 
@end table
 
@node M32R-Directives
@section M32R Directives
@cindex directives, M32R
@cindex M32R directives
 
The Renease M32R version of @code{@value{AS}} has a few architecture
specific directives:
 
@table @code
 
@cindex @code{low} directive, M32R
@item low @var{expression}
The @code{low} directive computes the value of its expression and
places the lower 16-bits of the result into the immediate-field of the
instruction. For example:
 
@smallexample
or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred
@end smallexample
 
@item high @var{expression}
@cindex @code{high} directive, M32R
The @code{high} directive computes the value of its expression and
places the upper 16-bits of the result into the immediate-field of the
instruction. For example:
 
@smallexample
seth r0, #high(0x12345678) ; compute r0 = 0x12340000
seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred
@end smallexample
 
@item shigh @var{expression}
@cindex @code{shigh} directive, M32R
The @code{shigh} directive is very similar to the @code{high}
directive. It also computes the value of its expression and places
the upper 16-bits of the result into the immediate-field of the
instruction. The difference is that @code{shigh} also checks to see
if the lower 16-bits could be interpreted as a signed number, and if
so it assumes that a borrow will occur from the upper-16 bits. To
compensate for this the @code{shigh} directive pre-biases the upper
16 bit value by adding one to it. For example:
 
For example:
 
@smallexample
seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000
seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000
@end smallexample
 
In the second example the lower 16-bits are 0x8000. If these are
treated as a signed value and sign extended to 32-bits then the value
becomes 0xffff8000. If this value is then added to 0x00010000 then
the result is 0x00008000.
 
This behaviour is to allow for the different semantics of the
@code{or3} and @code{add3} instructions. The @code{or3} instruction
treats its 16-bit immediate argument as unsigned whereas the
@code{add3} treats its 16-bit immediate as a signed value. So for
example:
 
@smallexample
seth r0, #shigh(0x00008000)
add3 r0, r0, #low(0x00008000)
@end smallexample
 
Produces the correct result in r0, whereas:
 
@smallexample
seth r0, #shigh(0x00008000)
or3 r0, r0, #low(0x00008000)
@end smallexample
 
Stores 0xffff8000 into r0.
 
Note - the @code{shigh} directive does not know where in the assembly
source code the lower 16-bits of the value are going set, so it cannot
check to make sure that an @code{or3} instruction is being used rather
than an @code{add3} instruction. It is up to the programmer to make
sure that correct directives are used.
 
@cindex @code{.m32r} directive, M32R
@item .m32r
The directive performs a similar thing as the @emph{-m32r} command
line option. It tells the assembler to only accept M32R instructions
from now on. An instructions from later M32R architectures are
refused.
 
@cindex @code{.m32rx} directive, M32RX
@item .m32rx
The directive performs a similar thing as the @emph{-m32rx} command
line option. It tells the assembler to start accepting the extra
instructions in the M32RX ISA as well as the ordinary M32R ISA.
 
@cindex @code{.m32r2} directive, M32R2
@item .m32r2
The directive performs a similar thing as the @emph{-m32r2} command
line option. It tells the assembler to start accepting the extra
instructions in the M32R2 ISA as well as the ordinary M32R ISA.
 
@cindex @code{.little} directive, M32RX
@item .little
The directive performs a similar thing as the @emph{-little} command
line option. It tells the assembler to start producing little-endian
code and data. This option should be used with care as producing
mixed-endian binary files is fraught with danger.
 
@cindex @code{.big} directive, M32RX
@item .big
The directive performs a similar thing as the @emph{-big} command
line option. It tells the assembler to start producing big-endian
code and data. This option should be used with care as producing
mixed-endian binary files is fraught with danger.
 
@end table
 
@node M32R-Warnings
@section M32R Warnings
 
@cindex warnings, M32R
@cindex M32R warnings
 
There are several warning and error messages that can be produced by
@code{@value{AS}} which are specific to the M32R:
 
@table @code
 
@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?
This message is only produced if warnings for explicit parallel
conflicts have been enabled. It indicates that the assembler has
encountered a parallel instruction in which the destination register of
the left hand instruction is used as an input register in the right hand
instruction. For example in this code fragment
@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the
move instruction and the input to the neg instruction.
 
@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?
This message is only produced if warnings for explicit parallel
conflicts have been enabled. It indicates that the assembler has
encountered a parallel instruction in which the destination register of
the right hand instruction is used as an input register in the left hand
instruction. For example in this code fragment
@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the
neg instruction and the input to the move instruction.
 
@item instruction @samp{...} is for the M32RX only
This message is produced when the assembler encounters an instruction
which is only supported by the M32Rx processor, and the @samp{-m32rx}
command line flag has not been specified to allow assembly of such
instructions.
 
@item unknown instruction @samp{...}
This message is produced when the assembler encounters an instruction
which it does not recognize.
 
@item only the NOP instruction can be issued in parallel on the m32r
This message is produced when the assembler encounters a parallel
instruction which does not involve a NOP instruction and the
@samp{-m32rx} command line flag has not been specified. Only the M32Rx
processor is able to execute two instructions in parallel.
 
@item instruction @samp{...} cannot be executed in parallel.
This message is produced when the assembler encounters a parallel
instruction which is made up of one or two instructions which cannot be
executed in parallel.
 
@item Instructions share the same execution pipeline
This message is produced when the assembler encounters a parallel
instruction whoes components both use the same execution pipeline.
 
@item Instructions write to the same destination register.
This message is produced when the assembler encounters a parallel
instruction where both components attempt to modify the same register.
For example these code fragments will produce this message:
@samp{mv r1, r2 || neg r1, r3}
@samp{jl r0 || mv r14, r1}
@samp{st r2, @@-r1 || mv r1, r3}
@samp{mv r1, r2 || ld r0, @@r1+}
@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit)
 
@end table
/binutils/gas/doc/c-m68hc11.texi
0,0 → 1,462
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003,
@c 2006, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node M68HC11-Dependent
@chapter M68HC11 and M68HC12 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter M68HC11 and M68HC12 Dependent Features
@end ifclear
 
@cindex M68HC11 and M68HC12 support
@menu
* M68HC11-Opts:: M68HC11 and M68HC12 Options
* M68HC11-Syntax:: Syntax
* M68HC11-Modifiers:: Symbolic Operand Modifiers
* M68HC11-Directives:: Assembler Directives
* M68HC11-Float:: Floating Point
* M68HC11-opcodes:: Opcodes
@end menu
 
@node M68HC11-Opts
@section M68HC11 and M68HC12 Options
 
@cindex options, M68HC11
@cindex M68HC11 options
The Motorola 68HC11 and 68HC12 version of @code{@value{AS}} have a few machine
dependent options.
 
@table @code
 
@cindex @samp{-m68hc11}
@item -m68hc11
This option switches the assembler in the M68HC11 mode. In this mode,
the assembler only accepts 68HC11 operands and mnemonics. It produces
code for the 68HC11.
 
@cindex @samp{-m68hc12}
@item -m68hc12
This option switches the assembler in the M68HC12 mode. In this mode,
the assembler also accepts 68HC12 operands and mnemonics. It produces
code for the 68HC12. A few 68HC11 instructions are replaced by
some 68HC12 instructions as recommended by Motorola specifications.
 
@cindex @samp{-m68hcs12}
@item -m68hcs12
This option switches the assembler in the M68HCS12 mode. This mode is
similar to @samp{-m68hc12} but specifies to assemble for the 68HCS12
series. The only difference is on the assembling of the @samp{movb}
and @samp{movw} instruction when a PC-relative operand is used.
 
@cindex @samp{-mshort}
@item -mshort
This option controls the ABI and indicates to use a 16-bit integer ABI.
It has no effect on the assembled instructions.
This is the default.
 
@cindex @samp{-mlong}
@item -mlong
This option controls the ABI and indicates to use a 32-bit integer ABI.
 
@cindex @samp{-mshort-double}
@item -mshort-double
This option controls the ABI and indicates to use a 32-bit float ABI.
This is the default.
 
@cindex @samp{-mlong-double}
@item -mlong-double
This option controls the ABI and indicates to use a 64-bit float ABI.
 
@cindex @samp{--strict-direct-mode}
@item --strict-direct-mode
You can use the @samp{--strict-direct-mode} option to disable
the automatic translation of direct page mode addressing into
extended mode when the instruction does not support direct mode.
For example, the @samp{clr} instruction does not support direct page
mode addressing. When it is used with the direct page mode,
@code{@value{AS}} will ignore it and generate an absolute addressing.
This option prevents @code{@value{AS}} from doing this, and the wrong
usage of the direct page mode will raise an error.
 
@cindex @samp{--short-branches}
@item --short-branches
The @samp{--short-branches} option turns off the translation of
relative branches into absolute branches when the branch offset is
out of range. By default @code{@value{AS}} transforms the relative
branch (@samp{bsr}, @samp{bgt}, @samp{bge}, @samp{beq}, @samp{bne},
@samp{ble}, @samp{blt}, @samp{bhi}, @samp{bcc}, @samp{bls},
@samp{bcs}, @samp{bmi}, @samp{bvs}, @samp{bvs}, @samp{bra}) into
an absolute branch when the offset is out of the -128 .. 127 range.
In that case, the @samp{bsr} instruction is translated into a
@samp{jsr}, the @samp{bra} instruction is translated into a
@samp{jmp} and the conditional branches instructions are inverted and
followed by a @samp{jmp}. This option disables these translations
and @code{@value{AS}} will generate an error if a relative branch
is out of range. This option does not affect the optimization
associated to the @samp{jbra}, @samp{jbsr} and @samp{jbXX} pseudo opcodes.
 
@cindex @samp{--force-long-branches}
@item --force-long-branches
The @samp{--force-long-branches} option forces the translation of
relative branches into absolute branches. This option does not affect
the optimization associated to the @samp{jbra}, @samp{jbsr} and
@samp{jbXX} pseudo opcodes.
 
@cindex @samp{--print-insn-syntax}
@item --print-insn-syntax
You can use the @samp{--print-insn-syntax} option to obtain the
syntax description of the instruction when an error is detected.
 
@cindex @samp{--print-opcodes}
@item --print-opcodes
The @samp{--print-opcodes} option prints the list of all the
instructions with their syntax. The first item of each line
represents the instruction name and the rest of the line indicates
the possible operands for that instruction. The list is printed
in alphabetical order. Once the list is printed @code{@value{AS}}
exits.
 
@cindex @samp{--generate-example}
@item --generate-example
The @samp{--generate-example} option is similar to @samp{--print-opcodes}
but it generates an example for each instruction instead.
@end table
 
@node M68HC11-Syntax
@section Syntax
 
@cindex M68HC11 syntax
@cindex syntax, M68HC11
 
In the M68HC11 syntax, the instruction name comes first and it may
be followed by one or several operands (up to three). Operands are
separated by comma (@samp{,}). In the normal mode,
@code{@value{AS}} will complain if too many operands are specified for
a given instruction. In the MRI mode (turned on with @samp{-M} option),
it will treat them as comments. Example:
 
@smallexample
inx
lda #23
bset 2,x #4
brclr *bot #8 foo
@end smallexample
 
@cindex line comment character, M68HC11
@cindex M68HC11 line comment character
The presence of a @samp{;} character or a @samp{!} character anywhere
on a line indicates the start of a comment that extends to the end of
that line.
 
A @samp{*} or a @samp{#} character at the start of a line also
introduces a line comment, but these characters do not work elsewhere
on the line. If the first character of the line is a @samp{#} then as
well as starting a comment, the line could also be logical line number
directive (@pxref{Comments}) or a preprocessor control command
(@pxref{Preprocessing}).
 
@cindex line separator, M68HC11
@cindex statement separator, M68HC11
@cindex M68HC11 line separator
The M68HC11 assembler does not currently support a line separator
character.
 
@cindex M68HC11 addressing modes
@cindex addressing modes, M68HC11
The following addressing modes are understood for 68HC11 and 68HC12:
@table @dfn
@item Immediate
@samp{#@var{number}}
 
@item Address Register
@samp{@var{number},X}, @samp{@var{number},Y}
 
The @var{number} may be omitted in which case 0 is assumed.
 
@item Direct Addressing mode
@samp{*@var{symbol}}, or @samp{*@var{digits}}
 
@item Absolute
@samp{@var{symbol}}, or @samp{@var{digits}}
@end table
 
The M68HC12 has other more complex addressing modes. All of them
are supported and they are represented below:
 
@table @dfn
@item Constant Offset Indexed Addressing Mode
@samp{@var{number},@var{reg}}
 
The @var{number} may be omitted in which case 0 is assumed.
The register can be either @samp{X}, @samp{Y}, @samp{SP} or
@samp{PC}. The assembler will use the smaller post-byte definition
according to the constant value (5-bit constant offset, 9-bit constant
offset or 16-bit constant offset). If the constant is not known by
the assembler it will use the 16-bit constant offset post-byte and the value
will be resolved at link time.
 
@item Offset Indexed Indirect
@samp{[@var{number},@var{reg}]}
 
The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}.
 
@item Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement
@samp{@var{number},-@var{reg}}
@samp{@var{number},+@var{reg}}
@samp{@var{number},@var{reg}-}
@samp{@var{number},@var{reg}+}
 
The number must be in the range @samp{-8}..@samp{+8} and must not be 0.
The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}.
 
@item Accumulator Offset
@samp{@var{acc},@var{reg}}
 
The accumulator register can be either @samp{A}, @samp{B} or @samp{D}.
The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}.
 
@item Accumulator D offset indexed-indirect
@samp{[D,@var{reg}]}
 
The register can be either @samp{X}, @samp{Y}, @samp{SP} or @samp{PC}.
 
@end table
 
For example:
 
@smallexample
ldab 1024,sp
ldd [10,x]
orab 3,+x
stab -2,y-
ldx a,pc
sty [d,sp]
@end smallexample
 
 
@node M68HC11-Modifiers
@section Symbolic Operand Modifiers
 
@cindex M68HC11 modifiers
@cindex syntax, M68HC11
 
The assembler supports several modifiers when using symbol addresses
in 68HC11 and 68HC12 instruction operands. The general syntax is
the following:
 
@smallexample
%modifier(symbol)
@end smallexample
 
@table @code
@cindex symbol modifiers
@item %addr
This modifier indicates to the assembler and linker to use
the 16-bit physical address corresponding to the symbol. This is intended
to be used on memory window systems to map a symbol in the memory bank window.
If the symbol is in a memory expansion part, the physical address
corresponds to the symbol address within the memory bank window.
If the symbol is not in a memory expansion part, this is the symbol address
(using or not using the %addr modifier has no effect in that case).
 
@item %page
This modifier indicates to use the memory page number corresponding
to the symbol. If the symbol is in a memory expansion part, its page
number is computed by the linker as a number used to map the page containing
the symbol in the memory bank window. If the symbol is not in a memory
expansion part, the page number is 0.
 
@item %hi
This modifier indicates to use the 8-bit high part of the physical
address of the symbol.
 
@item %lo
This modifier indicates to use the 8-bit low part of the physical
address of the symbol.
 
@end table
 
For example a 68HC12 call to a function @samp{foo_example} stored in memory
expansion part could be written as follows:
 
@smallexample
call %addr(foo_example),%page(foo_example)
@end smallexample
 
and this is equivalent to
 
@smallexample
call foo_example
@end smallexample
 
And for 68HC11 it could be written as follows:
 
@smallexample
ldab #%page(foo_example)
stab _page_switch
jsr %addr(foo_example)
@end smallexample
 
@node M68HC11-Directives
@section Assembler Directives
 
@cindex assembler directives, M68HC11
@cindex assembler directives, M68HC12
@cindex M68HC11 assembler directives
@cindex M68HC12 assembler directives
 
The 68HC11 and 68HC12 version of @code{@value{AS}} have the following
specific assembler directives:
 
@table @code
@item .relax
@cindex assembler directive .relax, M68HC11
@cindex M68HC11 assembler directive .relax
The relax directive is used by the @samp{GNU Compiler} to emit a specific
relocation to mark a group of instructions for linker relaxation.
The sequence of instructions within the group must be known to the linker
so that relaxation can be performed.
 
@item .mode [mshort|mlong|mshort-double|mlong-double]
@cindex assembler directive .mode, M68HC11
@cindex M68HC11 assembler directive .mode
This directive specifies the ABI. It overrides the @samp{-mshort},
@samp{-mlong}, @samp{-mshort-double} and @samp{-mlong-double} options.
 
@item .far @var{symbol}
@cindex assembler directive .far, M68HC11
@cindex M68HC11 assembler directive .far
This directive marks the symbol as a @samp{far} symbol meaning that it
uses a @samp{call/rtc} calling convention as opposed to @samp{jsr/rts}.
During a final link, the linker will identify references to the @samp{far}
symbol and will verify the proper calling convention.
 
@item .interrupt @var{symbol}
@cindex assembler directive .interrupt, M68HC11
@cindex M68HC11 assembler directive .interrupt
This directive marks the symbol as an interrupt entry point.
This information is then used by the debugger to correctly unwind the
frame across interrupts.
 
@item .xrefb @var{symbol}
@cindex assembler directive .xrefb, M68HC11
@cindex M68HC11 assembler directive .xrefb
This directive is defined for compatibility with the
@samp{Specification for Motorola 8 and 16-Bit Assembly Language Input
Standard} and is ignored.
 
@end table
 
@node M68HC11-Float
@section Floating Point
 
@cindex floating point, M68HC11
@cindex M68HC11 floating point
Packed decimal (P) format floating literals are not supported.
Feel free to add the code!
 
The floating point formats generated by directives are these.
 
@table @code
@cindex @code{float} directive, M68HC11
@item .float
@code{Single} precision floating point constants.
 
@cindex @code{double} directive, M68HC11
@item .double
@code{Double} precision floating point constants.
 
@cindex @code{extend} directive M68HC11
@cindex @code{ldouble} directive M68HC11
@item .extend
@itemx .ldouble
@code{Extended} precision (@code{long double}) floating point constants.
@end table
 
@need 2000
@node M68HC11-opcodes
@section Opcodes
 
@cindex M68HC11 opcodes
@cindex opcodes, M68HC11
@cindex instruction set, M68HC11
 
@menu
* M68HC11-Branch:: Branch Improvement
@end menu
 
@node M68HC11-Branch
@subsection Branch Improvement
 
@cindex pseudo-opcodes, M68HC11
@cindex M68HC11 pseudo-opcodes
@cindex branch improvement, M68HC11
@cindex M68HC11 branch improvement
 
Certain pseudo opcodes are permitted for branch instructions.
They expand to the shortest branch instruction that reach the
target. Generally these mnemonics are made by prepending @samp{j} to
the start of Motorola mnemonic. These pseudo opcodes are not affected
by the @samp{--short-branches} or @samp{--force-long-branches} options.
 
The following table summarizes the pseudo-operations.
 
@smallexample
Displacement Width
+-------------------------------------------------------------+
| Options |
| --short-branches --force-long-branches |
+--------------------------+----------------------------------+
Op |BYTE WORD | BYTE WORD |
+--------------------------+----------------------------------+
bsr | bsr <pc-rel> <error> | jsr <abs> |
bra | bra <pc-rel> <error> | jmp <abs> |
jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> |
jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> |
bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> |
jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> |
| jmp <abs> | |
+--------------------------+----------------------------------+
XX: condition
NX: negative of condition XX
 
@end smallexample
 
@table @code
@item jbsr
@itemx jbra
These are the simplest jump pseudo-operations; they always map to one
particular machine instruction, depending on the displacement to the
branch target.
 
@item jb@var{XX}
Here, @samp{jb@var{XX}} stands for an entire family of pseudo-operations,
where @var{XX} is a conditional branch or condition-code test. The full
list of pseudo-ops in this family is:
@smallexample
jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo
jbcs jbne jblt jble jbls jbvc jbmi
@end smallexample
 
For the cases of non-PC relative displacements and long displacements,
@code{@value{AS}} issues a longer code fragment in terms of
@var{NX}, the opposite condition to @var{XX}. For example, for the
non-PC relative case:
@smallexample
jb@var{XX} foo
@end smallexample
gives
@smallexample
b@var{NX}s oof
jmp foo
oof:
@end smallexample
 
@end table
 
 
/binutils/gas/doc/c-m68k.texi
0,0 → 1,637
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003,
@c 2004, 2006, 2007, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node M68K-Dependent
@chapter M680x0 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter M680x0 Dependent Features
@end ifclear
 
@cindex M680x0 support
@menu
* M68K-Opts:: M680x0 Options
* M68K-Syntax:: Syntax
* M68K-Moto-Syntax:: Motorola Syntax
* M68K-Float:: Floating Point
* M68K-Directives:: 680x0 Machine Directives
* M68K-opcodes:: Opcodes
@end menu
 
@node M68K-Opts
@section M680x0 Options
 
@cindex options, M680x0
@cindex M680x0 options
The Motorola 680x0 version of @code{@value{AS}} has a few machine
dependent options:
 
@table @samp
 
@cindex @samp{-march=} command line option, M680x0
@item -march=@var{architecture}
This option specifies a target architecture. The following
architectures are recognized:
@code{68000},
@code{68010},
@code{68020},
@code{68030},
@code{68040},
@code{68060},
@code{cpu32},
@code{isaa},
@code{isaaplus},
@code{isab},
@code{isac} and
@code{cfv4e}.
 
 
@cindex @samp{-mcpu=} command line option, M680x0
@item -mcpu=@var{cpu}
This option specifies a target cpu. When used in conjunction with the
@option{-march} option, the cpu must be within the specified
architecture. Also, the generic features of the architecture are used
for instruction generation, rather than those of the specific chip.
 
@cindex @samp{-m[no-]68851} command line option, M680x0
@cindex @samp{-m[no-]68881} command line option, M680x0
@cindex @samp{-m[no-]div} command line option, M680x0
@cindex @samp{-m[no-]usp} command line option, M680x0
@cindex @samp{-m[no-]float} command line option, M680x0
@cindex @samp{-m[no-]mac} command line option, M680x0
@cindex @samp{-m[no-]emac} command line option, M680x0
@item -m[no-]68851
@itemx -m[no-]68881
@itemx -m[no-]div
@itemx -m[no-]usp
@itemx -m[no-]float
@itemx -m[no-]mac
@itemx -m[no-]emac
 
Enable or disable various architecture specific features. If a chip
or architecture by default supports an option (for instance
@option{-march=isaaplus} includes the @option{-mdiv} option),
explicitly disabling the option will override the default.
 
@cindex @samp{-l} option, M680x0
@item -l
You can use the @samp{-l} option to shorten the size of references to undefined
symbols. If you do not use the @samp{-l} option, references to undefined
symbols are wide enough for a full @code{long} (32 bits). (Since
@code{@value{AS}} cannot know where these symbols end up, @code{@value{AS}} can
only allocate space for the linker to fill in later. Since @code{@value{AS}}
does not know how far away these symbols are, it allocates as much space as it
can.) If you use this option, the references are only one word wide (16 bits).
This may be useful if you want the object file to be as small as possible, and
you know that the relevant symbols are always less than 17 bits away.
 
@cindex @samp{--register-prefix-optional} option, M680x0
@item --register-prefix-optional
For some configurations, especially those where the compiler normally
does not prepend an underscore to the names of user variables, the
assembler requires a @samp{%} before any use of a register name. This
is intended to let the assembler distinguish between C variables and
functions named @samp{a0} through @samp{a7}, and so on. The @samp{%} is
always accepted, but is not required for certain configurations, notably
@samp{sun3}. The @samp{--register-prefix-optional} option may be used
to permit omitting the @samp{%} even for configurations for which it is
normally required. If this is done, it will generally be impossible to
refer to C variables and functions with the same names as register
names.
 
@cindex @samp{--bitwise-or} option, M680x0
@item --bitwise-or
Normally the character @samp{|} is treated as a comment character, which
means that it can not be used in expressions. The @samp{--bitwise-or}
option turns @samp{|} into a normal character. In this mode, you must
either use C style comments, or start comments with a @samp{#} character
at the beginning of a line.
 
@cindex @samp{--base-size-default-16}
@cindex @samp{--base-size-default-32}
@item --base-size-default-16 --base-size-default-32
If you use an addressing mode with a base register without specifying
the size, @code{@value{AS}} will normally use the full 32 bit value.
For example, the addressing mode @samp{%a0@@(%d0)} is equivalent to
@samp{%a0@@(%d0:l)}. You may use the @samp{--base-size-default-16}
option to tell @code{@value{AS}} to default to using the 16 bit value.
In this case, @samp{%a0@@(%d0)} is equivalent to @samp{%a0@@(%d0:w)}.
You may use the @samp{--base-size-default-32} option to restore the
default behaviour.
 
@cindex @samp{--disp-size-default-16}
@cindex @samp{--disp-size-default-32}
@item --disp-size-default-16 --disp-size-default-32
If you use an addressing mode with a displacement, and the value of the
displacement is not known, @code{@value{AS}} will normally assume that
the value is 32 bits. For example, if the symbol @samp{disp} has not
been defined, @code{@value{AS}} will assemble the addressing mode
@samp{%a0@@(disp,%d0)} as though @samp{disp} is a 32 bit value. You may
use the @samp{--disp-size-default-16} option to tell @code{@value{AS}}
to instead assume that the displacement is 16 bits. In this case,
@code{@value{AS}} will assemble @samp{%a0@@(disp,%d0)} as though
@samp{disp} is a 16 bit value. You may use the
@samp{--disp-size-default-32} option to restore the default behaviour.
 
@cindex @samp{--pcrel}
@item --pcrel
Always keep branches PC-relative. In the M680x0 architecture all branches
are defined as PC-relative. However, on some processors they are limited
to word displacements maximum. When @code{@value{AS}} needs a long branch
that is not available, it normally emits an absolute jump instead. This
option disables this substitution. When this option is given and no long
branches are available, only word branches will be emitted. An error
message will be generated if a word branch cannot reach its target. This
option has no effect on 68020 and other processors that have long branches.
@pxref{M68K-Branch,,Branch Improvement}.
 
@cindex @samp{-m68000} and related options
@cindex architecture options, M680x0
@cindex M680x0 architecture options
@item -m68000
@code{@value{AS}} can assemble code for several different members of the
Motorola 680x0 family. The default depends upon how @code{@value{AS}}
was configured when it was built; normally, the default is to assemble
code for the 68020 microprocessor. The following options may be used to
change the default. These options control which instructions and
addressing modes are permitted. The members of the 680x0 family are
very similar. For detailed information about the differences, see the
Motorola manuals.
 
@table @samp
@item -m68000
@itemx -m68ec000
@itemx -m68hc000
@itemx -m68hc001
@itemx -m68008
@itemx -m68302
@itemx -m68306
@itemx -m68307
@itemx -m68322
@itemx -m68356
Assemble for the 68000. @samp{-m68008}, @samp{-m68302}, and so on are synonyms
for @samp{-m68000}, since the chips are the same from the point of view
of the assembler.
 
@item -m68010
Assemble for the 68010.
 
@item -m68020
@itemx -m68ec020
Assemble for the 68020. This is normally the default.
 
@item -m68030
@itemx -m68ec030
Assemble for the 68030.
 
@item -m68040
@itemx -m68ec040
Assemble for the 68040.
 
@item -m68060
@itemx -m68ec060
Assemble for the 68060.
 
@item -mcpu32
@itemx -m68330
@itemx -m68331
@itemx -m68332
@itemx -m68333
@itemx -m68334
@itemx -m68336
@itemx -m68340
@itemx -m68341
@itemx -m68349
@itemx -m68360
Assemble for the CPU32 family of chips.
 
@item -m5200
@itemx -m5202
@itemx -m5204
@itemx -m5206
@itemx -m5206e
@itemx -m521x
@itemx -m5249
@itemx -m528x
@itemx -m5307
@itemx -m5407
@itemx -m547x
@itemx -m548x
@itemx -mcfv4
@itemx -mcfv4e
Assemble for the ColdFire family of chips.
 
@item -m68881
@itemx -m68882
Assemble 68881 floating point instructions. This is the default for the
68020, 68030, and the CPU32. The 68040 and 68060 always support
floating point instructions.
 
@item -mno-68881
Do not assemble 68881 floating point instructions. This is the default
for 68000 and the 68010. The 68040 and 68060 always support floating
point instructions, even if this option is used.
 
@item -m68851
Assemble 68851 MMU instructions. This is the default for the 68020,
68030, and 68060. The 68040 accepts a somewhat different set of MMU
instructions; @samp{-m68851} and @samp{-m68040} should not be used
together.
 
@item -mno-68851
Do not assemble 68851 MMU instructions. This is the default for the
68000, 68010, and the CPU32. The 68040 accepts a somewhat different set
of MMU instructions.
@end table
@end table
 
@node M68K-Syntax
@section Syntax
 
@cindex @sc{mit}
This syntax for the Motorola 680x0 was developed at @sc{mit}.
 
@cindex M680x0 syntax
@cindex syntax, M680x0
@cindex M680x0 size modifiers
@cindex size modifiers, M680x0
The 680x0 version of @code{@value{AS}} uses instructions names and
syntax compatible with the Sun assembler. Intervening periods are
ignored; for example, @samp{movl} is equivalent to @samp{mov.l}.
 
In the following table @var{apc} stands for any of the address registers
(@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the
zero-address relative to the program counter (@samp{%zpc}), a suppressed
address register (@samp{%za0} through @samp{%za7}), or it may be omitted
entirely. The use of @var{size} means one of @samp{w} or @samp{l}, and
it may be omitted, along with the leading colon, unless a scale is also
specified. The use of @var{scale} means one of @samp{1}, @samp{2},
@samp{4}, or @samp{8}, and it may always be omitted along with the
leading colon.
 
@cindex M680x0 addressing modes
@cindex addressing modes, M680x0
The following addressing modes are understood:
@table @dfn
@item Immediate
@samp{#@var{number}}
 
@item Data Register
@samp{%d0} through @samp{%d7}
 
@item Address Register
@samp{%a0} through @samp{%a7}@*
@samp{%a7} is also known as @samp{%sp}, i.e., the Stack Pointer. @code{%a6}
is also known as @samp{%fp}, the Frame Pointer.
 
@item Address Register Indirect
@samp{%a0@@} through @samp{%a7@@}
 
@item Address Register Postincrement
@samp{%a0@@+} through @samp{%a7@@+}
 
@item Address Register Predecrement
@samp{%a0@@-} through @samp{%a7@@-}
 
@item Indirect Plus Offset
@samp{@var{apc}@@(@var{number})}
 
@item Index
@samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})}
 
The @var{number} may be omitted.
 
@item Postindex
@samp{@var{apc}@@(@var{number})@@(@var{onumber},@var{register}:@var{size}:@var{scale})}
 
The @var{onumber} or the @var{register}, but not both, may be omitted.
 
@item Preindex
@samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})@@(@var{onumber})}
 
The @var{number} may be omitted. Omitting the @var{register} produces
the Postindex addressing mode.
 
@item Absolute
@samp{@var{symbol}}, or @samp{@var{digits}}, optionally followed by
@samp{:b}, @samp{:w}, or @samp{:l}.
@end table
 
@node M68K-Moto-Syntax
@section Motorola Syntax
 
@cindex Motorola syntax for the 680x0
@cindex alternate syntax for the 680x0
 
The standard Motorola syntax for this chip differs from the syntax
already discussed (@pxref{M68K-Syntax,,Syntax}). @code{@value{AS}} can
accept Motorola syntax for operands, even if @sc{mit} syntax is used for
other operands in the same instruction. The two kinds of syntax are
fully compatible.
 
In the following table @var{apc} stands for any of the address registers
(@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the
zero-address relative to the program counter (@samp{%zpc}), or a
suppressed address register (@samp{%za0} through @samp{%za7}). The use
of @var{size} means one of @samp{w} or @samp{l}, and it may always be
omitted along with the leading dot. The use of @var{scale} means one of
@samp{1}, @samp{2}, @samp{4}, or @samp{8}, and it may always be omitted
along with the leading asterisk.
 
The following additional addressing modes are understood:
 
@table @dfn
@item Address Register Indirect
@samp{(%a0)} through @samp{(%a7)}@*
@samp{%a7} is also known as @samp{%sp}, i.e., the Stack Pointer. @code{%a6}
is also known as @samp{%fp}, the Frame Pointer.
 
@item Address Register Postincrement
@samp{(%a0)+} through @samp{(%a7)+}
 
@item Address Register Predecrement
@samp{-(%a0)} through @samp{-(%a7)}
 
@item Indirect Plus Offset
@samp{@var{number}(@var{%a0})} through @samp{@var{number}(@var{%a7})},
or @samp{@var{number}(@var{%pc})}.
 
The @var{number} may also appear within the parentheses, as in
@samp{(@var{number},@var{%a0})}. When used with the @var{pc}, the
@var{number} may be omitted (with an address register, omitting the
@var{number} produces Address Register Indirect mode).
 
@item Index
@samp{@var{number}(@var{apc},@var{register}.@var{size}*@var{scale})}
 
The @var{number} may be omitted, or it may appear within the
parentheses. The @var{apc} may be omitted. The @var{register} and the
@var{apc} may appear in either order. If both @var{apc} and
@var{register} are address registers, and the @var{size} and @var{scale}
are omitted, then the first register is taken as the base register, and
the second as the index register.
 
@item Postindex
@samp{([@var{number},@var{apc}],@var{register}.@var{size}*@var{scale},@var{onumber})}
 
The @var{onumber}, or the @var{register}, or both, may be omitted.
Either the @var{number} or the @var{apc} may be omitted, but not both.
 
@item Preindex
@samp{([@var{number},@var{apc},@var{register}.@var{size}*@var{scale}],@var{onumber})}
 
The @var{number}, or the @var{apc}, or the @var{register}, or any two of
them, may be omitted. The @var{onumber} may be omitted. The
@var{register} and the @var{apc} may appear in either order. If both
@var{apc} and @var{register} are address registers, and the @var{size}
and @var{scale} are omitted, then the first register is taken as the
base register, and the second as the index register.
@end table
 
@node M68K-Float
@section Floating Point
 
@cindex floating point, M680x0
@cindex M680x0 floating point
Packed decimal (P) format floating literals are not supported.
Feel free to add the code!
 
The floating point formats generated by directives are these.
 
@table @code
@cindex @code{float} directive, M680x0
@item .float
@code{Single} precision floating point constants.
 
@cindex @code{double} directive, M680x0
@item .double
@code{Double} precision floating point constants.
 
@cindex @code{extend} directive M680x0
@cindex @code{ldouble} directive M680x0
@item .extend
@itemx .ldouble
@code{Extended} precision (@code{long double}) floating point constants.
@end table
 
@node M68K-Directives
@section 680x0 Machine Directives
 
@cindex M680x0 directives
@cindex directives, M680x0
In order to be compatible with the Sun assembler the 680x0 assembler
understands the following directives.
 
@table @code
@cindex @code{data1} directive, M680x0
@item .data1
This directive is identical to a @code{.data 1} directive.
 
@cindex @code{data2} directive, M680x0
@item .data2
This directive is identical to a @code{.data 2} directive.
 
@cindex @code{even} directive, M680x0
@item .even
This directive is a special case of the @code{.align} directive; it
aligns the output to an even byte boundary.
 
@cindex @code{skip} directive, M680x0
@item .skip
This directive is identical to a @code{.space} directive.
 
@cindex @code{arch} directive, M680x0
@item .arch @var{name}
Select the target architecture and extension features. Valid values
for @var{name} are the same as for the @option{-march} command line
option. This directive cannot be specified after
any instructions have been assembled. If it is given multiple times,
or in conjunction with the @option{-march} option, all uses must be for
the same architecture and extension set.
 
@cindex @code{cpu} directive, M680x0
@item .cpu @var{name}
Select the target cpu. Valid valuse
for @var{name} are the same as for the @option{-mcpu} command line
option. This directive cannot be specified after
any instructions have been assembled. If it is given multiple times,
or in conjunction with the @option{-mopt} option, all uses must be for
the same cpu.
 
@end table
 
@need 2000
@node M68K-opcodes
@section Opcodes
 
@cindex M680x0 opcodes
@cindex opcodes, M680x0
@cindex instruction set, M680x0
@c doc@cygnus.com: I don't see any point in the following
@c paragraph. Bugs are bugs; how does saying this
@c help anyone?
@ignore
Danger: Several bugs have been found in the opcode table (and
fixed). More bugs may exist. Be careful when using obscure
instructions.
@end ignore
 
@menu
* M68K-Branch:: Branch Improvement
* M68K-Chars:: Special Characters
@end menu
 
@node M68K-Branch
@subsection Branch Improvement
 
@cindex pseudo-opcodes, M680x0
@cindex M680x0 pseudo-opcodes
@cindex branch improvement, M680x0
@cindex M680x0 branch improvement
Certain pseudo opcodes are permitted for branch instructions.
They expand to the shortest branch instruction that reach the
target. Generally these mnemonics are made by substituting @samp{j} for
@samp{b} at the start of a Motorola mnemonic.
 
The following table summarizes the pseudo-operations. A @code{*} flags
cases that are more fully described after the table:
 
@smallexample
Displacement
+------------------------------------------------------------
| 68020 68000/10, not PC-relative OK
Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP **
+------------------------------------------------------------
jbsr |bsrs bsrw bsrl jsr
jra |bras braw bral jmp
* jXX |bXXs bXXw bXXl bNXs;jmp
* dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp
fjXX | N/A fbXXw fbXXl N/A
 
XX: condition
NX: negative of condition XX
 
@end smallexample
@center @code{*}---see full description below
@center @code{**}---this expansion mode is disallowed by @samp{--pcrel}
 
@table @code
@item jbsr
@itemx jra
These are the simplest jump pseudo-operations; they always map to one
particular machine instruction, depending on the displacement to the
branch target. This instruction will be a byte or word branch is that
is sufficient. Otherwise, a long branch will be emitted if available.
If no long branches are available and the @samp{--pcrel} option is not
given, an absolute long jump will be emitted instead. If no long
branches are available, the @samp{--pcrel} option is given, and a word
branch cannot reach the target, an error message is generated.
 
In addition to standard branch operands, @code{@value{AS}} allows these
pseudo-operations to have all operands that are allowed for jsr and jmp,
substituting these instructions if the operand given is not valid for a
branch instruction.
 
@item j@var{XX}
Here, @samp{j@var{XX}} stands for an entire family of pseudo-operations,
where @var{XX} is a conditional branch or condition-code test. The full
list of pseudo-ops in this family is:
@smallexample
jhi jls jcc jcs jne jeq jvc
jvs jpl jmi jge jlt jgt jle
@end smallexample
 
Usually, each of these pseudo-operations expands to a single branch
instruction. However, if a word branch is not sufficient, no long branches
are available, and the @samp{--pcrel} option is not given, @code{@value{AS}}
issues a longer code fragment in terms of @var{NX}, the opposite condition
to @var{XX}. For example, under these conditions:
@smallexample
j@var{XX} foo
@end smallexample
gives
@smallexample
b@var{NX}s oof
jmp foo
oof:
@end smallexample
 
@item db@var{XX}
The full family of pseudo-operations covered here is
@smallexample
dbhi dbls dbcc dbcs dbne dbeq dbvc
dbvs dbpl dbmi dbge dblt dbgt dble
dbf dbra dbt
@end smallexample
 
Motorola @samp{db@var{XX}} instructions allow word displacements only. When
a word displacement is sufficient, each of these pseudo-operations expands
to the corresponding Motorola instruction. When a word displacement is not
sufficient and long branches are available, when the source reads
@samp{db@var{XX} foo}, @code{@value{AS}} emits
@smallexample
db@var{XX} oo1
bras oo2
oo1:bral foo
oo2:
@end smallexample
 
If, however, long branches are not available and the @samp{--pcrel} option is
not given, @code{@value{AS}} emits
@smallexample
db@var{XX} oo1
bras oo2
oo1:jmp foo
oo2:
@end smallexample
 
@item fj@var{XX}
This family includes
@smallexample
fjne fjeq fjge fjlt fjgt fjle fjf
fjt fjgl fjgle fjnge fjngl fjngle fjngt
fjnle fjnlt fjoge fjogl fjogt fjole fjolt
fjor fjseq fjsf fjsne fjst fjueq fjuge
fjugt fjule fjult fjun
@end smallexample
 
Each of these pseudo-operations always expands to a single Motorola
coprocessor branch instruction, word or long. All Motorola coprocessor
branch instructions allow both word and long displacements.
 
@end table
 
@node M68K-Chars
@subsection Special Characters
 
@cindex special characters, M680x0
 
@cindex M680x0 line comment character
@cindex line comment character, M680x0
@cindex comments, M680x0
Line comments are introduced by the @samp{|} character appearing
anywhere on a line, unless the @option{--bitwise-or} command line option
has been specified.
 
An asterisk (@samp{*}) as the first character on a line marks the
start of a line comment as well.
 
@cindex M680x0 immediate character
@cindex immediate character, M680x0
 
A hash character (@samp{#}) as the first character on a line also
marks the start of a line comment, but in this case it could also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}). If the hash character
appears elsewhere on a line it is used to introduce an immediate
value. (This is for compatibility with Sun's assembler).
 
@cindex M680x0 line separator
@cindex line separator, M680x0
 
Multiple statements on the same line can appear if they are separated
by the @samp{;} character.
/binutils/gas/doc/c-microblaze.texi
0,0 → 1,100
@c Copyright 2009, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node MicroBlaze-Dependent
@chapter MicroBlaze Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter MicroBlaze Dependent Features
@end ifclear
 
@cindex MicroBlaze architectures
The Xilinx MicroBlaze processor family includes several variants, all using
the same core instruction set. This chapter covers features of the @sc{gnu}
assembler that are specific to the MicroBlaze architecture. For details about
the MicroBlaze instruction set, please see the @cite{MicroBlaze Processor
Reference Guide (UG081)} available at www.xilinx.com.
 
@cindex MicroBlaze support
@menu
* MicroBlaze Directives:: Directives for MicroBlaze Processors.
* MicroBlaze Syntax:: Syntax for the MicroBlaze
@end menu
 
@node MicroBlaze Directives
@section Directives
@cindex MicroBlaze directives
A number of assembler directives are available for MicroBlaze.
 
@table @code
@item .data8 @var{expression},...
This directive is an alias for @code{.byte}. Each expression is assembled
into an eight-bit value.
 
@item .data16 @var{expression},...
This directive is an alias for @code{.hword}. Each expression is assembled
into an 16-bit value.
 
@item .data32 @var{expression},...
This directive is an alias for @code{.word}. Each expression is assembled
into an 32-bit value.
 
@item .ent @var{name}[,@var{label}]
This directive is an alias for @code{.func} denoting the start of function
@var{name} at (optional) @var{label}.
 
@item .end @var{name}[,@var{label}]
This directive is an alias for @code{.endfunc} denoting the end of function
@var{name}.
 
@item .gpword @var{label},...
This directive is an alias for @code{.rva}. The resolved address of @var{label}
is stored in the data section.
 
@item .weakext @var{label}
Declare that @var{label} is a weak external symbol.
 
@item .rodata
Switch to .rodata section. Equivalent to @code{.section .rodata}
 
@item .sdata2
Switch to .sdata2 section. Equivalent to @code{.section .sdata2}
 
@item .sdata
Switch to .sdata section. Equivalent to @code{.section .sdata}
 
@item .bss
Switch to .bss section. Equivalent to @code{.section .bss}
 
@item .sbss
Switch to .sbss section. Equivalent to @code{.section .sbss}
@end table
 
@node MicroBlaze Syntax
@section Syntax for the MicroBlaze
@menu
* MicroBlaze-Chars:: Special Characters
@end menu
 
@node MicroBlaze-Chars
@subsection Special Characters
 
@cindex line comment character, MicroBlaze
@cindex MicroBlaze line comment character
The presence of a @samp{#} on a line indicates the start of a comment
that extends to the end of the current line.
 
If a @samp{#} appears as the first character of a line, the whole line
is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a
preprocessor control command (@pxref{Preprocessing}).
 
@cindex line separator, MicroBlaze
@cindex statement separator, MicroBlaze
@cindex MicroBlaze line separator
The @samp{;} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-mmix.texi
0,0 → 1,589
@c Copyright 2001, 2002, 2003, 2006, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c MMIX description by Hans-Peter Nilsson, hp@bitrange.com
@ifset GENERIC
@page
@node MMIX-Dependent
@chapter MMIX Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter MMIX Dependent Features
@end ifclear
 
@cindex MMIX support
@menu
* MMIX-Opts:: Command-line Options
* MMIX-Expand:: Instruction expansion
* MMIX-Syntax:: Syntax
* MMIX-mmixal:: Differences to @code{mmixal} syntax and semantics
@end menu
 
@node MMIX-Opts
@section Command-line Options
 
@cindex options, MMIX
@cindex MMIX options
The MMIX version of @code{@value{AS}} has some machine-dependent options.
 
@cindex @samp{--fixed-special-register-names} command line option, MMIX
When @samp{--fixed-special-register-names} is specified, only the register
names specified in @ref{MMIX-Regs} are recognized in the instructions
@code{PUT} and @code{GET}.
 
@cindex @samp{--globalize-symbols} command line option, MMIX
You can use the @samp{--globalize-symbols} to make all symbols global.
This option is useful when splitting up a @code{mmixal} program into
several files.
 
@cindex @samp{--gnu-syntax} command line option, MMIX
The @samp{--gnu-syntax} turns off most syntax compatibility with
@code{mmixal}. Its usability is currently doubtful.
 
@cindex @samp{--relax} command line option, MMIX
The @samp{--relax} option is not fully supported, but will eventually make
the object file prepared for linker relaxation.
 
@cindex @samp{--no-predefined-syms} command line option, MMIX
If you want to avoid inadvertently calling a predefined symbol and would
rather get an error, for example when using @code{@value{AS}} with a
compiler or other machine-generated code, specify
@samp{--no-predefined-syms}. This turns off built-in predefined
definitions of all such symbols, including rounding-mode symbols, segment
symbols, @samp{BIT} symbols, and @code{TRAP} symbols used in @code{mmix}
``system calls''. It also turns off predefined special-register names,
except when used in @code{PUT} and @code{GET} instructions.
 
@cindex @samp{--no-expand} command line option, MMIX
By default, some instructions are expanded to fit the size of the operand
or an external symbol (@pxref{MMIX-Expand}). By passing
@samp{--no-expand}, no such expansion will be done, instead causing errors
at link time if the operand does not fit.
 
@cindex @samp{--no-merge-gregs} command line option, MMIX
The @code{mmixal} documentation (@pxref{mmixsite}) specifies that global
registers allocated with the @samp{GREG} directive (@pxref{MMIX-greg}) and
initialized to the same non-zero value, will refer to the same global
register. This isn't strictly enforceable in @code{@value{AS}} since the
final addresses aren't known until link-time, but it will do an effort
unless the @samp{--no-merge-gregs} option is specified. (Register merging
isn't yet implemented in @code{@value{LD}}.)
 
@cindex @samp{-x} command line option, MMIX
@code{@value{AS}} will warn every time it expands an instruction to fit an
operand unless the option @samp{-x} is specified. It is believed that
this behaviour is more useful than just mimicking @code{mmixal}'s
behaviour, in which instructions are only expanded if the @samp{-x} option
is specified, and assembly fails otherwise, when an instruction needs to
be expanded. It needs to be kept in mind that @code{mmixal} is both an
assembler and linker, while @code{@value{AS}} will expand instructions
that at link stage can be contracted. (Though linker relaxation isn't yet
implemented in @code{@value{LD}}.) The option @samp{-x} also imples
@samp{--linker-allocated-gregs}.
 
@cindex @samp{--no-pushj-stubs} command line option, MMIX
@cindex @samp{--no-stubs} command line option, MMIX
If instruction expansion is enabled, @code{@value{AS}} can expand a
@samp{PUSHJ} instruction into a series of instructions. The shortest
expansion is to not expand it, but just mark the call as redirectable to a
stub, which @code{@value{LD}} creates at link-time, but only if the
original @samp{PUSHJ} instruction is found not to reach the target. The
stub consists of the necessary instructions to form a jump to the target.
This happens if @code{@value{AS}} can assert that the @samp{PUSHJ}
instruction can reach such a stub. The option @samp{--no-pushj-stubs}
disables this shorter expansion, and the longer series of instructions is
then created at assembly-time. The option @samp{--no-stubs} is a synonym,
intended for compatibility with future releases, where generation of stubs
for other instructions may be implemented.
 
@cindex @samp{--linker-allocated-gregs} command line option, MMIX
Usually a two-operand-expression (@pxref{GREG-base}) without a matching
@samp{GREG} directive is treated as an error by @code{@value{AS}}. When
the option @samp{--linker-allocated-gregs} is in effect, they are instead
passed through to the linker, which will allocate as many global registers
as is needed.
 
@node MMIX-Expand
@section Instruction expansion
 
@cindex instruction expansion, MMIX
When @code{@value{AS}} encounters an instruction with an operand that is
either not known or does not fit the operand size of the instruction,
@code{@value{AS}} (and @code{@value{LD}}) will expand the instruction into
a sequence of instructions semantically equivalent to the operand fitting
the instruction. Expansion will take place for the following
instructions:
 
@table @asis
@item @samp{GETA}
Expands to a sequence of four instructions: @code{SETL}, @code{INCML},
@code{INCMH} and @code{INCH}. The operand must be a multiple of four.
@item Conditional branches
A branch instruction is turned into a branch with the complemented
condition and prediction bit over five instructions; four instructions
setting @code{$255} to the operand value, which like with @code{GETA} must
be a multiple of four, and a final @code{GO $255,$255,0}.
@item @samp{PUSHJ}
Similar to expansion for conditional branches; four instructions set
@code{$255} to the operand value, followed by a @code{PUSHGO $255,$255,0}.
@item @samp{JMP}
Similar to conditional branches and @code{PUSHJ}. The final instruction
is @code{GO $255,$255,0}.
@end table
 
The linker @code{@value{LD}} is expected to shrink these expansions for
code assembled with @samp{--relax} (though not currently implemented).
 
@node MMIX-Syntax
@section Syntax
 
The assembly syntax is supposed to be upward compatible with that
described in Sections 1.3 and 1.4 of @samp{The Art of Computer
Programming, Volume 1}. Draft versions of those chapters as well as other
MMIX information is located at
@anchor{mmixsite}@url{http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html}.
Most code examples from the mmixal package located there should work
unmodified when assembled and linked as single files, with a few
noteworthy exceptions (@pxref{MMIX-mmixal}).
 
Before an instruction is emitted, the current location is aligned to the
next four-byte boundary. If a label is defined at the beginning of the
line, its value will be the aligned value.
 
In addition to the traditional hex-prefix @samp{0x}, a hexadecimal number
can also be specified by the prefix character @samp{#}.
 
After all operands to an MMIX instruction or directive have been
specified, the rest of the line is ignored, treated as a comment.
 
@menu
* MMIX-Chars:: Special Characters
* MMIX-Symbols:: Symbols
* MMIX-Regs:: Register Names
* MMIX-Pseudos:: Assembler Directives
@end menu
 
@node MMIX-Chars
@subsection Special Characters
@cindex line comment characters, MMIX
@cindex MMIX line comment characters
 
The characters @samp{*} and @samp{#} are line comment characters; each
start a comment at the beginning of a line, but only at the beginning of a
line. A @samp{#} prefixes a hexadecimal number if found elsewhere on a
line. If a @samp{#} appears at the start of a line the whole line is
treated as a comment, but the line can also act as a logical line
number directive (@pxref{Comments}) or a preprocessor control command
(@pxref{Preprocessing}).
 
Two other characters, @samp{%} and @samp{!}, each start a comment anywhere
on the line. Thus you can't use the @samp{modulus} and @samp{not}
operators in expressions normally associated with these two characters.
 
A @samp{;} is a line separator, treated as a new-line, so separate
instructions can be specified on a single line.
 
@node MMIX-Symbols
@subsection Symbols
The character @samp{:} is permitted in identifiers. There are two
exceptions to it being treated as any other symbol character: if a symbol
begins with @samp{:}, it means that the symbol is in the global namespace
and that the current prefix should not be prepended to that symbol
(@pxref{MMIX-prefix}). The @samp{:} is then not considered part of the
symbol. For a symbol in the label position (first on a line), a @samp{:}
at the end of a symbol is silently stripped off. A label is permitted,
but not required, to be followed by a @samp{:}, as with many other
assembly formats.
 
The character @samp{@@} in an expression, is a synonym for @samp{.}, the
current location.
 
In addition to the common forward and backward local symbol formats
(@pxref{Symbol Names}), they can be specified with upper-case @samp{B} and
@samp{F}, as in @samp{8B} and @samp{9F}. A local label defined for the
current position is written with a @samp{H} appended to the number:
@smallexample
3H LDB $0,$1,2
@end smallexample
This and traditional local-label formats cannot be mixed: a label must be
defined and referred to using the same format.
 
There's a minor caveat: just as for the ordinary local symbols, the local
symbols are translated into ordinary symbols using control characters are
to hide the ordinal number of the symbol. Unfortunately, these symbols
are not translated back in error messages. Thus you may see confusing
error messages when local symbols are used. Control characters
@samp{\003} (control-C) and @samp{\004} (control-D) are used for the
MMIX-specific local-symbol syntax.
 
The symbol @samp{Main} is handled specially; it is always global.
 
By defining the symbols @samp{__.MMIX.start..text} and
@samp{__.MMIX.start..data}, the address of respectively the @samp{.text}
and @samp{.data} segments of the final program can be defined, though when
linking more than one object file, the code or data in the object file
containing the symbol is not guaranteed to be start at that position; just
the final executable. @xref{MMIX-loc}.
 
@node MMIX-Regs
@subsection Register names
@cindex register names, MMIX
@cindex MMIX register names
 
Local and global registers are specified as @samp{$0} to @samp{$255}.
The recognized special register names are @samp{rJ}, @samp{rA}, @samp{rB},
@samp{rC}, @samp{rD}, @samp{rE}, @samp{rF}, @samp{rG}, @samp{rH},
@samp{rI}, @samp{rK}, @samp{rL}, @samp{rM}, @samp{rN}, @samp{rO},
@samp{rP}, @samp{rQ}, @samp{rR}, @samp{rS}, @samp{rT}, @samp{rU},
@samp{rV}, @samp{rW}, @samp{rX}, @samp{rY}, @samp{rZ}, @samp{rBB},
@samp{rTT}, @samp{rWW}, @samp{rXX}, @samp{rYY} and @samp{rZZ}. A leading
@samp{:} is optional for special register names.
 
Local and global symbols can be equated to register names and used in
place of ordinary registers.
 
Similarly for special registers, local and global symbols can be used.
Also, symbols equated from numbers and constant expressions are allowed in
place of a special register, except when either of the options
@code{--no-predefined-syms} and @code{--fixed-special-register-names} are
specified. Then only the special register names above are allowed for the
instructions having a special register operand; @code{GET} and @code{PUT}.
 
@node MMIX-Pseudos
@subsection Assembler Directives
@cindex assembler directives, MMIX
@cindex pseudo-ops, MMIX
@cindex MMIX assembler directives
@cindex MMIX pseudo-ops
 
@table @code
@item LOC
@cindex assembler directive LOC, MMIX
@cindex pseudo-op LOC, MMIX
@cindex MMIX assembler directive LOC
@cindex MMIX pseudo-op LOC
 
@anchor{MMIX-loc}
The @code{LOC} directive sets the current location to the value of the
operand field, which may include changing sections. If the operand is a
constant, the section is set to either @code{.data} if the value is
@code{0x2000000000000000} or larger, else it is set to @code{.text}.
Within a section, the current location may only be changed to
monotonically higher addresses. A LOC expression must be a previously
defined symbol or a ``pure'' constant.
 
An example, which sets the label @var{prev} to the current location, and
updates the current location to eight bytes forward:
@smallexample
prev LOC @@+8
@end smallexample
 
When a LOC has a constant as its operand, a symbol
@code{__.MMIX.start..text} or @code{__.MMIX.start..data} is defined
depending on the address as mentioned above. Each such symbol is
interpreted as special by the linker, locating the section at that
address. Note that if multiple files are linked, the first object file
with that section will be mapped to that address (not necessarily the file
with the LOC definition).
 
@item LOCAL
@cindex assembler directive LOCAL, MMIX
@cindex pseudo-op LOCAL, MMIX
@cindex MMIX assembler directive LOCAL
@cindex MMIX pseudo-op LOCAL
 
@anchor{MMIX-local}
Example:
@smallexample
LOCAL external_symbol
LOCAL 42
.local asymbol
@end smallexample
 
This directive-operation generates a link-time assertion that the operand
does not correspond to a global register. The operand is an expression
that at link-time resolves to a register symbol or a number. A number is
treated as the register having that number. There is one restriction on
the use of this directive: the pseudo-directive must be placed in a
section with contents, code or data.
 
@item IS
@cindex assembler directive IS, MMIX
@cindex pseudo-op IS, MMIX
@cindex MMIX assembler directive IS
@cindex MMIX pseudo-op IS
 
@anchor{MMIX-is}
The @code{IS} directive:
@smallexample
asymbol IS an_expression
@end smallexample
sets the symbol @samp{asymbol} to @samp{an_expression}. A symbol may not
be set more than once using this directive. Local labels may be set using
this directive, for example:
@smallexample
5H IS @@+4
@end smallexample
 
@item GREG
@cindex assembler directive GREG, MMIX
@cindex pseudo-op GREG, MMIX
@cindex MMIX assembler directive GREG
@cindex MMIX pseudo-op GREG
 
@anchor{MMIX-greg}
This directive reserves a global register, gives it an initial value and
optionally gives it a symbolic name. Some examples:
 
@smallexample
areg GREG
breg GREG data_value
GREG data_buffer
.greg creg, another_data_value
@end smallexample
 
The symbolic register name can be used in place of a (non-special)
register. If a value isn't provided, it defaults to zero. Unless the
option @samp{--no-merge-gregs} is specified, non-zero registers allocated
with this directive may be eliminated by @code{@value{AS}}; another
register with the same value used in its place.
Any of the instructions
@samp{CSWAP},
@samp{GO},
@samp{LDA},
@samp{LDBU},
@samp{LDB},
@samp{LDHT},
@samp{LDOU},
@samp{LDO},
@samp{LDSF},
@samp{LDTU},
@samp{LDT},
@samp{LDUNC},
@samp{LDVTS},
@samp{LDWU},
@samp{LDW},
@samp{PREGO},
@samp{PRELD},
@samp{PREST},
@samp{PUSHGO},
@samp{STBU},
@samp{STB},
@samp{STCO},
@samp{STHT},
@samp{STOU},
@samp{STSF},
@samp{STTU},
@samp{STT},
@samp{STUNC},
@samp{SYNCD},
@samp{SYNCID},
can have a value nearby @anchor{GREG-base}an initial value in place of its
second and third operands. Here, ``nearby'' is defined as within the
range 0@dots{}255 from the initial value of such an allocated register.
 
@smallexample
buffer1 BYTE 0,0,0,0,0
buffer2 BYTE 0,0,0,0,0
@dots{}
GREG buffer1
LDOU $42,buffer2
@end smallexample
In the example above, the @samp{Y} field of the @code{LDOUI} instruction
(LDOU with a constant Z) will be replaced with the global register
allocated for @samp{buffer1}, and the @samp{Z} field will have the value
5, the offset from @samp{buffer1} to @samp{buffer2}. The result is
equivalent to this code:
@smallexample
buffer1 BYTE 0,0,0,0,0
buffer2 BYTE 0,0,0,0,0
@dots{}
tmpreg GREG buffer1
LDOU $42,tmpreg,(buffer2-buffer1)
@end smallexample
 
Global registers allocated with this directive are allocated in order
higher-to-lower within a file. Other than that, the exact order of
register allocation and elimination is undefined. For example, the order
is undefined when more than one file with such directives are linked
together. With the options @samp{-x} and @samp{--linker-allocated-gregs},
@samp{GREG} directives for two-operand cases like the one mentioned above
can be omitted. Sufficient global registers will then be allocated by the
linker.
 
@item BYTE
@cindex assembler directive BYTE, MMIX
@cindex pseudo-op BYTE, MMIX
@cindex MMIX assembler directive BYTE
@cindex MMIX pseudo-op BYTE
 
@anchor{MMIX-byte}
The @samp{BYTE} directive takes a series of operands separated by a comma.
If an operand is a string (@pxref{Strings}), each character of that string
is emitted as a byte. Other operands must be constant expressions without
forward references, in the range 0@dots{}255. If you need operands having
expressions with forward references, use @samp{.byte} (@pxref{Byte}). An
operand can be omitted, defaulting to a zero value.
 
@item WYDE
@itemx TETRA
@itemx OCTA
@cindex assembler directive WYDE, MMIX
@cindex pseudo-op WYDE, MMIX
@cindex MMIX assembler directive WYDE
@cindex MMIX pseudo-op WYDE
@cindex assembler directive TETRA, MMIX
@cindex pseudo-op TETRA, MMIX
@cindex MMIX assembler directive TETRA
@cindex MMIX pseudo-op TETRA
@cindex assembler directive OCTA, MMIX
@cindex pseudo-op OCTA, MMIX
@cindex MMIX assembler directive OCTA
@cindex MMIX pseudo-op OCTA
 
@anchor{MMIX-constants}
The directives @samp{WYDE}, @samp{TETRA} and @samp{OCTA} emit constants of
two, four and eight bytes size respectively. Before anything else happens
for the directive, the current location is aligned to the respective
constant-size boundary. If a label is defined at the beginning of the
line, its value will be that after the alignment. A single operand can be
omitted, defaulting to a zero value emitted for the directive. Operands
can be expressed as strings (@pxref{Strings}), in which case each
character in the string is emitted as a separate constant of the size
indicated by the directive.
 
@item PREFIX
@cindex assembler directive PREFIX, MMIX
@cindex pseudo-op PREFIX, MMIX
@cindex MMIX assembler directive PREFIX
@cindex MMIX pseudo-op PREFIX
 
@anchor{MMIX-prefix}
The @samp{PREFIX} directive sets a symbol name prefix to be prepended to
all symbols (except local symbols, @pxref{MMIX-Symbols}), that are not
prefixed with @samp{:}, until the next @samp{PREFIX} directive. Such
prefixes accumulate. For example,
@smallexample
PREFIX a
PREFIX b
c IS 0
@end smallexample
defines a symbol @samp{abc} with the value 0.
 
@item BSPEC
@itemx ESPEC
@cindex assembler directive BSPEC, MMIX
@cindex pseudo-op BSPEC, MMIX
@cindex MMIX assembler directive BSPEC
@cindex MMIX pseudo-op BSPEC
@cindex assembler directive ESPEC, MMIX
@cindex pseudo-op ESPEC, MMIX
@cindex MMIX assembler directive ESPEC
@cindex MMIX pseudo-op ESPEC
 
@anchor{MMIX-spec}
A pair of @samp{BSPEC} and @samp{ESPEC} directives delimit a section of
special contents (without specified semantics). Example:
@smallexample
BSPEC 42
TETRA 1,2,3
ESPEC
@end smallexample
The single operand to @samp{BSPEC} must be number in the range
0@dots{}255. The @samp{BSPEC} number 80 is used by the GNU binutils
implementation.
@end table
 
@node MMIX-mmixal
@section Differences to @code{mmixal}
@cindex mmixal differences
@cindex differences, mmixal
 
The binutils @code{@value{AS}} and @code{@value{LD}} combination has a few
differences in function compared to @code{mmixal} (@pxref{mmixsite}).
 
The replacement of a symbol with a GREG-allocated register
(@pxref{GREG-base}) is not handled the exactly same way in
@code{@value{AS}} as in @code{mmixal}. This is apparent in the
@code{mmixal} example file @code{inout.mms}, where different registers
with different offsets, eventually yielding the same address, are used in
the first instruction. This type of difference should however not affect
the function of any program unless it has specific assumptions about the
allocated register number.
 
Line numbers (in the @samp{mmo} object format) are currently not
supported.
 
Expression operator precedence is not that of mmixal: operator precedence
is that of the C programming language. It's recommended to use
parentheses to explicitly specify wanted operator precedence whenever more
than one type of operators are used.
 
The serialize unary operator @code{&}, the fractional division operator
@samp{//}, the logical not operator @code{!} and the modulus operator
@samp{%} are not available.
 
Symbols are not global by default, unless the option
@samp{--globalize-symbols} is passed. Use the @samp{.global} directive to
globalize symbols (@pxref{Global}).
 
Operand syntax is a bit stricter with @code{@value{AS}} than
@code{mmixal}. For example, you can't say @code{addu 1,2,3}, instead you
must write @code{addu $1,$2,3}.
 
You can't LOC to a lower address than those already visited
(i.e., ``backwards'').
 
A LOC directive must come before any emitted code.
 
Predefined symbols are visible as file-local symbols after use. (In the
ELF file, that is---the linked mmo file has no notion of a file-local
symbol.)
 
Some mapping of constant expressions to sections in LOC expressions is
attempted, but that functionality is easily confused and should be avoided
unless compatibility with @code{mmixal} is required. A LOC expression to
@samp{0x2000000000000000} or higher, maps to the @samp{.data} section and
lower addresses map to the @samp{.text} section (@pxref{MMIX-loc}).
 
The code and data areas are each contiguous. Sparse programs with
far-away LOC directives will take up the same amount of space as a
contiguous program with zeros filled in the gaps between the LOC
directives. If you need sparse programs, you might try and get the wanted
effect with a linker script and splitting up the code parts into sections
(@pxref{Section}). Assembly code for this, to be compatible with
@code{mmixal}, would look something like:
@smallexample
.if 0
LOC away_expression
.else
.section away,"ax"
.fi
@end smallexample
@code{@value{AS}} will not execute the LOC directive and @code{mmixal}
ignores the lines with @code{.}. This construct can be used generally to
help compatibility.
 
Symbols can't be defined twice--not even to the same value.
 
Instruction mnemonics are recognized case-insensitive, though the
@samp{IS} and @samp{GREG} pseudo-operations must be specified in
upper-case characters.
 
There's no unicode support.
 
The following is a list of programs in @samp{mmix.tar.gz}, available at
@url{http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html}, last
checked with the version dated 2001-08-25 (md5sum
c393470cfc86fac040487d22d2bf0172) that assemble with @code{mmixal} but do
not assemble with @code{@value{AS}}:
 
@table @code
@item silly.mms
LOC to a previous address.
@item sim.mms
Redefines symbol @samp{Done}.
@item test.mms
Uses the serial operator @samp{&}.
@end table
/binutils/gas/doc/c-msp430.texi
0,0 → 1,333
@c Copyright 2002, 2004, 2005, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node MSP430-Dependent
@chapter MSP 430 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter MSP 430 Dependent Features
@end ifclear
 
@cindex MSP 430 support
@cindex 430 support
@menu
* MSP430 Options:: Options
* MSP430 Syntax:: Syntax
* MSP430 Floating Point:: Floating Point
* MSP430 Directives:: MSP 430 Machine Directives
* MSP430 Opcodes:: Opcodes
* MSP430 Profiling Capability:: Profiling Capability
@end menu
 
@node MSP430 Options
@section Options
@cindex MSP 430 options (none)
@cindex options for MSP430 (none)
@table @code
 
@item -m
select the mpu arch. Currently has no effect.
@item -mP
enables polymorph instructions handler.
 
@item -mQ
enables relaxation at assembly time. DANGEROUS!
 
@end table
 
@node MSP430 Syntax
@section Syntax
@menu
* MSP430-Macros:: Macros
* MSP430-Chars:: Special Characters
* MSP430-Regs:: Register Names
* MSP430-Ext:: Assembler Extensions
@end menu
 
@node MSP430-Macros
@subsection Macros
 
@cindex Macros, MSP 430
@cindex MSP 430 macros
The macro syntax used on the MSP 430 is like that described in the MSP
430 Family Assembler Specification. Normal @code{@value{AS}}
macros should still work.
 
Additional built-in macros are:
 
@table @code
 
@item llo(exp)
Extracts least significant word from 32-bit expression 'exp'.
 
@item lhi(exp)
Extracts most significant word from 32-bit expression 'exp'.
 
@item hlo(exp)
Extracts 3rd word from 64-bit expression 'exp'.
 
@item hhi(exp)
Extracts 4rd word from 64-bit expression 'exp'.
 
@end table
 
They normally being used as an immediate source operand.
@smallexample
mov #llo(1), r10 ; == mov #1, r10
mov #lhi(1), r10 ; == mov #0, r10
@end smallexample
@node MSP430-Chars
@subsection Special Characters
 
@cindex line comment character, MSP 430
@cindex MSP 430 line comment character
A semicolon (@samp{;}) appearing anywhere on a line starts a comment
that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but it can also be a logical line number
directive (@pxref{Comments}) or a preprocessor control command
(@pxref{Preprocessing}).
 
@cindex line separator, MSP 430
@cindex statement separator, MSP 430
@cindex MSP 430 line separator
Multiple statements can appear on the same line provided that they are
separated by the @samp{@{} character.
 
@cindex identifiers, MSP 430
@cindex MSP 430 identifiers
The character @samp{$} in jump instructions indicates current location and
implemented only for TI syntax compatibility.
 
@node MSP430-Regs
@subsection Register Names
 
@cindex MSP 430 register names
@cindex register names, MSP 430
General-purpose registers are represented by predefined symbols of the
form @samp{r@var{N}} (for global registers), where @var{N} represents
a number between @code{0} and @code{15}. The leading
letters may be in either upper or lower case; for example, @samp{r13}
and @samp{R7} are both valid register names.
 
@cindex special purpose registers, MSP 430
Register names @samp{PC}, @samp{SP} and @samp{SR} cannot be used as register names
and will be treated as variables. Use @samp{r0}, @samp{r1}, and @samp{r2} instead.
 
 
@node MSP430-Ext
@subsection Assembler Extensions
@cindex MSP430 Assembler Extensions
 
@table @code
 
@item @@rN
As destination operand being treated as @samp{0(rn)}
 
@item 0(rN)
As source operand being treated as @samp{@@rn}
 
@item jCOND +N
Skips next N bytes followed by jump instruction and equivalent to
@samp{jCOND $+N+2}
 
@end table
 
Also, there are some instructions, which cannot be found in other assemblers.
These are branch instructions, which has different opcodes upon jump distance.
They all got PC relative addressing mode.
 
@table @code
@item beq label
A polymorph instruction which is @samp{jeq label} in case if jump distance
within allowed range for cpu's jump instruction. If not, this unrolls into
a sequence of
@smallexample
jne $+6
br label
@end smallexample
 
@item bne label
A polymorph instruction which is @samp{jne label} or @samp{jeq +4; br label}
 
@item blt label
A polymorph instruction which is @samp{jl label} or @samp{jge +4; br label}
 
@item bltn label
A polymorph instruction which is @samp{jn label} or @samp{jn +2; jmp +4; br label}
 
@item bltu label
A polymorph instruction which is @samp{jlo label} or @samp{jhs +2; br label}
 
@item bge label
A polymorph instruction which is @samp{jge label} or @samp{jl +4; br label}
 
@item bgeu label
A polymorph instruction which is @samp{jhs label} or @samp{jlo +4; br label}
 
@item bgt label
A polymorph instruction which is @samp{jeq +2; jge label} or @samp{jeq +6; jl +4; br label}
 
@item bgtu label
A polymorph instruction which is @samp{jeq +2; jhs label} or @samp{jeq +6; jlo +4; br label}
 
@item bleu label
A polymorph instruction which is @samp{jeq label; jlo label} or @samp{jeq +2; jhs +4; br label}
 
@item ble label
A polymorph instruction which is @samp{jeq label; jl label} or @samp{jeq +2; jge +4; br label}
 
@item jump label
A polymorph instruction which is @samp{jmp label} or @samp{br label}
@end table
 
 
@node MSP430 Floating Point
@section Floating Point
 
@cindex floating point, MSP 430 (@sc{ieee})
@cindex MSP 430 floating point (@sc{ieee})
The MSP 430 family uses @sc{ieee} 32-bit floating-point numbers.
 
@node MSP430 Directives
@section MSP 430 Machine Directives
 
@cindex machine directives, MSP 430
@cindex MSP 430 machine directives
@table @code
@cindex @code{file} directive, MSP 430
@item .file
This directive is ignored; it is accepted for compatibility with other
MSP 430 assemblers.
 
@quotation
@emph{Warning:} in other versions of the @sc{gnu} assembler, @code{.file} is
used for the directive called @code{.app-file} in the MSP 430 support.
@end quotation
 
@cindex @code{line} directive, MSP 430
@item .line
This directive is ignored; it is accepted for compatibility with other
MSP 430 assemblers.
 
@cindex @code{sect} directive, MSP 430
@item .arch
Currently this directive is ignored; it is accepted for compatibility with other
MSP 430 assemblers.
 
@cindex @code{profiler} directive, MSP 430
@item .profiler
This directive instructs assembler to add new profile entry to the object file.
 
@end table
 
@node MSP430 Opcodes
@section Opcodes
 
@cindex MSP 430 opcodes
@cindex opcodes for MSP 430
@code{@value{AS}} implements all the standard MSP 430 opcodes. No
additional pseudo-instructions are needed on this family.
 
For information on the 430 machine instruction set, see @cite{MSP430
User's Manual, document slau049d}, Texas Instrument, Inc.
 
@node MSP430 Profiling Capability
@section Profiling Capability
 
@cindex MSP 430 profiling capability
@cindex profiling capability for MSP 430
It is a performance hit to use gcc's profiling approach for this tiny target.
Even more -- jtag hardware facility does not perform any profiling functions.
However we've got gdb's built-in simulator where we can do anything.
 
We define new section @samp{.profiler} which holds all profiling information.
We define new pseudo operation @samp{.profiler} which will instruct assembler to
add new profile entry to the object file. Profile should take place at the
present address.
 
Pseudo operation format:
 
@samp{.profiler flags,function_to_profile [, cycle_corrector, extra]}
 
 
where:
 
@table @code
 
@table @code
 
@samp{flags} is a combination of the following characters:
 
@item s
function entry
@item x
function exit
@item i
function is in init section
@item f
function is in fini section
@item l
library call
@item c
libc standard call
@item d
stack value demand
@item I
interrupt service routine
@item P
prologue start
@item p
prologue end
@item E
epilogue start
@item e
epilogue end
@item j
long jump / sjlj unwind
@item a
an arbitrary code fragment
@item t
extra parameter saved (a constant value like frame size)
@end table
 
@item function_to_profile
a function address
@item cycle_corrector
a value which should be added to the cycle counter, zero if omitted.
@item extra
any extra parameter, zero if omitted.
 
@end table
 
For example:
@smallexample
.global fxx
.type fxx,@@function
fxx:
.LFrameOffset_fxx=0x08
.profiler "scdP", fxx ; function entry.
; we also demand stack value to be saved
push r11
push r10
push r9
push r8
.profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point
; (this is a prologue end)
; note, that spare var filled with
; the farme size
mov r15,r8
...
.profiler cdE,fxx ; check stack
pop r8
pop r9
pop r10
pop r11
.profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
ret ; cause 'ret' insn takes 3 cycles
@end smallexample
/binutils/gas/doc/c-mt.texi
0,0 → 1,71
@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@ifset GENERIC
@page
@node MT-Dependent
@chapter MT Dependent Features
@end ifset
 
@ifclear GENERIC
@node Machine Dependencies
@chapter MS1 Dependent Features
@end ifclear
 
@cindex MT support
@menu
* MT Options:: Options
* MY Syntax:: Syntax
@end menu
 
@node MT Options
@section Options
@cindex MT options (none)
@cindex options for MT (none)
 
@table @code
 
@cindex @code{-march=} command line option, MT
@item -march=@var{processor}
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
will not execute on the target processor. The following processor names are
recognized:
@code{ms1-64-001},
@code{ms1-16-002},
@code{ms1-16-003},
and @code{ms2}.
 
@cindex @code{-nosched} command line option, MT
@item -nosched
This option disables scheduling restriction checking.
 
@end table
 
@node MT Syntax
@section Syntax
@menu
* MT-Chars:: Special Characters
@end menu
 
@node MT-Chars
@subsection Special Characters
 
@cindex line comment character, MT
@cindex MT line comment character
The presence of a @samp{;} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, MT
@cindex statement separator, MT
@cindex MT line separator
The MT assembler does not currently support a line separator
character.
 
/binutils/gas/doc/c-ns32k.texi
0,0 → 1,77
@c Copyright 1991, 1992, 1993, 1994, 1995, 2002
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@ignore
@c FIXME! Stop ignoring when filled in.
@node 32x32
@chapter 32x32
 
@section Options
The 32x32 version of @code{@value{AS}} accepts a @samp{-m32032} option to
specify thiat it is compiling for a 32032 processor, or a
@samp{-m32532} to specify that it is compiling for a 32532 option.
The default (if neither is specified) is chosen when the assembler
is compiled.
 
@section Syntax
I don't know anything about the 32x32 syntax assembled by
@code{@value{AS}}. Someone who understands the processor (I've never seen
one) and the possible syntaxes should write this section.
 
@section Floating Point
The 32x32 uses @sc{ieee} floating point numbers, but @code{@value{AS}}
only creates single or double precision values. I don't know if the
32x32 understands extended precision numbers.
 
@section 32x32 Machine Directives
The 32x32 has no machine dependent directives.
 
@end ignore
 
@ifset GENERIC
@page
@node NS32K-Dependent
@chapter NS32K Dependent Features
@end ifset
 
@ifclear GENERIC
@node Machine Dependencies
@chapter NS32K Dependent Features
@end ifclear
 
@cindex N32K support
@menu
* NS32K Syntax:: Syntax
@end menu
 
 
@node NS32K Syntax
@section Syntax
@menu
* NS32K-Chars:: Special Characters
@end menu
 
@node NS32K-Chars
@subsection Special Characters
 
@cindex line comment character, NS32K
@cindex NS32K line comment character
The presence of a @samp{#} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
If Sequent compatibility has been configured into the assembler then
the @samp{|} character appearing as the first character on a line will
also indicate the start of a line comment.
 
@cindex line separator, NS32K
@cindex statement separator, NS32K
@cindex NS32K line separator
The @samp{;} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-pdp11.texi
0,0 → 1,357
@c Copyright 2001, 2002, 2006 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node PDP-11-Dependent
@chapter PDP-11 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter PDP-11 Dependent Features
@end ifclear
 
@cindex PDP-11 support
 
@menu
* PDP-11-Options:: Options
* PDP-11-Pseudos:: Assembler Directives
* PDP-11-Syntax:: DEC Syntax versus BSD Syntax
* PDP-11-Mnemonics:: Instruction Naming
* PDP-11-Synthetic:: Synthetic Instructions
@end menu
 
@node PDP-11-Options
@section Options
 
@cindex options for PDP-11
 
The PDP-11 version of @code{@value{AS}} has a rich set of machine
dependent options.
 
@subsection Code Generation Options
 
@table @code
@cindex -mpic
@cindex -mno-pic
@item -mpic | -mno-pic
Generate position-independent (or position-dependent) code.
 
The default is to generate position-independent code.
@end table
 
@subsection Instruction Set Extension Options
 
These options enables or disables the use of extensions over the base
line instruction set as introduced by the first PDP-11 CPU: the KA11.
Most options come in two variants: a @code{-m}@var{extension} that
enables @var{extension}, and a @code{-mno-}@var{extension} that disables
@var{extension}.
 
The default is to enable all extensions.
 
@table @code
@cindex -mall
@cindex -mall-extensions
@item -mall | -mall-extensions
Enable all instruction set extensions.
 
@cindex -mno-extensions
@item -mno-extensions
Disable all instruction set extensions.
 
@cindex -mcis
@cindex -mno-cis
@item -mcis | -mno-cis
Enable (or disable) the use of the commercial instruction set, which
consists of these instructions: @code{ADDNI}, @code{ADDN}, @code{ADDPI},
@code{ADDP}, @code{ASHNI}, @code{ASHN}, @code{ASHPI}, @code{ASHP},
@code{CMPCI}, @code{CMPC}, @code{CMPNI}, @code{CMPN}, @code{CMPPI},
@code{CMPP}, @code{CVTLNI}, @code{CVTLN}, @code{CVTLPI}, @code{CVTLP},
@code{CVTNLI}, @code{CVTNL}, @code{CVTNPI}, @code{CVTNP}, @code{CVTPLI},
@code{CVTPL}, @code{CVTPNI}, @code{CVTPN}, @code{DIVPI}, @code{DIVP},
@code{L2DR}, @code{L3DR}, @code{LOCCI}, @code{LOCC}, @code{MATCI},
@code{MATC}, @code{MOVCI}, @code{MOVC}, @code{MOVRCI}, @code{MOVRC},
@code{MOVTCI}, @code{MOVTC}, @code{MULPI}, @code{MULP}, @code{SCANCI},
@code{SCANC}, @code{SKPCI}, @code{SKPC}, @code{SPANCI}, @code{SPANC},
@code{SUBNI}, @code{SUBN}, @code{SUBPI}, and @code{SUBP}.
 
@cindex -mcsm
@cindex -mno-csm
@item -mcsm | -mno-csm
Enable (or disable) the use of the @code{CSM} instruction.
 
@cindex -meis
@cindex -mno-eis
@item -meis | -mno-eis
Enable (or disable) the use of the extended instruction set, which
consists of these instructions: @code{ASHC}, @code{ASH}, @code{DIV},
@code{MARK}, @code{MUL}, @code{RTT}, @code{SOB} @code{SXT}, and
@code{XOR}.
 
@cindex -mfis
@cindex -mno-fis
@cindex -mkev11
@cindex -mkev11
@cindex -mno-kev11
@item -mfis | -mkev11
@itemx -mno-fis | -mno-kev11
Enable (or disable) the use of the KEV11 floating-point instructions:
@code{FADD}, @code{FDIV}, @code{FMUL}, and @code{FSUB}.
 
@cindex -mfpp
@cindex -mno-fpp
@cindex -mfpu
@cindex -mno-fpu
@cindex -mfp-11
@cindex -mno-fp-11
@item -mfpp | -mfpu | -mfp-11
@itemx -mno-fpp | -mno-fpu | -mno-fp-11
Enable (or disable) the use of FP-11 floating-point instructions:
@code{ABSF}, @code{ADDF}, @code{CFCC}, @code{CLRF}, @code{CMPF},
@code{DIVF}, @code{LDCFF}, @code{LDCIF}, @code{LDEXP}, @code{LDF},
@code{LDFPS}, @code{MODF}, @code{MULF}, @code{NEGF}, @code{SETD},
@code{SETF}, @code{SETI}, @code{SETL}, @code{STCFF}, @code{STCFI},
@code{STEXP}, @code{STF}, @code{STFPS}, @code{STST}, @code{SUBF}, and
@code{TSTF}.
 
@cindex -mlimited-eis
@cindex -mno-limited-eis
@item -mlimited-eis | -mno-limited-eis
Enable (or disable) the use of the limited extended instruction set:
@code{MARK}, @code{RTT}, @code{SOB}, @code{SXT}, and @code{XOR}.
 
The -mno-limited-eis options also implies -mno-eis.
 
@cindex -mmfpt
@cindex -mno-mfpt
@item -mmfpt | -mno-mfpt
Enable (or disable) the use of the @code{MFPT} instruction.
 
@cindex -mmutiproc
@cindex -mno-mutiproc
@item -mmultiproc | -mno-multiproc
Enable (or disable) the use of multiprocessor instructions: @code{TSTSET} and
@code{WRTLCK}.
 
@cindex -mmxps
@cindex -mno-mxps
@item -mmxps | -mno-mxps
Enable (or disable) the use of the @code{MFPS} and @code{MTPS} instructions.
 
@cindex -mspl
@cindex -mno-spl
@item -mspl | -mno-spl
Enable (or disable) the use of the @code{SPL} instruction.
 
@cindex -mmicrocode
@cindex -mno-microcode
Enable (or disable) the use of the microcode instructions: @code{LDUB},
@code{MED}, and @code{XFC}.
@end table
 
@subsection CPU Model Options
 
These options enable the instruction set extensions supported by a
particular CPU, and disables all other extensions.
 
@table @code
@cindex -mka11
@item -mka11
KA11 CPU. Base line instruction set only.
 
@cindex -mkb11
@item -mkb11
KB11 CPU. Enable extended instruction set and @code{SPL}.
 
@cindex -mkd11a
@item -mkd11a
KD11-A CPU. Enable limited extended instruction set.
 
@cindex -mkd11b
@item -mkd11b
KD11-B CPU. Base line instruction set only.
 
@cindex -mkd11d
@item -mkd11d
KD11-D CPU. Base line instruction set only.
 
@cindex -mkd11e
@item -mkd11e
KD11-E CPU. Enable extended instruction set, @code{MFPS}, and @code{MTPS}.
 
@cindex -mkd11f
@cindex -mkd11h
@cindex -mkd11q
@item -mkd11f | -mkd11h | -mkd11q
KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended instruction set,
@code{MFPS}, and @code{MTPS}.
 
@cindex -mkd11k
@item -mkd11k
KD11-K CPU. Enable extended instruction set, @code{LDUB}, @code{MED},
@code{MFPS}, @code{MFPT}, @code{MTPS}, and @code{XFC}.
 
@cindex -mkd11z
@item -mkd11z
KD11-Z CPU. Enable extended instruction set, @code{CSM}, @code{MFPS},
@code{MFPT}, @code{MTPS}, and @code{SPL}.
 
@cindex -mf11
@item -mf11
F11 CPU. Enable extended instruction set, @code{MFPS}, @code{MFPT}, and
@code{MTPS}.
 
@cindex -mj11
@item -mj11
J11 CPU. Enable extended instruction set, @code{CSM}, @code{MFPS},
@code{MFPT}, @code{MTPS}, @code{SPL}, @code{TSTSET}, and @code{WRTLCK}.
 
@cindex -mt11
@item -mt11
T11 CPU. Enable limited extended instruction set, @code{MFPS}, and
@code{MTPS}.
@end table
 
@subsection Machine Model Options
 
These options enable the instruction set extensions supported by a
particular machine model, and disables all other extensions.
 
@table @code
@cindex -m11/03
@item -m11/03
Same as @code{-mkd11f}.
 
@cindex -m11/04
@item -m11/04
Same as @code{-mkd11d}.
 
@cindex -m11/05
@cindex -m11/10
@item -m11/05 | -m11/10
Same as @code{-mkd11b}.
 
@cindex -m11/15
@cindex -m11/20
@item -m11/15 | -m11/20
Same as @code{-mka11}.
 
@cindex -m11/21
@item -m11/21
Same as @code{-mt11}.
 
@cindex -m11/23
@cindex -m11/24
@item -m11/23 | -m11/24
Same as @code{-mf11}.
 
@cindex -m11/34
@item -m11/34
Same as @code{-mkd11e}.
 
@cindex -m11/34a
@item -m11/34a
Ame as @code{-mkd11e} @code{-mfpp}.
 
@cindex -m11/35
@cindex -m11/40
@item -m11/35 | -m11/40
Same as @code{-mkd11a}.
 
@cindex -m11/44
@item -m11/44
Same as @code{-mkd11z}.
 
@cindex -m11/45
@cindex -m11/50
@cindex -m11/55
@cindex -m11/70
@item -m11/45 | -m11/50 | -m11/55 | -m11/70
Same as @code{-mkb11}.
 
@cindex -m11/53
@cindex -m11/73
@cindex -m11/83
@cindex -m11/84
@cindex -m11/93
@cindex -m11/94
@item -m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94
Same as @code{-mj11}.
 
@cindex -m11/60
@item -m11/60
Same as @code{-mkd11k}.
@end table
 
@node PDP-11-Pseudos
@section Assembler Directives
 
The PDP-11 version of @code{@value{AS}} has a few machine
dependent assembler directives.
 
@table @code
@item .bss
Switch to the @code{bss} section.
 
@item .even
Align the location counter to an even number.
@end table
 
@node PDP-11-Syntax
@section PDP-11 Assembly Language Syntax
 
@cindex PDP-11 syntax
 
@cindex DEC syntax
@cindex BSD syntax
@code{@value{AS}} supports both DEC syntax and BSD syntax. The only
difference is that in DEC syntax, a @code{#} character is used to denote
an immediate constants, while in BSD syntax the character for this
purpose is @code{$}.
 
@cindex PDP-11 general-purpose register syntax
general-purpose registers are named @code{r0} through @code{r7}.
Mnemonic alternatives for @code{r6} and @code{r7} are @code{sp} and
@code{pc}, respectively.
 
@cindex PDP-11 floating-point register syntax
Floating-point registers are named @code{ac0} through @code{ac3}, or
alternatively @code{fr0} through @code{fr3}.
 
@cindex PDP-11 comments
Comments are started with a @code{#} or a @code{/} character, and extend
to the end of the line. (FIXME: clash with immediates?)
 
@cindex PDP-11 line separator
Multiple statements on the same line can be separated by the @samp{;} character.
 
@node PDP-11-Mnemonics
@section Instruction Naming
 
@cindex PDP-11 instruction naming
 
Some instructions have alternative names.
 
@table @code
@item BCC
@code{BHIS}
 
@item BCS
@code{BLO}
 
@item L2DR
@code{L2D}
 
@item L3DR
@code{L3D}
 
@item SYS
@code{TRAP}
@end table
 
@node PDP-11-Synthetic
@section Synthetic Instructions
 
The @code{JBR} and @code{J}@var{CC} synthetic instructions are not
supported yet.
/binutils/gas/doc/c-pj.texi
0,0 → 1,52
@c Copyright 1999, 2002, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node PJ-Dependent
@chapter picoJava Dependent Features
 
@cindex PJ support
@menu
* PJ Options:: Options
* PJ Syntax:: PJ Syntax
@end menu
 
@node PJ Options
@section Options
 
@cindex PJ options
@cindex options, PJ
@code{@value{AS}} has two additional command-line options for the picoJava
architecture.
@table @code
@item -ml
This option selects little endian data output.
 
@item -mb
This option selects big endian data output.
@end table
 
@node PJ Syntax
@section PJ Syntax
@menu
* PJ-Chars:: Special Characters
@end menu
 
@node PJ-Chars
@subsection Special Characters
 
@cindex line comment character, PJ
@cindex PJ line comment character
The presence of a @samp{!} or @samp{/} on a line indicates the start
of a comment that extends to the end of the current line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, PJ
@cindex statement separator, PJ
@cindex PJ line separator
The @samp{;} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-ppc.texi
0,0 → 1,215
@c Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c man end
@ifset GENERIC
@page
@node PPC-Dependent
@chapter PowerPC Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter PowerPC Dependent Features
@end ifclear
 
@cindex PowerPC support
@menu
* PowerPC-Opts:: Options
* PowerPC-Pseudo:: PowerPC Assembler Directives
* PowerPC-Syntax:: PowerPC Syntax
@end menu
 
@node PowerPC-Opts
@section Options
 
@cindex options for PowerPC
@cindex PowerPC options
@cindex architectures, PowerPC
@cindex PowerPC architectures
The PowerPC chip family includes several successive levels, using the same
core instruction set, but including a few additional instructions at
each level. There are exceptions to this however. For details on what
instructions each variant supports, please see the chip's architecture
reference manual.
 
The following table lists all available PowerPC options.
 
@c man begin OPTIONS
@table @gcctabopt
@item -a32
Generate ELF32 or XCOFF32.
 
@item -a64
Generate ELF64 or XCOFF64.
 
@item -K PIC
Set EF_PPC_RELOCATABLE_LIB in ELF flags.
 
@item -mpwrx | -mpwr2
Generate code for POWER/2 (RIOS2).
 
@item -mpwr
Generate code for POWER (RIOS1)
 
@item -m601
Generate code for PowerPC 601.
 
@item -mppc, -mppc32, -m603, -m604
Generate code for PowerPC 603/604.
 
@item -m403, -m405
Generate code for PowerPC 403/405.
 
@item -m440
Generate code for PowerPC 440. BookE and some 405 instructions.
 
@item -m464
Generate code for PowerPC 464.
 
@item -m476
Generate code for PowerPC 476.
 
@item -m7400, -m7410, -m7450, -m7455
Generate code for PowerPC 7400/7410/7450/7455.
 
@item -m750cl
Generate code for PowerPC 750CL.
 
@item -mppc64, -m620
Generate code for PowerPC 620/625/630.
 
@item -me500, -me500x2
Generate code for Motorola e500 core complex.
 
@item -me500mc
Generate code for Freescale e500mc core complex.
 
@item -me500mc64
Generate code for Freescale e500mc64 core complex.
 
@item -mspe
Generate code for Motorola SPE instructions.
 
@item -mtitan
Generate code for AppliedMicro Titan core complex.
 
@item -mppc64bridge
Generate code for PowerPC 64, including bridge insns.
 
@item -mbooke
Generate code for 32-bit BookE.
 
@item -ma2
Generate code for A2 architecture.
 
@item -me300
Generate code for PowerPC e300 family.
 
@item -maltivec
Generate code for processors with AltiVec instructions.
 
@item -mvsx
Generate code for processors with Vector-Scalar (VSX) instructions.
 
@item -mpower4, -mpwr4
Generate code for Power4 architecture.
 
@item -mpower5, -mpwr5, -mpwr5x
Generate code for Power5 architecture.
 
@item -mpower6, -mpwr6
Generate code for Power6 architecture.
 
@item -mpower7, -mpwr7
Generate code for Power7 architecture.
 
@item -mcell
Generate code for Cell Broadband Engine architecture.
 
@item -mcom
Generate code Power/PowerPC common instructions.
 
@item -many
Generate code for any architecture (PWR/PWRX/PPC).
 
@item -mregnames
Allow symbolic names for registers.
 
@item -mno-regnames
Do not allow symbolic names for registers.
 
@item -mrelocatable
Support for GCC's -mrelocatable option.
 
@item -mrelocatable-lib
Support for GCC's -mrelocatable-lib option.
 
@item -memb
Set PPC_EMB bit in ELF flags.
 
@item -mlittle, -mlittle-endian, -le
Generate code for a little endian machine.
 
@item -mbig, -mbig-endian, -be
Generate code for a big endian machine.
 
@item -msolaris
Generate code for Solaris.
 
@item -mno-solaris
Do not generate code for Solaris.
 
@item -nops=@var{count}
If an alignment directive inserts more than @var{count} nops, put a
branch at the beginning to skip execution of the nops.
@end table
@c man end
 
 
@node PowerPC-Pseudo
@section PowerPC Assembler Directives
 
@cindex directives for PowerPC
@cindex PowerPC directives
A number of assembler directives are available for PowerPC. The
following table is far from complete.
 
@table @code
@item .machine "string"
This directive allows you to change the machine for which code is
generated. @code{"string"} may be any of the -m cpu selection options
(without the -m) enclosed in double quotes, @code{"push"}, or
@code{"pop"}. @code{.machine "push"} saves the currently selected
cpu, which may be restored with @code{.machine "pop"}.
@end table
 
@node PowerPC-Syntax
@section PowerPC Syntax
@menu
* PowerPC-Chars:: Special Characters
@end menu
 
@node PowerPC-Chars
@subsection Special Characters
 
@cindex line comment character, PowerPC
@cindex PowerPC line comment character
The presence of a @samp{#} on a line indicates the start of a comment
that extends to the end of the current line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
If the assembler has been configured for the ppc-*-solaris* target
then the @samp{!} character also acts as a line comment character.
This can be disabled via the @option{-mno-solaris} command line
option.
 
@cindex line separator, PowerPC
@cindex statement separator, PowerPC
@cindex PowerPC line separator
The @samp{;} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-rl78.texi
0,0 → 1,120
@c Copyright 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node RL78-Dependent
@chapter RL78 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter RL78 Dependent Features
@end ifclear
 
@cindex RL78 support
@menu
* RL78-Opts:: RL78 Assembler Command Line Options
* RL78-Modifiers:: Symbolic Operand Modifiers
* RL78-Directives:: Assembler Directives
* RL78-Syntax:: Syntax
@end menu
 
@node RL78-Opts
@section RL78 Options
@cindex options, RL78
@cindex RL78 options
 
The Renesas RL78 port of @code{@value{AS}} has no target-specific
options.
 
@node RL78-Modifiers
@section Symbolic Operand Modifiers
 
@cindex RL78 modifiers
@cindex syntax, RL78
 
The RL78 has three modifiers that adjust the relocations used by the
linker:
 
@table @code
 
@item %lo16()
 
When loading a 20-bit (or wider) address into registers, this modifier
selects the 16 least significant bits.
 
@smallexample
movw ax,#%lo16(_sym)
@end smallexample
 
@item %hi16()
 
When loading a 20-bit (or wider) address into registers, this modifier
selects the 16 most significant bits.
 
@smallexample
movw ax,#%hi16(_sym)
@end smallexample
 
@item %hi8()
 
When loading a 20-bit (or wider) address into registers, this modifier
selects the 8 bits that would go into CS or ES (i.e. bits 23..16).
 
@smallexample
mov es, #%hi8(_sym)
@end smallexample
 
@end table
 
@node RL78-Directives
@section Assembler Directives
 
@cindex assembler directives, RL78
@cindex RL78 assembler directives
 
In addition to the common directives, the RL78 adds these:
 
@table @code
 
@item .double
Output a constant in ``double'' format, which is a 32-bit floating
point value on RL78.
 
@item .bss
Select the BSS section.
 
@item .3byte
Output a constant value in a three byte format.
 
@item .int
@itemx .word
Output a constant value in a four byte format.
 
@end table
 
@node RL78-Syntax
@section Syntax for the RL78
@menu
* RL78-Chars:: Special Characters
@end menu
 
@node RL78-Chars
@subsection Special Characters
 
@cindex line comment character, RL78
@cindex RL78 line comment character
The presence of a @samp{;} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, RL78
@cindex statement separator, RL78
@cindex RL78 line separator
The @samp{|} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-rx.texi
0,0 → 1,208
@c Copyright 2008, 2009, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node RX-Dependent
@chapter RX Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter RX Dependent Features
@end ifclear
 
@cindex RX support
@menu
* RX-Opts:: RX Assembler Command Line Options
* RX-Modifiers:: Symbolic Operand Modifiers
* RX-Directives:: Assembler Directives
* RX-Float:: Floating Point
* RX-Syntax:: Syntax
@end menu
 
@node RX-Opts
@section RX Options
@cindex options, RX
@cindex RX options
 
The Renesas RX port of @code{@value{AS}} has a few target specfic
command line options:
 
@table @code
 
@cindex @samp{-m32bit-doubles}
@item -m32bit-doubles
This option controls the ABI and indicates to use a 32-bit float ABI.
It has no effect on the assembled instructions, but it does influence
the behaviour of the @samp{.double} pseudo-op.
This is the default.
 
@cindex @samp{-m64bit-doubles}
@item -m64bit-doubles
This option controls the ABI and indicates to use a 64-bit float ABI.
It has no effect on the assembled instructions, but it does influence
the behaviour of the @samp{.double} pseudo-op.
 
@cindex @samp{-mbig-endian}
@item -mbig-endian
This option controls the ABI and indicates to use a big-endian data
ABI. It has no effect on the assembled instructions, but it does
influence the behaviour of the @samp{.short}, @samp{.hword}, @samp{.int},
@samp{.word}, @samp{.long}, @samp{.quad} and @samp{.octa} pseudo-ops.
 
@cindex @samp{-mlittle-endian}
@item -mlittle-endian
This option controls the ABI and indicates to use a little-endian data
ABI. It has no effect on the assembled instructions, but it does
influence the behaviour of the @samp{.short}, @samp{.hword}, @samp{.int},
@samp{.word}, @samp{.long}, @samp{.quad} and @samp{.octa} pseudo-ops.
This is the default.
 
@cindex @samp{-muse-conventional-section-names}
@item -muse-conventional-section-names
This option controls the default names given to the code (.text),
initialised data (.data) and uninitialised data sections (.bss).
 
@cindex @samp{-muse-renesas-section-names}
@item -muse-renesas-section-names
This option controls the default names given to the code (.P),
initialised data (.D_1) and uninitialised data sections (.B_1).
This is the default.
 
@cindex @samp{-msmall-data-limit}
@item -msmall-data-limit
This option tells the assembler that the small data limit feature of
the RX port of GCC is being used. This results in the assembler
generating an undefined reference to a symbol called @code{__gp} for
use by the relocations that are needed to support the small data limit
feature. This option is not enabled by default as it would otherwise
pollute the symbol table.
 
@cindex @samp{-mpid}
@item -mpid
This option tells the assembler that the position independent data of the
RX port of GCC is being used. This results in the assembler
generating an undefined reference to a symbol called @code{__pid_base},
and also setting the RX_PID flag bit in the e_flags field of the ELF
header of the object file.
 
@cindex @samp{-mint-register}
@item -mint-register=@var{num}
This option tells the assembler how many registers have been reserved
for use by interrupt handlers. This is needed in order to compute the
correct values for the @code{%gpreg} and @code{%pidreg} meta registers.
 
@end table
 
@node RX-Modifiers
@section Symbolic Operand Modifiers
 
@cindex RX modifiers
@cindex syntax, RX
@cindex %gp
 
The assembler supports one modifier when using symbol addresses
in RX instruction operands. The general syntax is the following:
 
@smallexample
%gp(symbol)
@end smallexample
 
The modifier returns the offset from the @var{__gp} symbol to the
specified symbol as a 16-bit value. The intent is that this offset
should be used in a register+offset move instruction when generating
references to small data. Ie, like this:
 
@smallexample
mov.W %gp(_foo)[%gpreg], r1
@end smallexample
 
The assembler also supports two meta register names which can be used
to refer to registers whose values may not be known to the
programmer. These meta register names are:
 
@table @code
 
@cindex @samp{%gpreg}
@item %gpreg
The small data address register.
 
@cindex @samp{%pidreg}
@item %pidreg
The PID base address register.
 
@end table
 
Both registers normally have the value r13, but this can change if
some registers have been reserved for use by interrupt handlers or if
both the small data limit and position independent data features are
being used at the same time.
 
@node RX-Directives
@section Assembler Directives
 
@cindex assembler directives, RX
@cindex RX assembler directives
 
The RX version of @code{@value{AS}} has the following specific
assembler directives:
 
@table @code
 
@item .3byte
@cindex assembler directive .3byte, RX
@cindex RX assembler directive .3byte
Inserts a 3-byte value into the output file at the current location.
 
@end table
 
@node RX-Float
@section Floating Point
 
@cindex floating point, RX
@cindex RX floating point
 
The floating point formats generated by directives are these.
 
@table @code
@cindex @code{float} directive, RX
 
@item .float
@code{Single} precision (32-bit) floating point constants.
 
@cindex @code{double} directive, RX
@item .double
If the @option{-m64bit-doubles} command line option has been specified
then then @code{double} directive generates @code{double} precision
(64-bit) floating point constants, otherwise it generates
@code{single} precision (32-bit) floating point constants. To force
the generation of 64-bit floating point constants used the @code{dc.d}
directive instead.
 
@end table
 
@node RX-Syntax
@section Syntax for the RX
@menu
* RX-Chars:: Special Characters
@end menu
 
@node RX-Chars
@subsection Special Characters
 
@cindex line comment character, RX
@cindex RX line comment character
The presence of a @samp{;} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, RX
@cindex statement separator, RX
@cindex RX line separator
The @samp{!} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-s390.texi
0,0 → 1,887
@c Copyright 2009, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node S/390-Dependent
@chapter IBM S/390 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter IBM S/390 Dependent Features
@end ifclear
 
@cindex s390 support
 
The s390 version of @code{@value{AS}} supports two architectures modes
and seven chip levels. The architecture modes are the Enterprise System
Architecture (ESA) and the newer z/Architecture mode. The chip levels
are g5, g6, z900, z990, z9-109, z9-ec, z10 and z196.
 
@menu
* s390 Options:: Command-line Options.
* s390 Characters:: Special Characters.
* s390 Syntax:: Assembler Instruction syntax.
* s390 Directives:: Assembler Directives.
* s390 Floating Point:: Floating Point.
@end menu
 
@node s390 Options
@section Options
@cindex options for s390
@cindex s390 options
 
The following table lists all available s390 specific options:
@table @code
@cindex @samp{-m31} option, s390
@cindex @samp{-m64} option, s390
@item -m31 | -m64
Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
 
These options are only available with the ELF object file format, and
require that the necessary BFD support has been included (on a 31-bit
platform you must add --enable-64-bit-bfd on the call to the configure
script to enable 64-bit usage and use s390x as target platform).
 
@cindex @samp{-mesa} option, s390
@cindex @samp{-mzarch} option, s390
@item -mesa | -mzarch
Select the architecture mode, either the Enterprise System Architecture
(esa) mode or the z/Architecture mode (zarch).
 
The 64-bit instructions are only available with the z/Architecture mode.
The combination of @samp{-m64} and @samp{-mesa} results in a warning
message.
 
@cindex @samp{-march=} option, s390
@item -march=@var{CPU}
This option specifies the target processor. The following processor names
are recognized:
@code{g5},
@code{g6},
@code{z900},
@code{z990},
@code{z9-109},
@code{z9-ec},
@code{z10} and
@code{z196}.
Assembling an instruction that is not supported on the target processor
results in an error message. Do not specify @code{g5} or @code{g6}
with @samp{-mzarch}.
 
@cindex @samp{-mregnames} option, s390
@item -mregnames
Allow symbolic names for registers.
 
@cindex @samp{-mno-regnames} option, s390
@item -mno-regnames
Do not allow symbolic names for registers.
 
@cindex @samp{-mwarn-areg-zero} option, s390
@item -mwarn-areg-zero
Warn whenever the operand for a base or index register has been specified
but evaluates to zero. This can indicate the misuse of general purpose
register 0 as an address register.
 
@end table
 
@node s390 Characters
@section Special Characters
@cindex line comment character, s390
@cindex s390 line comment character
 
@samp{#} is the line comment character.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, s390
@cindex statement separator, s390
@cindex s390 line separator
The @samp{;} character can be used instead of a newline to separate
statements.
 
@node s390 Syntax
@section Instruction syntax
@cindex instruction syntax, s390
@cindex s390 instruction syntax
 
The assembler syntax closely follows the syntax outlined in
Enterprise Systems Architecture/390 Principles of Operation (SA22-7201)
and the z/Architecture Principles of Operation (SA22-7832).
 
Each instruction has two major parts, the instruction mnemonic
and the instruction operands. The instruction format varies.
 
@menu
* s390 Register:: Register Naming
* s390 Mnemonics:: Instruction Mnemonics
* s390 Operands:: Instruction Operands
* s390 Formats:: Instruction Formats
* s390 Aliases:: Instruction Aliases
* s390 Operand Modifier:: Instruction Operand Modifier
* s390 Instruction Marker:: Instruction Marker
* s390 Literal Pool Entries:: Literal Pool Entries
@end menu
 
@node s390 Register
@subsection Register naming
@cindex register naming, s390
@cindex s390 register naming
 
The @code{@value{AS}} recognizes a number of predefined symbols for the
various processor registers. A register specification in one of the
instruction formats is an unsigned integer between 0 and 15. The specific
instruction and the position of the register in the instruction format
denotes the type of the register. The register symbols are prefixed with
@samp{%}:
 
@display
@multitable {%rN} {the 16 general purpose registers, 0 <= N <= 15}
@item %rN @tab the 16 general purpose registers, 0 <= N <= 15
@item %fN @tab the 16 floating point registers, 0 <= N <= 15
@item %aN @tab the 16 access registers, 0 <= N <= 15
@item %cN @tab the 16 control registers, 0 <= N <= 15
@item %lit @tab an alias for the general purpose register %r13
@item %sp @tab an alias for the general purpose register %r15
@end multitable
@end display
 
@node s390 Mnemonics
@subsection Instruction Mnemonics
@cindex instruction mnemonics, s390
@cindex s390 instruction mnemonics
 
All instructions documented in the Principles of Operation are supported
with the mnemonic and order of operands as described.
The instruction mnemonic identifies the instruction format
(@ref{s390 Formats}) and the specific operation code for the instruction.
For example, the @samp{lr} mnemonic denotes the instruction format @samp{RR}
with the operation code @samp{0x18}.
 
The definition of the various mnemonics follows a scheme, where the first
character usually hint at the type of the instruction:
 
@display
@multitable {sla, sll} {if r is the last character the instruction operates on registers}
@item a @tab add instruction, for example @samp{al} for add logical 32-bit
@item b @tab branch instruction, for example @samp{bc} for branch on condition
@item c @tab compare or convert instruction, for example @samp{cr} for compare
register 32-bit
@item d @tab divide instruction, for example @samp{dlr} devide logical register
64-bit to 32-bit
@item i @tab insert instruction, for example @samp{ic} insert character
@item l @tab load instruction, for example @samp{ltr} load and test register
@item mv @tab move instruction, for example @samp{mvc} move character
@item m @tab multiply instruction, for example @samp{mh} multiply halfword
@item n @tab and instruction, for example @samp{ni} and immediate
@item o @tab or instruction, for example @samp{oc} or character
@item sla, sll @tab shift left single instruction
@item sra, srl @tab shift right single instruction
@item st @tab store instruction, for example @samp{stm} store multiple
@item s @tab subtract instruction, for example @samp{slr} subtract
logical 32-bit
@item t @tab test or translate instruction, of example @samp{tm} test under mask
@item x @tab exclusive or instruction, for example @samp{xc} exclusive or
character
@end multitable
@end display
 
Certain characters at the end of the mnemonic may describe a property
of the instruction:
 
@display
@multitable {c} {if r is the last character the instruction operates on registers}
@item c @tab the instruction uses a 8-bit character operand
@item f @tab the instruction extends a 32-bit operand to 64 bit
@item g @tab the operands are treated as 64-bit values
@item h @tab the operand uses a 16-bit halfword operand
@item i @tab the instruction uses an immediate operand
@item l @tab the instruction uses unsigned, logical operands
@item m @tab the instruction uses a mask or operates on multiple values
@item r @tab if r is the last character, the instruction operates on registers
@item y @tab the instruction uses 20-bit displacements
@end multitable
@end display
 
There are many exceptions to the scheme outlined in the above lists, in
particular for the priviledged instructions. For non-priviledged
instruction it works quite well, for example the instruction @samp{clgfr}
c: compare instruction, l: unsigned operands, g: 64-bit operands,
f: 32- to 64-bit extension, r: register operands. The instruction compares
an 64-bit value in a register with the zero extended 32-bit value from
a second register.
For a complete list of all mnemonics see appendix B in the Principles
of Operation.
 
@node s390 Operands
@subsection Instruction Operands
@cindex instruction operands, s390
@cindex s390 instruction operands
 
Instruction operands can be grouped into three classes, operands located
in registers, immediate operands, and operands in storage.
 
A register operand can be located in general, floating-point, access,
or control register. The register is identified by a four-bit field.
The field containing the register operand is called the R field.
 
Immediate operands are contained within the instruction and can have
8, 16 or 32 bits. The field containing the immediate operand is called
the I field. Dependent on the instruction the I field is either signed
or unsigned.
 
A storage operand consists of an address and a length. The address of a
storage operands can be specified in any of these ways:
 
@itemize
@item The content of a single general R
@item The sum of the content of a general register called the base
register B plus the content of a displacement field D
@item The sum of the contents of two general registers called the
index register X and the base register B plus the content of a
displacement field
@item The sum of the current instruction address and a 32-bit signed
immediate field multiplied by two.
@end itemize
 
The length of a storage operand can be:
 
@itemize
@item Implied by the instruction
@item Specified by a bitmask
@item Specified by a four-bit or eight-bit length field L
@item Specified by the content of a general register
@end itemize
 
The notation for storage operand addresses formed from multiple fields is
as follows:
 
@table @code
@item Dn(Bn)
the address for operand number n is formed from the content of general
register Bn called the base register and the displacement field Dn.
@item Dn(Xn,Bn)
the address for operand number n is formed from the content of general
register Xn called the index register, general register Bn called the
base register and the displacement field Dn.
@item Dn(Ln,Bn)
the address for operand number n is formed from the content of general
regiser Bn called the base register and the displacement field Dn.
The length of the operand n is specified by the field Ln.
@end table
 
The base registers Bn and the index registers Xn of a storage operand can
be skipped. If Bn and Xn are skipped, a zero will be stored to the operand
field. The notation changes as follows:
 
@display
@multitable @columnfractions 0.30 0.30
@headitem full notation @tab short notation
@item Dn(0,Bn) @tab Dn(Bn)
@item Dn(0,0) @tab Dn
@item Dn(0) @tab Dn
@item Dn(Ln,0) @tab Dn(Ln)
@end multitable
@end display
 
 
@node s390 Formats
@subsection Instruction Formats
@cindex instruction formats, s390
@cindex s390 instruction formats
 
The Principles of Operation manuals lists 26 instruction formats where
some of the formats have multiple variants. For the @samp{.insn}
pseudo directive the assembler recognizes some of the formats.
Typically, the most general variant of the instruction format is used
by the @samp{.insn} directive.
 
The following table lists the abbreviations used in the table of
instruction formats:
 
@display
@multitable {OpCode / OpCd} {Displacement lower 12 bits for operand x.}
@item OpCode / OpCd @tab Part of the op code.
@item Bx @tab Base register number for operand x.
@item Dx @tab Displacement for operand x.
@item DLx @tab Displacement lower 12 bits for operand x.
@item DHx @tab Displacement higher 8-bits for operand x.
@item Rx @tab Register number for operand x.
@item Xx @tab Index register number for operand x.
@item Ix @tab Signed immediate for operand x.
@item Ux @tab Unsigned immediate for operand x.
@end multitable
@end display
 
An instruction is two, four, or six bytes in length and must be aligned
on a 2 byte boundary. The first two bits of the instruction specify the
length of the instruction, 00 indicates a two byte instruction, 01 and 10
indicates a four byte instruction, and 11 indicates a six byte instruction.
 
The following table lists the s390 instruction formats that are available
with the @samp{.insn} pseudo directive:
 
@table @code
@item E format
@verbatim
+-------------+
| OpCode |
+-------------+
0 15
@end verbatim
 
@item RI format: <insn> R1,I2
@verbatim
+--------+----+----+------------------+
| OpCode | R1 |OpCd| I2 |
+--------+----+----+------------------+
0 8 12 16 31
@end verbatim
 
@item RIE format: <insn> R1,R3,I2
@verbatim
+--------+----+----+------------------+--------+--------+
| OpCode | R1 | R3 | I2 |////////| OpCode |
+--------+----+----+------------------+--------+--------+
0 8 12 16 32 40 47
@end verbatim
 
@item RIL format: <insn> R1,I2
@verbatim
+--------+----+----+------------------------------------+
| OpCode | R1 |OpCd| I2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
@end verbatim
 
@item RILU format: <insn> R1,U2
@verbatim
+--------+----+----+------------------------------------+
| OpCode | R1 |OpCd| U2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
@end verbatim
 
@item RIS format: <insn> R1,I2,M3,D4(B4)
@verbatim
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 36 47
@end verbatim
 
@item RR format: <insn> R1,R2
@verbatim
+--------+----+----+
| OpCode | R1 | R2 |
+--------+----+----+
0 8 12 15
@end verbatim
 
@item RRE format: <insn> R1,R2
@verbatim
+------------------+--------+----+----+
| OpCode |////////| R1 | R2 |
+------------------+--------+----+----+
0 16 24 28 31
@end verbatim
 
@item RRF format: <insn> R1,R2,R3,M4
@verbatim
+------------------+----+----+----+----+
| OpCode | R3 | M4 | R1 | R2 |
+------------------+----+----+----+----+
0 16 20 24 28 31
@end verbatim
 
@item RRS format: <insn> R1,R2,M3,D4(B4)
@verbatim
+--------+----+----+----+-------------+----+----+--------+
| OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
+--------+----+----+----+-------------+----+----+--------+
0 8 12 16 20 32 36 40 47
@end verbatim
 
@item RS format: <insn> R1,R3,D2(B2)
@verbatim
+--------+----+----+----+-------------+
| OpCode | R1 | R3 | B2 | D2 |
+--------+----+----+----+-------------+
0 8 12 16 20 31
@end verbatim
 
@item RSE format: <insn> R1,R3,D2(B2)
@verbatim
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
@end verbatim
 
@item RSI format: <insn> R1,R3,I2
@verbatim
+--------+----+----+------------------------------------+
| OpCode | R1 | R3 | I2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
@end verbatim
 
@item RSY format: <insn> R1,R3,D2(B2)
@verbatim
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
@end verbatim
 
@item RX format: <insn> R1,D2(X2,B2)
@verbatim
+--------+----+----+----+-------------+
| OpCode | R1 | X2 | B2 | D2 |
+--------+----+----+----+-------------+
0 8 12 16 20 31
@end verbatim
 
@item RXE format: <insn> R1,D2(X2,B2)
@verbatim
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
@end verbatim
 
@item RXF format: <insn> R1,R3,D2(X2,B2)
@verbatim
+--------+----+----+----+-------------+----+---+--------+
| OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode |
+--------+----+----+----+-------------+----+---+--------+
0 8 12 16 20 32 36 40 47
@end verbatim
 
@item RXY format: <insn> R1,D2(X2,B2)
@verbatim
+--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 36 40 47
@end verbatim
 
@item S format: <insn> D2(B2)
@verbatim
+------------------+----+-------------+
| OpCode | B2 | D2 |
+------------------+----+-------------+
0 16 20 31
@end verbatim
 
@item SI format: <insn> D1(B1),I2
@verbatim
+--------+---------+----+-------------+
| OpCode | I2 | B1 | D1 |
+--------+---------+----+-------------+
0 8 16 20 31
@end verbatim
 
@item SIY format: <insn> D1(B1),U2
@verbatim
+--------+---------+----+-------------+--------+--------+
| OpCode | I2 | B1 | DL1 | DH1 | OpCode |
+--------+---------+----+-------------+--------+--------+
0 8 16 20 32 36 40 47
@end verbatim
 
@item SIL format: <insn> D1(B1),I2
@verbatim
+------------------+----+-------------+-----------------+
| OpCode | B1 | D1 | I2 |
+------------------+----+-------------+-----------------+
0 16 20 32 47
@end verbatim
 
@item SS format: <insn> D1(R1,B1),D2(B3),R3
@verbatim
+--------+----+----+----+-------------+----+------------+
| OpCode | R1 | R3 | B1 | D1 | B2 | D2 |
+--------+----+----+----+-------------+----+------------+
0 8 12 16 20 32 36 47
@end verbatim
 
@item SSE format: <insn> D1(B1),D2(B2)
@verbatim
+------------------+----+-------------+----+------------+
| OpCode | B1 | D1 | B2 | D2 |
+------------------+----+-------------+----+------------+
0 8 12 16 20 32 36 47
@end verbatim
 
@item SSF format: <insn> D1(B1),D2(B2),R3
@verbatim
+--------+----+----+----+-------------+----+------------+
| OpCode | R3 |OpCd| B1 | D1 | B2 | D2 |
+--------+----+----+----+-------------+----+------------+
0 8 12 16 20 32 36 47
@end verbatim
 
@end table
 
For the complete list of all instruction format variants see the
Principles of Operation manuals.
 
@node s390 Aliases
@subsection Instruction Aliases
@cindex instruction aliases, s390
@cindex s390 instruction aliases
 
A specific bit pattern can have multiple mnemonics, for example
the bit pattern @samp{0xa7000000} has the mnemonics @samp{tmh} and
@samp{tmlh}. In addition, there are a number of mnemonics recognized by
@code{@value{AS}} that are not present in the Principles of Operation.
These are the short forms of the branch instructions, where the condition
code mask operand is encoded in the mnemonic. This is relevant for the
branch instructions, the compare and branch instructions, and the
compare and trap instructions.
 
For the branch instructions there are 20 condition code strings that can
be used as part of the mnemonic in place of a mask operand in the instruction
format:
 
@display
@multitable @columnfractions .30 .30
@headitem instruction @tab short form
@item bcr M1,R2 @tab b<m>r R2
@item bc M1,D2(X2,B2) @tab b<m> D2(X2,B2)
@item brc M1,I2 @tab j<m> I2
@item brcl M1,I2 @tab jg<m> I2
@end multitable
@end display
 
In the mnemonic for a branch instruction the condition code string <m>
can be any of the following:
 
@display
@multitable {nle} {jump on not zero / if not zeros}
@item o @tab jump on overflow / if ones
@item h @tab jump on A high
@item p @tab jump on plus
@item nle @tab jump on not low or equal
@item l @tab jump on A low
@item m @tab jump on minus
@item nhe @tab jump on not high or equal
@item lh @tab jump on low or high
@item ne @tab jump on A not equal B
@item nz @tab jump on not zero / if not zeros
@item e @tab jump on A equal B
@item z @tab jump on zero / if zeroes
@item nlh @tab jump on not low or high
@item he @tab jump on high or equal
@item nl @tab jump on A not low
@item nm @tab jump on not minus / if not mixed
@item le @tab jump on low or equal
@item nh @tab jump on A not high
@item np @tab jump on not plus
@item no @tab jump on not overflow / if not ones
@end multitable
@end display
 
For the compare and branch, and compare and trap instructions there
are 12 condition code strings that can be used as part of the mnemonic in
place of a mask operand in the instruction format:
 
@display
@multitable @columnfractions .40 .40
@headitem instruction @tab short form
@item crb R1,R2,M3,D4(B4) @tab crb<m> R1,R2,D4(B4)
@item cgrb R1,R2,M3,D4(B4) @tab cgrb<m> R1,R2,D4(B4)
@item crj R1,R2,M3,I4 @tab crj<m> R1,R2,I4
@item cgrj R1,R2,M3,I4 @tab cgrj<m> R1,R2,I4
@item cib R1,I2,M3,D4(B4) @tab cib<m> R1,I2,D4(B4)
@item cgib R1,I2,M3,D4(B4) @tab cgib<m> R1,I2,D4(B4)
@item cij R1,I2,M3,I4 @tab cij<m> R1,I2,I4
@item cgij R1,I2,M3,I4 @tab cgij<m> R1,I2,I4
@item crt R1,R2,M3 @tab crt<m> R1,R2
@item cgrt R1,R2,M3 @tab cgrt<m> R1,R2
@item cit R1,I2,M3 @tab cit<m> R1,I2
@item cgit R1,I2,M3 @tab cgit<m> R1,I2
@item clrb R1,R2,M3,D4(B4) @tab clrb<m> R1,R2,D4(B4)
@item clgrb R1,R2,M3,D4(B4) @tab clgrb<m> R1,R2,D4(B4)
@item clrj R1,R2,M3,I4 @tab clrj<m> R1,R2,I4
@item clgrj R1,R2,M3,I4 @tab clgrj<m> R1,R2,I4
@item clib R1,I2,M3,D4(B4) @tab clib<m> R1,I2,D4(B4)
@item clgib R1,I2,M3,D4(B4) @tab clgib<m> R1,I2,D4(B4)
@item clij R1,I2,M3,I4 @tab clij<m> R1,I2,I4
@item clgij R1,I2,M3,I4 @tab clgij<m> R1,I2,I4
@item clrt R1,R2,M3 @tab clrt<m> R1,R2
@item clgrt R1,R2,M3 @tab clgrt<m> R1,R2
@item clfit R1,I2,M3 @tab clfit<m> R1,I2
@item clgit R1,I2,M3 @tab clgit<m> R1,I2
@end multitable
@end display
 
In the mnemonic for a compare and branch and compare and trap instruction
the condition code string <m> can be any of the following:
 
@display
@multitable {nle} {jump on not zero / if not zeros}
@item h @tab jump on A high
@item nle @tab jump on not low or equal
@item l @tab jump on A low
@item nhe @tab jump on not high or equal
@item ne @tab jump on A not equal B
@item lh @tab jump on low or high
@item e @tab jump on A equal B
@item nlh @tab jump on not low or high
@item nl @tab jump on A not low
@item he @tab jump on high or equal
@item nh @tab jump on A not high
@item le @tab jump on low or equal
@end multitable
@end display
 
@node s390 Operand Modifier
@subsection Instruction Operand Modifier
@cindex instruction operand modifier, s390
@cindex s390 instruction operand modifier
 
If a symbol modifier is attached to a symbol in an expression for an
instruction operand field, the symbol term is replaced with a reference
to an object in the global offset table (GOT) or the procedure linkage
table (PLT). The following expressions are allowed:
@samp{symbol@@modifier + constant},
@samp{symbol@@modifier + label + constant}, and
@samp{symbol@@modifier - label + constant}.
The term @samp{symbol} is the symbol that will be entered into the GOT or
PLT, @samp{label} is a local label, and @samp{constant} is an arbitrary
expression that the assembler can evaluate to a constant value.
 
The term @samp{(symbol + constant1)@@modifier +/- label + constant2}
is also accepted but a warning message is printed and the term is
converted to @samp{symbol@@modifier +/- label + constant1 + constant2}.
 
@table @code
@item @@got
@itemx @@got12
The @@got modifier can be used for displacement fields, 16-bit immediate
fields and 32-bit pc-relative immediate fields. The @@got12 modifier is
synonym to @@got. The symbol is added to the GOT. For displacement
fields and 16-bit immediate fields the symbol term is replaced with
the offset from the start of the GOT to the GOT slot for the symbol.
For a 32-bit pc-relative field the pc-relative offset to the GOT
slot from the current instruction address is used.
@item @@gotent
The @@gotent modifier can be used for 32-bit pc-relative immediate fields.
The symbol is added to the GOT and the symbol term is replaced with
the pc-relative offset from the current instruction to the GOT slot for the
symbol.
@item @@gotoff
The @@gotoff modifier can be used for 16-bit immediate fields. The symbol
term is replaced with the offset from the start of the GOT to the
address of the symbol.
@item @@gotplt
The @@gotplt modifier can be used for displacement fields, 16-bit immediate
fields, and 32-bit pc-relative immediate fields. A procedure linkage
table entry is generated for the symbol and a jump slot for the symbol
is added to the GOT. For displacement fields and 16-bit immediate
fields the symbol term is replaced with the offset from the start of the
GOT to the jump slot for the symbol. For a 32-bit pc-relative field
the pc-relative offset to the jump slot from the current instruction
address is used.
@item @@plt
The @@plt modifier can be used for 16-bit and 32-bit pc-relative immediate
fields. A procedure linkage table entry is generated for the symbol.
The symbol term is replaced with the relative offset from the current
instruction to the PLT entry for the symbol.
@item @@pltoff
The @@pltoff modifier can be used for 16-bit immediate fields. The symbol
term is replaced with the offset from the start of the PLT to the address
of the symbol.
@item @@gotntpoff
The @@gotntpoff modifier can be used for displacement fields. The symbol
is added to the static TLS block and the negated offset to the symbol
in the static TLS block is added to the GOT. The symbol term is replaced
with the offset to the GOT slot from the start of the GOT.
@item @@indntpoff
The @@indntpoff modifier can be used for 32-bit pc-relative immediate
fields. The symbol is added to the static TLS block and the negated offset
to the symbol in the static TLS block is added to the GOT. The symbol term
is replaced with the pc-relative offset to the GOT slot from the current
instruction address.
@end table
 
For more information about the thread local storage modifiers
@samp{gotntpoff} and @samp{indntpoff} see the ELF extension documentation
@samp{ELF Handling For Thread-Local Storage}.
 
@node s390 Instruction Marker
@subsection Instruction Marker
@cindex instruction marker, s390
@cindex s390 instruction marker
 
The thread local storage instruction markers are used by the linker to
perform code optimization.
 
@table @code
@item :tls_load
The :tls_load marker is used to flag the load instruction in the initial
exec TLS model that retrieves the offset from the thread pointer to a
thread local storage variable from the GOT.
@item :tls_gdcall
The :tls_gdcall marker is used to flag the branch-and-save instruction to
the __tls_get_offset function in the global dynamic TLS model.
@item :tls_ldcall
The :tls_ldcall marker is used to flag the branch-and-save instruction to
the __tls_get_offset function in the local dynamic TLS model.
@end table
 
For more information about the thread local storage instruction marker
and the linker optimizations see the ELF extension documentation
@samp{ELF Handling For Thread-Local Storage}.
 
@node s390 Literal Pool Entries
@subsection Literal Pool Entries
@cindex literal pool entries, s390
@cindex s390 literal pool entries
 
A literal pool is a collection of values. To access the values a pointer
to the literal pool is loaded to a register, the literal pool register.
Usually, register %r13 is used as the literal pool register
(@ref{s390 Register}). Literal pool entries are created by adding the
suffix :lit1, :lit2, :lit4, or :lit8 to the end of an expression for an
instruction operand. The expression is added to the literal pool and the
operand is replaced with the offset to the literal in the literal pool.
 
@table @code
@item :lit1
The literal pool entry is created as an 8-bit value. An operand modifier
must not be used for the original expression.
@item :lit2
The literal pool entry is created as a 16 bit value. The operand modifier
@@got may be used in the original expression. The term @samp{x@@got:lit2}
will put the got offset for the global symbol x to the literal pool as
16 bit value.
@item :lit4
The literal pool entry is created as a 32-bit value. The operand modifier
@@got and @@plt may be used in the original expression. The term
@samp{x@@got:lit4} will put the got offset for the global symbol x to the
literal pool as a 32-bit value. The term @samp{x@@plt:lit4} will put the
plt offset for the global symbol x to the literal pool as a 32-bit value.
@item :lit8
The literal pool entry is created as a 64-bit value. The operand modifier
@@got and @@plt may be used in the original expression. The term
@samp{x@@got:lit8} will put the got offset for the global symbol x to the
literal pool as a 64-bit value. The term @samp{x@@plt:lit8} will put the
plt offset for the global symbol x to the literal pool as a 64-bit value.
@end table
 
The assembler directive @samp{.ltorg} is used to emit all literal pool
entries to the current position.
 
@node s390 Directives
@section Assembler Directives
 
@code{@value{AS}} for s390 supports all of the standard ELF
assembler directives as outlined in the main part of this document.
Some directives have been extended and there are some additional
directives, which are only available for the s390 @code{@value{AS}}.
 
@table @code
@cindex @code{.insn} directive, s390
@item .insn
This directive permits the numeric representation of an instructions
and makes the assembler insert the operands according to one of the
instructions formats for @samp{.insn} (@ref{s390 Formats}).
For example, the instruction @samp{l %r1,24(%r15)} could be written as
@samp{.insn rx,0x58000000,%r1,24(%r15)}.
@cindex @code{.short} directive, s390
@cindex @code{.long} directive, s390
@cindex @code{.quad} directive, s390
@item .short
@itemx .long
@itemx .quad
This directive places one or more 16-bit (.short), 32-bit (.long), or
64-bit (.quad) values into the current section. If an ELF or TLS modifier
is used only the following expressions are allowed:
@samp{symbol@@modifier + constant},
@samp{symbol@@modifier + label + constant}, and
@samp{symbol@@modifier - label + constant}.
The following modifiers are available:
@table @code
@item @@got
@itemx @@got12
The @@got modifier can be used for .short, .long and .quad. The @@got12
modifier is synonym to @@got. The symbol is added to the GOT. The symbol
term is replaced with offset from the start of the GOT to the GOT slot for
the symbol.
@item @@gotoff
The @@gotoff modifier can be used for .short, .long and .quad. The symbol
term is replaced with the offset from the start of the GOT to the address
of the symbol.
@item @@gotplt
The @@gotplt modifier can be used for .long and .quad. A procedure linkage
table entry is generated for the symbol and a jump slot for the symbol
is added to the GOT. The symbol term is replaced with the offset from the
start of the GOT to the jump slot for the symbol.
@item @@plt
The @@plt modifier can be used for .long and .quad. A procedure linkage
table entry us generated for the symbol. The symbol term is replaced with
the address of the PLT entry for the symbol.
@item @@pltoff
The @@pltoff modifier can be used for .short, .long and .quad. The symbol
term is replaced with the offset from the start of the PLT to the address
of the symbol.
@item @@tlsgd
@itemx @@tlsldm
The @@tlsgd and @@tlsldm modifier can be used for .long and .quad. A
tls_index structure for the symbol is added to the GOT. The symbol term is
replaced with the offset from the start of the GOT to the tls_index structure.
@item @@gotntpoff
@itemx @@indntpoff
The @@gotntpoff and @@indntpoff modifier can be used for .long and .quad.
The symbol is added to the static TLS block and the negated offset to the
symbol in the static TLS block is added to the GOT. For @@gotntpoff the
symbol term is replaced with the offset from the start of the GOT to the
GOT slot, for @@indntpoff the symbol term is replaced with the address
of the GOT slot.
@item @@dtpoff
The @@dtpoff modifier can be used for .long and .quad. The symbol term
is replaced with the offset of the symbol relative to the start of the
TLS block it is contained in.
@item @@ntpoff
The @@ntpoff modifier can be used for .long and .quad. The symbol term
is replaced with the offset of the symbol relative to the TCB pointer.
@end table
 
For more information about the thread local storage modifiers see the
ELF extension documentation @samp{ELF Handling For Thread-Local Storage}.
 
@cindex @code{.ltorg} directive, s390
@item .ltorg
This directive causes the current contents of the literal pool to be
dumped to the current location (@ref{s390 Literal Pool Entries}).
 
@cindex @code{.machine} directive, s390
@item .machine string
This directive allows you to change the machine for which code is
generated. @code{string} may be any of the @code{-march=} selection
options (without the -march=), @code{push}, or @code{pop}.
@code{.machine push} saves the currently selected cpu, which may be
restored with @code{.machine pop}. Be aware that the cpu string has
to be put into double quotes in case it contains characters not
appropriate for identifiers. So you have to write @code{"z9-109"}
instead of just @code{z9-109}.
@end table
 
@node s390 Floating Point
@section Floating Point
@cindex floating point, s390
@cindex s390 floating point
 
The assembler recognizes both the @sc{ieee} floating-point instruction and
the hexadecimal floating-point instructions. The floating-point constructors
@samp{.float}, @samp{.single}, and @samp{.double} always emit the
@sc{ieee} format. To assemble hexadecimal floating-point constants the
@samp{.long} and @samp{.quad} directives must be used.
/binutils/gas/doc/c-score.texi
0,0 → 1,168
@c Copyright 2009, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node SCORE-Dependent
@chapter SCORE Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter SCORE Dependent Features
@end ifclear
 
@cindex SCORE processor
@menu
* SCORE-Opts:: Assembler options
* SCORE-Pseudo:: SCORE Assembler Directives
* SCORE-Syntax:: Syntax
@end menu
 
@node SCORE-Opts
@section Options
 
@cindex options for SCORE
@cindex SCORE options
@cindex architectures, SCORE
@cindex SCORE architectures
 
The following table lists all available SCORE options.
 
@table @code
@item -G @var{num}
This option sets the largest size of an object that can be referenced
implicitly with the @code{gp} register. The default value is 8.
 
@item -EB
Assemble code for a big-endian cpu
 
@itemx -EL
Assemble code for a little-endian cpu
 
@item -FIXDD
Assemble code for fix data dependency
 
@item -NWARN
Assemble code for no warning message for fix data dependency
 
@item -SCORE5
Assemble code for target is SCORE5
 
@itemx -SCORE5U
Assemble code for target is SCORE5U
 
@itemx -SCORE7
Assemble code for target is SCORE7, this is default setting
 
@itemx -SCORE3
Assemble code for target is SCORE3
 
@item -march=score7
Assemble code for target is SCORE7, this is default setting
 
@item -march=score3
Assemble code for target is SCORE3
 
@item -USE_R1
Assemble code for no warning message when using temp register r1
 
@item -KPIC
Generate code for PIC. This option tells the assembler to generate
score position-independent macro expansions. It also tells the
assembler to mark the output file as PIC.
 
@item -O0
Assembler will not perform any optimizations
 
@item -V
Sunplus release version
 
@end table
 
@node SCORE-Pseudo
@section SCORE Assembler Directives
 
@cindex directives for SCORE
@cindex SCORE directives
A number of assembler directives are available for SCORE. The
following table is far from complete.
 
@table @code
@item .set nwarn
Let the assembler not to generate warnings if the source machine
language instructions happen data dependency.
 
@item .set fixdd
Let the assembler to insert bubbles (32 bit nop instruction /
16 bit nop! Instruction) if the source machine language instructions
happen data dependency.
 
@item .set nofixdd
Let the assembler to generate warnings if the source machine
language instructions happen data dependency. (Default)
 
@item .set r1
Let the assembler not to generate warnings if the source program
uses r1. allow user to use r1
 
@item set nor1
Let the assembler to generate warnings if the source program uses
r1. (Default)
 
@item .sdata
Tell the assembler to add subsequent data into the sdata section
 
@item .rdata
Tell the assembler to add subsequent data into the rdata section
 
@item .frame "frame-register", "offset", "return-pc-register"
Describe a stack frame. "frame-register" is the frame register,
"offset" is the distance from the frame register to the virtual
frame pointer, "return-pc-register" is the return program register.
You must use ".ent" before ".frame" and only one ".frame" can be
used per ".ent".
 
@item .mask "bitmask", "frameoffset"
Indicate which of the integer registers are saved in the current
function's stack frame, this is for the debugger to explain the
frame chain.
 
@item .ent "proc-name"
Set the beginning of the procedure "proc_name". Use this directive
when you want to generate information for the debugger.
 
@item .end proc-name
Set the end of a procedure. Use this directive to generate information
for the debugger.
 
@item .bss
Switch the destination of following statements into the bss section,
which is used for data that is uninitialized anywhere.
 
@end table
 
@node SCORE-Syntax
@section SCORE Syntax
@menu
* SCORE-Chars:: Special Characters
@end menu
 
@node SCORE-Chars
@subsection Special Characters
 
@cindex line comment character, SCORE
@cindex SCORE line comment character
The presence of a @samp{#} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, SCORE
@cindex statement separator, SCORE
@cindex SCORE line separator
The @samp{;} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-sh.texi
0,0 → 1,343
@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004,
@c 2005, 2008, 2010, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node SH-Dependent
@chapter Renesas / SuperH SH Dependent Features
 
@cindex SH support
@menu
* SH Options:: Options
* SH Syntax:: Syntax
* SH Floating Point:: Floating Point
* SH Directives:: SH Machine Directives
* SH Opcodes:: Opcodes
@end menu
 
@node SH Options
@section Options
 
@cindex SH options
@cindex options, SH
@code{@value{AS}} has following command-line options for the Renesas
(formerly Hitachi) / SuperH SH family.
 
@table @code
@kindex --little
@kindex --big
@kindex --relax
@kindex --small
@kindex --dsp
@kindex --renesas
@kindex --allow-reg-prefix
 
@item --little
Generate little endian code.
 
@item --big
Generate big endian code.
 
@item --relax
Alter jump instructions for long displacements.
 
@item --small
Align sections to 4 byte boundaries, not 16.
 
@item --dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
 
@item --renesas
Disable optimization with section symbol for compatibility with
Renesas assembler.
 
@item --allow-reg-prefix
Allow '$' as a register name prefix.
 
@kindex --fdpic
@item --fdpic
Generate an FDPIC object file.
 
@item --isa=sh4 | sh4a
Specify the sh4 or sh4a instruction set.
@item --isa=dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
@item --isa=fp
Enable sh2e, sh3e, sh4, and sh4a insn sets.
@item --isa=all
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
 
@item -h-tick-hex
Support H'00 style hex constants in addition to 0x00 style.
 
@end table
 
@node SH Syntax
@section Syntax
 
@menu
* SH-Chars:: Special Characters
* SH-Regs:: Register Names
* SH-Addressing:: Addressing Modes
@end menu
 
@node SH-Chars
@subsection Special Characters
 
@cindex line comment character, SH
@cindex SH line comment character
@samp{!} is the line comment character.
 
@cindex line separator, SH
@cindex statement separator, SH
@cindex SH line separator
You can use @samp{;} instead of a newline to separate statements.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
Since @samp{$} has no special meaning, you may use it in symbol names.
 
@node SH-Regs
@subsection Register Names
 
@cindex SH registers
@cindex registers, SH
You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8},
@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14},
and @samp{r15} to refer to the SH registers.
 
The SH also has these control registers:
 
@table @code
@item pr
procedure register (holds return address)
 
@item pc
program counter
 
@item mach
@itemx macl
high and low multiply accumulator registers
 
@item sr
status register
 
@item gbr
global base register
 
@item vbr
vector base register (for interrupt vectors)
@end table
 
@node SH-Addressing
@subsection Addressing Modes
 
@cindex addressing modes, SH
@cindex SH addressing modes
@code{@value{AS}} understands the following addressing modes for the SH.
@code{R@var{n}} in the following refers to any of the numbered
registers, but @emph{not} the control registers.
 
@table @code
@item R@var{n}
Register direct
 
@item @@R@var{n}
Register indirect
 
@item @@-R@var{n}
Register indirect with pre-decrement
 
@item @@R@var{n}+
Register indirect with post-increment
 
@item @@(@var{disp}, R@var{n})
Register indirect with displacement
 
@item @@(R0, R@var{n})
Register indexed
 
@item @@(@var{disp}, GBR)
@code{GBR} offset
 
@item @@(R0, GBR)
GBR indexed
 
@item @var{addr}
@itemx @@(@var{disp}, PC)
PC relative address (for branch or for addressing memory). The
@code{@value{AS}} implementation allows you to use the simpler form
@var{addr} anywhere a PC relative address is called for; the alternate
form is supported for compatibility with other assemblers.
 
@item #@var{imm}
Immediate data
@end table
 
@node SH Floating Point
@section Floating Point
 
@cindex floating point, SH (@sc{ieee})
@cindex SH floating point (@sc{ieee})
SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
SH groups can use @code{.float} directive to generate @sc{ieee}
floating-point numbers.
 
SH2E and SH3E support single-precision floating point calculations as
well as entirely PCAPI compatible emulation of double-precision
floating point calculations. SH2E and SH3E instructions are a subset of
the floating point calculations conforming to the IEEE754 standard.
 
In addition to single-precision and double-precision floating-point
operation capability, the on-chip FPU of SH4 has a 128-bit graphic
engine that enables 32-bit floating-point data to be processed 128
bits at a time. It also supports 4 * 4 array operations and inner
product operations. Also, a superscalar architecture is employed that
enables simultaneous execution of two instructions (including FPU
instructions), providing performance of up to twice that of
conventional architectures at the same frequency.
 
@node SH Directives
@section SH Machine Directives
 
@cindex SH machine directives
@cindex machine directives, SH
@cindex @code{uaword} directive, SH
@cindex @code{ualong} directive, SH
 
@table @code
@item uaword
@itemx ualong
@code{@value{AS}} will issue a warning when a misaligned @code{.word} or
@code{.long} directive is used. You may use @code{.uaword} or
@code{.ualong} to indicate that the value is intentionally misaligned.
@end table
 
@node SH Opcodes
@section Opcodes
 
@cindex SH opcode summary
@cindex opcode summary, SH
@cindex mnemonics, SH
@cindex instruction summary, SH
For detailed information on the SH machine instruction set, see
@cite{SH-Microcomputer User's Manual} (Renesas) or
@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and
@cite{SuperH (SH) 64-Bit RISC Series} (SuperH).
 
@code{@value{AS}} implements all the standard SH opcodes. No additional
pseudo-instructions are needed on this family. Note, however, that
because @code{@value{AS}} supports a simpler form of PC-relative
addressing, you may simply write (for example)
 
@example
mov.l bar,r0
@end example
 
@noindent
where other assemblers might require an explicit displacement to
@code{bar} from the program counter:
 
@example
mov.l @@(@var{disp}, PC)
@end example
 
@ifset SMALL
@c this table, due to the multi-col faking and hardcoded order, looks silly
@c except in smallbook. See comments below "@set SMALL" near top of this file.
 
Here is a summary of SH opcodes:
 
@page
@smallexample
@i{Legend:}
Rn @r{a numbered register}
Rm @r{another numbered register}
#imm @r{immediate data}
disp @r{displacement}
disp8 @r{8-bit displacement}
disp12 @r{12-bit displacement}
 
add #imm,Rn lds.l @@Rn+,PR
add Rm,Rn mac.w @@Rm+,@@Rn+
addc Rm,Rn mov #imm,Rn
addv Rm,Rn mov Rm,Rn
and #imm,R0 mov.b Rm,@@(R0,Rn)
and Rm,Rn mov.b Rm,@@-Rn
and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn
bf disp8 mov.b @@(disp,Rm),R0
bra disp12 mov.b @@(disp,GBR),R0
bsr disp12 mov.b @@(R0,Rm),Rn
bt disp8 mov.b @@Rm+,Rn
clrmac mov.b @@Rm,Rn
clrt mov.b R0,@@(disp,Rm)
cmp/eq #imm,R0 mov.b R0,@@(disp,GBR)
cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn)
cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn)
cmp/gt Rm,Rn mov.l Rm,@@-Rn
cmp/hi Rm,Rn mov.l Rm,@@Rn
cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm
cmp/pl Rn mov.l @@(disp,GBR),R0
cmp/pz Rn mov.l @@(disp,PC),Rn
cmp/str Rm,Rn mov.l @@(R0,Rm),Rn
div0s Rm,Rn mov.l @@Rm+,Rn
div0u mov.l @@Rm,Rn
div1 Rm,Rn mov.l R0,@@(disp,GBR)
exts.b Rm,Rn mov.w Rm,@@(R0,Rn)
exts.w Rm,Rn mov.w Rm,@@-Rn
extu.b Rm,Rn mov.w Rm,@@Rn
extu.w Rm,Rn mov.w @@(disp,Rm),R0
jmp @@Rn mov.w @@(disp,GBR),R0
jsr @@Rn mov.w @@(disp,PC),Rn
ldc Rn,GBR mov.w @@(R0,Rm),Rn
ldc Rn,SR mov.w @@Rm+,Rn
ldc Rn,VBR mov.w @@Rm,Rn
ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm)
ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
ldc.l @@Rn+,VBR mova @@(disp,PC),R0
lds Rn,MACH movt Rn
lds Rn,MACL muls Rm,Rn
lds Rn,PR mulu Rm,Rn
lds.l @@Rn+,MACH neg Rm,Rn
lds.l @@Rn+,MACL negc Rm,Rn
@page
nop stc VBR,Rn
not Rm,Rn stc.l GBR,@@-Rn
or #imm,R0 stc.l SR,@@-Rn
or Rm,Rn stc.l VBR,@@-Rn
or.b #imm,@@(R0,GBR) sts MACH,Rn
rotcl Rn sts MACL,Rn
rotcr Rn sts PR,Rn
rotl Rn sts.l MACH,@@-Rn
rotr Rn sts.l MACL,@@-Rn
rte sts.l PR,@@-Rn
rts sub Rm,Rn
sett subc Rm,Rn
shal Rn subv Rm,Rn
shar Rn swap.b Rm,Rn
shll Rn swap.w Rm,Rn
shll16 Rn tas.b @@Rn
shll2 Rn trapa #imm
shll8 Rn tst #imm,R0
shlr Rn tst Rm,Rn
shlr16 Rn tst.b #imm,@@(R0,GBR)
shlr2 Rn xor #imm,R0
shlr8 Rn xor Rm,Rn
sleep xor.b #imm,@@(R0,GBR)
stc GBR,Rn xtrct Rm,Rn
stc SR,Rn
@end smallexample
@end ifset
 
@ifset Renesas-all
@ifclear GENERIC
@raisesections
@end ifclear
@end ifset
 
/binutils/gas/doc/c-sh64.texi
0,0 → 1,223
@c Copyright (C) 2002, 2003, 2008, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@page
@node SH64-Dependent
@chapter SuperH SH64 Dependent Features
 
@cindex SH64 support
@menu
* SH64 Options:: Options
* SH64 Syntax:: Syntax
* SH64 Directives:: SH64 Machine Directives
* SH64 Opcodes:: Opcodes
@end menu
 
@node SH64 Options
@section Options
 
@cindex SH64 options
@cindex options, SH64
@table @code
 
@cindex SH64 ISA options
@cindex ISA options, SH64
@item -isa=sh4 | sh4a
Specify the sh4 or sh4a instruction set.
@item -isa=dsp
Enable sh-dsp insns, and disable sh3e / sh4 insns.
@item -isa=fp
Enable sh2e, sh3e, sh4, and sh4a insn sets.
@item -isa=all
Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
@item -isa=shmedia | -isa=shcompact
Specify the default instruction set. @code{SHmedia} specifies the
32-bit opcodes, and @code{SHcompact} specifies the 16-bit opcodes
compatible with previous SH families. The default depends on the ABI
selected; the default for the 64-bit ABI is SHmedia, and the default for
the 32-bit ABI is SHcompact. If neither the ABI nor the ISA is
specified, the default is 32-bit SHcompact.
 
Note that the @code{.mode} pseudo-op is not permitted if the ISA is not
specified on the command line.
 
@cindex SH64 ABI options
@cindex ABI options, SH64
@item -abi=32 | -abi=64
Specify the default ABI. If the ISA is specified and the ABI is not,
the default ABI depends on the ISA, with SHmedia defaulting to 64-bit
and SHcompact defaulting to 32-bit.
 
Note that the @code{.abi} pseudo-op is not permitted if the ABI is not
specified on the command line. When the ABI is specified on the command
line, any @code{.abi} pseudo-ops in the source must match it.
 
@item -shcompact-const-crange
Emit code-range descriptors for constants in SHcompact code sections.
 
@item -no-mix
Disallow SHmedia code in the same section as constants and SHcompact
code.
 
@item -no-expand
Do not expand MOVI, PT, PTA or PTB instructions.
 
@item -expand-pt32
With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
 
@item -h-tick-hex
Support H'00 style hex constants in addition to 0x00 style.
 
@end table
 
@node SH64 Syntax
@section Syntax
 
@menu
* SH64-Chars:: Special Characters
* SH64-Regs:: Register Names
* SH64-Addressing:: Addressing Modes
@end menu
 
@node SH64-Chars
@subsection Special Characters
 
@cindex line comment character, SH64
@cindex SH64 line comment character
@samp{!} is the line comment character.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, SH64
@cindex statement separator, SH64
@cindex SH64 line separator
You can use @samp{;} instead of a newline to separate statements.
 
@cindex symbol names, @samp{$} in
@cindex @code{$} in symbol names
Since @samp{$} has no special meaning, you may use it in symbol names.
 
@node SH64-Regs
@subsection Register Names
 
@cindex SH64 registers
@cindex registers, SH64
You can use the predefined symbols @samp{r0} through @samp{r63} to refer
to the SH64 general registers, @samp{cr0} through @code{cr63} for
control registers, @samp{tr0} through @samp{tr7} for target address
registers, @samp{fr0} through @samp{fr63} for single-precision floating
point registers, @samp{dr0} through @samp{dr62} (even numbered registers
only) for double-precision floating point registers, @samp{fv0} through
@samp{fv60} (multiples of four only) for single-precision floating point
vectors, @samp{fp0} through @samp{fp62} (even numbered registers only)
for single-precision floating point pairs, @samp{mtrx0} through
@samp{mtrx48} (multiples of 16 only) for 4x4 matrices of
single-precision floating point registers, @samp{pc} for the program
counter, and @samp{fpscr} for the floating point status and control
register.
 
You can also refer to the control registers by the mnemonics @samp{sr},
@samp{ssr}, @samp{pssr}, @samp{intevt}, @samp{expevt}, @samp{pexpevt},
@samp{tra}, @samp{spc}, @samp{pspc}, @samp{resvec}, @samp{vbr},
@samp{tea}, @samp{dcr}, @samp{kcr0}, @samp{kcr1}, @samp{ctc}, and
@samp{usr}.
 
@node SH64-Addressing
@subsection Addressing Modes
 
@cindex addressing modes, SH64
@cindex SH64 addressing modes
 
SH64 operands consist of either a register or immediate value. The
immediate value can be a constant or label reference (or portion of a
label reference), as in this example:
 
@example
movi 4,r2
pt function, tr4
movi (function >> 16) & 65535,r0
shori function & 65535, r0
ld.l r0,4,r0
@end example
 
@cindex datalabel, SH64
Instruction label references can reference labels in either SHmedia or
SHcompact. To differentiate between the two, labels in SHmedia sections
will always have the least significant bit set (i.e. they will be odd),
which SHcompact labels will have the least significant bit reset
(i.e. they will be even). If you need to reference the actual address
of a label, you can use the @code{datalabel} modifier, as in this
example:
 
@example
.long function
.long datalabel function
@end example
 
In that example, the first longword may or may not have the least
significant bit set depending on whether the label is an SHmedia label
or an SHcompact label. The second longword will be the actual address
of the label, regardless of what type of label it is.
 
@node SH64 Directives
@section SH64 Machine Directives
 
In addition to the SH directives, the SH64 provides the following
directives:
 
@cindex SH64 machine directives
@cindex machine directives, SH64
 
@table @code
 
@item .mode [shmedia|shcompact]
@itemx .isa [shmedia|shcompact]
Specify the ISA for the following instructions (the two directives are
equivalent). Note that programs such as @code{objdump} rely on symbolic
labels to determine when such mode switches occur (by checking the least
significant bit of the label's address), so such mode/isa changes should
always be followed by a label (in practice, this is true anyway). Note
that you cannot use these directives if you didn't specify an ISA on the
command line.
 
@item .abi [32|64]
Specify the ABI for the following instructions. Note that you cannot use
this directive unless you specified an ABI on the command line, and the
ABIs specified must match.
 
@item .uaquad
Like .uaword and .ualong, this allows you to specify an intentionally
unaligned quadword (64 bit word).
 
@end table
 
@node SH64 Opcodes
@section Opcodes
 
@cindex SH64 opcode summary
@cindex opcode summary, SH64
@cindex mnemonics, SH64
@cindex instruction summary, SH64
For detailed information on the SH64 machine instruction set, see
@cite{SuperH 64 bit RISC Series Architecture Manual} (SuperH, Inc.).
 
@code{@value{AS}} implements all the standard SH64 opcodes. In
addition, the following pseudo-opcodes may be expanded into one or more
alternate opcodes:
 
@table @code
 
@item movi
If the value doesn't fit into a standard @code{movi} opcode,
@code{@value{AS}} will replace the @code{movi} with a sequence of
@code{movi} and @code{shori} opcodes.
 
@item pt
This expands to a sequence of @code{movi} and @code{shori} opcode,
followed by a @code{ptrel} opcode, or to a @code{pta} or @code{ptb}
opcode, depending on the label referenced.
 
@end table
/binutils/gas/doc/c-sparc.texi
0,0 → 1,860
@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002, 2008,
@c 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node Sparc-Dependent
@chapter SPARC Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter SPARC Dependent Features
@end ifclear
 
@cindex SPARC support
@menu
* Sparc-Opts:: Options
* Sparc-Aligned-Data:: Option to enforce aligned data
* Sparc-Syntax:: Syntax
* Sparc-Float:: Floating Point
* Sparc-Directives:: Sparc Machine Directives
@end menu
 
@node Sparc-Opts
@section Options
 
@cindex options for SPARC
@cindex SPARC options
@cindex architectures, SPARC
@cindex SPARC architectures
The SPARC chip family includes several successive versions, using the same
core instruction set, but including a few additional instructions at
each version. There are exceptions to this however. For details on what
instructions each variant supports, please see the chip's architecture
reference manual.
 
By default, @code{@value{AS}} assumes the core instruction set (SPARC
v6), but ``bumps'' the architecture level as needed: it switches to
successively higher architectures as it encounters instructions that
only exist in the higher levels.
 
If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
past sparclite by default, an option must be passed to enable the
v9 instructions.
 
GAS treats sparclite as being compatible with v8, unless an architecture
is explicitly requested. SPARC v9 is always incompatible with sparclite.
 
@c The order here is the same as the order of enum sparc_opcode_arch_val
@c to give the user a sense of the order of the "bumping".
 
@table @code
@kindex -Av6
@kindex -Av7
@kindex -Av8
@kindex -Asparclet
@kindex -Asparclite
@kindex -Av9
@kindex -Av9a
@kindex -Av9b
@kindex -Av9c
@kindex -Av9d
@kindex -Av9v
@kindex -Asparc
@kindex -Asparcvis
@kindex -Asparcvis2
@kindex -Asparcfmaf
@kindex -Asparcima
@kindex -Asparcvis3
@kindex -Asparcvis3r
@item -Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite
@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
@itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
@itemx -Asparcvis3 | -Asparcvis3r
Use one of the @samp{-A} options to select one of the SPARC
architectures explicitly. If you select an architecture explicitly,
@code{@value{AS}} reports a fatal error if it encounters an instruction
or feature requiring an incompatible or higher level.
 
@samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
@samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
 
@samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and
@samp{-Av9v} select a 64 bit environment and are not available unless GAS
is explicitly configured with 64 bit environment support.
 
@samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
UltraSPARC VIS 1.0 extensions.
 
@samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions,
as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}.
 
@samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions,
as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
 
@samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused
multiply-add, VIS 3.0, and HPC extension instructions, as well as the
instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
 
@samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional
memory, floating point unfused multiply-add, integer multiply-add, and
cache sparing store instructions, as well as the instructions enabled
by @samp{-Av8plusd} and @samp{-Av9d}.
 
@samp{-Asparc} specifies a v9 environment. It is equivalent to
@samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
 
@samp{-Asparcvis} specifies a v9a environment. It is equivalent to
@samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise.
 
@samp{-Asparcvis2} specifies a v9b environment. It is equivalent to
@samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise.
 
@samp{-Asparcfmaf} specifies a v9b environment with the floating point
fused multiply-add instructions enabled.
 
@samp{-Asparcima} specifies a v9b environment with the integer
multiply-add instructions enabled.
 
@samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
HPC , and floating point fused multiply-add instructions enabled.
 
@samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0,
HPC, transactional memory, random, and floating point unfused multiply-add
instructions enabled.
 
@item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v
@itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
@itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
@itemx -xarch=sparcvis3r
For compatibility with the SunOS v9 assembler. These options are
equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
-Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis,
-Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r,
respectively.
 
@item -bump
Warn whenever it is necessary to switch to another level.
If an architecture level is explicitly requested, GAS will not issue
warnings until that level is reached, and will then bump the level
as required (except between incompatible levels).
 
@item -32 | -64
Select the word size, either 32 bits or 64 bits.
These options are only available with the ELF object file format,
and require that the necessary BFD support has been included.
@end table
 
@node Sparc-Aligned-Data
@section Enforcing aligned data
 
@cindex data alignment on SPARC
@cindex SPARC data alignment
SPARC GAS normally permits data to be misaligned. For example, it
permits the @code{.long} pseudo-op to be used on a byte boundary.
However, the native SunOS assemblers issue an error when they see
misaligned data.
 
@kindex --enforce-aligned-data
You can use the @code{--enforce-aligned-data} option to make SPARC GAS
also issue an error about misaligned data, just as the SunOS
assemblers do.
 
The @code{--enforce-aligned-data} option is not the default because gcc
issues misaligned data pseudo-ops when it initializes certain packed
data structures (structures defined using the @code{packed} attribute).
You may have to assemble with GAS in order to initialize packed data
structures in your own code.
 
@cindex SPARC syntax
@cindex syntax, SPARC
@node Sparc-Syntax
@section Sparc Syntax
The assembler syntax closely follows The Sparc Architecture Manual,
versions 8 and 9, as well as most extensions defined by Sun
for their UltraSPARC and Niagara line of processors.
 
@menu
* Sparc-Chars:: Special Characters
* Sparc-Regs:: Register Names
* Sparc-Constants:: Constant Names
* Sparc-Relocs:: Relocations
* Sparc-Size-Translations:: Size Translations
@end menu
 
@node Sparc-Chars
@subsection Special Characters
 
@cindex line comment character, Sparc
@cindex Sparc line comment character
A @samp{!} character appearing anywhere on a line indicates the start
of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, Sparc
@cindex statement separator, Sparc
@cindex Sparc line separator
@samp{;} can be used instead of a newline to separate statements.
 
@node Sparc-Regs
@subsection Register Names
@cindex Sparc registers
@cindex register names, Sparc
 
The Sparc integer register file is broken down into global,
outgoing, local, and incoming.
 
@itemize @bullet
@item
The 8 global registers are referred to as @samp{%g@var{n}}.
 
@item
The 8 outgoing registers are referred to as @samp{%o@var{n}}.
 
@item
The 8 local registers are referred to as @samp{%l@var{n}}.
 
@item
The 8 incoming registers are referred to as @samp{%i@var{n}}.
 
@item
The frame pointer register @samp{%i6} can be referenced using
the alias @samp{%fp}.
 
@item
The stack pointer register @samp{%o6} can be referenced using
the alias @samp{%sp}.
@end itemize
 
Floating point registers are simply referred to as @samp{%f@var{n}}.
When assembling for pre-V9, only 32 floating point registers
are available. For V9 and later there are 64, but there are
restrictions when referencing the upper 32 registers. They
can only be accessed as double or quad, and thus only even
or quad numbered accesses are allowed. For example, @samp{%f34}
is a legal floating point register, but @samp{%f35} is not.
 
Certain V9 instructions allow access to ancillary state registers.
Most simply they can be referred to as @samp{%asr@var{n}} where
@var{n} can be from 16 to 31. However, there are some aliases
defined to reference ASR registers defined for various UltraSPARC
processors:
 
@itemize @bullet
@item
The tick compare register is referred to as @samp{%tick_cmpr}.
 
@item
The system tick register is referred to as @samp{%stick}. An alias,
@samp{%sys_tick}, exists but is deprecated and should not be used
by new software.
 
@item
The system tick compare register is referred to as @samp{%stick_cmpr}.
An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should
not be used by new software.
 
@item
The software interrupt register is referred to as @samp{%softint}.
 
@item
The set software interrupt register is referred to as @samp{%set_softint}.
The mnemonic @samp{%softint_set} is provided as an alias.
 
@item
The clear software interrupt register is referred to as
@samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
as an alias.
 
@item
The performance instrumentation counters register is referred to as
@samp{%pic}.
 
@item
The performance control register is referred to as @samp{%pcr}.
 
@item
The graphics status register is referred to as @samp{%gsr}.
 
@item
The V9 dispatch control register is referred to as @samp{%dcr}.
@end itemize
 
Various V9 branch and conditional move instructions allow
specification of which set of integer condition codes to
test. These are referred to as @samp{%xcc} and @samp{%icc}.
 
In V9, there are 4 sets of floating point condition codes
which are referred to as @samp{%fcc@var{n}}.
 
Several special privileged and non-privileged registers
exist:
 
@itemize @bullet
@item
The V9 address space identifier register is referred to as @samp{%asi}.
 
@item
The V9 restorable windows register is referred to as @samp{%canrestore}.
 
@item
The V9 savable windows register is referred to as @samp{%cansave}.
 
@item
The V9 clean windows register is referred to as @samp{%cleanwin}.
 
@item
The V9 current window pointer register is referred to as @samp{%cwp}.
 
@item
The floating-point queue register is referred to as @samp{%fq}.
 
@item
The V8 co-processor queue register is referred to as @samp{%cq}.
 
@item
The floating point status register is referred to as @samp{%fsr}.
 
@item
The other windows register is referred to as @samp{%otherwin}.
 
@item
The V9 program counter register is referred to as @samp{%pc}.
 
@item
The V9 next program counter register is referred to as @samp{%npc}.
 
@item
The V9 processor interrupt level register is referred to as @samp{%pil}.
 
@item
The V9 processor state register is referred to as @samp{%pstate}.
 
@item
The trap base address register is referred to as @samp{%tba}.
 
@item
The V9 tick register is referred to as @samp{%tick}.
 
@item
The V9 trap level is referred to as @samp{%tl}.
 
@item
The V9 trap program counter is referred to as @samp{%tpc}.
 
@item
The V9 trap next program counter is referred to as @samp{%tnpc}.
 
@item
The V9 trap state is referred to as @samp{%tstate}.
 
@item
The V9 trap type is referred to as @samp{%tt}.
 
@item
The V9 condition codes is referred to as @samp{%ccr}.
 
@item
The V9 floating-point registers state is referred to as @samp{%fprs}.
 
@item
The V9 version register is referred to as @samp{%ver}.
 
@item
The V9 window state register is referred to as @samp{%wstate}.
 
@item
The Y register is referred to as @samp{%y}.
 
@item
The V8 window invalid mask register is referred to as @samp{%wim}.
 
@item
The V8 processor state register is referred to as @samp{%psr}.
 
@item
The V9 global register level register is referred to as @samp{%gl}.
@end itemize
 
Several special register names exist for hypervisor mode code:
 
@itemize @bullet
@item
The hyperprivileged processor state register is referred to as
@samp{%hpstate}.
 
@item
The hyperprivileged trap state register is referred to as @samp{%htstate}.
 
@item
The hyperprivileged interrupt pending register is referred to as
@samp{%hintp}.
 
@item
The hyperprivileged trap base address register is referred to as
@samp{%htba}.
 
@item
The hyperprivileged implementation version register is referred
to as @samp{%hver}.
 
@item
The hyperprivileged system tick compare register is referred
to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick}
register, the normal @samp{%stick} is used.
@end itemize
 
@node Sparc-Constants
@subsection Constants
@cindex Sparc constants
@cindex constants, Sparc
 
Several Sparc instructions take an immediate operand field for
which mnemonic names exist. Two such examples are @samp{membar}
and @samp{prefetch}. Another example are the set of V9
memory access instruction that allow specification of an
address space identifier.
 
The @samp{membar} instruction specifies a memory barrier that is
the defined by the operand which is a bitmask. The supported
mask mnemonics are:
 
@itemize @bullet
@item
@samp{#Sync} requests that all operations (including nonmemory
reference operations) appearing prior to the @code{membar} must have
been performed and the effects of any exceptions become visible before
any instructions after the @code{membar} may be initiated. This
corresponds to @code{membar} cmask field bit 2.
 
@item
@samp{#MemIssue} requests that all memory reference operations
appearing prior to the @code{membar} must have been performed before
any memory operation after the @code{membar} may be initiated. This
corresponds to @code{membar} cmask field bit 1.
 
@item
@samp{#Lookaside} requests that a store appearing prior to the
@code{membar} must complete before any load following the
@code{membar} referencing the same address can be initiated. This
corresponds to @code{membar} cmask field bit 0.
 
@item
@samp{#StoreStore} defines that the effects of all stores appearing
prior to the @code{membar} instruction must be visible to all
processors before the effect of any stores following the
@code{membar}. Equivalent to the deprecated @code{stbar} instruction.
This corresponds to @code{membar} mmask field bit 3.
 
@item
@samp{#LoadStore} defines all loads appearing prior to the
@code{membar} instruction must have been performed before the effect
of any stores following the @code{membar} is visible to any other
processor. This corresponds to @code{membar} mmask field bit 2.
 
@item
@samp{#StoreLoad} defines that the effects of all stores appearing
prior to the @code{membar} instruction must be visible to all
processors before loads following the @code{membar} may be performed.
This corresponds to @code{membar} mmask field bit 1.
 
@item
@samp{#LoadLoad} defines that all loads appearing prior to the
@code{membar} instruction must have been performed before any loads
following the @code{membar} may be performed. This corresponds to
@code{membar} mmask field bit 0.
 
@end itemize
 
These values can be ored together, for example:
 
@example
membar #Sync
membar #StoreLoad | #LoadLoad
membar #StoreLoad | #StoreStore
@end example
 
The @code{prefetch} and @code{prefetcha} instructions take a prefetch
function code. The following prefetch function code constant
mnemonics are available:
 
@itemize @bullet
@item
@samp{#n_reads} requests a prefetch for several reads, and corresponds
to a prefetch function code of 0.
 
@samp{#one_read} requests a prefetch for one read, and corresponds
to a prefetch function code of 1.
 
@samp{#n_writes} requests a prefetch for several writes (and possibly
reads), and corresponds to a prefetch function code of 2.
 
@samp{#one_write} requests a prefetch for one write, and corresponds
to a prefetch function code of 3.
 
@samp{#page} requests a prefetch page, and corresponds to a prefetch
function code of 4.
 
@samp{#invalidate} requests a prefetch invalidate, and corresponds to
a prefetch function code of 16.
 
@samp{#unified} requests a prefetch to the nearest unified cache, and
corresponds to a prefetch function code of 17.
 
@samp{#n_reads_strong} requests a strong prefetch for several reads,
and corresponds to a prefetch function code of 20.
 
@samp{#one_read_strong} requests a strong prefetch for one read,
and corresponds to a prefetch function code of 21.
 
@samp{#n_writes_strong} requests a strong prefetch for several writes,
and corresponds to a prefetch function code of 22.
 
@samp{#one_write_strong} requests a strong prefetch for one write,
and corresponds to a prefetch function code of 23.
 
Onle one prefetch code may be specified. Here are some examples:
 
@example
prefetch [%l0 + %l2], #one_read
prefetch [%g2 + 8], #n_writes
prefetcha [%g1] 0x8, #unified
prefetcha [%o0 + 0x10] %asi, #n_reads
@end example
 
The actual behavior of a given prefetch function code is processor
specific. If a processor does not implement a given prefetch
function code, it will treat the prefetch instruction as a nop.
 
For instructions that accept an immediate address space identifier,
@code{@value{AS}} provides many mnemonics corresponding to
V9 defined as well as UltraSPARC and Niagara extended values.
For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}.
See the V9 and processor specific manuals for details.
 
@end itemize
 
@node Sparc-Relocs
@subsection Relocations
@cindex Sparc relocations
@cindex relocations, Sparc
 
ELF relocations are available as defined in the 32-bit and 64-bit
Sparc ELF specifications.
 
@code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10}
is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is
obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained
using @samp{%lox}. For example:
 
@example
sethi %hi(symbol), %g1
or %g1, %lo(symbol), %g1
 
sethi %hix(symbol), %g1
xor %g1, %lox(symbol), %g1
@end example
 
These ``high'' mnemonics extract bits 31:10 of their operand,
and the ``low'' mnemonics extract bits 9:0 of their operand.
 
V9 code model relocations can be requested as follows:
 
@itemize @bullet
@item
@code{R_SPARC_HH22} is requested using @samp{%hh}. It can
also be generated using @samp{%uhi}.
@item
@code{R_SPARC_HM10} is requested using @samp{%hm}. It can
also be generated using @samp{%ulo}.
@item
@code{R_SPARC_LM22} is requested using @samp{%lm}.
 
@item
@code{R_SPARC_H44} is requested using @samp{%h44}.
@item
@code{R_SPARC_M44} is requested using @samp{%m44}.
@item
@code{R_SPARC_L44} is requested using @samp{%l44}.
@end itemize
 
The PC relative relocation @code{R_SPARC_PC22} can be obtained by
enclosing an operand inside of @samp{%pc22}. Likewise, the
@code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
These are mostly used when assembling PIC code. For example, the
standard PIC sequence on Sparc to get the base of the global offset
table, PC relative, into a register, can be performed as:
 
@example
sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
@end example
 
Several relocations exist to allow the link editor to potentially
optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22}
relocation can obtained by enclosing an operand inside of
@samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10}
relocation can obtained by enclosing an operand inside of
@samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be
obtained by enclosing an operand inside of @samp{%gdop}.
For example, assuming the GOT base is in register @code{%l7}:
 
@example
sethi %gdop_hix22(symbol), %l1
xor %l1, %gdop_lox10(symbol), %l1
ld [%l7 + %l1], %l2, %gdop(symbol)
@end example
 
There are many relocations that can be requested for access to
thread local storage variables. All of the Sparc TLS mnemonics
are supported:
 
@itemize @bullet
@item
@code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}.
@item
@code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}.
@item
@code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}.
@item
@code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}.
 
@item
@code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}.
@item
@code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}.
@item
@code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}.
@item
@code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}.
 
@item
@code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}.
@item
@code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}.
@item
@code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}.
 
@item
@code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}.
@item
@code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}.
@item
@code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}.
@item
@code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}.
@item
@code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}.
 
@item
@code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}.
@item
@code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}.
@end itemize
 
Here are some example TLS model sequences.
 
First, General Dynamic:
 
@example
sethi %tgd_hi22(symbol), %l1
add %l1, %tgd_lo10(symbol), %l1
add %l7, %l1, %o0, %tgd_add(symbol)
call __tls_get_addr, %tgd_call(symbol)
nop
@end example
 
Local Dynamic:
 
@example
sethi %tldm_hi22(symbol), %l1
add %l1, %tldm_lo10(symbol), %l1
add %l7, %l1, %o0, %tldm_add(symbol)
call __tls_get_addr, %tldm_call(symbol)
nop
 
sethi %tldo_hix22(symbol), %l1
xor %l1, %tldo_lox10(symbol), %l1
add %o0, %l1, %l1, %tldo_add(symbol)
@end example
 
Initial Exec:
 
@example
sethi %tie_hi22(symbol), %l1
add %l1, %tie_lo10(symbol), %l1
ld [%l7 + %l1], %o0, %tie_ld(symbol)
add %g7, %o0, %o0, %tie_add(symbol)
 
sethi %tie_hi22(symbol), %l1
add %l1, %tie_lo10(symbol), %l1
ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
add %g7, %o0, %o0, %tie_add(symbol)
@end example
 
And finally, Local Exec:
 
@example
sethi %tle_hix22(symbol), %l1
add %l1, %tle_lox10(symbol), %l1
add %g7, %l1, %l1
@end example
 
When assembling for 64-bit, and a secondary constant addend is
specified in an address expression that would normally generate
an @code{R_SPARC_LO10} relocation, the assembler will emit an
@code{R_SPARC_OLO10} instead.
 
@node Sparc-Size-Translations
@subsection Size Translations
@cindex Sparc size translations
@cindex size, translations, Sparc
 
Often it is desirable to write code in an operand size agnostic
manner. @code{@value{AS}} provides support for this via
operand size opcode translations. Translations are supported
for loads, stores, shifts, compare-and-swap atomics, and the
@samp{clr} synthetic instruction.
 
If generating 32-bit code, @code{@value{AS}} will generate the
32-bit opcode. Whereas if 64-bit code is being generated,
the 64-bit opcode will be emitted. For example @code{ldn}
will be transformed into @code{ld} for 32-bit code and
@code{ldx} for 64-bit code.
 
Here is an example meant to demonstrate all the supported
opcode translations:
 
@example
ldn [%o0], %o1
ldna [%o0] %asi, %o2
stn %o1, [%o0]
stna %o2, [%o0] %asi
slln %o3, 3, %o3
srln %o4, 8, %o4
sran %o5, 12, %o5
casn [%o0], %o1, %o2
casna [%o0] %asi, %o1, %o2
clrn %g1
@end example
 
In 32-bit mode @code{@value{AS}} will emit:
 
@example
ld [%o0], %o1
lda [%o0] %asi, %o2
st %o1, [%o0]
sta %o2, [%o0] %asi
sll %o3, 3, %o3
srl %o4, 8, %o4
sra %o5, 12, %o5
cas [%o0], %o1, %o2
casa [%o0] %asi, %o1, %o2
clr %g1
@end example
 
And in 64-bit mode @code{@value{AS}} will emit:
 
@example
ldx [%o0], %o1
ldxa [%o0] %asi, %o2
stx %o1, [%o0]
stxa %o2, [%o0] %asi
sllx %o3, 3, %o3
srlx %o4, 8, %o4
srax %o5, 12, %o5
casx [%o0], %o1, %o2
casxa [%o0] %asi, %o1, %o2
clrx %g1
@end example
 
Finally, the @samp{.nword} translating directive is supported
as well. It is documented in the section on Sparc machine
directives.
 
@node Sparc-Float
@section Floating Point
 
@cindex floating point, SPARC (@sc{ieee})
@cindex SPARC floating point (@sc{ieee})
The Sparc uses @sc{ieee} floating-point numbers.
 
@node Sparc-Directives
@section Sparc Machine Directives
 
@cindex SPARC machine directives
@cindex machine directives, SPARC
The Sparc version of @code{@value{AS}} supports the following additional
machine directives:
 
@table @code
@cindex @code{align} directive, SPARC
@item .align
This must be followed by the desired alignment in bytes.
 
@cindex @code{common} directive, SPARC
@item .common
This must be followed by a symbol name, a positive number, and
@code{"bss"}. This behaves somewhat like @code{.comm}, but the
syntax is different.
 
@cindex @code{half} directive, SPARC
@item .half
This is functionally identical to @code{.short}.
 
@cindex @code{nword} directive, SPARC
@item .nword
On the Sparc, the @code{.nword} directive produces native word sized value,
ie. if assembling with -32 it is equivalent to @code{.word}, if assembling
with -64 it is equivalent to @code{.xword}.
 
@cindex @code{proc} directive, SPARC
@item .proc
This directive is ignored. Any text following it on the same
line is also ignored.
 
@cindex @code{register} directive, SPARC
@item .register
This directive declares use of a global application or system register.
It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
the symbol name for that register. If symbol name is @code{#scratch},
it is a scratch register, if it is @code{#ignore}, it just suppresses any
errors about using undeclared global register, but does not emit any
information about it into the object file. This can be useful e.g. if you
save the register before use and restore it after.
 
@cindex @code{reserve} directive, SPARC
@item .reserve
This must be followed by a symbol name, a positive number, and
@code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
syntax is different.
 
@cindex @code{seg} directive, SPARC
@item .seg
This must be followed by @code{"text"}, @code{"data"}, or
@code{"data1"}. It behaves like @code{.text}, @code{.data}, or
@code{.data 1}.
 
@cindex @code{skip} directive, SPARC
@item .skip
This is functionally identical to the @code{.space} directive.
 
@cindex @code{word} directive, SPARC
@item .word
On the Sparc, the @code{.word} directive produces 32 bit values,
instead of the 16 bit values it produces on many other machines.
 
@cindex @code{xword} directive, SPARC
@item .xword
On the Sparc V9 processor, the @code{.xword} directive produces
64 bit values.
@end table
/binutils/gas/doc/c-tic54x.texi
0,0 → 1,797
@c Copyright 2000, 2002, 2003, 2006, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c TI TMS320C54X description by Timothy Wall, twall@cygnus.com
@ifset GENERIC
@page
@node TIC54X-Dependent
@chapter TIC54X Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter TIC54X Dependent Features
@end ifclear
 
@cindex TIC54X support
@menu
* TIC54X-Opts:: Command-line Options
* TIC54X-Block:: Blocking
* TIC54X-Env:: Environment Settings
* TIC54X-Constants:: Constants Syntax
* TIC54X-Subsyms:: String Substitution
* TIC54X-Locals:: Local Label Syntax
* TIC54X-Builtins:: Builtin Assembler Math Functions
* TIC54X-Ext:: Extended Addressing Support
* TIC54X-Directives:: Directives
* TIC54X-Macros:: Macro Features
* TIC54X-MMRegs:: Memory-mapped Registers
* TIC54X-Syntax:: Syntax
@end menu
 
@node TIC54X-Opts
@section Options
 
@cindex options, TIC54X
@cindex TIC54X options
The TMS320C54X version of @code{@value{AS}} has a few machine-dependent options.
 
@cindex @samp{-mfar-mode} option, far-mode
@cindex @samp{-mf} option, far-mode
You can use the @samp{-mfar-mode} option to enable extended addressing mode.
All addresses will be assumed to be > 16 bits, and the appropriate
relocation types will be used. This option is equivalent to using the
@samp{.far_mode} directive in the assembly code. If you do not use the
@samp{-mfar-mode} option, all references will be assumed to be 16 bits.
This option may be abbreviated to @samp{-mf}.
 
@cindex @samp{-mcpu} option, cpu
You can use the @samp{-mcpu} option to specify a particular CPU.
This option is equivalent to using the @samp{.version} directive in the
assembly code. For recognized CPU codes, see
@xref{TIC54X-Directives,,@code{.version}}. The default CPU version is
@samp{542}.
 
@cindex @samp{-merrors-to-file} option, stderr redirect
@cindex @samp{-me} option, stderr redirect
You can use the @samp{-merrors-to-file} option to redirect error output
to a file (this provided for those deficient environments which don't
provide adequate output redirection). This option may be abbreviated to
@samp{-me}.
 
@node TIC54X-Block
@section Blocking
A blocked section or memory block is guaranteed not to cross the blocking
boundary (usually a page, or 128 words) if it is smaller than the
blocking size, or to start on a page boundary if it is larger than the
blocking size.
 
@node TIC54X-Env
@section Environment Settings
 
@cindex environment settings, TIC54X
@cindex @samp{A_DIR} environment variable, TIC54X
@cindex @samp{C54XDSP_DIR} environment variable, TIC54X
@samp{C54XDSP_DIR} and @samp{A_DIR} are semicolon-separated
paths which are added to the list of directories normally searched for
source and include files. @samp{C54XDSP_DIR} will override @samp{A_DIR}.
 
@node TIC54X-Constants
@section Constants Syntax
 
@cindex constants, TIC54X
The TIC54X version of @code{@value{AS}} allows the following additional
constant formats, using a suffix to indicate the radix:
@smallexample
@cindex binary constants, TIC54X
 
Binary @code{000000B, 011000b}
Octal @code{10Q, 224q}
Hexadecimal @code{45h, 0FH}
 
@end smallexample
 
@node TIC54X-Subsyms
@section String Substitution
A subset of allowable symbols (which we'll call subsyms) may be assigned
arbitrary string values. This is roughly equivalent to C preprocessor
#define macros. When @code{@value{AS}} encounters one of these
symbols, the symbol is replaced in the input stream by its string value.
Subsym names @strong{must} begin with a letter.
 
Subsyms may be defined using the @code{.asg} and @code{.eval} directives
(@xref{TIC54X-Directives,,@code{.asg}},
@xref{TIC54X-Directives,,@code{.eval}}.
 
Expansion is recursive until a previously encountered symbol is seen, at
which point substitution stops.
 
In this example, x is replaced with SYM2; SYM2 is replaced with SYM1, and SYM1
is replaced with x. At this point, x has already been encountered
and the substitution stops.
 
@smallexample @code
.asg "x",SYM1
.asg "SYM1",SYM2
.asg "SYM2",x
add x,a ; final code assembled is "add x, a"
@end smallexample
 
Macro parameters are converted to subsyms; a side effect of this is the normal
@code{@value{AS}} '\ARG' dereferencing syntax is unnecessary. Subsyms
defined within a macro will have global scope, unless the @code{.var}
directive is used to identify the subsym as a local macro variable
@pxref{TIC54X-Directives,,@code{.var}}.
 
Substitution may be forced in situations where replacement might be
ambiguous by placing colons on either side of the subsym. The following
code:
 
@smallexample @code
.eval "10",x
LAB:X: add #x, a
@end smallexample
 
When assembled becomes:
 
@smallexample @code
LAB10 add #10, a
@end smallexample
 
Smaller parts of the string assigned to a subsym may be accessed with
the following syntax:
 
@table @code
@item @code{:@var{symbol}(@var{char_index}):}
Evaluates to a single-character string, the character at @var{char_index}.
@item @code{:@var{symbol}(@var{start},@var{length}):}
Evaluates to a substring of @var{symbol} beginning at @var{start} with
length @var{length}.
@end table
 
@node TIC54X-Locals
@section Local Labels
Local labels may be defined in two ways:
 
@itemize @bullet
@item
$N, where N is a decimal number between 0 and 9
@item
LABEL?, where LABEL is any legal symbol name.
@end itemize
 
Local labels thus defined may be redefined or automatically generated.
The scope of a local label is based on when it may be undefined or reset.
This happens when one of the following situations is encountered:
 
@itemize @bullet
@item
.newblock directive @pxref{TIC54X-Directives,,@code{.newblock}}
@item
The current section is changed (.sect, .text, or .data)
@item
Entering or leaving an included file
@item
The macro scope where the label was defined is exited
@end itemize
 
@node TIC54X-Builtins
@section Math Builtins
 
@cindex math builtins, TIC54X
@cindex TIC54X builtin math functions
@cindex builtin math functions, TIC54X
 
The following built-in functions may be used to generate a
floating-point value. All return a floating-point value except
@samp{$cvi}, @samp{$int}, and @samp{$sgn}, which return an integer
value.
 
@table @code
@cindex @code{$acos} math builtin, TIC54X
@item @code{$acos(@var{expr})}
Returns the floating point arccosine of @var{expr}.
 
@cindex @code{$asin} math builtin, TIC54X
@item @code{$asin(@var{expr})}
Returns the floating point arcsine of @var{expr}.
 
@cindex @code{$atan} math builtin, TIC54X
@item @code{$atan(@var{expr})}
Returns the floating point arctangent of @var{expr}.
 
@cindex @code{$atan2} math builtin, TIC54X
@item @code{$atan2(@var{expr1},@var{expr2})}
Returns the floating point arctangent of @var{expr1} / @var{expr2}.
 
@cindex @code{$ceil} math builtin, TIC54X
@item @code{$ceil(@var{expr})}
Returns the smallest integer not less than @var{expr} as floating point.
 
@cindex @code{$cosh} math builtin, TIC54X
@item @code{$cosh(@var{expr})}
Returns the floating point hyperbolic cosine of @var{expr}.
 
@cindex @code{$cos} math builtin, TIC54X
@item @code{$cos(@var{expr})}
Returns the floating point cosine of @var{expr}.
 
@cindex @code{$cvf} math builtin, TIC54X
@item @code{$cvf(@var{expr})}
Returns the integer value @var{expr} converted to floating-point.
 
@cindex @code{$cvi} math builtin, TIC54X
@item @code{$cvi(@var{expr})}
Returns the floating point value @var{expr} converted to integer.
 
@cindex @code{$exp} math builtin, TIC54X
@item @code{$exp(@var{expr})}
Returns the floating point value e ^ @var{expr}.
 
@cindex @code{$fabs} math builtin, TIC54X
@item @code{$fabs(@var{expr})}
Returns the floating point absolute value of @var{expr}.
 
@cindex @code{$floor} math builtin, TIC54X
@item @code{$floor(@var{expr})}
Returns the largest integer that is not greater than @var{expr} as
floating point.
 
@cindex @code{$fmod} math builtin, TIC54X
@item @code{$fmod(@var{expr1},@var{expr2})}
Returns the floating point remainder of @var{expr1} / @var{expr2}.
 
@cindex @code{$int} math builtin, TIC54X
@item @code{$int(@var{expr})}
Returns 1 if @var{expr} evaluates to an integer, zero otherwise.
 
@cindex @code{$ldexp} math builtin, TIC54X
@item @code{$ldexp(@var{expr1},@var{expr2})}
Returns the floating point value @var{expr1} * 2 ^ @var{expr2}.
 
@cindex @code{$log10} math builtin, TIC54X
@item @code{$log10(@var{expr})}
Returns the base 10 logarithm of @var{expr}.
 
@cindex @code{$log} math builtin, TIC54X
@item @code{$log(@var{expr})}
Returns the natural logarithm of @var{expr}.
 
@cindex @code{$max} math builtin, TIC54X
@item @code{$max(@var{expr1},@var{expr2})}
Returns the floating point maximum of @var{expr1} and @var{expr2}.
 
@cindex @code{$min} math builtin, TIC54X
@item @code{$min(@var{expr1},@var{expr2})}
Returns the floating point minimum of @var{expr1} and @var{expr2}.
 
@cindex @code{$pow} math builtin, TIC54X
@item @code{$pow(@var{expr1},@var{expr2})}
Returns the floating point value @var{expr1} ^ @var{expr2}.
 
@cindex @code{$round} math builtin, TIC54X
@item @code{$round(@var{expr})}
Returns the nearest integer to @var{expr} as a floating point number.
 
@cindex @code{$sgn} math builtin, TIC54X
@item @code{$sgn(@var{expr})}
Returns -1, 0, or 1 based on the sign of @var{expr}.
 
@cindex @code{$sin} math builtin, TIC54X
@item @code{$sin(@var{expr})}
Returns the floating point sine of @var{expr}.
 
@cindex @code{$sinh} math builtin, TIC54X
@item @code{$sinh(@var{expr})}
Returns the floating point hyperbolic sine of @var{expr}.
 
@cindex @code{$sqrt} math builtin, TIC54X
@item @code{$sqrt(@var{expr})}
Returns the floating point square root of @var{expr}.
 
@cindex @code{$tan} math builtin, TIC54X
@item @code{$tan(@var{expr})}
Returns the floating point tangent of @var{expr}.
 
@cindex @code{$tanh} math builtin, TIC54X
@item @code{$tanh(@var{expr})}
Returns the floating point hyperbolic tangent of @var{expr}.
 
@cindex @code{$trunc} math builtin, TIC54X
@item @code{$trunc(@var{expr})}
Returns the integer value of @var{expr} truncated towards zero as
floating point.
 
@end table
 
@node TIC54X-Ext
@section Extended Addressing
The @code{LDX} pseudo-op is provided for loading the extended addressing bits
of a label or address. For example, if an address @code{_label} resides
in extended program memory, the value of @code{_label} may be loaded as
follows:
@smallexample @code
ldx #_label,16,a ; loads extended bits of _label
or #_label,a ; loads lower 16 bits of _label
bacc a ; full address is in accumulator A
@end smallexample
 
@node TIC54X-Directives
@section Directives
 
@cindex machine directives, TIC54X
@cindex TIC54X machine directives
 
@table @code
 
@cindex @code{align} directive, TIC54X
@cindex @code{even} directive, TIC54X
@item .align [@var{size}]
@itemx .even
Align the section program counter on the next boundary, based on
@var{size}. @var{size} may be any power of 2. @code{.even} is
equivalent to @code{.align} with a @var{size} of 2.
@table @code
@item 1
Align SPC to word boundary
@item 2
Align SPC to longword boundary (same as .even)
@item 128
Align SPC to page boundary
@end table
 
@cindex @code{asg} directive, TIC54X
@item .asg @var{string}, @var{name}
Assign @var{name} the string @var{string}. String replacement is
performed on @var{string} before assignment.
 
@cindex @code{eval} directive, TIC54X
@itemx .eval @var{string}, @var{name}
Evaluate the contents of string @var{string} and assign the result as a
string to the subsym @var{name}. String replacement is performed on
@var{string} before assignment.
 
@cindex @code{bss} directive, TIC54X
@item .bss @var{symbol}, @var{size} [, [@var{blocking_flag}] [,@var{alignment_flag}]]
Reserve space for @var{symbol} in the .bss section. @var{size} is in
words. If present, @var{blocking_flag} indicates the allocated space
should be aligned on a page boundary if it would otherwise cross a page
boundary. If present, @var{alignment_flag} causes the assembler to
allocate @var{size} on a long word boundary.
 
@cindex @code{byte} directive, TIC54X
@cindex @code{ubyte} directive, TIC54X
@cindex @code{char} directive, TIC54X
@cindex @code{uchar} directive, TIC54X
@item .byte @var{value} [,...,@var{value_n}]
@itemx .ubyte @var{value} [,...,@var{value_n}]
@itemx .char @var{value} [,...,@var{value_n}]
@itemx .uchar @var{value} [,...,@var{value_n}]
Place one or more bytes into consecutive words of the current section.
The upper 8 bits of each word is zero-filled. If a label is used, it
points to the word allocated for the first byte encountered.
 
@cindex @code{clink} directive, TIC54X
@item .clink ["@var{section_name}"]
Set STYP_CLINK flag for this section, which indicates to the linker that
if no symbols from this section are referenced, the section should not
be included in the link. If @var{section_name} is omitted, the current
section is used.
 
@cindex @code{c_mode} directive, TIC54X
@item .c_mode
TBD.
 
@cindex @code{copy} directive, TIC54X
@item .copy "@var{filename}" | @var{filename}
@itemx .include "@var{filename}" | @var{filename}
Read source statements from @var{filename}. The normal include search
path is used. Normally .copy will cause statements from the included
file to be printed in the assembly listing and .include will not, but
this distinction is not currently implemented.
 
@cindex @code{data} directive, TIC54X
@item .data
Begin assembling code into the .data section.
 
@cindex @code{double} directive, TIC54X
@cindex @code{ldouble} directive, TIC54X
@cindex @code{float} directive, TIC54X
@cindex @code{xfloat} directive, TIC54X
@item .double @var{value} [,...,@var{value_n}]
@itemx .ldouble @var{value} [,...,@var{value_n}]
@itemx .float @var{value} [,...,@var{value_n}]
@itemx .xfloat @var{value} [,...,@var{value_n}]
Place an IEEE single-precision floating-point representation of one or
more floating-point values into the current section. All but
@code{.xfloat} align the result on a longword boundary. Values are
stored most-significant word first.
 
@cindex @code{drlist} directive, TIC54X
@cindex @code{drnolist} directive, TIC54X
@item .drlist
@itemx .drnolist
Control printing of directives to the listing file. Ignored.
 
@cindex @code{emsg} directive, TIC54X
@cindex @code{mmsg} directive, TIC54X
@cindex @code{wmsg} directive, TIC54X
@item .emsg @var{string}
@itemx .mmsg @var{string}
@itemx .wmsg @var{string}
Emit a user-defined error, message, or warning, respectively.
 
@cindex @code{far_mode} directive, TIC54X
@item .far_mode
Use extended addressing when assembling statements. This should appear
only once per file, and is equivalent to the -mfar-mode option @pxref{TIC54X-Opts,,@code{-mfar-mode}}.
 
@cindex @code{fclist} directive, TIC54X
@cindex @code{fcnolist} directive, TIC54X
@item .fclist
@itemx .fcnolist
Control printing of false conditional blocks to the listing file.
 
@cindex @code{field} directive, TIC54X
@item .field @var{value} [,@var{size}]
Initialize a bitfield of @var{size} bits in the current section. If
@var{value} is relocatable, then @var{size} must be 16. @var{size}
defaults to 16 bits. If @var{value} does not fit into @var{size} bits,
the value will be truncated. Successive @code{.field} directives will
pack starting at the current word, filling the most significant bits
first, and aligning to the start of the next word if the field size does
not fit into the space remaining in the current word. A @code{.align}
directive with an operand of 1 will force the next @code{.field}
directive to begin packing into a new word. If a label is used, it
points to the word that contains the specified field.
 
@cindex @code{global} directive, TIC54X
@cindex @code{def} directive, TIC54X
@cindex @code{ref} directive, TIC54X
@item .global @var{symbol} [,...,@var{symbol_n}]
@itemx .def @var{symbol} [,...,@var{symbol_n}]
@itemx .ref @var{symbol} [,...,@var{symbol_n}]
@code{.def} nominally identifies a symbol defined in the current file
and available to other files. @code{.ref} identifies a symbol used in
the current file but defined elsewhere. Both map to the standard
@code{.global} directive.
 
@cindex @code{half} directive, TIC54X
@cindex @code{uhalf} directive, TIC54X
@cindex @code{short} directive, TIC54X
@cindex @code{ushort} directive, TIC54X
@cindex @code{int} directive, TIC54X
@cindex @code{uint} directive, TIC54X
@cindex @code{word} directive, TIC54X
@cindex @code{uword} directive, TIC54X
@item .half @var{value} [,...,@var{value_n}]
@itemx .uhalf @var{value} [,...,@var{value_n}]
@itemx .short @var{value} [,...,@var{value_n}]
@itemx .ushort @var{value} [,...,@var{value_n}]
@itemx .int @var{value} [,...,@var{value_n}]
@itemx .uint @var{value} [,...,@var{value_n}]
@itemx .word @var{value} [,...,@var{value_n}]
@itemx .uword @var{value} [,...,@var{value_n}]
Place one or more values into consecutive words of the current section.
If a label is used, it points to the word allocated for the first value
encountered.
 
@cindex @code{label} directive, TIC54X
@item .label @var{symbol}
Define a special @var{symbol} to refer to the load time address of the
current section program counter.
 
@cindex @code{length} directive, TIC54X
@cindex @code{width} directive, TIC54X
@item .length
@itemx .width
Set the page length and width of the output listing file. Ignored.
 
@cindex @code{list} directive, TIC54X
@cindex @code{nolist} directive, TIC54X
@item .list
@itemx .nolist
Control whether the source listing is printed. Ignored.
 
@cindex @code{long} directive, TIC54X
@cindex @code{ulong} directive, TIC54X
@cindex @code{xlong} directive, TIC54X
@item .long @var{value} [,...,@var{value_n}]
@itemx .ulong @var{value} [,...,@var{value_n}]
@itemx .xlong @var{value} [,...,@var{value_n}]
Place one or more 32-bit values into consecutive words in the current
section. The most significant word is stored first. @code{.long} and
@code{.ulong} align the result on a longword boundary; @code{xlong} does
not.
 
@cindex @code{loop} directive, TIC54X
@cindex @code{break} directive, TIC54X
@cindex @code{endloop} directive, TIC54X
@item .loop [@var{count}]
@itemx .break [@var{condition}]
@itemx .endloop
Repeatedly assemble a block of code. @code{.loop} begins the block, and
@code{.endloop} marks its termination. @var{count} defaults to 1024,
and indicates the number of times the block should be repeated.
@code{.break} terminates the loop so that assembly begins after the
@code{.endloop} directive. The optional @var{condition} will cause the
loop to terminate only if it evaluates to zero.
 
@cindex @code{macro} directive, TIC54X
@cindex @code{endm} directive, TIC54X
@item @var{macro_name} .macro [@var{param1}][,...@var{param_n}]
@itemx [.mexit]
@itemx .endm
See the section on macros for more explanation (@xref{TIC54X-Macros}.
 
@cindex @code{mlib} directive, TIC54X
@item .mlib "@var{filename}" | @var{filename}
Load the macro library @var{filename}. @var{filename} must be an
archived library (BFD ar-compatible) of text files, expected to contain
only macro definitions. The standard include search path is used.
 
@cindex @code{mlist} directive, TIC54X
@cindex @code{mnolist} directive, TIC54X
@item .mlist
@itemx .mnolist
Control whether to include macro and loop block expansions in the
listing output. Ignored.
 
@cindex @code{mmregs} directive, TIC54X
@item .mmregs
Define global symbolic names for the 'c54x registers. Supposedly
equivalent to executing @code{.set} directives for each register with
its memory-mapped value, but in reality is provided only for
compatibility and does nothing.
 
@cindex @code{newblock} directive, TIC54X
@item .newblock
This directive resets any TIC54X local labels currently defined. Normal
@code{@value{AS}} local labels are unaffected.
 
@cindex @code{option} directive, TIC54X
@item .option @var{option_list}
Set listing options. Ignored.
 
@cindex @code{sblock} directive, TIC54X
@item .sblock "@var{section_name}" | @var{section_name} [,"@var{name_n}" | @var{name_n}]
Designate @var{section_name} for blocking. Blocking guarantees that a
section will start on a page boundary (128 words) if it would otherwise
cross a page boundary. Only initialized sections may be designated with
this directive. See also @xref{TIC54X-Block}.
 
@cindex @code{sect} directive, TIC54X
@item .sect "@var{section_name}"
Define a named initialized section and make it the current section.
 
@cindex @code{set} directive, TIC54X
@cindex @code{equ} directive, TIC54X
@item @var{symbol} .set "@var{value}"
@itemx @var{symbol} .equ "@var{value}"
Equate a constant @var{value} to a @var{symbol}, which is placed in the
symbol table. @var{symbol} may not be previously defined.
 
@cindex @code{space} directive, TIC54X
@cindex @code{bes} directive, TIC54X
@item .space @var{size_in_bits}
@itemx .bes @var{size_in_bits}
Reserve the given number of bits in the current section and zero-fill
them. If a label is used with @code{.space}, it points to the
@strong{first} word reserved. With @code{.bes}, the label points to the
@strong{last} word reserved.
 
@cindex @code{sslist} directive, TIC54X
@cindex @code{ssnolist} directive, TIC54X
@item .sslist
@itemx .ssnolist
Controls the inclusion of subsym replacement in the listing output. Ignored.
 
@cindex @code{string} directive, TIC54X
@cindex @code{pstring} directive, TIC54X
@item .string "@var{string}" [,...,"@var{string_n}"]
@itemx .pstring "@var{string}" [,...,"@var{string_n}"]
Place 8-bit characters from @var{string} into the current section.
@code{.string} zero-fills the upper 8 bits of each word, while
@code{.pstring} puts two characters into each word, filling the
most-significant bits first. Unused space is zero-filled. If a label
is used, it points to the first word initialized.
 
@cindex @code{struct} directive, TIC54X
@cindex @code{tag} directive, TIC54X
@cindex @code{endstruct} directive, TIC54X
@item [@var{stag}] .struct [@var{offset}]
@itemx [@var{name_1}] element [@var{count_1}]
@itemx [@var{name_2}] element [@var{count_2}]
@itemx [@var{tname}] .tag @var{stagx} [@var{tcount}]
@itemx ...
@itemx [@var{name_n}] element [@var{count_n}]
@itemx [@var{ssize}] .endstruct
@itemx @var{label} .tag [@var{stag}]
Assign symbolic offsets to the elements of a structure. @var{stag}
defines a symbol to use to reference the structure. @var{offset}
indicates a starting value to use for the first element encountered;
otherwise it defaults to zero. Each element can have a named offset,
@var{name}, which is a symbol assigned the value of the element's offset
into the structure. If @var{stag} is missing, these become global
symbols. @var{count} adjusts the offset that many times, as if
@code{element} were an array. @code{element} may be one of
@code{.byte}, @code{.word}, @code{.long}, @code{.float}, or any
equivalent of those, and the structure offset is adjusted accordingly.
@code{.field} and @code{.string} are also allowed; the size of
@code{.field} is one bit, and @code{.string} is considered to be one
word in size. Only element descriptors, structure/union tags,
@code{.align} and conditional assembly directives are allowed within
@code{.struct}/@code{.endstruct}. @code{.align} aligns member offsets
to word boundaries only. @var{ssize}, if provided, will always be
assigned the size of the structure.
 
The @code{.tag} directive, in addition to being used to define a
structure/union element within a structure, may be used to apply a
structure to a symbol. Once applied to @var{label}, the individual
structure elements may be applied to @var{label} to produce the desired
offsets using @var{label} as the structure base.
 
@cindex @code{tab} directive, TIC54X
@item .tab
Set the tab size in the output listing. Ignored.
 
@cindex @code{union} directive, TIC54X
@cindex @code{tag} directive, TIC54X
@cindex @code{endunion} directive, TIC54X
@item [@var{utag}] .union
@itemx [@var{name_1}] element [@var{count_1}]
@itemx [@var{name_2}] element [@var{count_2}]
@itemx [@var{tname}] .tag @var{utagx}[,@var{tcount}]
@itemx ...
@itemx [@var{name_n}] element [@var{count_n}]
@itemx [@var{usize}] .endstruct
@itemx @var{label} .tag [@var{utag}]
Similar to @code{.struct}, but the offset after each element is reset to
zero, and the @var{usize} is set to the maximum of all defined elements.
Starting offset for the union is always zero.
 
@cindex @code{usect} directive, TIC54X
@item [@var{symbol}] .usect "@var{section_name}", @var{size}, [,[@var{blocking_flag}] [,@var{alignment_flag}]]
Reserve space for variables in a named, uninitialized section (similar to
.bss). @code{.usect} allows definitions sections independent of .bss.
@var{symbol} points to the first location reserved by this allocation.
The symbol may be used as a variable name. @var{size} is the allocated
size in words. @var{blocking_flag} indicates whether to block this
section on a page boundary (128 words) (@pxref{TIC54X-Block}).
@var{alignment flag} indicates whether the section should be
longword-aligned.
 
@cindex @code{var} directive, TIC54X
@item .var @var{sym}[,..., @var{sym_n}]
Define a subsym to be a local variable within a macro. See
@xref{TIC54X-Macros}.
 
@cindex @code{version} directive, TIC54X
@item .version @var{version}
Set which processor to build instructions for. Though the following
values are accepted, the op is ignored.
@table @code
@item 541
@itemx 542
@itemx 543
@itemx 545
@itemx 545LP
@itemx 546LP
@itemx 548
@itemx 549
@end table
@end table
 
@node TIC54X-Macros
@section Macros
 
@cindex TIC54X-specific macros
@cindex macros, TIC54X
Macros do not require explicit dereferencing of arguments (i.e., \ARG).
 
During macro expansion, the macro parameters are converted to subsyms.
If the number of arguments passed the macro invocation exceeds the
number of parameters defined, the last parameter is assigned the string
equivalent of all remaining arguments. If fewer arguments are given
than parameters, the missing parameters are assigned empty strings. To
include a comma in an argument, you must enclose the argument in quotes.
 
@cindex subsym builtins, TIC54X
@cindex TIC54X subsym builtins
@cindex builtin subsym functions, TIC54X
The following built-in subsym functions allow examination of the string
value of subsyms (or ordinary strings). The arguments are strings
unless otherwise indicated (subsyms passed as args will be replaced by
the strings they represent).
@table @code
@cindex @code{$symlen} subsym builtin, TIC54X
@item @code{$symlen(@var{str})}
Returns the length of @var{str}.
 
@cindex @code{$symcmp} subsym builtin, TIC54X
@item @code{$symcmp(@var{str1},@var{str2})}
Returns 0 if @var{str1} == @var{str2}, non-zero otherwise.
 
@cindex @code{$firstch} subsym builtin, TIC54X
@item @code{$firstch(@var{str},@var{ch})}
Returns index of the first occurrence of character constant @var{ch} in
@var{str}.
 
@cindex @code{$lastch} subsym builtin, TIC54X
@item @code{$lastch(@var{str},@var{ch})}
Returns index of the last occurrence of character constant @var{ch} in
@var{str}.
 
@cindex @code{$isdefed} subsym builtin, TIC54X
@item @code{$isdefed(@var{symbol})}
Returns zero if the symbol @var{symbol} is not in the symbol table,
non-zero otherwise.
 
@cindex @code{$ismember} subsym builtin, TIC54X
@item @code{$ismember(@var{symbol},@var{list})}
Assign the first member of comma-separated string @var{list} to
@var{symbol}; @var{list} is reassigned the remainder of the list. Returns
zero if @var{list} is a null string. Both arguments must be subsyms.
 
@cindex @code{$iscons} subsym builtin, TIC54X
@item @code{$iscons(@var{expr})}
Returns 1 if string @var{expr} is binary, 2 if octal, 3 if hexadecimal,
4 if a character, 5 if decimal, and zero if not an integer.
 
@cindex @code{$isname} subsym builtin, TIC54X
@item @code{$isname(@var{name})}
Returns 1 if @var{name} is a valid symbol name, zero otherwise.
 
@cindex @code{$isreg} subsym builtin, TIC54X
@item @code{$isreg(@var{reg})}
Returns 1 if @var{reg} is a valid predefined register name (AR0-AR7 only).
 
@cindex @code{$structsz} subsym builtin, TIC54X
@item @code{$structsz(@var{stag})}
Returns the size of the structure or union represented by @var{stag}.
 
@cindex @code{$structacc} subsym builtin, TIC54X
@item @code{$structacc(@var{stag})}
Returns the reference point of the structure or union represented by
@var{stag}. Always returns zero.
 
@end table
 
@node TIC54X-MMRegs
@section Memory-mapped Registers
 
@cindex TIC54X memory-mapped registers
@cindex registers, TIC54X memory-mapped
@cindex memory-mapped registers, TIC54X
The following symbols are recognized as memory-mapped registers:
 
@table @code
@end table
 
@node TIC54X-Syntax
@section TIC54X Syntax
@menu
* TIC54X-Chars:: Special Characters
@end menu
 
@node TIC54X-Chars
@subsection Special Characters
 
@cindex line comment character, TIC54X
@cindex TIC54X line comment character
The presence of a @samp{;} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
The presence of an asterisk (@samp{*}) at the start of a line also
indicates a comment that extends to the end of that line.
 
@cindex line separator, TIC54X
@cindex statement separator, TIC54X
@cindex TIC54X line separator
The TIC54X assembler does not currently support a line separator
character.
 
/binutils/gas/doc/c-tilepro.texi
0,0 → 1,332
@c Copyright 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node TILEPro-Dependent
@chapter TILEPro Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter TILEPro Dependent Features
@end ifclear
 
@cindex TILEPro support
@menu
* TILEPro Options:: TILEPro Options
* TILEPro Syntax:: TILEPro Syntax
* TILEPro Directives:: TILEPro Directives
@end menu
 
@node TILEPro Options
@section Options
 
@code{@value{AS}} has no machine-dependent command-line options for
TILEPro.
 
@node TILEPro Syntax
@section Syntax
@cindex TILEPro syntax
@cindex syntax, TILEPro
 
Block comments are delimited by @samp{/*} and @samp{*/}. End of line
comments may be introduced by @samp{#}.
 
Instructions consist of a leading opcode or macro name followed by
whitespace and an optional comma-separated list of operands:
 
@smallexample
@var{opcode} [@var{operand}, @dots{}]
@end smallexample
 
Instructions must be separated by a newline or semicolon.
 
There are two ways to write code: either write naked instructions,
which the assembler is free to combine into VLIW bundles, or specify
the VLIW bundles explicitly.
 
Bundles are specified using curly braces:
 
@smallexample
@{ @var{add} r3,r4,r5 ; @var{add} r7,r8,r9 ; @var{lw} r10,r11 @}
@end smallexample
 
A bundle can span multiple lines. If you want to put multiple
instructions on a line, whether in a bundle or not, you need to
separate them with semicolons as in this example.
 
A bundle may contain one or more instructions, up to the limit
specified by the ISA (currently three). If fewer instructions are
specified than the hardware supports in a bundle, the assembler
inserts @code{fnop} instructions automatically.
 
The assembler will prefer to preserve the ordering of instructions
within the bundle, putting the first instruction in a lower-numbered
pipeline than the next one, etc. This fact, combined with the
optional use of explicit @code{fnop} or @code{nop} instructions,
allows precise control over which pipeline executes each instruction.
 
If the instructions cannot be bundled in the listed order, the
assembler will automatically try to find a valid pipeline
assignment. If there is no way to bundle the instructions together,
the assembler reports an error.
 
The assembler does not yet auto-bundle (automatically combine multiple
instructions into one bundle), but it reserves the right to do so in
the future. If you want to force an instruction to run by itself, put
it in a bundle explicitly with curly braces and use @code{nop}
instructions (not @code{fnop}) to fill the remaining pipeline slots in
that bundle.
 
@menu
* TILEPro Opcodes:: Opcode Naming Conventions.
* TILEPro Registers:: Register Naming.
* TILEPro Modifiers:: Symbolic Operand Modifiers.
@end menu
 
@node TILEPro Opcodes
@subsection Opcode Names
@cindex TILEPro opcode names
@cindex opcode names, TILEPro
 
For a complete list of opcodes and descriptions of their semantics,
see @cite{TILE Processor User Architecture Manual}, available upon
request at www.tilera.com.
 
@node TILEPro Registers
@subsection Register Names
@cindex TILEPro register names
@cindex register names, TILEPro
 
General-purpose registers are represented by predefined symbols of the
form @samp{r@var{N}}, where @var{N} represents a number between
@code{0} and @code{63}. However, the following registers have
canonical names that must be used instead:
 
@table @code
@item r54
sp
 
@item r55
lr
 
@item r56
sn
 
@item r57
idn0
 
@item r58
idn1
 
@item r59
udn0
 
@item r60
udn1
 
@item r61
udn2
 
@item r62
udn3
 
@item r63
zero
 
@end table
 
The assembler will emit a warning if a numeric name is used instead of
the canonical name. The @code{.no_require_canonical_reg_names}
assembler pseudo-op turns off this
warning. @code{.require_canonical_reg_names} turns it back on.
 
@node TILEPro Modifiers
@subsection Symbolic Operand Modifiers
@cindex TILEPro modifiers
@cindex symbol modifiers, TILEPro
 
The assembler supports several modifiers when using symbol addresses
in TILEPro instruction operands. The general syntax is the following:
 
@smallexample
modifier(symbol)
@end smallexample
 
The following modifiers are supported:
 
@table @code
 
@item lo16
 
This modifier is used to load the low 16 bits of the symbol's address,
sign-extended to a 32-bit value (sign-extension allows it to be
range-checked against signed 16 bit immediate operands without
complaint).
 
@item hi16
 
This modifier is used to load the high 16 bits of the symbol's
address, also sign-extended to a 32-bit value.
 
@item ha16
 
@code{ha16(N)} is identical to @code{hi16(N)}, except if
@code{lo16(N)} is negative it adds one to the @code{hi16(N)}
value. This way @code{lo16} and @code{ha16} can be added to create any
32-bit value using @code{auli}. For example, here is how you move an
arbitrary 32-bit address into r3:
 
@smallexample
moveli r3, lo16(sym)
auli r3, r3, ha16(sym)
@end smallexample
 
@item got
 
This modifier is used to load the offset of the GOT entry
corresponding to the symbol.
 
@item got_lo16
 
This modifier is used to load the sign-extended low 16 bits of the
offset of the GOT entry corresponding to the symbol.
 
@item got_hi16
 
This modifier is used to load the sign-extended high 16 bits of the
offset of the GOT entry corresponding to the symbol.
 
@item got_ha16
 
This modifier is like @code{got_hi16}, but it adds one if
@code{got_lo16} of the input value is negative.
 
@item plt
 
This modifier is used for function symbols. It causes a
@emph{procedure linkage table}, an array of code stubs, to be created
at the time the shared object is created or linked against, together
with a global offset table entry. The value is a pc-relative offset
to the corresponding stub code in the procedure linkage table. This
arrangement causes the run-time symbol resolver to be called to look
up and set the value of the symbol the first time the function is
called (at latest; depending environment variables). It is only safe
to leave the symbol unresolved this way if all references are function
calls.
 
@item tls_gd
 
This modifier is used to load the offset of the GOT entry of the
symbol's TLS descriptor, to be used for general-dynamic TLS accesses.
 
@item tls_gd_lo16
 
This modifier is used to load the sign-extended low 16 bits of the
offset of the GOT entry of the symbol's TLS descriptor, to be used for
general dynamic TLS accesses.
 
@item tls_gd_hi16
 
This modifier is used to load the sign-extended high 16 bits of the
offset of the GOT entry of the symbol's TLS descriptor, to be used for
general dynamic TLS accesses.
 
@item tls_gd_ha16
 
This modifier is like @code{tls_gd_hi16}, but it adds one to the value
if @code{tls_gd_lo16} of the input value is negative.
 
@item tls_ie
 
This modifier is used to load the offset of the GOT entry containing
the offset of the symbol's address from the TCB, to be used for
initial-exec TLS accesses.
 
@item tls_ie_lo16
 
This modifier is used to load the low 16 bits of the offset of the GOT
entry containing the offset of the symbol's address from the TCB, to
be used for initial-exec TLS accesses.
 
@item tls_ie_hi16
 
This modifier is used to load the high 16 bits of the offset of the
GOT entry containing the offset of the symbol's address from the TCB,
to be used for initial-exec TLS accesses.
 
@item tls_ie_ha16
 
This modifier is like @code{tls_ie_hi16}, but it adds one to the value
if @code{tls_ie_lo16} of the input value is negative.
 
@item tls_le
 
This modifier is used to load the offset of the symbol's address from
the TCB, to be used for local-exec TLS accesses.
 
@item tls_le_lo16
 
This modifier is used to load the low 16 bits of the offset of the
symbol's address from the TCB, to be used for local-exec TLS accesses.
 
@item tls_le_hi16
 
This modifier is used to load the high 16 bits of the offset of the
symbol's address from the TCB, to be used for local-exec TLS accesses.
 
@item tls_le_ha16
 
This modifier is like @code{tls_le_hi16}, but it adds one to the value
if @code{tls_le_lo16} of the input value is negative.
 
@item tls_gd_call
 
This modifier is used to tag an instrution as the ``call'' part of a
calling sequence for a TLS GD reference of its operand.
 
@item tls_gd_add
 
This modifier is used to tag an instruction as the ``add'' part of a
calling sequence for a TLS GD reference of its operand.
 
@item tls_ie_load
 
This modifier is used to tag an instruction as the ``load'' part of a
calling sequence for a TLS IE reference of its operand.
 
@end table
 
@node TILEPro Directives
@section TILEPro Directives
@cindex machine directives, TILEPro
@cindex TILEPro machine directives
 
@table @code
 
@cindex @code{.align} directive, TILEPro
@item .align @var{expression} [, @var{expression}]
This is the generic @var{.align} directive. The first argument is the
requested alignment in bytes.
 
@cindex @code{.allow_suspicious_bundles} directive, TILEPro
@item .allow_suspicious_bundles
Turns on error checking for combinations of instructions in a bundle
that probably indicate a programming error. This is on by default.
 
@item .no_allow_suspicious_bundles
Turns off error checking for combinations of instructions in a bundle
that probably indicate a programming error.
 
@cindex @code{.require_canonical_reg_names} directive, TILEPro
@item .require_canonical_reg_names
Require that canonical register names be used, and emit a warning if
the numeric names are used. This is on by default.
 
@item .no_require_canonical_reg_names
Permit the use of numeric names for registers that have canonical
names.
 
@end table
 
/binutils/gas/doc/c-v850.texi
0,0 → 1,434
@c Copyright 1997, 2002, 2003, 2006, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@node V850-Dependent
@chapter v850 Dependent Features
 
@cindex V850 support
@menu
* V850 Options:: Options
* V850 Syntax:: Syntax
* V850 Floating Point:: Floating Point
* V850 Directives:: V850 Machine Directives
* V850 Opcodes:: Opcodes
@end menu
 
@node V850 Options
@section Options
@cindex V850 options (none)
@cindex options for V850 (none)
@code{@value{AS}} supports the following additional command-line options
for the V850 processor family:
 
@cindex command line options, V850
@cindex V850 command line options
@table @code
 
@cindex @code{-wsigned_overflow} command line option, V850
@item -wsigned_overflow
Causes warnings to be produced when signed immediate values overflow the
space available for then within their opcodes. By default this option
is disabled as it is possible to receive spurious warnings due to using
exact bit patterns as immediate constants.
 
@cindex @code{-wunsigned_overflow} command line option, V850
@item -wunsigned_overflow
Causes warnings to be produced when unsigned immediate values overflow
the space available for then within their opcodes. By default this
option is disabled as it is possible to receive spurious warnings due to
using exact bit patterns as immediate constants.
 
@cindex @code{-mv850} command line option, V850
@item -mv850
Specifies that the assembled code should be marked as being targeted at
the V850 processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@cindex @code{-mv850e} command line option, V850
@item -mv850e
Specifies that the assembled code should be marked as being targeted at
the V850E processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@cindex @code{-mv850e1} command line option, V850
@item -mv850e1
Specifies that the assembled code should be marked as being targeted at
the V850E1 processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@cindex @code{-mv850any} command line option, V850
@item -mv850any
Specifies that the assembled code should be marked as being targeted at
the V850 processor but support instructions that are specific to the
extended variants of the process. This allows the production of
binaries that contain target specific code, but which are also intended
to be used in a generic fashion. For example libgcc.a contains generic
routines used by the code produced by GCC for all versions of the v850
architecture, together with support routines only used by the V850E
architecture.
 
@cindex @code{-mv850e2} command line option, V850
@item -mv850e2
Specifies that the assembled code should be marked as being targeted at
the V850E2 processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@cindex @code{-mv850e2v3} command line option, V850
@item -mv850e2v3
Specifies that the assembled code should be marked as being targeted at
the V850E2V3 processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@cindex @code{-mrelax} command line option, V850
@item -mrelax
Enables relaxation. This allows the .longcall and .longjump pseudo
ops to be used in the assembler source code. These ops label sections
of code which are either a long function call or a long branch. The
assembler will then flag these sections of code and the linker will
attempt to relax them.
 
@end table
 
 
@node V850 Syntax
@section Syntax
@menu
* V850-Chars:: Special Characters
* V850-Regs:: Register Names
@end menu
 
@node V850-Chars
@subsection Special Characters
 
@cindex line comment character, V850
@cindex V850 line comment character
@samp{#} is the line comment character. If a @samp{#} appears as the
first character of a line, the whole line is treated as a comment, but
in this case the line can also be a logical line number directive
(@pxref{Comments}) or a preprocessor control command
(@pxref{Preprocessing}).
 
Two dashes (@samp{--}) can also be used to start a line comment.
 
@cindex line separator, V850
@cindex statement separator, V850
@cindex V850 line separator
 
The @samp{;} character can be used to separate statements on the same
line.
 
@node V850-Regs
@subsection Register Names
 
@cindex V850 register names
@cindex register names, V850
@code{@value{AS}} supports the following names for registers:
@table @code
@cindex @code{zero} register, V850
@item general register 0
r0, zero
@item general register 1
r1
@item general register 2
r2, hp
@cindex @code{sp} register, V850
@item general register 3
r3, sp
@cindex @code{gp} register, V850
@item general register 4
r4, gp
@cindex @code{tp} register, V850
@item general register 5
r5, tp
@item general register 6
r6
@item general register 7
r7
@item general register 8
r8
@item general register 9
r9
@item general register 10
r10
@item general register 11
r11
@item general register 12
r12
@item general register 13
r13
@item general register 14
r14
@item general register 15
r15
@item general register 16
r16
@item general register 17
r17
@item general register 18
r18
@item general register 19
r19
@item general register 20
r20
@item general register 21
r21
@item general register 22
r22
@item general register 23
r23
@item general register 24
r24
@item general register 25
r25
@item general register 26
r26
@item general register 27
r27
@item general register 28
r28
@item general register 29
r29
@cindex @code{ep} register, V850
@item general register 30
r30, ep
@cindex @code{lp} register, V850
@item general register 31
r31, lp
@cindex @code{eipc} register, V850
@item system register 0
eipc
@cindex @code{eipsw} register, V850
@item system register 1
eipsw
@cindex @code{fepc} register, V850
@item system register 2
fepc
@cindex @code{fepsw} register, V850
@item system register 3
fepsw
@cindex @code{ecr} register, V850
@item system register 4
ecr
@cindex @code{psw} register, V850
@item system register 5
psw
@cindex @code{ctpc} register, V850
@item system register 16
ctpc
@cindex @code{ctpsw} register, V850
@item system register 17
ctpsw
@cindex @code{dbpc} register, V850
@item system register 18
dbpc
@cindex @code{dbpsw} register, V850
@item system register 19
dbpsw
@cindex @code{ctbp} register, V850
@item system register 20
ctbp
@end table
 
@node V850 Floating Point
@section Floating Point
 
@cindex floating point, V850 (@sc{ieee})
@cindex V850 floating point (@sc{ieee})
The V850 family uses @sc{ieee} floating-point numbers.
 
@node V850 Directives
@section V850 Machine Directives
 
@cindex machine directives, V850
@cindex V850 machine directives
@table @code
@cindex @code{offset} directive, V850
@item .offset @var{<expression>}
Moves the offset into the current section to the specified amount.
 
@cindex @code{section} directive, V850
@item .section "name", <type>
This is an extension to the standard .section directive. It sets the
current section to be <type> and creates an alias for this section
called "name".
 
@cindex @code{.v850} directive, V850
@item .v850
Specifies that the assembled code should be marked as being targeted at
the V850 processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@cindex @code{.v850e} directive, V850
@item .v850e
Specifies that the assembled code should be marked as being targeted at
the V850E processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@cindex @code{.v850e1} directive, V850
@item .v850e1
Specifies that the assembled code should be marked as being targeted at
the V850E1 processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@cindex @code{.v850e2} directive, V850
@item .v850e2
Specifies that the assembled code should be marked as being targeted at
the V850E2 processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@cindex @code{.v850e2v3} directive, V850
@item .v850e2v3
Specifies that the assembled code should be marked as being targeted at
the V850E2V3 processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
 
@end table
 
@node V850 Opcodes
@section Opcodes
 
@cindex V850 opcodes
@cindex opcodes for V850
@code{@value{AS}} implements all the standard V850 opcodes.
 
@code{@value{AS}} also implements the following pseudo ops:
 
@table @code
 
@cindex @code{hi0} pseudo-op, V850
@item hi0()
Computes the higher 16 bits of the given expression and stores it into
the immediate operand field of the given instruction. For example:
 
@samp{mulhi hi0(here - there), r5, r6}
 
computes the difference between the address of labels 'here' and
'there', takes the upper 16 bits of this difference, shifts it down 16
bits and then multiplies it by the lower 16 bits in register 5, putting
the result into register 6.
 
@cindex @code{lo} pseudo-op, V850
@item lo()
Computes the lower 16 bits of the given expression and stores it into
the immediate operand field of the given instruction. For example:
 
@samp{addi lo(here - there), r5, r6}
 
computes the difference between the address of labels 'here' and
'there', takes the lower 16 bits of this difference and adds it to
register 5, putting the result into register 6.
 
@cindex @code{hi} pseudo-op, V850
@item hi()
Computes the higher 16 bits of the given expression and then adds the
value of the most significant bit of the lower 16 bits of the expression
and stores the result into the immediate operand field of the given
instruction. For example the following code can be used to compute the
address of the label 'here' and store it into register 6:
 
@samp{movhi hi(here), r0, r6}
@samp{movea lo(here), r6, r6}
 
The reason for this special behaviour is that movea performs a sign
extension on its immediate operand. So for example if the address of
'here' was 0xFFFFFFFF then without the special behaviour of the hi()
pseudo-op the movhi instruction would put 0xFFFF0000 into r6, then the
movea instruction would takes its immediate operand, 0xFFFF, sign extend
it to 32 bits, 0xFFFFFFFF, and then add it into r6 giving 0xFFFEFFFF
which is wrong (the fifth nibble is E). With the hi() pseudo op adding
in the top bit of the lo() pseudo op, the movhi instruction actually
stores 0 into r6 (0xFFFF + 1 = 0x0000), so that the movea instruction
stores 0xFFFFFFFF into r6 - the right value.
 
@cindex @code{hilo} pseudo-op, V850
@item hilo()
Computes the 32 bit value of the given expression and stores it into
the immediate operand field of the given instruction (which must be a
mov instruction). For example:
 
@samp{mov hilo(here), r6}
 
computes the absolute address of label 'here' and puts the result into
register 6.
 
@cindex @code{sdaoff} pseudo-op, V850
@item sdaoff()
Computes the offset of the named variable from the start of the Small
Data Area (whoes address is held in register 4, the GP register) and
stores the result as a 16 bit signed value in the immediate operand
field of the given instruction. For example:
 
@samp{ld.w sdaoff(_a_variable)[gp],r6}
 
loads the contents of the location pointed to by the label '_a_variable'
into register 6, provided that the label is located somewhere within +/-
32K of the address held in the GP register. [Note the linker assumes
that the GP register contains a fixed address set to the address of the
label called '__gp'. This can either be set up automatically by the
linker, or specifically set by using the @samp{--defsym __gp=<value>}
command line option].
 
@cindex @code{tdaoff} pseudo-op, V850
@item tdaoff()
Computes the offset of the named variable from the start of the Tiny
Data Area (whoes address is held in register 30, the EP register) and
stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
operand field of the given instruction. For example:
 
@samp{sld.w tdaoff(_a_variable)[ep],r6}
 
loads the contents of the location pointed to by the label '_a_variable'
into register 6, provided that the label is located somewhere within +256
bytes of the address held in the EP register. [Note the linker assumes
that the EP register contains a fixed address set to the address of the
label called '__ep'. This can either be set up automatically by the
linker, or specifically set by using the @samp{--defsym __ep=<value>}
command line option].
 
@cindex @code{zdaoff} pseudo-op, V850
@item zdaoff()
Computes the offset of the named variable from address 0 and stores the
result as a 16 bit signed value in the immediate operand field of the
given instruction. For example:
 
@samp{movea zdaoff(_a_variable),zero,r6}
 
puts the address of the label '_a_variable' into register 6, assuming
that the label is somewhere within the first 32K of memory. (Strictly
speaking it also possible to access the last 32K of memory as well, as
the offsets are signed).
 
@cindex @code{ctoff} pseudo-op, V850
@item ctoff()
Computes the offset of the named variable from the start of the Call
Table Area (whoes address is helg in system register 20, the CTBP
register) and stores the result a 6 or 16 bit unsigned value in the
immediate field of then given instruction or piece of data. For
example:
 
@samp{callt ctoff(table_func1)}
 
will put the call the function whoes address is held in the call table
at the location labeled 'table_func1'.
 
@cindex @code{longcall} pseudo-op, V850
@item .longcall @code{name}
Indicates that the following sequence of instructions is a long call
to function @code{name}. The linker will attempt to shorten this call
sequence if @code{name} is within a 22bit offset of the call. Only
valid if the @code{-mrelax} command line switch has been enabled.
 
@cindex @code{longjump} pseudo-op, V850
@item .longjump @code{name}
Indicates that the following sequence of instructions is a long jump
to label @code{name}. The linker will attempt to shorten this code
sequence if @code{name} is within a 22bit offset of the jump. Only
valid if the @code{-mrelax} command line switch has been enabled.
 
@end table
 
 
For information on the V850 instruction set, see @cite{V850
Family 32-/16-Bit single-Chip Microcontroller Architecture Manual} from NEC.
Ltd.
/binutils/gas/doc/c-vax.texi
0,0 → 1,384
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2002, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c VAX/VMS description enhanced and corrected by Klaus K"aempf, kkaempf@progis.de
@ifset GENERIC
@node Vax-Dependent
@chapter VAX Dependent Features
@cindex VAX support
 
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter VAX Dependent Features
@cindex VAX support
 
@end ifclear
 
@menu
* VAX-Opts:: VAX Command-Line Options
* VAX-float:: VAX Floating Point
* VAX-directives:: Vax Machine Directives
* VAX-opcodes:: VAX Opcodes
* VAX-branch:: VAX Branch Improvement
* VAX-operands:: VAX Operands
* VAX-no:: Not Supported on VAX
* VAX-Syntax:: VAX Syntax
@end menu
 
 
@node VAX-Opts
@section VAX Command-Line Options
 
@cindex command-line options ignored, VAX
@cindex VAX command-line options ignored
The Vax version of @code{@value{AS}} accepts any of the following options,
gives a warning message that the option was ignored and proceeds.
These options are for compatibility with scripts designed for other
people's assemblers.
 
@table @code
@cindex @code{-D}, ignored on VAX
@cindex @code{-S}, ignored on VAX
@cindex @code{-T}, ignored on VAX
@item @code{-D} (Debug)
@itemx @code{-S} (Symbol Table)
@itemx @code{-T} (Token Trace)
These are obsolete options used to debug old assemblers.
 
@cindex @code{-d}, VAX option
@item @code{-d} (Displacement size for JUMPs)
This option expects a number following the @samp{-d}. Like options
that expect filenames, the number may immediately follow the
@samp{-d} (old standard) or constitute the whole of the command line
argument that follows @samp{-d} (@sc{gnu} standard).
 
@cindex @code{-V}, redundant on VAX
@item @code{-V} (Virtualize Interpass Temporary File)
Some other assemblers use a temporary file. This option
commanded them to keep the information in active memory rather
than in a disk file. @code{@value{AS}} always does this, so this
option is redundant.
 
@cindex @code{-J}, ignored on VAX
@item @code{-J} (JUMPify Longer Branches)
Many 32-bit computers permit a variety of branch instructions
to do the same job. Some of these instructions are short (and
fast) but have a limited range; others are long (and slow) but
can branch anywhere in virtual memory. Often there are 3
flavors of branch: short, medium and long. Some other
assemblers would emit short and medium branches, unless told by
this option to emit short and long branches.
 
@cindex @code{-t}, ignored on VAX
@item @code{-t} (Temporary File Directory)
Some other assemblers may use a temporary file, and this option
takes a filename being the directory to site the temporary
file. Since @code{@value{AS}} does not use a temporary disk file, this
option makes no difference. @samp{-t} needs exactly one
filename.
@end table
 
@cindex VMS (VAX) options
@cindex options for VAX/VMS
@cindex VAX/VMS options
@cindex Vax-11 C compatibility
@cindex symbols with uppercase, VAX/VMS
The Vax version of the assembler accepts additional options when
compiled for VMS:
 
@table @samp
@cindex @samp{-h} option, VAX/VMS
@item -h @var{n}
External symbol or section (used for global variables) names are not
case sensitive on VAX/VMS and always mapped to upper case. This is
contrary to the C language definition which explicitly distinguishes
upper and lower case. To implement a standard conforming C compiler,
names must be changed (mapped) to preserve the case information. The
default mapping is to convert all lower case characters to uppercase and
adding an underscore followed by a 6 digit hex value, representing a 24
digit binary value. The one digits in the binary value represent which
characters are uppercase in the original symbol name.
 
The @samp{-h @var{n}} option determines how we map names. This takes
several values. No @samp{-h} switch at all allows case hacking as
described above. A value of zero (@samp{-h0}) implies names should be
upper case, and inhibits the case hack. A value of 2 (@samp{-h2})
implies names should be all lower case, with no case hack. A value of 3
(@samp{-h3}) implies that case should be preserved. The value 1 is
unused. The @code{-H} option directs @code{@value{AS}} to display
every mapped symbol during assembly.
 
Symbols whose names include a dollar sign @samp{$} are exceptions to the
general name mapping. These symbols are normally only used to reference
VMS library names. Such symbols are always mapped to upper case.
 
@cindex @samp{-+} option, VAX/VMS
@item -+
The @samp{-+} option causes @code{@value{AS}} to truncate any symbol
name larger than 31 characters. The @samp{-+} option also prevents some
code following the @samp{_main} symbol normally added to make the object
file compatible with Vax-11 "C".
 
@cindex @samp{-1} option, VAX/VMS
@item -1
This option is ignored for backward compatibility with @code{@value{AS}}
version 1.x.
 
@cindex @samp{-H} option, VAX/VMS
@item -H
The @samp{-H} option causes @code{@value{AS}} to print every symbol
which was changed by case mapping.
@end table
 
@node VAX-float
@section VAX Floating Point
 
@cindex VAX floating point
@cindex floating point, VAX
Conversion of flonums to floating point is correct, and
compatible with previous assemblers. Rounding is
towards zero if the remainder is exactly half the least significant bit.
 
@code{D}, @code{F}, @code{G} and @code{H} floating point formats
are understood.
 
Immediate floating literals (@emph{e.g.} @samp{S`$6.9})
are rendered correctly. Again, rounding is towards zero in the
boundary case.
 
@cindex @code{float} directive, VAX
@cindex @code{double} directive, VAX
The @code{.float} directive produces @code{f} format numbers.
The @code{.double} directive produces @code{d} format numbers.
 
@node VAX-directives
@section Vax Machine Directives
 
@cindex machine directives, VAX
@cindex VAX machine directives
The Vax version of the assembler supports four directives for
generating Vax floating point constants. They are described in the
table below.
 
@cindex wide floating point directives, VAX
@table @code
@cindex @code{dfloat} directive, VAX
@item .dfloat
This expects zero or more flonums, separated by commas, and
assembles Vax @code{d} format 64-bit floating point constants.
 
@cindex @code{ffloat} directive, VAX
@item .ffloat
This expects zero or more flonums, separated by commas, and
assembles Vax @code{f} format 32-bit floating point constants.
 
@cindex @code{gfloat} directive, VAX
@item .gfloat
This expects zero or more flonums, separated by commas, and
assembles Vax @code{g} format 64-bit floating point constants.
 
@cindex @code{hfloat} directive, VAX
@item .hfloat
This expects zero or more flonums, separated by commas, and
assembles Vax @code{h} format 128-bit floating point constants.
 
@end table
 
@node VAX-opcodes
@section VAX Opcodes
 
@cindex VAX opcode mnemonics
@cindex opcode mnemonics, VAX
@cindex mnemonics for opcodes, VAX
All DEC mnemonics are supported. Beware that @code{case@dots{}}
instructions have exactly 3 operands. The dispatch table that
follows the @code{case@dots{}} instruction should be made with
@code{.word} statements. This is compatible with all unix
assemblers we know of.
 
@node VAX-branch
@section VAX Branch Improvement
 
@cindex VAX branch improvement
@cindex branch improvement, VAX
@cindex pseudo-ops for branch, VAX
Certain pseudo opcodes are permitted. They are for branch
instructions. They expand to the shortest branch instruction that
reaches the target. Generally these mnemonics are made by
substituting @samp{j} for @samp{b} at the start of a DEC mnemonic.
This feature is included both for compatibility and to help
compilers. If you do not need this feature, avoid these
opcodes. Here are the mnemonics, and the code they can expand into.
 
@table @code
@item jbsb
@samp{Jsb} is already an instruction mnemonic, so we chose @samp{jbsb}.
@table @asis
@item (byte displacement)
@kbd{bsbb @dots{}}
@item (word displacement)
@kbd{bsbw @dots{}}
@item (long displacement)
@kbd{jsb @dots{}}
@end table
@item jbr
@itemx jr
Unconditional branch.
@table @asis
@item (byte displacement)
@kbd{brb @dots{}}
@item (word displacement)
@kbd{brw @dots{}}
@item (long displacement)
@kbd{jmp @dots{}}
@end table
@item j@var{COND}
@var{COND} may be any one of the conditional branches
@code{neq}, @code{nequ}, @code{eql}, @code{eqlu}, @code{gtr},
@code{geq}, @code{lss}, @code{gtru}, @code{lequ}, @code{vc}, @code{vs},
@code{gequ}, @code{cc}, @code{lssu}, @code{cs}.
@var{COND} may also be one of the bit tests
@code{bs}, @code{bc}, @code{bss}, @code{bcs}, @code{bsc}, @code{bcc},
@code{bssi}, @code{bcci}, @code{lbs}, @code{lbc}.
@var{NOTCOND} is the opposite condition to @var{COND}.
@table @asis
@item (byte displacement)
@kbd{b@var{COND} @dots{}}
@item (word displacement)
@kbd{b@var{NOTCOND} foo ; brw @dots{} ; foo:}
@item (long displacement)
@kbd{b@var{NOTCOND} foo ; jmp @dots{} ; foo:}
@end table
@item jacb@var{X}
@var{X} may be one of @code{b d f g h l w}.
@table @asis
@item (word displacement)
@kbd{@var{OPCODE} @dots{}}
@item (long displacement)
@example
@var{OPCODE} @dots{}, foo ;
brb bar ;
foo: jmp @dots{} ;
bar:
@end example
@end table
@item jaob@var{YYY}
@var{YYY} may be one of @code{lss leq}.
@item jsob@var{ZZZ}
@var{ZZZ} may be one of @code{geq gtr}.
@table @asis
@item (byte displacement)
@kbd{@var{OPCODE} @dots{}}
@item (word displacement)
@example
@var{OPCODE} @dots{}, foo ;
brb bar ;
foo: brw @var{destination} ;
bar:
@end example
@item (long displacement)
@example
@var{OPCODE} @dots{}, foo ;
brb bar ;
foo: jmp @var{destination} ;
bar:
@end example
@end table
@item aobleq
@itemx aoblss
@itemx sobgeq
@itemx sobgtr
@table @asis
@item (byte displacement)
@kbd{@var{OPCODE} @dots{}}
@item (word displacement)
@example
@var{OPCODE} @dots{}, foo ;
brb bar ;
foo: brw @var{destination} ;
bar:
@end example
@item (long displacement)
@example
@var{OPCODE} @dots{}, foo ;
brb bar ;
foo: jmp @var{destination} ;
bar:
@end example
@end table
@end table
 
@node VAX-operands
@section VAX Operands
 
@cindex VAX operand notation
@cindex operand notation, VAX
@cindex immediate character, VAX
@cindex VAX immediate character
The immediate character is @samp{$} for Unix compatibility, not
@samp{#} as DEC writes it.
 
@cindex indirect character, VAX
@cindex VAX indirect character
The indirect character is @samp{*} for Unix compatibility, not
@samp{@@} as DEC writes it.
 
@cindex displacement sizing character, VAX
@cindex VAX displacement sizing character
The displacement sizing character is @samp{`} (an accent grave) for
Unix compatibility, not @samp{^} as DEC writes it. The letter
preceding @samp{`} may have either case. @samp{G} is not
understood, but all other letters (@code{b i l s w}) are understood.
 
@cindex register names, VAX
@cindex VAX register names
Register names understood are @code{r0 r1 r2 @dots{} r15 ap fp sp
pc}. Upper and lower case letters are equivalent.
 
For instance
@smallexample
tstb *w`$4(r5)
@end smallexample
 
Any expression is permitted in an operand. Operands are comma
separated.
 
@c There is some bug to do with recognizing expressions
@c in operands, but I forget what it is. It is
@c a syntax clash because () is used as an address mode
@c and to encapsulate sub-expressions.
 
@node VAX-no
@section Not Supported on VAX
 
@cindex VAX bitfields not supported
@cindex bitfields, not supported on VAX
Vax bit fields can not be assembled with @code{@value{AS}}. Someone
can add the required code if they really need it.
 
@node VAX-Syntax
@section VAX Syntax
@menu
* VAX-Chars:: Special Characters
@end menu
 
@node VAX-Chars
@subsection Special Characters
 
@cindex line comment character, VAX
@cindex VAX line comment character
The presence of a @samp{#} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, VAX
@cindex statement separator, VAX
@cindex VAX line separator
The @samp{;} character can be used to separate statements on the same
line.
/binutils/gas/doc/c-xc16x.texi
0,0 → 1,80
@c Copyright 2006, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@page
@node xc16x-Dependent
@chapter Infineon xc16x Dependent Features
 
@cindex xc16x support
@menu
* xc16x Directives:: xc16x Machine Directives
* xc16x Syntax:: xc16x Syntax
@end menu
 
@node xc16x Directives
@section xc16x Machine Directives
 
The xc16x version of the assembler supports the following machine
directives:
 
@table @code
@cindex @code{align} directive, xc16x
@item .align
This directive aligns the section program counter on the next 2-byte
boundary.
 
 
@cindex @code{byte} directive, xc16x
@item .byte @var{expr}
This directive assembles a half-word (8-bit) constant.
 
@cindex @code{word} directive, xc16x
@item .word @var{expr}
This assembles a word (16-bit) constant.
 
@cindex @code{ascii} directive, xc16x
@item .ascii "@var{ascii}"
This directive used for copying @var{str} into the object file.
The string is terminated with a null byte.
 
@cindex @code{set} directive, xc16x
@item .set @var{symbol}, @var{value}
This directive creates a symbol named @var{symbol} which is an alias for
another symbol (possibly not yet defined). This should not be confused
with the mnemonic @code{set}, which is a legitimate xc16x instruction.
 
 
 
@cindex @code{bss} directive, xc16x
@item .bss @var{symbol}, @var{length}
Reserve @var{length} bytes in the bss section for a local @var{symbol},
aligned to the power of two specified by @var{align}. @var{length} and
@var{align} must be positive absolute expressions. This directive
differs from @samp{.lcomm} only in that it permits you to specify
an alignment.
@end table
 
@node xc16x Syntax
@section xc16x Syntax
@menu
* xc16x-Chars:: Special Characters
@end menu
 
@node xc16x-Chars
@subsection Special Characters
 
@cindex line comment character, xc16x
@cindex xc16c line comment character
The presence of a @samp{;} appearing anywhere on a line indicates the
start of a comment that extends to the end of that line.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line can also be a
logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, xc16x
@cindex statement separator, xc16x
@cindex xc16x line separator
The XC16X assembler does not support a line separator character.
/binutils/gas/doc/c-xstormy16.texi
0,0 → 1,104
@c Copyright 2010, 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@node XSTORMY16-Dependent
@chapter XStormy16 Dependent Features
 
@cindex XStormy16 support
@menu
* XStormy16 Syntax:: Syntax
* XStormy16 Directives:: Machine Directives
* XStormy16 Opcodes:: Pseudo-Opcodes
@end menu
 
@node XStormy16 Syntax
@section Syntax
@menu
* XStormy16-Chars:: Special Characters
@end menu
 
@node XStormy16-Chars
@subsection Special Characters
 
@cindex line comment character, XStormy16
@cindex XStormy16 line comment character
@samp{#} is the line comment character. If a @samp{#} appears as the
first character of a line, the whole line is treated as a comment, but
in this case the line can also be a logical line number directive
(@pxref{Comments}) or a preprocessor control command
(@pxref{Preprocessing}).
 
@cindex comment character, XStormy16
@cindex XStormy16 comment character
A semicolon (@samp{;}) can be used to start a comment that extends
from wherever the character appears on the line up to the end of the
line.
 
@cindex line separator, XStormy16
@cindex statement separator, XStormy16
@cindex XStormy16 line separator
 
The @samp{|} character can be used to separate statements on the same
line.
 
 
@node XStormy16 Directives
@section XStormy16 Machine Directives
 
@cindex machine directives, XStormy16
@cindex XStormy16 machine directives
@table @code
 
@cindex @code{16bit_pointers} directive, XStormy16
@item .16bit_pointers
Like the @option{--16bit-pointers} command line option this directive
indicates that the assembly code makes use of 16-bit pointers.
 
@cindex @code{32bit_pointers} directive, XStormy16
@item .32bit_pointers
Like the @option{--32bit-pointers} command line option this directive
indicates that the assembly code makes use of 32-bit pointers.
 
@cindex @code{.no_pointers} directive, XStormy16
@item .no_pointers
Like the @option{--no-pointers} command line option this directive
indicates that the assembly code does not makes use pointers.
 
@end table
 
@node XStormy16 Opcodes
@section XStormy16 Pseudo-Opcodes
 
@cindex XStormy16 pseudo-opcodes
@cindex pseudo-opcodes for XStormy16
@code{@value{AS}} implements all the standard XStormy16 opcodes.
 
@code{@value{AS}} also implements the following pseudo ops:
 
@table @code
 
@cindex @code{@@lo} pseudo-op, XStormy16
@item @@lo()
Computes the lower 16 bits of the given expression and stores it into
the immediate operand field of the given instruction. For example:
 
@samp{add r6, @@lo(here - there)}
 
computes the difference between the address of labels 'here' and
'there', takes the lower 16 bits of this difference and adds it to
register 6.
 
@cindex @code{@@hi} pseudo-op, XStormy16
@item @@hi()
Computes the higher 16 bits of the given expression and stores it into
the immediate operand field of the given instruction. For example:
 
@samp{addc r7, @@hi(here - there)}
 
computes the difference between the address of labels 'here' and
'there', takes the upper 16 bits of this difference, shifts it down 16
bits and then adds it, along with the carry bit, to the value in
register 7.
 
@end table
/binutils/gas/doc/c-xtensa.texi
0,0 → 1,820
@c Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@c
@c man end
@ifset GENERIC
@page
@node Xtensa-Dependent
@chapter Xtensa Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter Xtensa Dependent Features
@end ifclear
 
@cindex Xtensa architecture
This chapter covers features of the @sc{gnu} assembler that are specific
to the Xtensa architecture. For details about the Xtensa instruction
set, please consult the @cite{Xtensa Instruction Set Architecture (ISA)
Reference Manual}.
 
@menu
* Xtensa Options:: Command-line Options.
* Xtensa Syntax:: Assembler Syntax for Xtensa Processors.
* Xtensa Optimizations:: Assembler Optimizations.
* Xtensa Relaxation:: Other Automatic Transformations.
* Xtensa Directives:: Directives for Xtensa Processors.
@end menu
 
@node Xtensa Options
@section Command Line Options
 
@c man begin OPTIONS
@table @gcctabopt
 
@item --text-section-literals | --no-text-section-literals
@kindex --text-section-literals
@kindex --no-text-section-literals
Control the treatment of literal pools. The default is
@samp{--no-@-text-@-section-@-literals}, which places literals in
separate sections in the output file. This allows the literal pool to be
placed in a data RAM/ROM. With @samp{--text-@-section-@-literals}, the
literals are interspersed in the text section in order to keep them as
close as possible to their references. This may be necessary for large
assembly files, where the literals would otherwise be out of range of the
@code{L32R} instructions in the text section. These options only affect
literals referenced via PC-relative @code{L32R} instructions; literals
for absolute mode @code{L32R} instructions are handled separately.
@xref{Literal Directive, ,literal}.
 
@item --absolute-literals | --no-absolute-literals
@kindex --absolute-literals
@kindex --no-absolute-literals
Indicate to the assembler whether @code{L32R} instructions use absolute
or PC-relative addressing. If the processor includes the absolute
addressing option, the default is to use absolute @code{L32R}
relocations. Otherwise, only the PC-relative @code{L32R} relocations
can be used.
 
@item --target-align | --no-target-align
@kindex --target-align
@kindex --no-target-align
Enable or disable automatic alignment to reduce branch penalties at some
expense in code size. @xref{Xtensa Automatic Alignment, ,Automatic
Instruction Alignment}. This optimization is enabled by default. Note
that the assembler will always align instructions like @code{LOOP} that
have fixed alignment requirements.
 
@item --longcalls | --no-longcalls
@kindex --longcalls
@kindex --no-longcalls
Enable or disable transformation of call instructions to allow calls
across a greater range of addresses. @xref{Xtensa Call Relaxation,
,Function Call Relaxation}. This option should be used when call
targets can potentially be out of range. It may degrade both code size
and performance, but the linker can generally optimize away the
unnecessary overhead when a call ends up within range. The default is
@samp{--no-@-longcalls}.
 
@item --transform | --no-transform
@kindex --transform
@kindex --no-transform
Enable or disable all assembler transformations of Xtensa instructions,
including both relaxation and optimization. The default is
@samp{--transform}; @samp{--no-transform} should only be used in the
rare cases when the instructions must be exactly as specified in the
assembly source. Using @samp{--no-transform} causes out of range
instruction operands to be errors.
 
@item --rename-section @var{oldname}=@var{newname}
@kindex --rename-section
Rename the @var{oldname} section to @var{newname}. This option can be used
multiple times to rename multiple sections.
@end table
 
@c man end
 
@node Xtensa Syntax
@section Assembler Syntax
@cindex syntax, Xtensa assembler
@cindex Xtensa assembler syntax
@cindex FLIX syntax
 
Block comments are delimited by @samp{/*} and @samp{*/}. End of line
comments may be introduced with either @samp{#} or @samp{//}.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
Instructions consist of a leading opcode or macro name followed by
whitespace and an optional comma-separated list of operands:
 
@smallexample
@var{opcode} [@var{operand}, @dots{}]
@end smallexample
 
Instructions must be separated by a newline or semicolon (@samp{;}).
 
FLIX instructions, which bundle multiple opcodes together in a single
instruction, are specified by enclosing the bundled opcodes inside
braces:
 
@smallexample
@group
@{
[@var{format}]
@var{opcode0} [@var{operands}]
@end group
@var{opcode1} [@var{operands}]
@group
@var{opcode2} [@var{operands}]
@dots{}
@}
@end group
@end smallexample
 
The opcodes in a FLIX instruction are listed in the same order as the
corresponding instruction slots in the TIE format declaration.
Directives and labels are not allowed inside the braces of a FLIX
instruction. A particular TIE format name can optionally be specified
immediately after the opening brace, but this is usually unnecessary.
The assembler will automatically search for a format that can encode the
specified opcodes, so the format name need only be specified in rare
cases where there is more than one applicable format and where it
matters which of those formats is used. A FLIX instruction can also be
specified on a single line by separating the opcodes with semicolons:
 
@smallexample
@{ [@var{format};] @var{opcode0} [@var{operands}]; @var{opcode1} [@var{operands}]; @var{opcode2} [@var{operands}]; @dots{} @}
@end smallexample
 
If an opcode can only be encoded in a FLIX instruction but is not
specified as part of a FLIX bundle, the assembler will choose the
smallest format where the opcode can be encoded and
will fill unused instruction slots with no-ops.
 
@menu
* Xtensa Opcodes:: Opcode Naming Conventions.
* Xtensa Registers:: Register Naming.
@end menu
 
@node Xtensa Opcodes
@subsection Opcode Names
@cindex Xtensa opcode names
@cindex opcode names, Xtensa
 
See the @cite{Xtensa Instruction Set Architecture (ISA) Reference
Manual} for a complete list of opcodes and descriptions of their
semantics.
 
@cindex _ opcode prefix
If an opcode name is prefixed with an underscore character (@samp{_}),
@command{@value{AS}} will not transform that instruction in any way. The
underscore prefix disables both optimization (@pxref{Xtensa
Optimizations, ,Xtensa Optimizations}) and relaxation (@pxref{Xtensa
Relaxation, ,Xtensa Relaxation}) for that particular instruction. Only
use the underscore prefix when it is essential to select the exact
opcode produced by the assembler. Using this feature unnecessarily
makes the code less efficient by disabling assembler optimization and
less flexible by disabling relaxation.
 
Note that this special handling of underscore prefixes only applies to
Xtensa opcodes, not to either built-in macros or user-defined macros.
When an underscore prefix is used with a macro (e.g., @code{_MOV}), it
refers to a different macro. The assembler generally provides built-in
macros both with and without the underscore prefix, where the underscore
versions behave as if the underscore carries through to the instructions
in the macros. For example, @code{_MOV} may expand to @code{_MOV.N}@.
 
The underscore prefix only applies to individual instructions, not to
series of instructions. For example, if a series of instructions have
underscore prefixes, the assembler will not transform the individual
instructions, but it may insert other instructions between them (e.g.,
to align a @code{LOOP} instruction). To prevent the assembler from
modifying a series of instructions as a whole, use the
@code{no-transform} directive. @xref{Transform Directive, ,transform}.
 
@node Xtensa Registers
@subsection Register Names
@cindex Xtensa register names
@cindex register names, Xtensa
@cindex sp register
 
The assembly syntax for a register file entry is the ``short'' name for
a TIE register file followed by the index into that register file. For
example, the general-purpose @code{AR} register file has a short name of
@code{a}, so these registers are named @code{a0}@dots{}@code{a15}.
As a special feature, @code{sp} is also supported as a synonym for
@code{a1}. Additional registers may be added by processor configuration
options and by designer-defined TIE extensions. An initial @samp{$}
character is optional in all register names.
 
@node Xtensa Optimizations
@section Xtensa Optimizations
@cindex optimizations
 
The optimizations currently supported by @command{@value{AS}} are
generation of density instructions where appropriate and automatic
branch target alignment.
 
@menu
* Density Instructions:: Using Density Instructions.
* Xtensa Automatic Alignment:: Automatic Instruction Alignment.
@end menu
 
@node Density Instructions
@subsection Using Density Instructions
@cindex density instructions
 
The Xtensa instruction set has a code density option that provides
16-bit versions of some of the most commonly used opcodes. Use of these
opcodes can significantly reduce code size. When possible, the
assembler automatically translates instructions from the core
Xtensa instruction set into equivalent instructions from the Xtensa code
density option. This translation can be disabled by using underscore
prefixes (@pxref{Xtensa Opcodes, ,Opcode Names}), by using the
@samp{--no-transform} command-line option (@pxref{Xtensa Options, ,Command
Line Options}), or by using the @code{no-transform} directive
(@pxref{Transform Directive, ,transform}).
 
It is a good idea @emph{not} to use the density instructions directly.
The assembler will automatically select dense instructions where
possible. If you later need to use an Xtensa processor without the code
density option, the same assembly code will then work without modification.
 
@node Xtensa Automatic Alignment
@subsection Automatic Instruction Alignment
@cindex alignment of @code{LOOP} instructions
@cindex alignment of branch targets
@cindex @code{LOOP} instructions, alignment
@cindex branch target alignment
 
The Xtensa assembler will automatically align certain instructions, both
to optimize performance and to satisfy architectural requirements.
 
As an optimization to improve performance, the assembler attempts to
align branch targets so they do not cross instruction fetch boundaries.
(Xtensa processors can be configured with either 32-bit or 64-bit
instruction fetch widths.) An
instruction immediately following a call is treated as a branch target
in this context, because it will be the target of a return from the
call. This alignment has the potential to reduce branch penalties at
some expense in code size.
This optimization is enabled by default. You can disable it with the
@samp{--no-target-@-align} command-line option (@pxref{Xtensa Options,
,Command Line Options}).
 
The target alignment optimization is done without adding instructions
that could increase the execution time of the program. If there are
density instructions in the code preceding a target, the assembler can
change the target alignment by widening some of those instructions to
the equivalent 24-bit instructions. Extra bytes of padding can be
inserted immediately following unconditional jump and return
instructions.
This approach is usually successful in aligning many, but not all,
branch targets.
 
The @code{LOOP} family of instructions must be aligned such that the
first instruction in the loop body does not cross an instruction fetch
boundary (e.g., with a 32-bit fetch width, a @code{LOOP} instruction
must be on either a 1 or 2 mod 4 byte boundary). The assembler knows
about this restriction and inserts the minimal number of 2 or 3 byte
no-op instructions to satisfy it. When no-op instructions are added,
any label immediately preceding the original loop will be moved in order
to refer to the loop instruction, not the newly generated no-op
instruction. To preserve binary compatibility across processors with
different fetch widths, the assembler conservatively assumes a 32-bit
fetch width when aligning @code{LOOP} instructions (except if the first
instruction in the loop is a 64-bit instruction).
 
Previous versions of the assembler automatically aligned @code{ENTRY}
instructions to 4-byte boundaries, but that alignment is now the
programmer's responsibility.
 
@node Xtensa Relaxation
@section Xtensa Relaxation
@cindex relaxation
 
When an instruction operand is outside the range allowed for that
particular instruction field, @command{@value{AS}} can transform the code
to use a functionally-equivalent instruction or sequence of
instructions. This process is known as @dfn{relaxation}. This is
typically done for branch instructions because the distance of the
branch targets is not known until assembly-time. The Xtensa assembler
offers branch relaxation and also extends this concept to function
calls, @code{MOVI} instructions and other instructions with immediate
fields.
 
@menu
* Xtensa Branch Relaxation:: Relaxation of Branches.
* Xtensa Call Relaxation:: Relaxation of Function Calls.
* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields.
@end menu
 
@node Xtensa Branch Relaxation
@subsection Conditional Branch Relaxation
@cindex relaxation of branch instructions
@cindex branch instructions, relaxation
 
When the target of a branch is too far away from the branch itself,
i.e., when the offset from the branch to the target is too large to fit
in the immediate field of the branch instruction, it may be necessary to
replace the branch with a branch around a jump. For example,
 
@smallexample
beqz a2, L
@end smallexample
 
may result in:
 
@smallexample
@group
bnez.n a2, M
j L
M:
@end group
@end smallexample
 
(The @code{BNEZ.N} instruction would be used in this example only if the
density option is available. Otherwise, @code{BNEZ} would be used.)
 
This relaxation works well because the unconditional jump instruction
has a much larger offset range than the various conditional branches.
However, an error will occur if a branch target is beyond the range of a
jump instruction. @command{@value{AS}} cannot relax unconditional jumps.
Similarly, an error will occur if the original input contains an
unconditional jump to a target that is out of range.
 
Branch relaxation is enabled by default. It can be disabled by using
underscore prefixes (@pxref{Xtensa Opcodes, ,Opcode Names}), the
@samp{--no-transform} command-line option (@pxref{Xtensa Options,
,Command Line Options}), or the @code{no-transform} directive
(@pxref{Transform Directive, ,transform}).
 
@node Xtensa Call Relaxation
@subsection Function Call Relaxation
@cindex relaxation of call instructions
@cindex call instructions, relaxation
 
Function calls may require relaxation because the Xtensa immediate call
instructions (@code{CALL0}, @code{CALL4}, @code{CALL8} and
@code{CALL12}) provide a PC-relative offset of only 512 Kbytes in either
direction. For larger programs, it may be necessary to use indirect
calls (@code{CALLX0}, @code{CALLX4}, @code{CALLX8} and @code{CALLX12})
where the target address is specified in a register. The Xtensa
assembler can automatically relax immediate call instructions into
indirect call instructions. This relaxation is done by loading the
address of the called function into the callee's return address register
and then using a @code{CALLX} instruction. So, for example:
 
@smallexample
call8 func
@end smallexample
 
might be relaxed to:
 
@smallexample
@group
.literal .L1, func
l32r a8, .L1
callx8 a8
@end group
@end smallexample
 
Because the addresses of targets of function calls are not generally
known until link-time, the assembler must assume the worst and relax all
the calls to functions in other source files, not just those that really
will be out of range. The linker can recognize calls that were
unnecessarily relaxed, and it will remove the overhead introduced by the
assembler for those cases where direct calls are sufficient.
 
Call relaxation is disabled by default because it can have a negative
effect on both code size and performance, although the linker can
usually eliminate the unnecessary overhead. If a program is too large
and some of the calls are out of range, function call relaxation can be
enabled using the @samp{--longcalls} command-line option or the
@code{longcalls} directive (@pxref{Longcalls Directive, ,longcalls}).
 
@node Xtensa Immediate Relaxation
@subsection Other Immediate Field Relaxation
@cindex immediate fields, relaxation
@cindex relaxation of immediate fields
 
The assembler normally performs the following other relaxations. They
can be disabled by using underscore prefixes (@pxref{Xtensa Opcodes,
,Opcode Names}), the @samp{--no-transform} command-line option
(@pxref{Xtensa Options, ,Command Line Options}), or the
@code{no-transform} directive (@pxref{Transform Directive, ,transform}).
 
@cindex @code{MOVI} instructions, relaxation
@cindex relaxation of @code{MOVI} instructions
The @code{MOVI} machine instruction can only materialize values in the
range from -2048 to 2047. Values outside this range are best
materialized with @code{L32R} instructions. Thus:
 
@smallexample
movi a0, 100000
@end smallexample
 
is assembled into the following machine code:
 
@smallexample
@group
.literal .L1, 100000
l32r a0, .L1
@end group
@end smallexample
 
@cindex @code{L8UI} instructions, relaxation
@cindex @code{L16SI} instructions, relaxation
@cindex @code{L16UI} instructions, relaxation
@cindex @code{L32I} instructions, relaxation
@cindex relaxation of @code{L8UI} instructions
@cindex relaxation of @code{L16SI} instructions
@cindex relaxation of @code{L16UI} instructions
@cindex relaxation of @code{L32I} instructions
The @code{L8UI} machine instruction can only be used with immediate
offsets in the range from 0 to 255. The @code{L16SI} and @code{L16UI}
machine instructions can only be used with offsets from 0 to 510. The
@code{L32I} machine instruction can only be used with offsets from 0 to
1020. A load offset outside these ranges can be materialized with
an @code{L32R} instruction if the destination register of the load
is different than the source address register. For example:
 
@smallexample
l32i a1, a0, 2040
@end smallexample
 
is translated to:
 
@smallexample
@group
.literal .L1, 2040
l32r a1, .L1
@end group
@group
add a1, a0, a1
l32i a1, a1, 0
@end group
@end smallexample
 
@noindent
If the load destination and source address register are the same, an
out-of-range offset causes an error.
 
@cindex @code{ADDI} instructions, relaxation
@cindex relaxation of @code{ADDI} instructions
The Xtensa @code{ADDI} instruction only allows immediate operands in the
range from -128 to 127. There are a number of alternate instruction
sequences for the @code{ADDI} operation. First, if the
immediate is 0, the @code{ADDI} will be turned into a @code{MOV.N}
instruction (or the equivalent @code{OR} instruction if the code density
option is not available). If the @code{ADDI} immediate is outside of
the range -128 to 127, but inside the range -32896 to 32639, an
@code{ADDMI} instruction or @code{ADDMI}/@code{ADDI} sequence will be
used. Finally, if the immediate is outside of this range and a free
register is available, an @code{L32R}/@code{ADD} sequence will be used
with a literal allocated from the literal pool.
 
For example:
 
@smallexample
@group
addi a5, a6, 0
addi a5, a6, 512
@end group
@group
addi a5, a6, 513
addi a5, a6, 50000
@end group
@end smallexample
 
is assembled into the following:
 
@smallexample
@group
.literal .L1, 50000
mov.n a5, a6
@end group
addmi a5, a6, 0x200
addmi a5, a6, 0x200
addi a5, a5, 1
@group
l32r a5, .L1
add a5, a6, a5
@end group
@end smallexample
 
@node Xtensa Directives
@section Directives
@cindex Xtensa directives
@cindex directives, Xtensa
 
The Xtensa assembler supports a region-based directive syntax:
 
@smallexample
@group
.begin @var{directive} [@var{options}]
@dots{}
.end @var{directive}
@end group
@end smallexample
 
All the Xtensa-specific directives that apply to a region of code use
this syntax.
 
The directive applies to code between the @code{.begin} and the
@code{.end}. The state of the option after the @code{.end} reverts to
what it was before the @code{.begin}.
A nested @code{.begin}/@code{.end} region can further
change the state of the directive without having to be aware of its
outer state. For example, consider:
 
@smallexample
@group
.begin no-transform
L: add a0, a1, a2
@end group
.begin transform
M: add a0, a1, a2
.end transform
@group
N: add a0, a1, a2
.end no-transform
@end group
@end smallexample
 
The @code{ADD} opcodes at @code{L} and @code{N} in the outer
@code{no-transform} region both result in @code{ADD} machine instructions,
but the assembler selects an @code{ADD.N} instruction for the
@code{ADD} at @code{M} in the inner @code{transform} region.
 
The advantage of this style is that it works well inside macros which can
preserve the context of their callers.
 
The following directives are available:
@menu
* Schedule Directive:: Enable instruction scheduling.
* Longcalls Directive:: Use Indirect Calls for Greater Range.
* Transform Directive:: Disable All Assembler Transformations.
* Literal Directive:: Intermix Literals with Instructions.
* Literal Position Directive:: Specify Inline Literal Pool Locations.
* Literal Prefix Directive:: Specify Literal Section Name Prefix.
* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
@end menu
 
@node Schedule Directive
@subsection schedule
@cindex @code{schedule} directive
@cindex @code{no-schedule} directive
 
The @code{schedule} directive is recognized only for compatibility with
Tensilica's assembler.
 
@smallexample
@group
.begin [no-]schedule
.end [no-]schedule
@end group
@end smallexample
 
This directive is ignored and has no effect on @command{@value{AS}}.
 
@node Longcalls Directive
@subsection longcalls
@cindex @code{longcalls} directive
@cindex @code{no-longcalls} directive
 
The @code{longcalls} directive enables or disables function call
relaxation. @xref{Xtensa Call Relaxation, ,Function Call Relaxation}.
 
@smallexample
@group
.begin [no-]longcalls
.end [no-]longcalls
@end group
@end smallexample
 
Call relaxation is disabled by default unless the @samp{--longcalls}
command-line option is specified. The @code{longcalls} directive
overrides the default determined by the command-line options.
 
@node Transform Directive
@subsection transform
@cindex @code{transform} directive
@cindex @code{no-transform} directive
 
This directive enables or disables all assembler transformation,
including relaxation (@pxref{Xtensa Relaxation, ,Xtensa Relaxation}) and
optimization (@pxref{Xtensa Optimizations, ,Xtensa Optimizations}).
 
@smallexample
@group
.begin [no-]transform
.end [no-]transform
@end group
@end smallexample
 
Transformations are enabled by default unless the @samp{--no-transform}
option is used. The @code{transform} directive overrides the default
determined by the command-line options. An underscore opcode prefix,
disabling transformation of that opcode, always takes precedence over
both directives and command-line flags.
 
@node Literal Directive
@subsection literal
@cindex @code{literal} directive
 
The @code{.literal} directive is used to define literal pool data, i.e.,
read-only 32-bit data accessed via @code{L32R} instructions.
 
@smallexample
.literal @var{label}, @var{value}[, @var{value}@dots{}]
@end smallexample
 
This directive is similar to the standard @code{.word} directive, except
that the actual location of the literal data is determined by the
assembler and linker, not by the position of the @code{.literal}
directive. Using this directive gives the assembler freedom to locate
the literal data in the most appropriate place and possibly to combine
identical literals. For example, the code:
 
@smallexample
@group
entry sp, 40
.literal .L1, sym
l32r a4, .L1
@end group
@end smallexample
 
can be used to load a pointer to the symbol @code{sym} into register
@code{a4}. The value of @code{sym} will not be placed between the
@code{ENTRY} and @code{L32R} instructions; instead, the assembler puts
the data in a literal pool.
 
Literal pools are placed by default in separate literal sections;
however, when using the @samp{--text-@-section-@-literals}
option (@pxref{Xtensa Options, ,Command Line Options}), the literal
pools for PC-relative mode @code{L32R} instructions
are placed in the current section.@footnote{Literals for the
@code{.init} and @code{.fini} sections are always placed in separate
sections, even when @samp{--text-@-section-@-literals} is enabled.}
These text section literal
pools are created automatically before @code{ENTRY} instructions and
manually after @samp{.literal_position} directives (@pxref{Literal
Position Directive, ,literal_position}). If there are no preceding
@code{ENTRY} instructions, explicit @code{.literal_position} directives
must be used to place the text section literal pools; otherwise,
@command{@value{AS}} will report an error.
 
When literals are placed in separate sections, the literal section names
are derived from the names of the sections where the literals are
defined. The base literal section names are @code{.literal} for
PC-relative mode @code{L32R} instructions and @code{.lit4} for absolute
mode @code{L32R} instructions (@pxref{Absolute Literals Directive,
,absolute-literals}). These base names are used for literals defined in
the default @code{.text} section. For literals defined in other
sections or within the scope of a @code{literal_prefix} directive
(@pxref{Literal Prefix Directive, ,literal_prefix}), the following rules
determine the literal section name:
 
@enumerate
@item
If the current section is a member of a section group, the literal
section name includes the group name as a suffix to the base
@code{.literal} or @code{.lit4} name, with a period to separate the base
name and group name. The literal section is also made a member of the
group.
 
@item
If the current section name (or @code{literal_prefix} value) begins with
``@code{.gnu.linkonce.@var{kind}.}'', the literal section name is formed
by replacing ``@code{.@var{kind}}'' with the base @code{.literal} or
@code{.lit4} name. For example, for literals defined in a section named
@code{.gnu.linkonce.t.func}, the literal section will be
@code{.gnu.linkonce.literal.func} or @code{.gnu.linkonce.lit4.func}.
 
@item
If the current section name (or @code{literal_prefix} value) ends with
@code{.text}, the literal section name is formed by replacing that
suffix with the base @code{.literal} or @code{.lit4} name. For example,
for literals defined in a section named @code{.iram0.text}, the literal
section will be @code{.iram0.literal} or @code{.iram0.lit4}.
 
@item
If none of the preceding conditions apply, the literal section name is
formed by adding the base @code{.literal} or @code{.lit4} name as a
suffix to the current section name (or @code{literal_prefix} value).
@end enumerate
 
@node Literal Position Directive
@subsection literal_position
@cindex @code{literal_position} directive
 
When using @samp{--text-@-section-@-literals} to place literals inline
in the section being assembled, the @code{.literal_position} directive
can be used to mark a potential location for a literal pool.
 
@smallexample
.literal_position
@end smallexample
 
The @code{.literal_position} directive is ignored when the
@samp{--text-@-section-@-literals} option is not used or when
@code{L32R} instructions use the absolute addressing mode.
 
The assembler will automatically place text section literal pools
before @code{ENTRY} instructions, so the @code{.literal_position}
directive is only needed to specify some other location for a literal
pool. You may need to add an explicit jump instruction to skip over an
inline literal pool.
 
For example, an interrupt vector does not begin with an @code{ENTRY}
instruction so the assembler will be unable to automatically find a good
place to put a literal pool. Moreover, the code for the interrupt
vector must be at a specific starting address, so the literal pool
cannot come before the start of the code. The literal pool for the
vector must be explicitly positioned in the middle of the vector (before
any uses of the literals, due to the negative offsets used by
PC-relative @code{L32R} instructions). The @code{.literal_position}
directive can be used to do this. In the following code, the literal
for @samp{M} will automatically be aligned correctly and is placed after
the unconditional jump.
 
@smallexample
@group
.global M
code_start:
@end group
j continue
.literal_position
.align 4
@group
continue:
movi a4, M
@end group
@end smallexample
 
@node Literal Prefix Directive
@subsection literal_prefix
@cindex @code{literal_prefix} directive
 
The @code{literal_prefix} directive allows you to override the default
literal section names, which are derived from the names of the sections
where the literals are defined.
 
@smallexample
@group
.begin literal_prefix [@var{name}]
.end literal_prefix
@end group
@end smallexample
 
For literals defined within the delimited region, the literal section
names are derived from the @var{name} argument instead of the name of
the current section. The rules used to derive the literal section names
do not change. @xref{Literal Directive, ,literal}. If the @var{name}
argument is omitted, the literal sections revert to the defaults. This
directive has no effect when using the
@samp{--text-@-section-@-literals} option (@pxref{Xtensa Options,
,Command Line Options}).
 
@node Absolute Literals Directive
@subsection absolute-literals
@cindex @code{absolute-literals} directive
@cindex @code{no-absolute-literals} directive
 
The @code{absolute-@-literals} and @code{no-@-absolute-@-literals}
directives control the absolute vs.@: PC-relative mode for @code{L32R}
instructions. These are relevant only for Xtensa configurations that
include the absolute addressing option for @code{L32R} instructions.
 
@smallexample
@group
.begin [no-]absolute-literals
.end [no-]absolute-literals
@end group
@end smallexample
 
These directives do not change the @code{L32R} mode---they only cause
the assembler to emit the appropriate kind of relocation for @code{L32R}
instructions and to place the literal values in the appropriate section.
To change the @code{L32R} mode, the program must write the
@code{LITBASE} special register. It is the programmer's responsibility
to keep track of the mode and indicate to the assembler which mode is
used in each region of code.
 
If the Xtensa configuration includes the absolute @code{L32R} addressing
option, the default is to assume absolute @code{L32R} addressing unless
the @samp{--no-@-absolute-@-literals} command-line option is specified.
Otherwise, the default is to assume PC-relative @code{L32R} addressing.
The @code{absolute-@-literals} directive can then be used to override
the default determined by the command-line options.
 
@c Local Variables:
@c fill-column: 72
@c End:
/binutils/gas/doc/c-z80.texi
0,0 → 1,268
@c Copyright 2011 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
 
@ifset GENERIC
@page
@node Z80-Dependent
@chapter Z80 Dependent Features
@end ifset
 
 
@ifclear GENERIC
@node Machine Dependencies
@chapter Z80 Dependent Features
@end ifclear
 
@cindex Z80 support
@menu
* Z80 Options:: Options
* Z80 Syntax:: Syntax
* Z80 Floating Point:: Floating Point
* Z80 Directives:: Z80 Machine Directives
* Z80 Opcodes:: Opcodes
@end menu
 
@node Z80 Options
@section Options
@cindex Z80 options
@cindex options for Z80
The Zilog Z80 and Ascii R800 version of @code{@value{AS}} have a few machine
dependent options.
@table @option
@cindex @code{-z80} command line option, Z80
@item -z80
Produce code for the Z80 processor. There are additional options to
request warnings and error messages for undocumented instructions.
@item -ignore-undocumented-instructions
@itemx -Wnud
Silently assemble undocumented Z80-instructions that have been adopted
as documented R800-instructions.
@item -ignore-unportable-instructions
@itemx -Wnup
Silently assemble all undocumented Z80-instructions.
@item -warn-undocumented-instructions
@itemx -Wud
Issue warnings for undocumented Z80-instructions that work on R800, do
not assemble other undocumented instructions without warning.
@item -warn-unportable-instructions
@itemx -Wup
Issue warnings for other undocumented Z80-instructions, do not treat any
undocumented instructions as errors.
@item -forbid-undocumented-instructions
@itemx -Fud
Treat all undocumented z80-instructions as errors.
@item -forbid-unportable-instructions
@itemx -Fup
Treat undocumented z80-instructions that do not work on R800 as errors.
 
@cindex @code{-r800} command line option, Z80
@item -r800
Produce code for the R800 processor. The assembler does not support
undocumented instructions for the R800.
In line with common practice, @code{@value{AS}} uses Z80 instruction names
for the R800 processor, as far as they exist.
@end table
 
@cindex Z80 Syntax
@node Z80 Syntax
@section Syntax
The assembler syntax closely follows the 'Z80 family CPU User Manual' by
Zilog.
In expressions a single @samp{=} may be used as ``is equal to''
comparison operator.
 
Suffices can be used to indicate the radix of integer constants;
@samp{H} or @samp{h} for hexadecimal, @samp{D} or @samp{d} for decimal,
@samp{Q}, @samp{O}, @samp{q} or @samp{o} for octal, and @samp{B} for
binary.
 
The suffix @samp{b} denotes a backreference to local label.
 
@menu
* Z80-Chars:: Special Characters
* Z80-Regs:: Register Names
* Z80-Case:: Case Sensitivity
@end menu
 
@node Z80-Chars
@subsection Special Characters
 
@cindex line comment character, Z80
@cindex Z80 line comment character
The semicolon @samp{;} is the line comment character;
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, Z80
@cindex statement separator, Z80
@cindex Z80 line separator
The Z80 assembler does not support a line separator character.
 
@cindex location counter, Z80
@cindex hexadecimal prefix, Z80
@cindex Z80 $
The dollar sign @samp{$} can be used as a prefix for hexadecimal numbers
and as a symbol denoting the current location counter.
 
@cindex character escapes, Z80
@cindex Z80, \
A backslash @samp{\} is an ordinary character for the Z80 assembler.
@cindex character constant, Z80
@cindex single quote, Z80
@cindex Z80 '
The single quote @samp{'} must be followed by a closing quote. If there
is one character in between, it is a character constant, otherwise it is
a string constant.
 
@node Z80-Regs
@subsection Register Names
@cindex Z80 registers
@cindex register names, Z80
 
The registers are referred to with the letters assigned to them by
Zilog. In addition @command{@value{AS}} recognizes @samp{ixl} and
@samp{ixh} as the least and most significant octet in @samp{ix}, and
similarly @samp{iyl} and @samp{iyh} as parts of @samp{iy}.
 
@c The @samp{'} in @samp{ex af,af'} may be omitted.
 
@node Z80-Case
@subsection Case Sensitivity
@cindex Z80, case sensitivity
@cindex case sensitivity, Z80
 
Upper and lower case are equivalent in register names, opcodes,
condition codes and assembler directives.
The case of letters is significant in labels and symbol names. The case
is also important to distinguish the suffix @samp{b} for a backward reference
to a local label from the suffix @samp{B} for a number in binary notation.
 
@node Z80 Floating Point
@section Floating Point
@cindex floating point, Z80
@cindex Z80 floating point
Floating-point numbers are not supported.
 
@node Z80 Directives
@section Z80 Assembler Directives
 
@command{@value{AS}} for the Z80 supports some additional directives for
compatibility with other assemblers.
 
@cindex Z80-only directives
These are the additional directives in @code{@value{AS}} for the Z80:
 
@table @code
@item db @var{expression}|@var{string}[,@var{expression}|@var{string}...]
@itemx defb @var{expression}|@var{string}[,@var{expression}|@var{string}...]
For each @var{string} the characters are copied to the object file, for
each other @var{expression} the value is stored in one byte.
A warning is issued in case of an overflow.
 
@item dw @var{expression}[,@var{expression}...]
@itemx defw @var{expression}[,@var{expression}...]
For each @var{expression} the value is stored in two bytes, ignoring
overflow.
 
@item d24 @var{expression}[,@var{expression}...]
@itemx def24 @var{expression}[,@var{expression}...]
For each @var{expression} the value is stored in three bytes, ignoring
overflow.
 
@item d32 @var{expression}[,@var{expression}...]
@itemx def32 @var{expression}[,@var{expression}...]
For each @var{expression} the value is stored in four bytes, ignoring
overflow.
 
@item ds @var{count}[, @var{value}]
@itemx defs @var{count}[, @var{value}]
@c Synonyms for @code{ds.b},
@c which should have been described elsewhere
Fill @var{count} bytes in the object file with @var{value}, if
@var{value} is omitted it defaults to zero.
 
@item @var{symbol} equ @var{expression}
@itemx @var{symbol} defl @var{expression}
These directives set the value of @var{symbol} to @var{expression}. If
@code{equ} is used, it is an error if @var{symbol} is already defined.
Symbols defined with @code{equ} are not protected from redefinition.
 
@item set
This is a normal instruction on Z80, and not an assembler directive.
 
@item psect @var{name}
A synonym for @xref{Section}, no second argument should be given.
@ignore
 
The following attributes will possibly be recognized in the future
@table @code
@item abs
The section is to be absolute. @code{@value{AS}} will issue an error
message because it can not produce an absolute section.
@item global
The section is to be concatenated with other sections of the same name
by the linker, this is the default.
@item local
The section is not global. @code{@value{AS}} will issue a warning if
object file format is not soff.
@item ovrld
The section is to be overlapped with other sections of the same name by
the linker. @code{@value{AS}} will issue an error message
because it can not mark a section as such.
@item pure
The section is marked as read only.
@end table
@end ignore
 
@end table
 
@node Z80 Opcodes
@section Opcodes
In line with common practice, Z80 mnemonics are used for both the Z80 and
the R800.
 
In many instructions it is possible to use one of the half index
registers (@samp{ixl},@samp{ixh},@samp{iyl},@samp{iyh}) in stead of an
8-bit general purpose register. This yields instructions that are
documented on the R800 and undocumented on the Z80.
Similarly @code{in f,(c)} is documented on the R800 and undocumented on
the Z80.
 
The assembler also supports the following undocumented Z80-instructions,
that have not been adopted in the R800 instruction set:
@table @code
@item out (c),0
Sends zero to the port pointed to by register c.
 
@item sli @var{m}
Equivalent to @code{@var{m} = (@var{m}<<1)+1}, the operand @var{m} can
be any operand that is valid for @samp{sla}. One can use @samp{sll} as a
synonym for @samp{sli}.
 
@item @var{op} (ix+@var{d}), @var{r}
This is equivalent to
 
@example
ld @var{r}, (ix+@var{d})
@var{opc} @var{r}
ld (ix+@var{d}), @var{r}
@end example
 
The operation @samp{@var{opc}} may be any of @samp{res @var{b},},
@samp{set @var{b},}, @samp{rl}, @samp{rlc}, @samp{rr}, @samp{rrc},
@samp{sla}, @samp{sli}, @samp{sra} and @samp{srl}, and the register
@samp{@var{r}} may be any of @samp{a}, @samp{b}, @samp{c}, @samp{d},
@samp{e}, @samp{h} and @samp{l}.
 
@item @var{opc} (iy+@var{d}), @var{r}
As above, but with @samp{iy} instead of @samp{ix}.
@end table
 
The web site at @uref{http://www.z80.info} is a good starting place to
find more information on programming the Z80.
 
/binutils/gas/doc/c-z8k.texi
0,0 → 1,405
@c Copyright 1991, 1992, 1993, 1994, 1995, 2003, 2011
@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@ifset GENERIC
@page
@node Z8000-Dependent
@chapter Z8000 Dependent Features
@end ifset
@ifclear GENERIC
@node Machine Dependencies
@chapter Z8000 Dependent Features
@end ifclear
 
@cindex Z8000 support
The Z8000 @value{AS} supports both members of the Z8000 family: the
unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
24 bit addresses.
 
When the assembler is in unsegmented mode (specified with the
@code{unsegm} directive), an address takes up one word (16 bit)
sized register. When the assembler is in segmented mode (specified with
the @code{segm} directive), a 24-bit address takes up a long (32 bit)
register. @xref{Z8000 Directives,,Assembler Directives for the Z8000},
for a list of other Z8000 specific assembler directives.
 
@menu
* Z8000 Options:: Command-line options for the Z8000
* Z8000 Syntax:: Assembler syntax for the Z8000
* Z8000 Directives:: Special directives for the Z8000
* Z8000 Opcodes:: Opcodes
@end menu
 
@node Z8000 Options
@section Options
 
@cindex Z8000 options
@cindex options, Z8000
@table @option
@cindex @code{-z8001} command line option, Z8000
@item -z8001
Generate segmented code by default.
 
@cindex @code{-z8002} command line option, Z8000
@item -z8002
Generate unsegmented code by default.
@end table
 
@node Z8000 Syntax
@section Syntax
@menu
* Z8000-Chars:: Special Characters
* Z8000-Regs:: Register Names
* Z8000-Addressing:: Addressing Modes
@end menu
 
@node Z8000-Chars
@subsection Special Characters
 
@cindex line comment character, Z8000
@cindex Z8000 line comment character
@samp{!} is the line comment character.
 
If a @samp{#} appears as the first character of a line then the whole
line is treated as a comment, but in this case the line could also be
a logical line number directive (@pxref{Comments}) or a preprocessor
control command (@pxref{Preprocessing}).
 
@cindex line separator, Z8000
@cindex statement separator, Z8000
@cindex Z8000 line separator
You can use @samp{;} instead of a newline to separate statements.
 
@node Z8000-Regs
@subsection Register Names
 
@cindex Z8000 registers
@cindex registers, Z8000
The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer
to different sized groups of registers by register number, with the
prefix @samp{r} for 16 bit registers, @samp{rr} for 32 bit registers and
@samp{rq} for 64 bit registers. You can also refer to the contents of
the first eight (of the sixteen 16 bit registers) by bytes. They are
named @samp{rl@var{n}} and @samp{rh@var{n}}.
 
@smallexample
@exdent @emph{byte registers}
rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
 
@exdent @emph{word registers}
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
 
@exdent @emph{long word registers}
rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
 
@exdent @emph{quad word registers}
rq0 rq4 rq8 rq12
@end smallexample
 
@node Z8000-Addressing
@subsection Addressing Modes
 
@cindex addressing modes, Z8000
@cindex Z800 addressing modes
@value{AS} understands the following addressing modes for the Z8000:
 
@table @code
@item rl@var{n}
@itemx rh@var{n}
@itemx r@var{n}
@itemx rr@var{n}
@itemx rq@var{n}
Register direct: 8bit, 16bit, 32bit, and 64bit registers.
 
@item @@r@var{n}
@itemx @@rr@var{n}
Indirect register: @@rr@var{n} in segmented mode, @@r@var{n} in unsegmented
mode.
 
@item @var{addr}
Direct: the 16 bit or 24 bit address (depending on whether the assembler
is in segmented or unsegmented mode) of the operand is in the instruction.
 
@item address(r@var{n})
Indexed: the 16 or 24 bit address is added to the 16 bit register to produce
the final address in memory of the operand.
 
@item r@var{n}(#@var{imm})
@itemx rr@var{n}(#@var{imm})
Base Address: the 16 or 24 bit register is added to the 16 bit sign
extended immediate displacement to produce the final address in memory
of the operand.
 
@item r@var{n}(r@var{m})
@itemx rr@var{n}(r@var{m})
Base Index: the 16 or 24 bit register r@var{n} or rr@var{n} is added to
the sign extended 16 bit index register r@var{m} to produce the final
address in memory of the operand.
 
@item #@var{xx}
Immediate data @var{xx}.
@end table
 
@node Z8000 Directives
@section Assembler Directives for the Z8000
 
@cindex Z8000 directives
@cindex directives, Z8000
The Z8000 port of @value{AS} includes additional assembler directives,
for compatibility with other Z8000 assemblers. These do not begin with
@samp{.} (unlike the ordinary @value{AS} directives).
 
@table @code
@kindex segm
@item segm
@kindex .z8001
@itemx .z8001
Generate code for the segmented Z8001.
 
@kindex unsegm
@item unsegm
@kindex .z8002
@itemx .z8002
Generate code for the unsegmented Z8002.
 
@kindex name
@item name
Synonym for @code{.file}
 
@kindex global
@item global
Synonym for @code{.global}
 
@kindex wval
@item wval
Synonym for @code{.word}
 
@kindex lval
@item lval
Synonym for @code{.long}
 
@kindex bval
@item bval
Synonym for @code{.byte}
 
@kindex sval
@item sval
Assemble a string. @code{sval} expects one string literal, delimited by
single quotes. It assembles each byte of the string into consecutive
addresses. You can use the escape sequence @samp{%@var{xx}} (where
@var{xx} represents a two-digit hexadecimal number) to represent the
character whose @sc{ascii} value is @var{xx}. Use this feature to
describe single quote and other characters that may not appear in string
literals as themselves. For example, the C statement @w{@samp{char *a =
"he said \"it's 50% off\"";}} is represented in Z8000 assembly language
(shown with the assembler output in hex at the left) as
 
@iftex
@begingroup
@let@nonarrowing=@comment
@end iftex
@smallexample
68652073 sval 'he said %22it%27s 50%25 off%22%00'
61696420
22697427
73203530
25206F66
662200
@end smallexample
@iftex
@endgroup
@end iftex
 
@kindex rsect
@item rsect
synonym for @code{.section}
 
@kindex block
@item block
synonym for @code{.space}
 
@kindex even
@item even
special case of @code{.align}; aligns output to even byte boundary.
@end table
 
@node Z8000 Opcodes
@section Opcodes
 
@cindex Z8000 opcode summary
@cindex opcode summary, Z8000
@cindex mnemonics, Z8000
@cindex instruction summary, Z8000
For detailed information on the Z8000 machine instruction set, see
@cite{Z8000 Technical Manual}.
 
@ifset SMALL
@c this table, due to the multi-col faking and hardcoded order, looks silly
@c except in smallbook. See comments below "@set SMALL" near top of this file.
 
The following table summarizes the opcodes and their arguments:
@iftex
@begingroup
@let@nonarrowing=@comment
@end iftex
@smallexample
 
rs @r{16 bit source register}
rd @r{16 bit destination register}
rbs @r{8 bit source register}
rbd @r{8 bit destination register}
rrs @r{32 bit source register}
rrd @r{32 bit destination register}
rqs @r{64 bit source register}
rqd @r{64 bit destination register}
addr @r{16/24 bit address}
imm @r{immediate data}
 
adc rd,rs clrb addr cpsir @@rd,@@rs,rr,cc
adcb rbd,rbs clrb addr(rd) cpsirb @@rd,@@rs,rr,cc
add rd,@@rs clrb rbd dab rbd
add rd,addr com @@rd dbjnz rbd,disp7
add rd,addr(rs) com addr dec @@rd,imm4m1
add rd,imm16 com addr(rd) dec addr(rd),imm4m1
add rd,rs com rd dec addr,imm4m1
addb rbd,@@rs comb @@rd dec rd,imm4m1
addb rbd,addr comb addr decb @@rd,imm4m1
addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1
addb rbd,imm8 comb rbd decb addr,imm4m1
addb rbd,rbs comflg flags decb rbd,imm4m1
addl rrd,@@rs cp @@rd,imm16 di i2
addl rrd,addr cp addr(rd),imm16 div rrd,@@rs
addl rrd,addr(rs) cp addr,imm16 div rrd,addr
addl rrd,imm32 cp rd,@@rs div rrd,addr(rs)
addl rrd,rrs cp rd,addr div rrd,imm16
and rd,@@rs cp rd,addr(rs) div rrd,rs
and rd,addr cp rd,imm16 divl rqd,@@rs
and rd,addr(rs) cp rd,rs divl rqd,addr
and rd,imm16 cpb @@rd,imm8 divl rqd,addr(rs)
and rd,rs cpb addr(rd),imm8 divl rqd,imm32
andb rbd,@@rs cpb addr,imm8 divl rqd,rrs
andb rbd,addr cpb rbd,@@rs djnz rd,disp7
andb rbd,addr(rs) cpb rbd,addr ei i2
andb rbd,imm8 cpb rbd,addr(rs) ex rd,@@rs
andb rbd,rbs cpb rbd,imm8 ex rd,addr
bit @@rd,imm4 cpb rbd,rbs ex rd,addr(rs)
bit addr(rd),imm4 cpd rd,@@rs,rr,cc ex rd,rs
bit addr,imm4 cpdb rbd,@@rs,rr,cc exb rbd,@@rs
bit rd,imm4 cpdr rd,@@rs,rr,cc exb rbd,addr
bit rd,rs cpdrb rbd,@@rs,rr,cc exb rbd,addr(rs)
bitb @@rd,imm4 cpi rd,@@rs,rr,cc exb rbd,rbs
bitb addr(rd),imm4 cpib rbd,@@rs,rr,cc ext0e imm8
bitb addr,imm4 cpir rd,@@rs,rr,cc ext0f imm8
bitb rbd,imm4 cpirb rbd,@@rs,rr,cc ext8e imm8
bitb rbd,rs cpl rrd,@@rs ext8f imm8
bpt cpl rrd,addr exts rrd
call @@rd cpl rrd,addr(rs) extsb rd
call addr cpl rrd,imm32 extsl rqd
call addr(rd) cpl rrd,rrs halt
calr disp12 cpsd @@rd,@@rs,rr,cc in rd,@@rs
clr @@rd cpsdb @@rd,@@rs,rr,cc in rd,imm16
clr addr cpsdr @@rd,@@rs,rr,cc inb rbd,@@rs
clr addr(rd) cpsdrb @@rd,@@rs,rr,cc inb rbd,imm16
clr rd cpsi @@rd,@@rs,rr,cc inc @@rd,imm4m1
clrb @@rd cpsib @@rd,@@rs,rr,cc inc addr(rd),imm4m1
inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs)
inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16
incb @@rd,imm4m1 ldb rd(rx),rbs mult rrd,rs
incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@@rs
incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr
incb rbd,imm4m1 ldd @@rs,@@rd,rr multl rqd,addr(rs)
ind @@rd,@@rs,ra lddb @@rs,@@rd,rr multl rqd,imm32
indb @@rd,@@rs,rba lddr @@rs,@@rd,rr multl rqd,rrs
inib @@rd,@@rs,ra lddrb @@rs,@@rd,rr neg @@rd
inibr @@rd,@@rs,ra ldi @@rd,@@rs,rr neg addr
iret ldib @@rd,@@rs,rr neg addr(rd)
jp cc,@@rd ldir @@rd,@@rs,rr neg rd
jp cc,addr ldirb @@rd,@@rs,rr negb @@rd
jp cc,addr(rd) ldk rd,imm4 negb addr
jr cc,disp8 ldl @@rd,rrs negb addr(rd)
ld @@rd,imm16 ldl addr(rd),rrs negb rbd
ld @@rd,rs ldl addr,rrs nop
ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@@rs
ld addr(rd),rs ldl rd(rx),rrs or rd,addr
ld addr,imm16 ldl rrd,@@rs or rd,addr(rs)
ld addr,rs ldl rrd,addr or rd,imm16
ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs
ld rd(rx),rs ldl rrd,imm32 orb rbd,@@rs
ld rd,@@rs ldl rrd,rrs orb rbd,addr
ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs)
ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8
ld rd,imm16 ldm @@rd,rs,n orb rbd,rbs
ld rd,rs ldm addr(rd),rs,n out @@rd,rs
ld rd,rs(imm16) ldm addr,rs,n out imm16,rs
ld rd,rs(rx) ldm rd,@@rs,n outb @@rd,rbs
lda rd,addr ldm rd,addr(rs),n outb imm16,rbs
lda rd,addr(rs) ldm rd,addr,n outd @@rd,@@rs,ra
lda rd,rs(imm16) ldps @@rs outdb @@rd,@@rs,rba
lda rd,rs(rx) ldps addr outib @@rd,@@rs,ra
ldar rd,disp16 ldps addr(rs) outibr @@rd,@@rs,ra
ldb @@rd,imm8 ldr disp16,rs pop @@rd,@@rs
ldb @@rd,rbs ldr rd,disp16 pop addr(rd),@@rs
ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@@rs
ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@@rs
ldb addr,imm8 ldrl disp16,rrs popl @@rd,@@rs
ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@@rs
ldb rbd,@@rs mbit popl addr,@@rs
ldb rbd,addr mreq rd popl rrd,@@rs
ldb rbd,addr(rs) mres push @@rd,@@rs
ldb rbd,imm8 mset push @@rd,addr
ldb rbd,rbs mult rrd,@@rs push @@rd,addr(rs)
ldb rbd,rs(imm16) mult rrd,addr push @@rd,imm16
push @@rd,rs set addr,imm4 subl rrd,imm32
pushl @@rd,@@rs set rd,imm4 subl rrd,rrs
pushl @@rd,addr set rd,rs tcc cc,rd
pushl @@rd,addr(rs) setb @@rd,imm4 tccb cc,rbd
pushl @@rd,rrs setb addr(rd),imm4 test @@rd
res @@rd,imm4 setb addr,imm4 test addr
res addr(rd),imm4 setb rbd,imm4 test addr(rd)
res addr,imm4 setb rbd,rs test rd
res rd,imm4 setflg imm4 testb @@rd
res rd,rs sinb rbd,imm16 testb addr
resb @@rd,imm4 sinb rd,imm16 testb addr(rd)
resb addr(rd),imm4 sind @@rd,@@rs,ra testb rbd
resb addr,imm4 sindb @@rd,@@rs,rba testl @@rd
resb rbd,imm4 sinib @@rd,@@rs,ra testl addr
resb rbd,rs sinibr @@rd,@@rs,ra testl addr(rd)
resflg imm4 sla rd,imm8 testl rrd
ret cc slab rbd,imm8 trdb @@rd,@@rs,rba
rl rd,imm1or2 slal rrd,imm8 trdrb @@rd,@@rs,rba
rlb rbd,imm1or2 sll rd,imm8 trib @@rd,@@rs,rbr
rlc rd,imm1or2 sllb rbd,imm8 trirb @@rd,@@rs,rbr
rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @@ra,@@rb,rbr
rldb rbb,rba sout imm16,rs trtib @@ra,@@rb,rr
rr rd,imm1or2 soutb imm16,rbs trtirb @@ra,@@rb,rbr
rrb rbd,imm1or2 soutd @@rd,@@rs,ra trtrb @@ra,@@rb,rbr
rrc rd,imm1or2 soutdb @@rd,@@rs,rba tset @@rd
rrcb rbd,imm1or2 soutib @@rd,@@rs,ra tset addr
rrdb rbb,rba soutibr @@rd,@@rs,ra tset addr(rd)
rsvd36 sra rd,imm8 tset rd
rsvd38 srab rbd,imm8 tsetb @@rd
rsvd78 sral rrd,imm8 tsetb addr
rsvd7e srl rd,imm8 tsetb addr(rd)
rsvd9d srlb rbd,imm8 tsetb rbd
rsvd9f srll rrd,imm8 xor rd,@@rs
rsvdb9 sub rd,@@rs xor rd,addr
rsvdbf sub rd,addr xor rd,addr(rs)
sbc rd,rs sub rd,addr(rs) xor rd,imm16
sbcb rbd,rbs sub rd,imm16 xor rd,rs
sc imm8 sub rd,rs xorb rbd,@@rs
sda rd,rs subb rbd,@@rs xorb rbd,addr
sdab rbd,rs subb rbd,addr xorb rbd,addr(rs)
sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8
sdl rd,rs subb rbd,imm8 xorb rbd,rbs
sdlb rbd,rs subb rbd,rbs xorb rbd,rbs
sdll rrd,rs subl rrd,@@rs
set @@rd,imm4 subl rrd,addr
set addr(rd),imm4 subl rrd,addr(rs)
@end smallexample
@iftex
@endgroup
@end iftex
@end ifset
 
/binutils/gas/doc/fdl.texi
0,0 → 1,506
@c The GNU Free Documentation License.
@center Version 1.3, 3 November 2008
 
@c This file is intended to be included within another document,
@c hence no sectioning command or @node.
 
@display
Copyright @copyright{} 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
@uref{http://fsf.org/}
 
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
@end display
 
@enumerate 0
@item
PREAMBLE
 
The purpose of this License is to make a manual, textbook, or other
functional and useful document @dfn{free} in the sense of freedom: to
assure everyone the effective freedom to copy and redistribute it,
with or without modifying it, either commercially or noncommercially.
Secondarily, this License preserves for the author and publisher a way
to get credit for their work, while not being considered responsible
for modifications made by others.
 
This License is a kind of ``copyleft'', which means that derivative
works of the document must themselves be free in the same sense. It
complements the GNU General Public License, which is a copyleft
license designed for free software.
 
We have designed this License in order to use it for manuals for free
software, because free software needs free documentation: a free
program should come with manuals providing the same freedoms that the
software does. But this License is not limited to software manuals;
it can be used for any textual work, regardless of subject matter or
whether it is published as a printed book. We recommend this License
principally for works whose purpose is instruction or reference.
 
@item
APPLICABILITY AND DEFINITIONS
 
This License applies to any manual or other work, in any medium, that
contains a notice placed by the copyright holder saying it can be
distributed under the terms of this License. Such a notice grants a
world-wide, royalty-free license, unlimited in duration, to use that
work under the conditions stated herein. The ``Document'', below,
refers to any such manual or work. Any member of the public is a
licensee, and is addressed as ``you''. You accept the license if you
copy, modify or distribute the work in a way requiring permission
under copyright law.
 
A ``Modified Version'' of the Document means any work containing the
Document or a portion of it, either copied verbatim, or with
modifications and/or translated into another language.
 
A ``Secondary Section'' is a named appendix or a front-matter section
of the Document that deals exclusively with the relationship of the
publishers or authors of the Document to the Document's overall
subject (or to related matters) and contains nothing that could fall
directly within that overall subject. (Thus, if the Document is in
part a textbook of mathematics, a Secondary Section may not explain
any mathematics.) The relationship could be a matter of historical
connection with the subject or with related matters, or of legal,
commercial, philosophical, ethical or political position regarding
them.
 
The ``Invariant Sections'' are certain Secondary Sections whose titles
are designated, as being those of Invariant Sections, in the notice
that says that the Document is released under this License. If a
section does not fit the above definition of Secondary then it is not
allowed to be designated as Invariant. The Document may contain zero
Invariant Sections. If the Document does not identify any Invariant
Sections then there are none.
 
The ``Cover Texts'' are certain short passages of text that are listed,
as Front-Cover Texts or Back-Cover Texts, in the notice that says that
the Document is released under this License. A Front-Cover Text may
be at most 5 words, and a Back-Cover Text may be at most 25 words.
 
A ``Transparent'' copy of the Document means a machine-readable copy,
represented in a format whose specification is available to the
general public, that is suitable for revising the document
straightforwardly with generic text editors or (for images composed of
pixels) generic paint programs or (for drawings) some widely available
drawing editor, and that is suitable for input to text formatters or
for automatic translation to a variety of formats suitable for input
to text formatters. A copy made in an otherwise Transparent file
format whose markup, or absence of markup, has been arranged to thwart
or discourage subsequent modification by readers is not Transparent.
An image format is not Transparent if used for any substantial amount
of text. A copy that is not ``Transparent'' is called ``Opaque''.
 
Examples of suitable formats for Transparent copies include plain
@sc{ascii} without markup, Texinfo input format, La@TeX{} input
format, @acronym{SGML} or @acronym{XML} using a publicly available
@acronym{DTD}, and standard-conforming simple @acronym{HTML},
PostScript or @acronym{PDF} designed for human modification. Examples
of transparent image formats include @acronym{PNG}, @acronym{XCF} and
@acronym{JPG}. Opaque formats include proprietary formats that can be
read and edited only by proprietary word processors, @acronym{SGML} or
@acronym{XML} for which the @acronym{DTD} and/or processing tools are
not generally available, and the machine-generated @acronym{HTML},
PostScript or @acronym{PDF} produced by some word processors for
output purposes only.
 
The ``Title Page'' means, for a printed book, the title page itself,
plus such following pages as are needed to hold, legibly, the material
this License requires to appear in the title page. For works in
formats which do not have any title page as such, ``Title Page'' means
the text near the most prominent appearance of the work's title,
preceding the beginning of the body of the text.
 
The ``publisher'' means any person or entity that distributes copies
of the Document to the public.
 
A section ``Entitled XYZ'' means a named subunit of the Document whose
title either is precisely XYZ or contains XYZ in parentheses following
text that translates XYZ in another language. (Here XYZ stands for a
specific section name mentioned below, such as ``Acknowledgements'',
``Dedications'', ``Endorsements'', or ``History''.) To ``Preserve the Title''
of such a section when you modify the Document means that it remains a
section ``Entitled XYZ'' according to this definition.
 
The Document may include Warranty Disclaimers next to the notice which
states that this License applies to the Document. These Warranty
Disclaimers are considered to be included by reference in this
License, but only as regards disclaiming warranties: any other
implication that these Warranty Disclaimers may have is void and has
no effect on the meaning of this License.
 
@item
VERBATIM COPYING
 
You may copy and distribute the Document in any medium, either
commercially or noncommercially, provided that this License, the
copyright notices, and the license notice saying this License applies
to the Document are reproduced in all copies, and that you add no other
conditions whatsoever to those of this License. You may not use
technical measures to obstruct or control the reading or further
copying of the copies you make or distribute. However, you may accept
compensation in exchange for copies. If you distribute a large enough
number of copies you must also follow the conditions in section 3.
 
You may also lend copies, under the same conditions stated above, and
you may publicly display copies.
 
@item
COPYING IN QUANTITY
 
If you publish printed copies (or copies in media that commonly have
printed covers) of the Document, numbering more than 100, and the
Document's license notice requires Cover Texts, you must enclose the
copies in covers that carry, clearly and legibly, all these Cover
Texts: Front-Cover Texts on the front cover, and Back-Cover Texts on
the back cover. Both covers must also clearly and legibly identify
you as the publisher of these copies. The front cover must present
the full title with all words of the title equally prominent and
visible. You may add other material on the covers in addition.
Copying with changes limited to the covers, as long as they preserve
the title of the Document and satisfy these conditions, can be treated
as verbatim copying in other respects.
 
If the required texts for either cover are too voluminous to fit
legibly, you should put the first ones listed (as many as fit
reasonably) on the actual cover, and continue the rest onto adjacent
pages.
 
If you publish or distribute Opaque copies of the Document numbering
more than 100, you must either include a machine-readable Transparent
copy along with each Opaque copy, or state in or with each Opaque copy
a computer-network location from which the general network-using
public has access to download using public-standard network protocols
a complete Transparent copy of the Document, free of added material.
If you use the latter option, you must take reasonably prudent steps,
when you begin distribution of Opaque copies in quantity, to ensure
that this Transparent copy will remain thus accessible at the stated
location until at least one year after the last time you distribute an
Opaque copy (directly or through your agents or retailers) of that
edition to the public.
 
It is requested, but not required, that you contact the authors of the
Document well before redistributing any large number of copies, to give
them a chance to provide you with an updated version of the Document.
 
@item
MODIFICATIONS
 
You may copy and distribute a Modified Version of the Document under
the conditions of sections 2 and 3 above, provided that you release
the Modified Version under precisely this License, with the Modified
Version filling the role of the Document, thus licensing distribution
and modification of the Modified Version to whoever possesses a copy
of it. In addition, you must do these things in the Modified Version:
 
@enumerate A
@item
Use in the Title Page (and on the covers, if any) a title distinct
from that of the Document, and from those of previous versions
(which should, if there were any, be listed in the History section
of the Document). You may use the same title as a previous version
if the original publisher of that version gives permission.
 
@item
List on the Title Page, as authors, one or more persons or entities
responsible for authorship of the modifications in the Modified
Version, together with at least five of the principal authors of the
Document (all of its principal authors, if it has fewer than five),
unless they release you from this requirement.
 
@item
State on the Title page the name of the publisher of the
Modified Version, as the publisher.
 
@item
Preserve all the copyright notices of the Document.
 
@item
Add an appropriate copyright notice for your modifications
adjacent to the other copyright notices.
 
@item
Include, immediately after the copyright notices, a license notice
giving the public permission to use the Modified Version under the
terms of this License, in the form shown in the Addendum below.
 
@item
Preserve in that license notice the full lists of Invariant Sections
and required Cover Texts given in the Document's license notice.
 
@item
Include an unaltered copy of this License.
 
@item
Preserve the section Entitled ``History'', Preserve its Title, and add
to it an item stating at least the title, year, new authors, and
publisher of the Modified Version as given on the Title Page. If
there is no section Entitled ``History'' in the Document, create one
stating the title, year, authors, and publisher of the Document as
given on its Title Page, then add an item describing the Modified
Version as stated in the previous sentence.
 
@item
Preserve the network location, if any, given in the Document for
public access to a Transparent copy of the Document, and likewise
the network locations given in the Document for previous versions
it was based on. These may be placed in the ``History'' section.
You may omit a network location for a work that was published at
least four years before the Document itself, or if the original
publisher of the version it refers to gives permission.
 
@item
For any section Entitled ``Acknowledgements'' or ``Dedications'', Preserve
the Title of the section, and preserve in the section all the
substance and tone of each of the contributor acknowledgements and/or
dedications given therein.
 
@item
Preserve all the Invariant Sections of the Document,
unaltered in their text and in their titles. Section numbers
or the equivalent are not considered part of the section titles.
 
@item
Delete any section Entitled ``Endorsements''. Such a section
may not be included in the Modified Version.
 
@item
Do not retitle any existing section to be Entitled ``Endorsements'' or
to conflict in title with any Invariant Section.
 
@item
Preserve any Warranty Disclaimers.
@end enumerate
 
If the Modified Version includes new front-matter sections or
appendices that qualify as Secondary Sections and contain no material
copied from the Document, you may at your option designate some or all
of these sections as invariant. To do this, add their titles to the
list of Invariant Sections in the Modified Version's license notice.
These titles must be distinct from any other section titles.
 
You may add a section Entitled ``Endorsements'', provided it contains
nothing but endorsements of your Modified Version by various
parties---for example, statements of peer review or that the text has
been approved by an organization as the authoritative definition of a
standard.
 
You may add a passage of up to five words as a Front-Cover Text, and a
passage of up to 25 words as a Back-Cover Text, to the end of the list
of Cover Texts in the Modified Version. Only one passage of
Front-Cover Text and one of Back-Cover Text may be added by (or
through arrangements made by) any one entity. If the Document already
includes a cover text for the same cover, previously added by you or
by arrangement made by the same entity you are acting on behalf of,
you may not add another; but you may replace the old one, on explicit
permission from the previous publisher that added the old one.
 
The author(s) and publisher(s) of the Document do not by this License
give permission to use their names for publicity for or to assert or
imply endorsement of any Modified Version.
 
@item
COMBINING DOCUMENTS
 
You may combine the Document with other documents released under this
License, under the terms defined in section 4 above for modified
versions, provided that you include in the combination all of the
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The combined work need only contain one copy of this License, and
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Make the same adjustment to the section titles in the list of
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In the combination, you must combine any sections Entitled ``History''
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@item
COLLECTIONS OF DOCUMENTS
 
You may make a collection consisting of the Document and other documents
released under this License, and replace the individual copies of this
License in the various documents with a single copy that is included in
the collection, provided that you follow the rules of this License for
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You may extract a single document from such a collection, and distribute
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@item
AGGREGATION WITH INDEPENDENT WORKS
 
A compilation of the Document or its derivatives with other separate
and independent documents or works, in or on a volume of a storage or
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When the Document is included in an aggregate, this License does not
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If the Cover Text requirement of section 3 is applicable to these
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@item
TRANSLATION
 
Translation is considered a kind of modification, so you may
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Replacing Invariant Sections with translations requires special
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If a section in the Document is Entitled ``Acknowledgements'',
``Dedications'', or ``History'', the requirement (section 4) to Preserve
its Title (section 1) will typically require changing the actual
title.
 
@item
TERMINATION
 
You may not copy, modify, sublicense, or distribute the Document
except as expressly provided under this License. Any attempt
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will automatically terminate your rights under this License.
 
However, if you cease all violation of this License, then your license
from a particular copyright holder is reinstated (a) provisionally,
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Moreover, your license from a particular copyright holder is
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violation by some reasonable means, this is the first time you have
received notice of violation of this License (for any work) from that
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Termination of your rights under this section does not terminate the
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this License. If your rights have been terminated and not permanently
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not give you any rights to use it.
 
@item
FUTURE REVISIONS OF THIS LICENSE
 
The Free Software Foundation may publish new, revised versions
of the GNU Free Documentation License from time to time. Such new
versions will be similar in spirit to the present version, but may
differ in detail to address new problems or concerns. See
@uref{http://www.gnu.org/copyleft/}.
 
Each version of the License is given a distinguishing version number.
If the Document specifies that a particular numbered version of this
License ``or any later version'' applies to it, you have the option of
following the terms and conditions either of that specified version or
of any later version that has been published (not as a draft) by the
Free Software Foundation. If the Document does not specify a version
number of this License, you may choose any version ever published (not
as a draft) by the Free Software Foundation. If the Document
specifies that a proxy can decide which future versions of this
License can be used, that proxy's public statement of acceptance of a
version permanently authorizes you to choose that version for the
Document.
 
@item
RELICENSING
 
``Massive Multiauthor Collaboration Site'' (or ``MMC Site'') means any
World Wide Web server that publishes copyrightable works and also
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public wiki that anybody can edit is an example of such a server. A
``Massive Multiauthor Collaboration'' (or ``MMC'') contained in the
site means any set of copyrightable works thus published on the MMC
site.
 
``CC-BY-SA'' means the Creative Commons Attribution-Share Alike 3.0
license published by Creative Commons Corporation, a not-for-profit
corporation with a principal place of business in San Francisco,
California, as well as future copyleft versions of that license
published by that same organization.
 
``Incorporate'' means to publish or republish a Document, in whole or
in part, as part of another Document.
 
An MMC is ``eligible for relicensing'' if it is licensed under this
License, and if all works that were first published under this License
somewhere other than this MMC, and subsequently incorporated in whole
or in part into the MMC, (1) had no cover texts or invariant sections,
and (2) were thus incorporated prior to November 1, 2008.
 
The operator of an MMC Site may republish an MMC contained in the site
under CC-BY-SA on the same site at any time before August 1, 2009,
provided the MMC is eligible for relicensing.
 
@end enumerate
 
@page
@heading ADDENDUM: How to use this License for your documents
 
To use this License in a document you have written, include a copy of
the License in the document and put the following copyright and
license notices just after the title page:
 
@smallexample
@group
Copyright (C) @var{year} @var{your name}.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
or any later version published by the Free Software Foundation;
with no Invariant Sections, no Front-Cover Texts, and no Back-Cover
Texts. A copy of the license is included in the section entitled ``GNU
Free Documentation License''.
@end group
@end smallexample
 
If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts,
replace the ``with@dots{}Texts.'' line with this:
 
@smallexample
@group
with the Invariant Sections being @var{list their titles}, with
the Front-Cover Texts being @var{list}, and with the Back-Cover Texts
being @var{list}.
@end group
@end smallexample
 
If you have Invariant Sections without Cover Texts, or some other
combination of the three, merge those two alternatives to suit the
situation.
 
If your document contains nontrivial examples of program code, we
recommend releasing these examples in parallel under your choice of
free software license, such as the GNU General Public License,
to permit their use in free software.
 
@c Local Variables:
@c ispell-local-pdict: "ispell-dict"
@c End:
 
/binutils/gas/doc/h8.texi
0,0 → 1,26
@clear ALL-ARCH
@clear GENERIC
@clear INTERNALS
@clear MULTI-OBJ
@clear AOUT
@clear BOUT
@set COFF
@clear ELF
@set Renesas-all
@set H8/300
@set H8/500
@set SH
@clear DIFF-TBL-KLUGE
@set IEEEFLOAT
@clear W32
@set W16
@set SPECIAL-SYMS
@set AS as
@set GCC gcc
@set LD ld
@set TARGET H8/300 and H8/500
@set TARGET H8/300, H8/500, and Renesas SH
@set OBJ-NAME COFF
@c
@clear have-stabs
@set abnormal-separator
/binutils/gas/doc/internals.texi
0,0 → 1,1990
\input texinfo
@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
@c Free Software Foundation, Inc.
@setfilename internals.info
@node Top
@top Assembler Internals
@raisesections
@cindex internals
 
This chapter describes the internals of the assembler. It is incomplete, but
it may help a bit.
 
This chapter is not updated regularly, and it may be out of date.
 
@menu
* Data types:: Data types
* GAS processing:: What GAS does when it runs
* Porting GAS:: Porting GAS
* Relaxation:: Relaxation
* Broken words:: Broken words
* Internal functions:: Internal functions
* Test suite:: Test suite
@end menu
 
@node Data types
@section Data types
@cindex internals, data types
 
This section describes some fundamental GAS data types.
 
@menu
* Symbols:: The symbolS structure
* Expressions:: The expressionS structure
* Fixups:: The fixS structure
* Frags:: The fragS structure
@end menu
 
@node Symbols
@subsection Symbols
@cindex internals, symbols
@cindex symbols, internal
@cindex symbolS structure
 
The definition for the symbol structure, @code{symbolS}, is located in
@file{struc-symbol.h}.
 
In general, the fields of this structure may not be referred to directly.
Instead, you must use one of the accessor functions defined in @file{symbol.h}.
These accessor functions should work for any GAS version.
 
Symbol structures contain the following fields:
 
@table @code
@item sy_value
This is an @code{expressionS} that describes the value of the symbol. It might
refer to one or more other symbols; if so, its true value may not be known
until @code{resolve_symbol_value} is called with @var{finalize_syms} non-zero
in @code{write_object_file}.
 
The expression is often simply a constant. Before @code{resolve_symbol_value}
is called with @var{finalize_syms} set, the value is the offset from the frag
(@pxref{Frags}). Afterward, the frag address has been added in.
 
@item sy_resolved
This field is non-zero if the symbol's value has been completely resolved. It
is used during the final pass over the symbol table.
 
@item sy_resolving
This field is used to detect loops while resolving the symbol's value.
 
@item sy_used_in_reloc
This field is non-zero if the symbol is used by a relocation entry. If a local
symbol is used in a relocation entry, it must be possible to redirect those
relocations to other symbols, or this symbol cannot be removed from the final
symbol list.
 
@item sy_next
@itemx sy_previous
These pointers to other @code{symbolS} structures describe a doubly
linked list. These fields should be accessed with
the @code{symbol_next} and @code{symbol_previous} macros.
 
@item sy_frag
This points to the frag (@pxref{Frags}) that this symbol is attached to.
 
@item sy_used
Whether the symbol is used as an operand or in an expression. Note: Not all of
the backends keep this information accurate; backends which use this bit are
responsible for setting it when a symbol is used in backend routines.
 
@item sy_mri_common
Whether the symbol is an MRI common symbol created by the @code{COMMON}
pseudo-op when assembling in MRI mode.
 
@item sy_volatile
Whether the symbol can be re-defined.
 
@item sy_forward_ref
Whether the symbol's value must only be evaluated upon use.
 
@item sy_weakrefr
Whether the symbol is a @code{weakref} alias to another symbol.
 
@item sy_weakrefd
Whether the symbol is or was referenced by one or more @code{weakref} aliases,
and has not had any direct references.
 
@item bsym
This points to the BFD @code{asymbol} that
will be used in writing the object file.
 
@item sy_obj
This format-specific data is of type @code{OBJ_SYMFIELD_TYPE}. If no macro by
that name is defined in @file{obj-format.h}, this field is not defined.
 
@item sy_tc
This processor-specific data is of type @code{TC_SYMFIELD_TYPE}. If no macro
by that name is defined in @file{targ-cpu.h}, this field is not defined.
 
@end table
 
Here is a description of the accessor functions. These should be used rather
than referring to the fields of @code{symbolS} directly.
 
@table @code
@item S_SET_VALUE
@cindex S_SET_VALUE
Set the symbol's value.
 
@item S_GET_VALUE
@cindex S_GET_VALUE
Get the symbol's value. This will cause @code{resolve_symbol_value} to be
called if necessary.
 
@item S_SET_SEGMENT
@cindex S_SET_SEGMENT
Set the section of the symbol.
 
@item S_GET_SEGMENT
@cindex S_GET_SEGMENT
Get the symbol's section.
 
@item S_GET_NAME
@cindex S_GET_NAME
Get the name of the symbol.
 
@item S_SET_NAME
@cindex S_SET_NAME
Set the name of the symbol.
 
@item S_IS_EXTERNAL
@cindex S_IS_EXTERNAL
Return non-zero if the symbol is externally visible.
 
@item S_IS_EXTERN
@cindex S_IS_EXTERN
A synonym for @code{S_IS_EXTERNAL}. Don't use it.
 
@item S_IS_WEAK
@cindex S_IS_WEAK
Return non-zero if the symbol is weak, or if it is a @code{weakref} alias or
symbol that has not been strongly referenced.
 
@item S_IS_WEAKREFR
@cindex S_IS_WEAKREFR
Return non-zero if the symbol is a @code{weakref} alias.
 
@item S_IS_WEAKREFD
@cindex S_IS_WEAKREFD
Return non-zero if the symbol was aliased by a @code{weakref} alias and has not
had any strong references.
 
@item S_IS_VOLATILE
@cindex S_IS_VOLATILE
Return non-zero if the symbol may be re-defined. Such symbols get created by
the @code{=} operator, @code{equ}, or @code{set}.
 
@item S_IS_FORWARD_REF
@cindex S_IS_FORWARD_REF
Return non-zero if the symbol is a forward reference, that is its value must
only be determined upon use.
 
@item S_IS_COMMON
@cindex S_IS_COMMON
Return non-zero if this is a common symbol. Common symbols are sometimes
represented as undefined symbols with a value, in which case this function will
not be reliable.
 
@item S_IS_DEFINED
@cindex S_IS_DEFINED
Return non-zero if this symbol is defined. This function is not reliable when
called on a common symbol.
 
@item S_IS_DEBUG
@cindex S_IS_DEBUG
Return non-zero if this is a debugging symbol.
 
@item S_IS_LOCAL
@cindex S_IS_LOCAL
Return non-zero if this is a local assembler symbol which should not be
included in the final symbol table. Note that this is not the opposite of
@code{S_IS_EXTERNAL}. The @samp{-L} assembler option affects the return value
of this function.
 
@item S_SET_EXTERNAL
@cindex S_SET_EXTERNAL
Mark the symbol as externally visible.
 
@item S_CLEAR_EXTERNAL
@cindex S_CLEAR_EXTERNAL
Mark the symbol as not externally visible.
 
@item S_SET_WEAK
@cindex S_SET_WEAK
Mark the symbol as weak.
 
@item S_SET_WEAKREFR
@cindex S_SET_WEAKREFR
Mark the symbol as the referrer in a @code{weakref} directive. The symbol it
aliases must have been set to the value expression before this point. If the
alias has already been used, the symbol is marked as used too.
 
@item S_CLEAR_WEAKREFR
@cindex S_CLEAR_WEAKREFR
Clear the @code{weakref} alias status of a symbol. This is implicitly called
whenever a symbol is defined or set to a new expression.
 
@item S_SET_WEAKREFD
@cindex S_SET_WEAKREFD
Mark the symbol as the referred symbol in a @code{weakref} directive.
Implicitly marks the symbol as weak, but see below. It should only be called
if the referenced symbol has just been added to the symbol table.
 
@item S_SET_WEAKREFD
@cindex S_SET_WEAKREFD
Clear the @code{weakref} aliased status of a symbol. This is implicitly called
whenever the symbol is looked up, as part of a direct reference or a
definition, but not as part of a @code{weakref} directive.
 
@item S_SET_VOLATILE
@cindex S_SET_VOLATILE
Indicate that the symbol may be re-defined.
 
@item S_CLEAR_VOLATILE
@cindex S_CLEAR_VOLATILE
Indicate that the symbol may no longer be re-defined.
 
@item S_SET_FORWARD_REF
@cindex S_SET_FORWARD_REF
Indicate that the symbol is a forward reference, that is its value must only
be determined upon use.
 
@item S_GET_TYPE
@itemx S_GET_DESC
@itemx S_GET_OTHER
@cindex S_GET_TYPE
@cindex S_GET_DESC
@cindex S_GET_OTHER
Get the @code{type}, @code{desc}, and @code{other} fields of the symbol. These
are only defined for object file formats for which they make sense (primarily
a.out).
 
@item S_SET_TYPE
@itemx S_SET_DESC
@itemx S_SET_OTHER
@cindex S_SET_TYPE
@cindex S_SET_DESC
@cindex S_SET_OTHER
Set the @code{type}, @code{desc}, and @code{other} fields of the symbol. These
are only defined for object file formats for which they make sense (primarily
a.out).
 
@item S_GET_SIZE
@cindex S_GET_SIZE
Get the size of a symbol. This is only defined for object file formats for
which it makes sense (primarily ELF).
 
@item S_SET_SIZE
@cindex S_SET_SIZE
Set the size of a symbol. This is only defined for object file formats for
which it makes sense (primarily ELF).
 
@item symbol_get_value_expression
@cindex symbol_get_value_expression
Get a pointer to an @code{expressionS} structure which represents the value of
the symbol as an expression.
 
@item symbol_set_value_expression
@cindex symbol_set_value_expression
Set the value of a symbol to an expression.
 
@item symbol_set_frag
@cindex symbol_set_frag
Set the frag where a symbol is defined.
 
@item symbol_get_frag
@cindex symbol_get_frag
Get the frag where a symbol is defined.
 
@item symbol_mark_used
@cindex symbol_mark_used
Mark a symbol as having been used in an expression.
 
@item symbol_clear_used
@cindex symbol_clear_used
Clear the mark indicating that a symbol was used in an expression.
 
@item symbol_used_p
@cindex symbol_used_p
Return whether a symbol was used in an expression.
 
@item symbol_mark_used_in_reloc
@cindex symbol_mark_used_in_reloc
Mark a symbol as having been used by a relocation.
 
@item symbol_clear_used_in_reloc
@cindex symbol_clear_used_in_reloc
Clear the mark indicating that a symbol was used in a relocation.
 
@item symbol_used_in_reloc_p
@cindex symbol_used_in_reloc_p
Return whether a symbol was used in a relocation.
 
@item symbol_mark_mri_common
@cindex symbol_mark_mri_common
Mark a symbol as an MRI common symbol.
 
@item symbol_clear_mri_common
@cindex symbol_clear_mri_common
Clear the mark indicating that a symbol is an MRI common symbol.
 
@item symbol_mri_common_p
@cindex symbol_mri_common_p
Return whether a symbol is an MRI common symbol.
 
@item symbol_mark_written
@cindex symbol_mark_written
Mark a symbol as having been written.
 
@item symbol_clear_written
@cindex symbol_clear_written
Clear the mark indicating that a symbol was written.
 
@item symbol_written_p
@cindex symbol_written_p
Return whether a symbol was written.
 
@item symbol_mark_resolved
@cindex symbol_mark_resolved
Mark a symbol as having been resolved.
 
@item symbol_resolved_p
@cindex symbol_resolved_p
Return whether a symbol has been resolved.
 
@item symbol_section_p
@cindex symbol_section_p
Return whether a symbol is a section symbol.
 
@item symbol_equated_p
@cindex symbol_equated_p
Return whether a symbol is equated to another symbol.
 
@item symbol_constant_p
@cindex symbol_constant_p
Return whether a symbol has a constant value, including being an offset within
some frag.
 
@item symbol_get_bfdsym
@cindex symbol_get_bfdsym
Return the BFD symbol associated with a symbol.
 
@item symbol_set_bfdsym
@cindex symbol_set_bfdsym
Set the BFD symbol associated with a symbol.
 
@item symbol_get_obj
@cindex symbol_get_obj
Return a pointer to the @code{OBJ_SYMFIELD_TYPE} field of a symbol.
 
@item symbol_set_obj
@cindex symbol_set_obj
Set the @code{OBJ_SYMFIELD_TYPE} field of a symbol.
 
@item symbol_get_tc
@cindex symbol_get_tc
Return a pointer to the @code{TC_SYMFIELD_TYPE} field of a symbol.
 
@item symbol_set_tc
@cindex symbol_set_tc
Set the @code{TC_SYMFIELD_TYPE} field of a symbol.
 
@end table
 
GAS attempts to store local
symbols--symbols which will not be written to the output file--using a
different structure, @code{struct local_symbol}. This structure can only
represent symbols whose value is an offset within a frag.
 
Code outside of the symbol handler will always deal with @code{symbolS}
structures and use the accessor functions. The accessor functions correctly
deal with local symbols. @code{struct local_symbol} is much smaller than
@code{symbolS} (which also automatically creates a bfd @code{asymbol}
structure), so this saves space when assembling large files.
 
The first field of @code{symbolS} is @code{bsym}, the pointer to the BFD
symbol. The first field of @code{struct local_symbol} is a pointer which is
always set to NULL. This is how the symbol accessor functions can distinguish
local symbols from ordinary symbols. The symbol accessor functions
automatically convert a local symbol into an ordinary symbol when necessary.
 
@node Expressions
@subsection Expressions
@cindex internals, expressions
@cindex expressions, internal
@cindex expressionS structure
 
Expressions are stored in an @code{expressionS} structure. The structure is
defined in @file{expr.h}.
 
@cindex expression
The macro @code{expression} will create an @code{expressionS} structure based
on the text found at the global variable @code{input_line_pointer}.
 
@cindex make_expr_symbol
@cindex expr_symbol_where
A single @code{expressionS} structure can represent a single operation.
Complex expressions are formed by creating @dfn{expression symbols} and
combining them in @code{expressionS} structures. An expression symbol is
created by calling @code{make_expr_symbol}. An expression symbol should
naturally never appear in a symbol table, and the implementation of
@code{S_IS_LOCAL} (@pxref{Symbols}) reflects that. The function
@code{expr_symbol_where} returns non-zero if a symbol is an expression symbol,
and also returns the file and line for the expression which caused it to be
created.
 
The @code{expressionS} structure has two symbol fields, a number field, an
operator field, and a field indicating whether the number is unsigned.
 
The operator field is of type @code{operatorT}, and describes how to interpret
the other fields; see the definition in @file{expr.h} for the possibilities.
 
An @code{operatorT} value of @code{O_big} indicates either a floating point
number, stored in the global variable @code{generic_floating_point_number}, or
an integer too large to store in an @code{offsetT} type, stored in the global
array @code{generic_bignum}. This rather inflexible approach makes it
impossible to use floating point numbers or large expressions in complex
expressions.
 
@node Fixups
@subsection Fixups
@cindex internals, fixups
@cindex fixups
@cindex fixS structure
 
A @dfn{fixup} is basically anything which can not be resolved in the first
pass. Sometimes a fixup can be resolved by the end of the assembly; if not,
the fixup becomes a relocation entry in the object file.
 
@cindex fix_new
@cindex fix_new_exp
A fixup is created by a call to @code{fix_new} or @code{fix_new_exp}. Both
take a frag (@pxref{Frags}), a position within the frag, a size, an indication
of whether the fixup is PC relative, and a type.
The type is nominally a @code{bfd_reloc_code_real_type}, but several
targets use other type codes to represent fixups that can not be described as
relocations.
 
The @code{fixS} structure has a number of fields, several of which are obsolete
or are only used by a particular target. The important fields are:
 
@table @code
@item fx_frag
The frag (@pxref{Frags}) this fixup is in.
 
@item fx_where
The location within the frag where the fixup occurs.
 
@item fx_addsy
The symbol this fixup is against. Typically, the value of this symbol is added
into the object contents. This may be NULL.
 
@item fx_subsy
The value of this symbol is subtracted from the object contents. This is
normally NULL.
 
@item fx_offset
A number which is added into the fixup.
 
@item fx_addnumber
Some CPU backends use this field to convey information between
@code{md_apply_fix} and @code{tc_gen_reloc}. The machine independent code does
not use it.
 
@item fx_next
The next fixup in the section.
 
@item fx_r_type
The type of the fixup.
 
@item fx_size
The size of the fixup. This is mostly used for error checking.
 
@item fx_pcrel
Whether the fixup is PC relative.
 
@item fx_done
Non-zero if the fixup has been applied, and no relocation entry needs to be
generated.
 
@item fx_file
@itemx fx_line
The file and line where the fixup was created.
 
@item tc_fix_data
This has the type @code{TC_FIX_TYPE}, and is only defined if the target defines
that macro.
@end table
 
@node Frags
@subsection Frags
@cindex internals, frags
@cindex frags
@cindex fragS structure.
 
The @code{fragS} structure is defined in @file{as.h}. Each frag represents a
portion of the final object file. As GAS reads the source file, it creates
frags to hold the data that it reads. At the end of the assembly the frags and
fixups are processed to produce the final contents.
 
@table @code
@item fr_address
The address of the frag. This is not set until the assembler rescans the list
of all frags after the entire input file is parsed. The function
@code{relax_segment} fills in this field.
 
@item fr_next
Pointer to the next frag in this (sub)section.
 
@item fr_fix
Fixed number of characters we know we're going to emit to the output file. May
be zero.
 
@item fr_var
Variable number of characters we may output, after the initial @code{fr_fix}
characters. May be zero.
 
@item fr_offset
The interpretation of this field is controlled by @code{fr_type}. Generally,
if @code{fr_var} is non-zero, this is a repeat count: the @code{fr_var}
characters are output @code{fr_offset} times.
 
@item line
Holds line number info when an assembler listing was requested.
 
@item fr_type
Relaxation state. This field indicates the interpretation of @code{fr_offset},
@code{fr_symbol} and the variable-length tail of the frag, as well as the
treatment it gets in various phases of processing. It does not affect the
initial @code{fr_fix} characters; they are always supposed to be output
verbatim (fixups aside). See below for specific values this field can have.
 
@item fr_subtype
Relaxation substate. If the macro @code{md_relax_frag} isn't defined, this is
assumed to be an index into @code{TC_GENERIC_RELAX_TABLE} for the generic
relaxation code to process (@pxref{Relaxation}). If @code{md_relax_frag} is
defined, this field is available for any use by the CPU-specific code.
 
@item fr_symbol
This normally indicates the symbol to use when relaxing the frag according to
@code{fr_type}.
 
@item fr_opcode
Points to the lowest-addressed byte of the opcode, for use in relaxation.
 
@item tc_frag_data
Target specific fragment data of type TC_FRAG_TYPE.
Only present if @code{TC_FRAG_TYPE} is defined.
 
@item fr_file
@itemx fr_line
The file and line where this frag was last modified.
 
@item fr_literal
Declared as a one-character array, this last field grows arbitrarily large to
hold the actual contents of the frag.
@end table
 
These are the possible relaxation states, provided in the enumeration type
@code{relax_stateT}, and the interpretations they represent for the other
fields:
 
@table @code
@item rs_align
@itemx rs_align_code
The start of the following frag should be aligned on some boundary. In this
frag, @code{fr_offset} is the logarithm (base 2) of the alignment in bytes.
(For example, if alignment on an 8-byte boundary were desired, @code{fr_offset}
would have a value of 3.) The variable characters indicate the fill pattern to
be used. The @code{fr_subtype} field holds the maximum number of bytes to skip
when doing this alignment. If more bytes are needed, the alignment is not
done. An @code{fr_subtype} value of 0 means no maximum, which is the normal
case. Target backends can use @code{rs_align_code} to handle certain types of
alignment differently.
 
@item rs_broken_word
This indicates that ``broken word'' processing should be done (@pxref{Broken
words}). If broken word processing is not necessary on the target machine,
this enumerator value will not be defined.
 
@item rs_cfa
This state is used to implement exception frame optimizations. The
@code{fr_symbol} is an expression symbol for the subtraction which may be
relaxed. The @code{fr_opcode} field holds the frag for the preceding command
byte. The @code{fr_offset} field holds the offset within that frag. The
@code{fr_subtype} field is used during relaxation to hold the current size of
the frag.
 
@item rs_fill
The variable characters are to be repeated @code{fr_offset} times. If
@code{fr_offset} is 0, this frag has a length of @code{fr_fix}. Most frags
have this type.
 
@item rs_leb128
This state is used to implement the DWARF ``little endian base 128''
variable length number format. The @code{fr_symbol} is always an expression
symbol, as constant expressions are emitted directly. The @code{fr_offset}
field is used during relaxation to hold the previous size of the number so
that we can determine if the fragment changed size.
 
@item rs_machine_dependent
Displacement relaxation is to be done on this frag. The target is indicated by
@code{fr_symbol} and @code{fr_offset}, and @code{fr_subtype} indicates the
particular machine-specific addressing mode desired. @xref{Relaxation}.
 
@item rs_org
The start of the following frag should be pushed back to some specific offset
within the section. (Some assemblers use the value as an absolute address; GAS
does not handle final absolute addresses, but rather requires that the linker
set them.) The offset is given by @code{fr_symbol} and @code{fr_offset}; one
character from the variable-length tail is used as the fill character.
@end table
 
@cindex frchainS structure
A chain of frags is built up for each subsection. The data structure
describing a chain is called a @code{frchainS}, and contains the following
fields:
 
@table @code
@item frch_root
Points to the first frag in the chain. May be NULL if there are no frags in
this chain.
@item frch_last
Points to the last frag in the chain, or NULL if there are none.
@item frch_next
Next in the list of @code{frchainS} structures.
@item frch_seg
Indicates the section this frag chain belongs to.
@item frch_subseg
Subsection (subsegment) number of this frag chain.
@item fix_root, fix_tail
Point to first and last @code{fixS} structures associated with this subsection.
@item frch_obstack
Not currently used. Intended to be used for frag allocation for this
subsection. This should reduce frag generation caused by switching sections.
@item frch_frag_now
The current frag for this subsegment.
@end table
 
A @code{frchainS} corresponds to a subsection; each section has a list of
@code{frchainS} records associated with it. In most cases, only one subsection
of each section is used, so the list will only be one element long, but any
processing of frag chains should be prepared to deal with multiple chains per
section.
 
After the input files have been completely processed, and no more frags are to
be generated, the frag chains are joined into one per section for further
processing. After this point, it is safe to operate on one chain per section.
 
The assembler always has a current frag, named @code{frag_now}. More space is
allocated for the current frag using the @code{frag_more} function; this
returns a pointer to the amount of requested space. The function
@code{frag_room} says by how much the current frag can be extended.
Relaxing is done using variant frags allocated by @code{frag_var}
or @code{frag_variant} (@pxref{Relaxation}).
 
@node GAS processing
@section What GAS does when it runs
@cindex internals, overview
 
This is a quick look at what an assembler run looks like.
 
@itemize @bullet
@item
The assembler initializes itself by calling various init routines.
 
@item
For each source file, the @code{read_a_source_file} function reads in the file
and parses it. The global variable @code{input_line_pointer} points to the
current text; it is guaranteed to be correct up to the end of the line, but not
farther.
 
@item
For each line, the assembler passes labels to the @code{colon} function, and
isolates the first word. If it looks like a pseudo-op, the word is looked up
in the pseudo-op hash table @code{po_hash} and dispatched to a pseudo-op
routine. Otherwise, the target dependent @code{md_assemble} routine is called
to parse the instruction.
 
@item
When pseudo-ops or instructions output data, they add it to a frag, calling
@code{frag_more} to get space to store it in.
 
@item
Pseudo-ops and instructions can also output fixups created by @code{fix_new} or
@code{fix_new_exp}.
 
@item
For certain targets, instructions can create variant frags which are used to
store relaxation information (@pxref{Relaxation}).
 
@item
When the input file is finished, the @code{write_object_file} routine is
called. It assigns addresses to all the frags (@code{relax_segment}), resolves
all the fixups (@code{fixup_segment}), resolves all the symbol values (using
@code{resolve_symbol_value}), and finally writes out the file.
@end itemize
 
@node Porting GAS
@section Porting GAS
@cindex porting
 
Each GAS target specifies two main things: the CPU file and the object format
file. Two main switches in the @file{configure.in} file handle this. The
first switches on CPU type to set the shell variable @code{cpu_type}. The
second switches on the entire target to set the shell variable @code{fmt}.
 
The configure script uses the value of @code{cpu_type} to select two files in
the @file{config} directory: @file{tc-@var{CPU}.c} and @file{tc-@var{CPU}.h}.
The configuration process will create a file named @file{targ-cpu.h} in the
build directory which includes @file{tc-@var{CPU}.h}.
 
The configure script also uses the value of @code{fmt} to select two files:
@file{obj-@var{fmt}.c} and @file{obj-@var{fmt}.h}. The configuration process
will create a file named @file{obj-format.h} in the build directory which
includes @file{obj-@var{fmt}.h}.
 
You can also set the emulation in the configure script by setting the @code{em}
variable. Normally the default value of @samp{generic} is fine. The
configuration process will create a file named @file{targ-env.h} in the build
directory which includes @file{te-@var{em}.h}.
 
There is a special case for COFF. For historical reason, the GNU COFF
assembler doesn't follow the documented behavior on certain debug symbols for
the compatibility with other COFF assemblers. A port can define
@code{STRICTCOFF} in the configure script to make the GNU COFF assembler
to follow the documented behavior.
 
Porting GAS to a new CPU requires writing the @file{tc-@var{CPU}} files.
Porting GAS to a new object file format requires writing the
@file{obj-@var{fmt}} files. There is sometimes some interaction between these
two files, but it is normally minimal.
 
The best approach is, of course, to copy existing files. The documentation
below assumes that you are looking at existing files to see usage details.
 
These interfaces have grown over time, and have never been carefully thought
out or designed. Nothing about the interfaces described here is cast in stone.
It is possible that they will change from one version of the assembler to the
next. Also, new macros are added all the time as they are needed.
 
@menu
* CPU backend:: Writing a CPU backend
* Object format backend:: Writing an object format backend
* Emulations:: Writing emulation files
@end menu
 
@node CPU backend
@subsection Writing a CPU backend
@cindex CPU backend
@cindex @file{tc-@var{CPU}}
 
The CPU backend files are the heart of the assembler. They are the only parts
of the assembler which actually know anything about the instruction set of the
processor.
 
You must define a reasonably small list of macros and functions in the CPU
backend files. You may define a large number of additional macros in the CPU
backend files, not all of which are documented here. You must, of course,
define macros in the @file{.h} file, which is included by every assembler
source file. You may define the functions as macros in the @file{.h} file, or
as functions in the @file{.c} file.
 
@table @code
@item TC_@var{CPU}
@cindex TC_@var{CPU}
By convention, you should define this macro in the @file{.h} file. For
example, @file{tc-m68k.h} defines @code{TC_M68K}. You might have to use this
if it is necessary to add CPU specific code to the object format file.
 
@item TARGET_FORMAT
This macro is the BFD target name to use when creating the output file. This
will normally depend upon the @code{OBJ_@var{FMT}} macro.
 
@item TARGET_ARCH
This macro is the BFD architecture to pass to @code{bfd_set_arch_mach}.
 
@item TARGET_MACH
This macro is the BFD machine number to pass to @code{bfd_set_arch_mach}. If
it is not defined, GAS will use 0.
 
@item TARGET_BYTES_BIG_ENDIAN
You should define this macro to be non-zero if the target is big endian, and
zero if the target is little endian.
 
@item md_shortopts
@itemx md_longopts
@itemx md_longopts_size
@itemx md_parse_option
@itemx md_show_usage
@itemx md_after_parse_args
@cindex md_shortopts
@cindex md_longopts
@cindex md_longopts_size
@cindex md_parse_option
@cindex md_show_usage
@cindex md_after_parse_args
GAS uses these variables and functions during option processing.
@code{md_shortopts} is a @code{const char *} which GAS adds to the machine
independent string passed to @code{getopt}. @code{md_longopts} is a
@code{struct option []} which GAS adds to the machine independent long options
passed to @code{getopt}; you may use @code{OPTION_MD_BASE}, defined in
@file{as.h}, as the start of a set of long option indices, if necessary.
@code{md_longopts_size} is a @code{size_t} holding the size @code{md_longopts}.
 
GAS will call @code{md_parse_option} whenever @code{getopt} returns an
unrecognized code, presumably indicating a special code value which appears in
@code{md_longopts}. This function should return non-zero if it handled the
option and zero otherwise. There is no need to print a message about an option
not being recognized. This will be handled by the generic code.
 
GAS will call @code{md_show_usage} when a usage message is printed; it should
print a description of the machine specific options. @code{md_after_pase_args},
if defined, is called after all options are processed, to let the backend
override settings done by the generic option parsing.
 
@item md_begin
@cindex md_begin
GAS will call this function at the start of the assembly, after the command
line arguments have been parsed and all the machine independent initializations
have been completed.
 
@item md_cleanup
@cindex md_cleanup
If you define this macro, GAS will call it at the end of each input file.
 
@item md_assemble
@cindex md_assemble
GAS will call this function for each input line which does not contain a
pseudo-op. The argument is a null terminated string. The function should
assemble the string as an instruction with operands. Normally
@code{md_assemble} will do this by calling @code{frag_more} and writing out
some bytes (@pxref{Frags}). @code{md_assemble} will call @code{fix_new} to
create fixups as needed (@pxref{Fixups}). Targets which need to do special
purpose relaxation will call @code{frag_var}.
 
@item md_pseudo_table
@cindex md_pseudo_table
This is a const array of type @code{pseudo_typeS}. It is a mapping from
pseudo-op names to functions. You should use this table to implement
pseudo-ops which are specific to the CPU.
 
@item tc_conditional_pseudoop
@cindex tc_conditional_pseudoop
If this macro is defined, GAS will call it with a @code{pseudo_typeS} argument.
It should return non-zero if the pseudo-op is a conditional which controls
whether code is assembled, such as @samp{.if}. GAS knows about the normal
conditional pseudo-ops, and you should normally not have to define this macro.
 
@item comment_chars
@cindex comment_chars
This is a null terminated @code{const char} array of characters which start a
comment.
 
@item tc_comment_chars
@cindex tc_comment_chars
If this macro is defined, GAS will use it instead of @code{comment_chars}.
 
@item tc_symbol_chars
@cindex tc_symbol_chars
If this macro is defined, it is a pointer to a null terminated list of
characters which may appear in an operand. GAS already assumes that all
alphanumeric characters, and @samp{$}, @samp{.}, and @samp{_} may appear in an
operand (see @samp{symbol_chars} in @file{app.c}). This macro may be defined
to treat additional characters as appearing in an operand. This affects the
way in which GAS removes whitespace before passing the string to
@samp{md_assemble}.
 
@item line_comment_chars
@cindex line_comment_chars
This is a null terminated @code{const char} array of characters which start a
comment when they appear at the start of a line.
 
@item line_separator_chars
@cindex line_separator_chars
This is a null terminated @code{const char} array of characters which separate
lines (null and newline are such characters by default, and need not be
listed in this array). Note that line_separator_chars do not separate lines
if found in a comment, such as after a character in line_comment_chars or
comment_chars.
 
@item EXP_CHARS
@cindex EXP_CHARS
This is a null terminated @code{const char} array of characters which may be
used as the exponent character in a floating point number. This is normally
@code{"eE"}.
 
@item FLT_CHARS
@cindex FLT_CHARS
This is a null terminated @code{const char} array of characters which may be
used to indicate a floating point constant. A zero followed by one of these
characters is assumed to be followed by a floating point number; thus they
operate the way that @code{0x} is used to indicate a hexadecimal constant.
Usually this includes @samp{r} and @samp{f}.
 
@item LEX_AT
@cindex LEX_AT
You may define this macro to the lexical type of the @kbd{@@} character. The
default is zero.
 
Lexical types are a combination of @code{LEX_NAME} and @code{LEX_BEGIN_NAME},
both defined in @file{read.h}. @code{LEX_NAME} indicates that the character
may appear in a name. @code{LEX_BEGIN_NAME} indicates that the character may
appear at the beginning of a name.
 
@item LEX_BR
@cindex LEX_BR
You may define this macro to the lexical type of the brace characters @kbd{@{},
@kbd{@}}, @kbd{[}, and @kbd{]}. The default value is zero.
 
@item LEX_PCT
@cindex LEX_PCT
You may define this macro to the lexical type of the @kbd{%} character. The
default value is zero.
 
@item LEX_QM
@cindex LEX_QM
You may define this macro to the lexical type of the @kbd{?} character. The
default value it zero.
 
@item LEX_DOLLAR
@cindex LEX_DOLLAR
You may define this macro to the lexical type of the @kbd{$} character. The
default value is @code{LEX_NAME | LEX_BEGIN_NAME}.
 
@item NUMBERS_WITH_SUFFIX
@cindex NUMBERS_WITH_SUFFIX
When this macro is defined to be non-zero, the parser allows the radix of a
constant to be indicated with a suffix. Valid suffixes are binary (B),
octal (Q), and hexadecimal (H). Case is not significant.
 
@item SINGLE_QUOTE_STRINGS
@cindex SINGLE_QUOTE_STRINGS
If you define this macro, GAS will treat single quotes as string delimiters.
Normally only double quotes are accepted as string delimiters.
 
@item NO_STRING_ESCAPES
@cindex NO_STRING_ESCAPES
If you define this macro, GAS will not permit escape sequences in a string.
 
@item ONLY_STANDARD_ESCAPES
@cindex ONLY_STANDARD_ESCAPES
If you define this macro, GAS will warn about the use of nonstandard escape
sequences in a string.
 
@item md_start_line_hook
@cindex md_start_line_hook
If you define this macro, GAS will call it at the start of each line.
 
@item LABELS_WITHOUT_COLONS
@cindex LABELS_WITHOUT_COLONS
If you define this macro, GAS will assume that any text at the start of a line
is a label, even if it does not have a colon.
 
@item TC_START_LABEL
@itemx TC_START_LABEL_WITHOUT_COLON
@cindex TC_START_LABEL
You may define this macro to control what GAS considers to be a label. The
default definition is to accept any name followed by a colon character.
 
@item TC_START_LABEL_WITHOUT_COLON
@cindex TC_START_LABEL_WITHOUT_COLON
Same as TC_START_LABEL, but should be used instead of TC_START_LABEL when
LABELS_WITHOUT_COLONS is defined.
 
@item TC_FAKE_LABEL
@cindex TC_FAKE_LABEL
You may define this macro to control what GAS considers to be a fake
label. The default fake label is FAKE_LABEL_NAME.
 
@item NO_PSEUDO_DOT
@cindex NO_PSEUDO_DOT
If you define this macro, GAS will not require pseudo-ops to start with a
@kbd{.} character.
 
@item TC_EQUAL_IN_INSN
@cindex TC_EQUAL_IN_INSN
If you define this macro, it should return nonzero if the instruction is
permitted to contain an @kbd{=} character. GAS will call it with two
arguments, the character before the @kbd{=} character, and the value of
the string preceding the equal sign. GAS uses this macro to decide if a
@kbd{=} is an assignment or an instruction.
 
@item TC_EOL_IN_INSN
@cindex TC_EOL_IN_INSN
If you define this macro, it should return nonzero if the current input line
pointer should be treated as the end of a line.
 
@item TC_CASE_SENSITIVE
@cindex TC_CASE_SENSITIVE
Define this macro if instruction mnemonics and pseudos are case sensitive.
The default is to have it undefined giving case insensitive names.
 
@item md_parse_name
@cindex md_parse_name
If this macro is defined, GAS will call it for any symbol found in an
expression. You can define this to handle special symbols in a special way.
If a symbol always has a certain value, you should normally enter it in the
symbol table, perhaps using @code{reg_section}.
 
@item md_undefined_symbol
@cindex md_undefined_symbol
GAS will call this function when a symbol table lookup fails, before it
creates a new symbol. Typically this would be used to supply symbols whose
name or value changes dynamically, possibly in a context sensitive way.
Predefined symbols with fixed values, such as register names or condition
codes, are typically entered directly into the symbol table when @code{md_begin}
is called. One argument is passed, a @code{char *} for the symbol.
 
@item md_operand
@cindex md_operand
GAS will call this function with one argument, an @code{expressionS}
pointer, for any expression that can not be recognized. When the function
is called, @code{input_line_pointer} will point to the start of the
expression.
 
@item md_register_arithmetic
@cindex md_register_arithmetic
If this macro is defined and evaluates to zero then GAS will not fold
expressions that add or subtract a constant to/from a register to give
another register. For example GAS's default behaviour is to fold the
expression "r8 + 1" into "r9", which is probably not the result
intended by the programmer. The default is to allow such folding,
since this maintains backwards compatibility with earlier releases of
GAS.
 
@item tc_unrecognized_line
@cindex tc_unrecognized_line
If you define this macro, GAS will call it when it finds a line that it can not
parse.
 
@item md_do_align
@cindex md_do_align
You may define this macro to handle an alignment directive. GAS will call it
when the directive is seen in the input file. For example, the i386 backend
uses this to generate efficient nop instructions of varying lengths, depending
upon the number of bytes that the alignment will skip.
 
@item HANDLE_ALIGN
@cindex HANDLE_ALIGN
You may define this macro to do special handling for an alignment directive.
GAS will call it at the end of the assembly.
 
@item TC_IMPLICIT_LCOMM_ALIGNMENT (@var{size}, @var{p2var})
@cindex TC_IMPLICIT_LCOMM_ALIGNMENT
An @code{.lcomm} directive with no explicit alignment parameter will use this
macro to set @var{p2var} to the alignment that a request for @var{size} bytes
will have. The alignment is expressed as a power of two. If no alignment
should take place, the macro definition should do nothing. Some targets define
a @code{.bss} directive that is also affected by this macro. The default
definition will set @var{p2var} to the truncated power of two of sizes up to
eight bytes.
 
@item md_flush_pending_output
@cindex md_flush_pending_output
If you define this macro, GAS will call it each time it skips any space because of a
space filling or alignment or data allocation pseudo-op.
 
@item TC_PARSE_CONS_EXPRESSION
@cindex TC_PARSE_CONS_EXPRESSION
You may define this macro to parse an expression used in a data allocation
pseudo-op such as @code{.word}. You can use this to recognize relocation
directives that may appear in such directives.
 
@item BITFIELD_CONS_EXPRESSION
@cindex BITFIELD_CONS_EXPRESSION
If you define this macro, GAS will recognize bitfield instructions in data
allocation pseudo-ops, as used on the i960.
 
@item REPEAT_CONS_EXPRESSION
@cindex REPEAT_CONS_EXPRESSION
If you define this macro, GAS will recognize repeat counts in data allocation
pseudo-ops, as used on the MIPS.
 
@item md_cons_align
@cindex md_cons_align
You may define this macro to do any special alignment before a data allocation
pseudo-op.
 
@item TC_CONS_FIX_NEW
@cindex TC_CONS_FIX_NEW
You may define this macro to generate a fixup for a data allocation pseudo-op.
 
@item TC_ADDRESS_BYTES
@cindex TC_ADDRESS_BYTES
Define this macro to specify the number of bytes used to store an address.
Used to implement @code{dc.a}. The target must have a reloc for this size.
 
@item TC_INIT_FIX_DATA (@var{fixp})
@cindex TC_INIT_FIX_DATA
A C statement to initialize the target specific fields of fixup @var{fixp}.
These fields are defined with the @code{TC_FIX_TYPE} macro.
 
@item TC_FIX_DATA_PRINT (@var{stream}, @var{fixp})
@cindex TC_FIX_DATA_PRINT
A C statement to output target specific debugging information for
fixup @var{fixp} to @var{stream}. This macro is called by @code{print_fixup}.
 
@item TC_FRAG_INIT (@var{fragp})
@cindex TC_FRAG_INIT
A C statement to initialize the target specific fields of frag @var{fragp}.
These fields are defined with the @code{TC_FRAG_TYPE} macro.
 
@item md_number_to_chars
@cindex md_number_to_chars
This should just call either @code{number_to_chars_bigendian} or
@code{number_to_chars_littleendian}, whichever is appropriate. On targets like
the MIPS which support options to change the endianness, which function to call
is a runtime decision. On other targets, @code{md_number_to_chars} can be a
simple macro.
 
@item md_atof (@var{type},@var{litP},@var{sizeP})
@cindex md_atof
This function is called to convert an ASCII string into a floating point value
in format used by the CPU. It takes three arguments. The first is @var{type}
which is a byte describing the type of floating point number to be created. It
is one of the characters defined in the @code{FLT_CHARS} macro. Possible
values are @var{'f'} or @var{'s'} for single precision, @var{'d'} or @var{'r'}
for double precision and @var{'x'} or @var{'p'} for extended precision. Either
lower or upper case versions of these letters can be used. Note: some targets
do not support all of these types, and some targets may also support other
types not mentioned here.
 
The second parameter is @var{litP} which is a pointer to a byte array where the
converted value should be stored. The value is converted into LITTLENUMs and
is stored in the target's endian-ness order. (@var{LITTLENUM} is defined in
gas/bignum.h). Single precision values occupy 2 littlenums. Double precision
values occupy 4 littlenums and extended precision values occupy either 5 or 6
littlenums, depending upon the target.
 
The third argument is @var{sizeP}, which is a pointer to a integer that should
be filled in with the number of chars emitted into the byte array.
 
The function should return NULL upon success or an error string upon failure.
 
@item TC_LARGEST_EXPONENT_IS_NORMAL
@cindex TC_LARGEST_EXPONENT_IS_NORMAL (@var{precision})
This macro is used only by @file{atof-ieee.c}. It should evaluate to true
if floats of the given precision use the largest exponent for normal numbers
instead of NaNs and infinities. @var{precision} is @samp{F_PRECISION} for
single precision, @samp{D_PRECISION} for double precision, or
@samp{X_PRECISION} for extended double precision.
 
The macro has a default definition which returns 0 for all cases.
 
@item WORKING_DOT_WORD
@itemx md_short_jump_size
@itemx md_long_jump_size
@itemx md_create_short_jump
@itemx md_create_long_jump
@itemx TC_CHECK_ADJUSTED_BROKEN_DOT_WORD
@cindex WORKING_DOT_WORD
@cindex md_short_jump_size
@cindex md_long_jump_size
@cindex md_create_short_jump
@cindex md_create_long_jump
@cindex TC_CHECK_ADJUSTED_BROKEN_DOT_WORD
If @code{WORKING_DOT_WORD} is defined, GAS will not do broken word processing
(@pxref{Broken words}). Otherwise, you should set @code{md_short_jump_size} to
the size of a short jump (a jump that is just long enough to jump around a
number of long jumps) and @code{md_long_jump_size} to the size of a long jump
(a jump that can go anywhere in the function). You should define
@code{md_create_short_jump} to create a short jump around a number of long
jumps, and define @code{md_create_long_jump} to create a long jump.
If defined, the macro TC_CHECK_ADJUSTED_BROKEN_DOT_WORD will be called for each
adjusted word just before the word is output. The macro takes two arguments,
an @code{addressT} with the adjusted word and a pointer to the current
@code{struct broken_word}.
 
@item md_estimate_size_before_relax
@cindex md_estimate_size_before_relax
This function returns an estimate of the size of a @code{rs_machine_dependent}
frag before any relaxing is done. It may also create any necessary
relocations.
 
@item md_relax_frag
@cindex md_relax_frag
This macro may be defined to relax a frag. GAS will call this with the
segment, the frag, and the change in size of all previous frags;
@code{md_relax_frag} should return the change in size of the frag.
@xref{Relaxation}.
 
@item TC_GENERIC_RELAX_TABLE
@cindex TC_GENERIC_RELAX_TABLE
If you do not define @code{md_relax_frag}, you may define
@code{TC_GENERIC_RELAX_TABLE} as a table of @code{relax_typeS} structures. The
machine independent code knows how to use such a table to relax PC relative
references. See @file{tc-m68k.c} for an example. @xref{Relaxation}.
 
@item md_prepare_relax_scan
@cindex md_prepare_relax_scan
If defined, it is a C statement that is invoked prior to scanning
the relax table.
 
@item LINKER_RELAXING_SHRINKS_ONLY
@cindex LINKER_RELAXING_SHRINKS_ONLY
If you define this macro, and the global variable @samp{linkrelax} is set
(because of a command line option, or unconditionally in @code{md_begin}), a
@samp{.align} directive will cause extra space to be allocated. The linker can
then discard this space when relaxing the section.
 
@item TC_LINKRELAX_FIXUP (@var{segT})
@cindex TC_LINKRELAX_FIXUP
If defined, this macro allows control over whether fixups for a
given section will be processed when the @var{linkrelax} variable is
set. The macro is given the N_TYPE bits for the section in its
@var{segT} argument. If the macro evaluates to a non-zero value
then the fixups will be converted into relocs, otherwise they will
be passed to @var{md_apply_fix} as normal.
 
@item md_convert_frag
@cindex md_convert_frag
GAS will call this for each rs_machine_dependent fragment.
The instruction is completed using the data from the relaxation pass.
It may also create any necessary relocations.
@xref{Relaxation}.
 
@item TC_FINALIZE_SYMS_BEFORE_SIZE_SEG
@cindex TC_FINALIZE_SYMS_BEFORE_SIZE_SEG
Specifies the value to be assigned to @code{finalize_syms} before the function
@code{size_segs} is called. Since @code{size_segs} calls @code{cvt_frag_to_fill}
which can call @code{md_convert_frag}, this constant governs whether the symbols
accessed in @code{md_convert_frag} will be fully resolved. In particular it
governs whether local symbols will have been resolved, and had their frag
information removed. Depending upon the processing performed by
@code{md_convert_frag} the frag information may or may not be necessary, as may
the resolved values of the symbols. The default value is 1.
 
@item TC_VALIDATE_FIX (@var{fixP}, @var{seg}, @var{skip})
@cindex TC_VALIDATE_FIX
This macro is evaluated for each fixup (when @var{linkrelax} is not set).
It may be used to change the fixup in @code{struct fix *@var{fixP}} before
the generic code sees it, or to fully process the fixup. In the latter case,
a @code{goto @var{skip}} will bypass the generic code.
 
@item md_apply_fix (@var{fixP}, @var{valP}, @var{seg})
@cindex md_apply_fix
GAS will call this for each fixup that passes the @code{TC_VALIDATE_FIX} test
when @var{linkrelax} is not set. It should store the correct value in the
object file. @code{struct fix *@var{fixP}} is the fixup @code{md_apply_fix}
is operating on. @code{valueT *@var{valP}} is the value to store into the
object files, or at least is the generic code's best guess. Specifically,
*@var{valP} is the value of the fixup symbol, perhaps modified by
@code{MD_APPLY_SYM_VALUE}, plus @code{@var{fixP}->fx_offset} (symbol addend),
less @code{MD_PCREL_FROM_SECTION} for pc-relative fixups.
@code{segT @var{seg}} is the section the fix is in.
@code{fixup_segment} performs a generic overflow check on *@var{valP} after
@code{md_apply_fix} returns. If the overflow check is relevant for the target
machine, then @code{md_apply_fix} should modify *@var{valP}, typically to the
value stored in the object file.
 
@item TC_FORCE_RELOCATION (@var{fix})
@cindex TC_FORCE_RELOCATION
If this macro returns non-zero, it guarantees that a relocation will be emitted
even when the value can be resolved locally, as @code{fixup_segment} tries to
reduce the number of relocations emitted. For example, a fixup expression
against an absolute symbol will normally not require a reloc. If undefined,
a default of @w{@code{(S_FORCE_RELOC ((@var{fix})->fx_addsy))}} is used.
 
@item TC_FORCE_RELOCATION_ABS (@var{fix})
@cindex TC_FORCE_RELOCATION_ABS
Like @code{TC_FORCE_RELOCATION}, but used only for fixup expressions against an
absolute symbol. If undefined, @code{TC_FORCE_RELOCATION} will be used.
 
@item TC_FORCE_RELOCATION_LOCAL (@var{fix})
@cindex TC_FORCE_RELOCATION_LOCAL
Like @code{TC_FORCE_RELOCATION}, but used only for fixup expressions against a
symbol in the current section. If undefined, fixups that are not
@code{fx_pcrel} or for which @code{TC_FORCE_RELOCATION}
returns non-zero, will emit relocs.
 
@item TC_FORCE_RELOCATION_SUB_SAME (@var{fix}, @var{seg})
@cindex TC_FORCE_RELOCATION_SUB_SAME
This macro controls resolution of fixup expressions involving the
difference of two symbols in the same section. If this macro returns zero,
the subtrahend will be resolved and @code{fx_subsy} set to @code{NULL} for
@code{md_apply_fix}. If undefined, the default of
@w{@code{! SEG_NORMAL (@var{seg})}} will be used.
 
@item TC_FORCE_RELOCATION_SUB_ABS (@var{fix}, @var{seg})
@cindex TC_FORCE_RELOCATION_SUB_ABS
Like @code{TC_FORCE_RELOCATION_SUB_SAME}, but used when the subtrahend is an
absolute symbol. If the macro is undefined a default of @code{0} is used.
 
@item TC_FORCE_RELOCATION_SUB_LOCAL (@var{fix}, @var{seg})
@cindex TC_FORCE_RELOCATION_SUB_LOCAL
Like @code{TC_FORCE_RELOCATION_SUB_ABS}, but the subtrahend is a symbol in the
same section as the fixup.
 
@item TC_VALIDATE_FIX_SUB (@var{fix}, @var{seg})
@cindex TC_VALIDATE_FIX_SUB
This macro is evaluated for any fixup with a @code{fx_subsy} that
@code{fixup_segment} cannot reduce to a number. If the macro returns
@code{false} an error will be reported.
 
@item TC_GLOBAL_REGISTER_SYMBOL_OK
@cindex TC_GLOBAL_REGISTER_SYMBOL_OK
Define this macro if global register symbols are supported. The default
is to disallow global register symbols.
 
@item MD_APPLY_SYM_VALUE (@var{fix})
@cindex MD_APPLY_SYM_VALUE
This macro controls whether the symbol value becomes part of the value passed
to @code{md_apply_fix}. If the macro is undefined, or returns non-zero, the
symbol value will be included. For ELF, a suitable definition might simply be
@code{0}, because ELF relocations don't include the symbol value in the addend.
 
@item S_FORCE_RELOC (@var{sym}, @var{strict})
@cindex S_FORCE_RELOC
This function returns true for symbols
that should not be reduced to section symbols or eliminated from expressions,
because they may be overridden by the linker. ie. for symbols that are
undefined or common, and when @var{strict} is set, weak, or global (for ELF
assemblers that support ELF shared library linking semantics).
 
@item EXTERN_FORCE_RELOC
@cindex EXTERN_FORCE_RELOC
This macro controls whether @code{S_FORCE_RELOC} returns true for global
symbols. If undefined, the default is @code{true} for ELF assemblers, and
@code{false} for non-ELF.
 
@item tc_gen_reloc
@cindex tc_gen_reloc
GAS will call this to generate a reloc. GAS will pass
the resulting reloc to @code{bfd_install_relocation}. This currently works
poorly, as @code{bfd_install_relocation} often does the wrong thing, and
instances of @code{tc_gen_reloc} have been written to work around the problems,
which in turns makes it difficult to fix @code{bfd_install_relocation}.
 
@item RELOC_EXPANSION_POSSIBLE
@cindex RELOC_EXPANSION_POSSIBLE
If you define this macro, it means that @code{tc_gen_reloc} may return multiple
relocation entries for a single fixup. In this case, the return value of
@code{tc_gen_reloc} is a pointer to a null terminated array.
 
@item MAX_RELOC_EXPANSION
@cindex MAX_RELOC_EXPANSION
You must define this if @code{RELOC_EXPANSION_POSSIBLE} is defined; it
indicates the largest number of relocs which @code{tc_gen_reloc} may return for
a single fixup.
 
@item tc_fix_adjustable
@cindex tc_fix_adjustable
You may define this macro to indicate whether a fixup against a locally defined
symbol should be adjusted to be against the section symbol. It should return a
non-zero value if the adjustment is acceptable.
 
@item MD_PCREL_FROM_SECTION (@var{fixp}, @var{section})
@cindex MD_PCREL_FROM_SECTION
If you define this macro, it should return the position from which the PC
relative adjustment for a PC relative fixup should be made. On many
processors, the base of a PC relative instruction is the next instruction,
so this macro would return the length of an instruction, plus the address of
the PC relative fixup. The latter can be calculated as
@var{fixp}->fx_where + @var{fixp}->fx_frag->fr_address .
 
@item md_pcrel_from
@cindex md_pcrel_from
This is the default value of @code{MD_PCREL_FROM_SECTION}. The difference is
that @code{md_pcrel_from} does not take a section argument.
 
@item tc_frob_label
@cindex tc_frob_label
If you define this macro, GAS will call it each time a label is defined.
 
@item tc_new_dot_label
@cindex tc_new_dot_label
If you define this macro, GAS will call it each time a fake label is created
off the special dot symbol.
 
@item md_section_align
@cindex md_section_align
GAS will call this function for each section at the end of the assembly, to
permit the CPU backend to adjust the alignment of a section. The function
must take two arguments, a @code{segT} for the section and a @code{valueT}
for the size of the section, and return a @code{valueT} for the rounded
size.
 
@item md_macro_start
@cindex md_macro_start
If defined, GAS will call this macro when it starts to include a macro
expansion. @code{macro_nest} indicates the current macro nesting level, which
includes the one being expanded.
 
@item md_macro_info
@cindex md_macro_info
If defined, GAS will call this macro after the macro expansion has been
included in the input and after parsing the macro arguments. The single
argument is a pointer to the macro processing's internal representation of the
macro (macro_entry *), which includes expansion of the formal arguments.
 
@item md_macro_end
@cindex md_macro_end
Complement to md_macro_start. If defined, it is called when finished
processing an inserted macro expansion, just before decrementing macro_nest.
 
@item DOUBLEBAR_PARALLEL
@cindex DOUBLEBAR_PARALLEL
Affects the preprocessor so that lines containing '||' don't have their
whitespace stripped following the double bar. This is useful for targets that
implement parallel instructions.
 
@item KEEP_WHITE_AROUND_COLON
@cindex KEEP_WHITE_AROUND_COLON
Normally, whitespace is compressed and removed when, in the presence of the
colon, the adjoining tokens can be distinguished. This option affects the
preprocessor so that whitespace around colons is preserved. This is useful
when colons might be removed from the input after preprocessing but before
assembling, so that adjoining tokens can still be distinguished if there is
whitespace, or concatenated if there is not.
 
@item tc_frob_section
@cindex tc_frob_section
If you define this macro, GAS will call it for each
section at the end of the assembly.
 
@item tc_frob_file_before_adjust
@cindex tc_frob_file_before_adjust
If you define this macro, GAS will call it after the symbol values are
resolved, but before the fixups have been changed from local symbols to section
symbols.
 
@item tc_frob_symbol
@cindex tc_frob_symbol
If you define this macro, GAS will call it for each symbol. You can indicate
that the symbol should not be included in the object file by defining this
macro to set its second argument to a non-zero value.
 
@item tc_frob_file
@cindex tc_frob_file
If you define this macro, GAS will call it after the symbol table has been
completed, but before the relocations have been generated.
 
@item tc_frob_file_after_relocs
If you define this macro, GAS will call it after the relocs have been
generated.
 
@item md_post_relax_hook
If you define this macro, GAS will call it after relaxing and sizing the
segments.
 
@item LISTING_HEADER
A string to use on the header line of a listing. The default value is simply
@code{"GAS LISTING"}.
 
@item LISTING_WORD_SIZE
The number of bytes to put into a word in a listing. This affects the way the
bytes are clumped together in the listing. For example, a value of 2 might
print @samp{1234 5678} where a value of 1 would print @samp{12 34 56 78}. The
default value is 4.
 
@item LISTING_LHS_WIDTH
The number of words of data to print on the first line of a listing for a
particular source line, where each word is @code{LISTING_WORD_SIZE} bytes. The
default value is 1.
 
@item LISTING_LHS_WIDTH_SECOND
Like @code{LISTING_LHS_WIDTH}, but applying to the second and subsequent line
of the data printed for a particular source line. The default value is 1.
 
@item LISTING_LHS_CONT_LINES
The maximum number of continuation lines to print in a listing for a particular
source line. The default value is 4.
 
@item LISTING_RHS_WIDTH
The maximum number of characters to print from one line of the input file. The
default value is 100.
 
@item TC_COFF_SECTION_DEFAULT_ATTRIBUTES
@cindex TC_COFF_SECTION_DEFAULT_ATTRIBUTES
The COFF @code{.section} directive will use the value of this macro to set
a new section's attributes when a directive has no valid flags or when the
flag is @code{w}. The default value of the macro is @code{SEC_LOAD | SEC_DATA}.
 
@item DWARF2_FORMAT (@var{sec})
@cindex DWARF2_FORMAT
If you define this, it should return one of @code{dwarf2_format_32bit},
@code{dwarf2_format_64bit}, or @code{dwarf2_format_64bit_irix} to indicate
the size of internal DWARF section offsets and the format of the DWARF initial
length fields. When @code{dwarf2_format_32bit} is returned, the initial
length field will be 4 bytes long and section offsets are 32 bits in size.
For @code{dwarf2_format_64bit} and @code{dwarf2_format_64bit_irix}, section
offsets are 64 bits in size, but the initial length field differs. An 8 byte
initial length is indicated by @code{dwarf2_format_64bit_irix} and
@code{dwarf2_format_64bit} indicates a 12 byte initial length field in
which the first four bytes are 0xffffffff and the next 8 bytes are
the section's length.
 
If you don't define this, @code{dwarf2_format_32bit} will be used as
the default.
 
This define only affects debug
sections generated by the assembler. DWARF 2 sections generated by
other tools will be unaffected by this setting.
 
@item DWARF2_ADDR_SIZE (@var{bfd})
@cindex DWARF2_ADDR_SIZE
It should return the size of an address, as it should be represented in
debugging info. If you don't define this macro, the default definition uses
the number of bits per address, as defined in @var{bfd}, divided by 8.
 
@item MD_DEBUG_FORMAT_SELECTOR
@cindex MD_DEBUG_FORMAT_SELECTOR
If defined this macro is the name of a function to be called when the
@samp{--gen-debug} switch is detected on the assembler's command line. The
prototype for the function looks like this:
 
@smallexample
enum debug_info_type MD_DEBUG_FORMAT_SELECTOR (int * use_gnu_extensions)
@end smallexample
 
The function should return the debug format that is preferred by the CPU
backend. This format will be used when generating assembler specific debug
information.
 
@item md_allow_local_subtract (@var{left}, @var{right}, @var{section})
If defined, GAS will call this macro when evaluating an expression which is the
difference of two symbols defined in the same section. It takes three
arguments: @code{expressioS * @var{left}} which is the symbolic expression on
the left hand side of the subtraction operation, @code{expressionS *
@var{right}} which is the symbolic expression on the right hand side of the
subtraction, and @code{segT @var{section}} which is the section containing the two
symbols. The macro should return a non-zero value if the expression should be
evaluated. Targets which implement link time relaxation which may change the
position of the two symbols relative to each other should ensure that this
macro returns zero in situations where this can occur.
 
@item md_allow_eh_opt
If defined, GAS will check this macro before performing any optimizations on
the DWARF call frame debug information that is emitted. Targets which
implement link time relaxation may need to define this macro and set it to zero
if it is possible to change the size of a function's prologue.
@end table
 
@node Object format backend
@subsection Writing an object format backend
@cindex object format backend
@cindex @file{obj-@var{fmt}}
 
As with the CPU backend, the object format backend must define a few things,
and may define some other things. The interface to the object format backend
is generally simpler; most of the support for an object file format consists of
defining a number of pseudo-ops.
 
The object format @file{.h} file must include @file{targ-cpu.h}.
 
@table @code
@item OBJ_@var{format}
@cindex OBJ_@var{format}
By convention, you should define this macro in the @file{.h} file. For
example, @file{obj-elf.h} defines @code{OBJ_ELF}. You might have to use this
if it is necessary to add object file format specific code to the CPU file.
 
@item obj_begin
If you define this macro, GAS will call it at the start of the assembly, after
the command line arguments have been parsed and all the machine independent
initializations have been completed.
 
@item obj_app_file
@cindex obj_app_file
If you define this macro, GAS will invoke it when it sees a @code{.file}
pseudo-op or a @samp{#} line as used by the C preprocessor.
 
@item OBJ_COPY_SYMBOL_ATTRIBUTES
@cindex OBJ_COPY_SYMBOL_ATTRIBUTES
You should define this macro to copy object format specific information from
one symbol to another. GAS will call it when one symbol is equated to
another.
 
@item obj_sec_sym_ok_for_reloc
@cindex obj_sec_sym_ok_for_reloc
You may define this macro to indicate that it is OK to use a section symbol in
a relocation entry. If it is not, GAS will define a new symbol at the start
of a section.
 
@item EMIT_SECTION_SYMBOLS
@cindex EMIT_SECTION_SYMBOLS
You should define this macro with a zero value if you do not want to include
section symbols in the output symbol table. The default value for this macro
is one.
 
@item obj_adjust_symtab
@cindex obj_adjust_symtab
If you define this macro, GAS will invoke it just before setting the symbol
table of the output BFD. For example, the COFF support uses this macro to
generate a @code{.file} symbol if none was generated previously.
 
@item SEPARATE_STAB_SECTIONS
@cindex SEPARATE_STAB_SECTIONS
You may define this macro to a nonzero value to indicate that stabs should be
placed in separate sections, as in ELF.
 
@item INIT_STAB_SECTION
@cindex INIT_STAB_SECTION
You may define this macro to initialize the stabs section in the output file.
 
@item OBJ_PROCESS_STAB
@cindex OBJ_PROCESS_STAB
You may define this macro to do specific processing on a stabs entry.
 
@item obj_frob_section
@cindex obj_frob_section
If you define this macro, GAS will call it for each section at the end of the
assembly.
 
@item obj_frob_file_before_adjust
@cindex obj_frob_file_before_adjust
If you define this macro, GAS will call it after the symbol values are
resolved, but before the fixups have been changed from local symbols to section
symbols.
 
@item obj_frob_symbol
@cindex obj_frob_symbol
If you define this macro, GAS will call it for each symbol. You can indicate
that the symbol should not be included in the object file by defining this
macro to set its second argument to a non-zero value.
 
@item obj_set_weak_hook
@cindex obj_set_weak_hook
If you define this macro, @code{S_SET_WEAK} will call it before modifying the
symbol's flags.
 
@item obj_clear_weak_hook
@cindex obj_clear_weak_hook
If you define this macro, @code{S_CLEAR_WEAKREFD} will call it after cleaning
the @code{weakrefd} flag, but before modifying any other flags.
 
@item obj_frob_file
@cindex obj_frob_file
If you define this macro, GAS will call it after the symbol table has been
completed, but before the relocations have been generated.
 
@item obj_frob_file_after_relocs
If you define this macro, GAS will call it after the relocs have been
generated.
 
@item SET_SECTION_RELOCS (@var{sec}, @var{relocs}, @var{n})
@cindex SET_SECTION_RELOCS
If you define this, it will be called after the relocations have been set for
the section @var{sec}. The list of relocations is in @var{relocs}, and the
number of relocations is in @var{n}.
@end table
 
@node Emulations
@subsection Writing emulation files
 
Normally you do not have to write an emulation file. You can just use
@file{te-generic.h}.
 
If you do write your own emulation file, it must include @file{obj-format.h}.
 
An emulation file will often define @code{TE_@var{EM}}; this may then be used
in other files to change the output.
 
@node Relaxation
@section Relaxation
@cindex relaxation
 
@dfn{Relaxation} is a generic term used when the size of some instruction or
data depends upon the value of some symbol or other data.
 
GAS knows to relax a particular type of PC relative relocation using a table.
You can also define arbitrarily complex forms of relaxation yourself.
 
@menu
* Relaxing with a table:: Relaxing with a table
* General relaxing:: General relaxing
@end menu
 
@node Relaxing with a table
@subsection Relaxing with a table
 
If you do not define @code{md_relax_frag}, and you do define
@code{TC_GENERIC_RELAX_TABLE}, GAS will relax @code{rs_machine_dependent} frags
based on the frag subtype and the displacement to some specified target
address. The basic idea is that several machines have different addressing
modes for instructions that can specify different ranges of values, with
successive modes able to access wider ranges, including the entirety of the
previous range. Smaller ranges are assumed to be more desirable (perhaps the
instruction requires one word instead of two or three); if this is not the
case, don't describe the smaller-range, inferior mode.
 
The @code{fr_subtype} field of a frag is an index into a CPU-specific
relaxation table. That table entry indicates the range of values that can be
stored, the number of bytes that will have to be added to the frag to
accommodate the addressing mode, and the index of the next entry to examine if
the value to be stored is outside the range accessible by the current
addressing mode. The @code{fr_symbol} field of the frag indicates what symbol
is to be accessed; the @code{fr_offset} field is added in.
 
If the @code{TC_PCREL_ADJUST} macro is defined, which currently should only happen
for the NS32k family, the @code{TC_PCREL_ADJUST} macro is called on the frag to
compute an adjustment to be made to the displacement.
 
The value fitted by the relaxation code is always assumed to be a displacement
from the current frag. (More specifically, from @code{fr_fix} bytes into the
frag.)
@ignore
This seems kinda silly. What about fitting small absolute values? I suppose
@code{md_assemble} is supposed to take care of that, but if the operand is a
difference between symbols, it might not be able to, if the difference was not
computable yet.
@end ignore
 
The end of the relaxation sequence is indicated by a ``next'' value of 0. This
means that the first entry in the table can't be used.
 
For some configurations, the linker can do relaxing within a section of an
object file. If call instructions of various sizes exist, the linker can
determine which should be used in each instance, when a symbol's value is
resolved. In order for the linker to avoid wasting space and having to insert
no-op instructions, it must be able to expand or shrink the section contents
while still preserving intra-section references and meeting alignment
requirements.
 
For the i960 using b.out format, no expansion is done; instead, each
@samp{.align} directive causes extra space to be allocated, enough that when
the linker is relaxing a section and removing unneeded space, it can discard
some or all of this extra padding and cause the following data to be correctly
aligned.
 
For the H8/300, I think the linker expands calls that can't reach, and doesn't
worry about alignment issues; the cpu probably never needs any significant
alignment beyond the instruction size.
 
The relaxation table type contains these fields:
 
@table @code
@item long rlx_forward
Forward reach, must be non-negative.
@item long rlx_backward
Backward reach, must be zero or negative.
@item rlx_length
Length in bytes of this addressing mode.
@item rlx_more
Index of the next-longer relax state, or zero if there is no next relax state.
@end table
 
The relaxation is done in @code{relax_segment} in @file{write.c}. The
difference in the length fields between the original mode and the one finally
chosen by the relaxing code is taken as the size by which the current frag will
be increased in size. For example, if the initial relaxing mode has a length
of 2 bytes, and because of the size of the displacement, it gets upgraded to a
mode with a size of 6 bytes, it is assumed that the frag will grow by 4 bytes.
(The initial two bytes should have been part of the fixed portion of the frag,
since it is already known that they will be output.) This growth must be
effected by @code{md_convert_frag}; it should increase the @code{fr_fix} field
by the appropriate size, and fill in the appropriate bytes of the frag.
(Enough space for the maximum growth should have been allocated in the call to
frag_var as the second argument.)
 
If relocation records are needed, they should be emitted by
@code{md_estimate_size_before_relax}. This function should examine the target
symbol of the supplied frag and correct the @code{fr_subtype} of the frag if
needed. When this function is called, if the symbol has not yet been defined,
it will not become defined later; however, its value may still change if the
section it is in gets relaxed.
 
Usually, if the symbol is in the same section as the frag (given by the
@var{sec} argument), the narrowest likely relaxation mode is stored in
@code{fr_subtype}, and that's that.
 
If the symbol is undefined, or in a different section (and therefore movable
to an arbitrarily large distance), the largest available relaxation mode is
specified, @code{fix_new} is called to produce the relocation record,
@code{fr_fix} is increased to include the relocated field (remember, this
storage was allocated when @code{frag_var} was called), and @code{frag_wane} is
called to convert the frag to an @code{rs_fill} frag with no variant part.
Sometimes changing addressing modes may also require rewriting the instruction.
It can be accessed via @code{fr_opcode} or @code{fr_fix}.
 
If you generate frags separately for the basic insn opcode and any relaxable
operands, do not call @code{fix_new} thinking you can emit fixups for the
opcode field from the relaxable frag. It is not guaranteed to be the same frag.
If you need to emit fixups for the opcode field from inspection of the
relaxable frag, then you need to generate a common frag for both the basic
opcode and relaxable fields, or you need to provide the frag for the opcode to
pass to @code{fix_new}. The latter can be done for example by defining
@code{TC_FRAG_TYPE} to include a pointer to it and defining @code{TC_FRAG_INIT}
to set the pointer.
 
Sometimes @code{fr_var} is increased instead, and @code{frag_wane} is not
called. I'm not sure, but I think this is to keep @code{fr_fix} referring to
an earlier byte, and @code{fr_subtype} set to @code{rs_machine_dependent} so
that @code{md_convert_frag} will get called.
 
@node General relaxing
@subsection General relaxing
 
If using a simple table is not suitable, you may implement arbitrarily complex
relaxation semantics yourself. For example, the MIPS backend uses this to emit
different instruction sequences depending upon the size of the symbol being
accessed.
 
When you assemble an instruction that may need relaxation, you should allocate
a frag using @code{frag_var} or @code{frag_variant} with a type of
@code{rs_machine_dependent}. You should store some sort of information in the
@code{fr_subtype} field so that you can figure out what to do with the frag
later.
 
When GAS reaches the end of the input file, it will look through the frags and
work out their final sizes.
 
GAS will first call @code{md_estimate_size_before_relax} on each
@code{rs_machine_dependent} frag. This function must return an estimated size
for the frag.
 
GAS will then loop over the frags, calling @code{md_relax_frag} on each
@code{rs_machine_dependent} frag. This function should return the change in
size of the frag. GAS will keep looping over the frags until none of the frags
changes size.
 
@node Broken words
@section Broken words
@cindex internals, broken words
@cindex broken words
 
Some compilers, including GCC, will sometimes emit switch tables specifying
16-bit @code{.word} displacements to branch targets, and branch instructions
that load entries from that table to compute the target address. If this is
done on a 32-bit machine, there is a chance (at least with really large
functions) that the displacement will not fit in 16 bits. The assembler
handles this using a concept called @dfn{broken words}. This idea is well
named, since there is an implied promise that the 16-bit field will in fact
hold the specified displacement.
 
If broken word processing is enabled, and a situation like this is encountered,
the assembler will insert a jump instruction into the instruction stream, close
enough to be reached with the 16-bit displacement. This jump instruction will
transfer to the real desired target address. Thus, as long as the @code{.word}
value really is used as a displacement to compute an address to jump to, the
net effect will be correct (minus a very small efficiency cost). If
@code{.word} directives with label differences for values are used for other
purposes, however, things may not work properly. For targets which use broken
words, the @samp{-K} option will warn when a broken word is discovered.
 
The broken word code is turned off by the @code{WORKING_DOT_WORD} macro. It
isn't needed if @code{.word} emits a value large enough to contain an address
(or, more correctly, any possible difference between two addresses).
 
@node Internal functions
@section Internal functions
 
This section describes basic internal functions used by GAS.
 
@menu
* Warning and error messages:: Warning and error messages
* Hash tables:: Hash tables
@end menu
 
@node Warning and error messages
@subsection Warning and error messages
 
@deftypefun @{@} int had_warnings (void)
@deftypefunx @{@} int had_errors (void)
Returns non-zero if any warnings or errors, respectively, have been printed
during this invocation.
@end deftypefun
 
@deftypefun @{@} void as_tsktsk (const char *@var{format}, ...)
@deftypefunx @{@} void as_warn (const char *@var{format}, ...)
@deftypefunx @{@} void as_bad (const char *@var{format}, ...)
@deftypefunx @{@} void as_fatal (const char *@var{format}, ...)
These functions display messages about something amiss with the input file, or
internal problems in the assembler itself. The current file name and line
number are printed, followed by the supplied message, formatted using
@code{vfprintf}, and a final newline.
 
An error indicated by @code{as_bad} will result in a non-zero exit status when
the assembler has finished. Calling @code{as_fatal} will result in immediate
termination of the assembler process.
@end deftypefun
 
@deftypefun @{@} void as_warn_where (char *@var{file}, unsigned int @var{line}, const char *@var{format}, ...)
@deftypefunx @{@} void as_bad_where (char *@var{file}, unsigned int @var{line}, const char *@var{format}, ...)
These variants permit specification of the file name and line number, and are
used when problems are detected when reprocessing information saved away when
processing some earlier part of the file. For example, fixups are processed
after all input has been read, but messages about fixups should refer to the
original filename and line number that they are applicable to.
@end deftypefun
 
@deftypefun @{@} void sprint_value (char *@var{buf}, valueT @var{val})
This function is helpful for converting a @code{valueT} value into printable
format, in case it's wider than modes that @code{*printf} can handle. If the
type is narrow enough, a decimal number will be produced; otherwise, it will be
in hexadecimal. The value itself is not examined to make this determination.
@end deftypefun
 
@node Hash tables
@subsection Hash tables
@cindex hash tables
 
@deftypefun @{@} @{struct hash_control *@} hash_new (void)
Creates the hash table control structure.
@end deftypefun
 
@deftypefun @{@} void hash_die (struct hash_control *)
Destroy a hash table.
@end deftypefun
 
@deftypefun @{@} void *hash_delete (struct hash_control *, const char *, int)
Deletes entry from the hash table, returns the value it had. If the last
arg is non-zero, free memory allocated for this entry and all entries
allocated more recently than this entry.
@end deftypefun
 
@deftypefun @{@} void *hash_replace (struct hash_control *, const char *, void *)
Updates the value for an entry already in the table, returning the old value.
If no entry was found, just returns NULL.
@end deftypefun
 
@deftypefun @{@} @{const char *@} hash_insert (struct hash_control *, const char *, void *)
Inserting a value already in the table is an error.
Returns an error message or NULL.
@end deftypefun
 
@deftypefun @{@} @{const char *@} hash_jam (struct hash_control *, const char *, void *)
Inserts if the value isn't already present, updates it if it is.
@end deftypefun
 
@node Test suite
@section Test suite
@cindex test suite
 
The test suite is kind of lame for most processors. Often it only checks to
see if a couple of files can be assembled without the assembler reporting any
errors. For more complete testing, write a test which either examines the
assembler listing, or runs @code{objdump} and examines its output. For the
latter, the TCL procedure @code{run_dump_test} may come in handy. It takes the
base name of a file, and looks for @file{@var{file}.d}. This file should
contain as its initial lines a set of variable settings in @samp{#} comments,
in the form:
 
@example
#@var{varname}: @var{value}
@end example
 
The @var{varname} may be @code{objdump}, @code{nm}, or @code{as}, in which case
it specifies the options to be passed to the specified programs. Exactly one
of @code{objdump} or @code{nm} must be specified, as that also specifies which
program to run after the assembler has finished. If @var{varname} is
@code{source}, it specifies the name of the source file; otherwise,
@file{@var{file}.s} is used. If @var{varname} is @code{name}, it specifies the
name of the test to be used in the @code{pass} or @code{fail} messages.
 
The non-commented parts of the file are interpreted as regular expressions, one
per line. Blank lines in the @code{objdump} or @code{nm} output are skipped,
as are blank lines in the @code{.d} file; the other lines are tested to see if
the regular expression matches the program output. If it does not, the test
fails.
 
Note that this means the tests must be modified if the @code{objdump} output
style is changed.
 
@bye
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