OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk
    from Rev 243 to Rev 244
    ↔ Reverse comparison
  •

Rev 243 → Rev 244

/VHDL/o8_7seg.vhd
35,6 → 35,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/08/19 Design Start
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
56,6 → 57,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
--
SegLED1 : out std_logic_vector(6 downto 0);
72,12 → 74,16
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic;
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0);
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
signal Rd_En : std_logic;
 
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal LED1_Reg : std_logic_vector(4 downto 0);
signal LED1_Brt : DATA_TYPE;
signal LED2_Reg : std_logic_vector(4 downto 0);
145,26 → 151,29
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Wr_En <= '0';
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
LED1_Reg <= Default_LED1_Value;
LED2_Reg <= Default_LED2_Value;
LED1_Brt <= Default_LED1_Bright;
LED2_Brt <= Default_LED2_Bright;
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
case( Reg_Sel )is
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
LED1_Reg <= Wr_Data_q(4 downto 0);
when "01" =>
178,10 → 187,10
end case;
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Sel )is
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= "000" & LED1_Reg;
when "01" =>
/VHDL/o8_alu16.vhd
156,6 → 156,7
-- Seth Henry 12/19/19 Renamed to o8_alu16 to fit "theme"
-- Seth Henry 04/10/20 Comment and code cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
172,6 → 173,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '0';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
245,14 → 247,17
Address(15 downto 5);
alias Comp_Addr is Open8_Bus.Address(15 downto 5);
 
signal Reg_Addr : std_logic_vector(4 downto 0) :=
(others => '0');
 
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Wr_Data_q : DATA_TYPE := (others => '0');
signal Rd_En : std_logic := '0';
 
alias Reg_Sel_d is Open8_Bus.Address(4 downto 0);
signal Reg_Sel_q : std_logic_vector(4 downto 0) := "00000";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
type REG_ARRAY is array( 0 to 7 ) of std_logic_vector(15 downto 0);
signal regfile : REG_ARRAY := (
x"0000",x"0000",x"0000",x"0000",
373,6 → 378,8
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
-- Sign-extend the base operands to created operands for signed math
S_Operand_1 <= signed(Operand_1(15) & Operand_1);
396,11 → 403,11
variable Oper_Sel : integer;
begin
if( Reset = Reset_Level )then
Wr_En <= '0';
Wr_Data_q <= (others => '0');
Rd_En <= '0';
Reg_Sel_q <= (others => '0');
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Reg_Addr <= (others => '0');
Opcode <= (others => '0');
Operand_Sel <= (others => '0');
Tolerance <= (others => '0');
435,16 → 442,16
elsif( rising_edge(Clock) )then
-- For convenience, convert these to integers and assign them to
-- variables
Reg_Sel := conv_integer(Reg_Addr(3 downto 1));
Reg_Sel := conv_integer(Reg_Sel_q(3 downto 1));
Oper_Sel := conv_integer(Operand_Sel);
 
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Reg_Addr <= Open8_Bus.Address(4 downto 0);
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
Reg_Sel_q <= Reg_Sel_d;
 
Start <= '0';
if( Wr_En = '1' )then
case( Reg_Addr )is
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
-- Even addresses go to the lower byte of the register
when "00000" | "00010" | "00100" | "00110" |
"01000" | "01010" | "01100" | "01110" =>
472,11 → 479,10
end case;
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
 
if( Rd_En = '1' )then
case( Reg_Addr )is
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00000" | "00010" | "00100" | "00110" |
"01000" | "01010" | "01100" | "01110" =>
Rd_Data <= regfile(Reg_Sel)(7 downto 0);
/VHDL/o8_async_serial.vhd
29,11 → 29,12
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x00 AAAAAAAA TX Data (WR) RX Data (RD) (RW)
-- 0x01 DCBA---- FIFO Status (RO)
-- A: RX FIFO Empty
-- B: RX FIFO almost full (922/1024)
-- C: TX FIFO Empty
-- D: TX FIFO almost full (922/1024)
-- 0x01 EDCBA--- FIFO Status (RO*)
-- A: RX Parity Error (write to clear)
-- B: RX FIFO Empty
-- C: RX FIFO almost full (922/1024)
-- D: TX FIFO Empty
-- E: TX FIFO almost full (922/1024)
--
-- Note: The baud rate generator will produce an approximate frequency. The
-- final bit rate should be within +/- 1% of the true bit rate to
47,6 → 48,7
-- Seth Henry 12/20/19 Design Start
-- Seth Henry 04/10/20 Code cleanup and register documentation
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
69,11 → 71,12
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
--
TX_Out : out std_logic;
CTS_In : in std_logic;
RX_In : in std_logic;
CTS_In : in std_logic := '1';
RX_In : in std_logic := '1';
RTS_Out : out std_logic
);
end entity;
83,6 → 86,9
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
alias Wr_En is Open8_Bus.Wr_En;
alias Wr_Data is Open8_Bus.Wr_Data;
alias Rd_En is Open8_Bus.Rd_En;
 
signal FIFO_Reset : std_logic := '0';
 
91,12 → 97,17
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Open8_Bus.Address(0);
signal Reg_Sel : std_logic := '0';
signal Rd_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(0);
signal Reg_Sel_q : std_logic := '0';
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal TX_FIFO_Wr_En : std_logic := '0';
alias TX_FIFO_Wr_Data is Open8_Bus.Wr_Data;
signal TX_FIFO_Wr_Data : DATA_TYPE := x"00";
signal TX_FIFO_Rd_En : std_logic := '0';
signal TX_FIFO_Empty : std_logic := '0';
signal TX_FIFO_AFull : std_logic := '0';
122,30 → 133,54
signal RX_FIFO_AFull : std_logic := '0';
signal RX_FIFO_Rd_Data : DATA_TYPE := x"00";
 
signal Rx_PErr : std_logic := '0';
signal RX_Parity_Err : std_logic := '0';
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Reg_Sel_q <= '0';
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
RTS_Out <= '0';
RX_Parity_Err <= '0';
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
TX_FIFO_Wr_En <= Wr_En_q and not Reg_Sel_q;
TX_FIFO_Wr_Data <= Wr_Data_q;
 
if( Rx_PErr = '1' )then
RX_Parity_Err <= '1';
elsif( Wr_En_q = '1' and Reg_Sel_q = '1' and Write_Qual = '1' )then
RX_Parity_Err <= '0';
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Reg_Sel <= Reg_Addr;
if( Rd_En = '1' and Reg_Sel = '1' )then
if( Rd_En_q = '1' and Reg_Sel_q = '1' )then
Rd_Data(3) <= RX_Parity_Err;
Rd_Data(4) <= RX_FIFO_Empty;
Rd_Data(5) <= RX_FIFO_AFull;
Rd_Data(6) <= TX_FIFO_Empty;
Rd_Data(7) <= TX_FIFO_AFull;
end if;
if( Rd_En = '1' and Reg_Sel = '0' )then
if( Rd_En_q = '1' and Reg_Sel_q = '0' )then
Rd_Data <= RX_FIFO_Rd_Data;
end if;
RTS_Out <= not RX_FIFO_AFull;
 
end if;
end process;
 
159,10 → 194,6
 
TX_Enabled : if( not Disable_Transmit )generate
 
TX_FIFO_Wr_En <= Open8_Bus.Wr_En and
Addr_Match and
(not Reg_Addr);
 
FIFO_Reset <= '1' when Reset = Reset_Level else '0';
 
U_TX_FIFO : entity work.fifo_1k_core
236,8 → 267,9
 
end generate;
 
RX_Disabled : if( Disable_Transmit )generate
RX_Disabled : if( Disable_Receive )generate
 
Rx_PErr <= '0';
RX_FIFO_Empty <= '1';
RX_FIFO_AFull <= '0';
RX_FIFO_Rd_Data <= x"00";
261,12 → 293,12
--
Rx_Data => RX_FIFO_Wr_Data,
Rx_Valid => RX_FIFO_Wr_En,
Rx_PErr => open
Rx_PErr => Rx_PErr
);
 
RX_FIFO_Rd_En <= Open8_Bus.Rd_En and
Addr_Match and
(not Reg_Addr);
(not Reg_Sel_d);
 
U_RX_FIFO : entity work.fifo_1k_core
port map(
/VHDL/o8_btn_int.vhd
67,9 → 67,11
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
signal Rd_En : std_logic := '0';
signal Addr_Match : std_logic := '0';
 
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
constant MSEC_DELAY : std_logic_vector(9 downto 0) :=
conv_std_logic_vector(1000,10);
 
81,19 → 83,19
 
begin
 
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
'0';
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Interrupt <= '0';
elsif( rising_edge( Clock ) )then
Rd_En <= Addr_Match;
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
if( Rd_En_q = '1' )then
Rd_Data <= Button_Pressed;
end if;
Interrupt <= or_reduce(Button_CoS);
/VHDL/o8_clk_detect.vhd
67,7 → 67,8
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
 
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
constant Threshold_bits : integer := ceil_log2(Threshold_Count);
constant THRESHOLD : std_logic_vector(Threshold_bits - 1 downto 0) :=
90,18 → 91,19
 
begin
 
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Rd_En <= Addr_Match;
Rd_En_q <= Rd_En_d;
 
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
if( Rd_En_q = '1' )then
Rd_Data(6) <= Ref_In_q2;
Rd_Data(7) <= Ref_Detect;
end if;
/VHDL/o8_cpu.vhd
76,6 → 76,17
-- : the lower four bits are restored, allowing ISR code to alter
-- : the GP flags persistently.
-- :
-- : Supervisor_Mode, when set, disables the STP PSR_I instruction
-- : preventing code from setting the I bit. When enabled, only
-- : interrupts can set the I bit, allowing for more robust memory
-- : protection by preventing errant code execution from
-- : inadvertently entering an interrupt state.
-- :
-- : Default_Int_Flag allows the initial state of the I bit to be
-- : set at startup. If set, initialization code may be run in an
-- : ISR context, disabling memory protection initially. Init code
-- : should clear the I bit when done;
-- :
-- : Default_Interrupt_Mask sets the intial/reset value of the
-- : interrupt mask. To remain true to the original core, which
-- : had no interrupt mask, this should be set to x"FF". Otherwise
205,6 → 216,14
-- Seth Henry 04/16/20 Modified to use new Open8 bus record. Also added
-- reset and usec_tick logic to drive utility
-- signals. Also added Halt_Ack output.
-- Seth Henry 05/20/20 Added two new generics to alter the way the I bit
-- is handled. The Supervisor_Mode setting disables
-- STP PSR_I from being executed, preventing it
-- from being set outside of an ISR. The
-- Default_Int_Flag setting allows the I bit to
-- start set so that initialization code can run,
-- but not be hijacked later to corrupt any memory
-- write protection later.
 
library ieee;
use ieee.std_logic_1164.all;
227,6 → 246,8
Enable_NMI : boolean := true; -- Force INTR0 enabled
Sequential_Interrupts : boolean := false; -- Interruptable ISRs
RTI_Ignores_GP_Flags : boolean := false; -- RTI sets all flags
Supervisor_Mode : boolean := false; -- I bit is restricted
Default_Int_Flag : boolean := false; -- Start with I bit set
Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
Clock_Frequency : real -- Clock Frequency
);
597,6 → 618,18
DP_Ctrl.Src <= DATA_WR_REG;
DP_Ctrl.Reg <= ACCUM;
 
when OP_STP =>
PC_Ctrl.Offset <= PC_NEXT;
if( Supervisor_Mode )then
if( SubOp /= PSR_I )then
ALU_Ctrl.Oper <= Opcode;
ALU_Ctrl.Reg <= SubOp;
end if;
else
ALU_Ctrl.Oper <= Opcode;
ALU_Ctrl.Reg <= SubOp;
end if;
 
when others =>
PC_Ctrl.Offset <= PC_NEXT;
ALU_Ctrl.Oper <= Opcode;
967,6 → 1000,9
Regfile(i) <= x"00";
end loop;
Flags <= x"00";
if( Default_Int_Flag )then
Flags(PSR_I) <= '1';
end if;
 
Open8_Bus.GP_Flags <= (others => '0');
 
/VHDL/o8_crc16_ccitt.vhd
42,6 → 42,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 12/19/19 Design Start
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
56,6 → 57,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE
);
end entity;
71,14 → 73,17
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0) :=
(others => '0');
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE := (others => '0');
signal Rd_En : std_logic;
 
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Next_Byte : DATA_TYPE := (others => '0');
signal Byte_Count : DATA_TYPE := (others => '0');
 
94,6 → 99,8
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
Exr(0) <= Reg(0) xor Data(0);
Exr(1) <= Reg(1) xor Data(1);
107,10 → 114,10
CRC16_Calc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Wr_En <= '0';
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
Byte_Count <= x"00";
119,13 → 126,13
Data <= x"00";
Reg <= x"0000";
elsif( rising_edge(Clock) )then
Reg_Sel <= Reg_Addr;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
if( Wr_En = '1' )then
case( Reg_Sel )is
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
when "00" => -- Load next byte
Data <= Wr_Data_q;
Calc_En <= '1';
138,10 → 145,10
end case;
end if;
 
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En = '1' )then
case( Reg_Sel )is
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" => -- Read last byte
Rd_Data <= Data;
 
/VHDL/o8_datalatch.vhd
65,16 → 65,18
 
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Rd_En : std_logic;
signal Addr_Match : std_logic := '0';
 
signal Strobe_sr : std_logic_vector(3 downto 0);
signal Strobe_re : std_logic;
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal LData_q1 : DATA_TYPE;
signal LData_q2 : DATA_TYPE;
signal LData_q3 : DATA_TYPE;
signal Strobe_sr : std_logic_vector(3 downto 0) := "0000";
signal Strobe_re : std_logic := '0';
 
signal LData_q1 : DATA_TYPE := x"00";
signal LData_q2 : DATA_TYPE := x"00";
signal LData_q3 : DATA_TYPE := x"00";
 
begin
 
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
83,7 → 85,7
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Strobe_sr <= (others => '0');
Interrupt <= '0';
101,8 → 103,8
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match;
if( Rd_En = '1' )then
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
Rd_Data <= LData_q3;
end if;
end if;
/VHDL/o8_elapsed_usec.vhd
42,6 → 42,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/20/20 Design Start
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
58,6 → 59,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE
);
end entity;
71,13 → 73,15
constant User_Addr : std_logic_vector(15 downto 2) :=
Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Addr_Match : std_logic := '0';
 
signal Addr_Match : std_logic := '0';
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
signal Wr_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Shadow_Time : std_logic_vector(23 downto 0) := x"000000";
94,28 → 98,31
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Wr_En <= '0';
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
Update_Shadow <= '0';
Timer_Reset <= '0';
Timer_En_Req <= '0';
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
Update_Shadow <= '0';
Timer_Reset <= '0';
if( Wr_En = '1' )then
case( Reg_Sel )is
if( Wr_En_q = '1' and Write_Qual = '1' )then
case( Reg_Sel_q )is
when "00" =>
Update_Shadow <= '1';
when "01" =>
130,9 → 137,9
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Sel )is
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= Shadow_Time_B0;
when "01" =>
/VHDL/o8_epoch_timer.vhd
54,6 → 54,7
-- Seth Henry 04/10/20 Overhauled the register interface of the timer to
-- make the interface more sensible to software.
-- Seth Henry 04/160/20 Modified to make use of Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
70,6 → 71,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
87,13 → 89,14
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Open8_Bus.Address(2 downto 0);
signal Reg_Addr_q : std_logic_vector(2 downto 0) :=
(others => '0');
 
signal Wr_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0) := "000";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal setpt_buffer : std_logic_vector(23 downto 0) :=
(others => '0');
134,15 → 137,18
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_Data_q <= (others => '0');
Reg_Addr_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Reg_Sel_q <= "000";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
setpt_buffer <= (others => '0');
buffer_pending <= '0';
buffer_update <= '0';
149,17 → 155,17
capture_epoch <= '0';
timer_clear <= '0';
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel_d;
 
Reg_Addr_q <= Reg_Addr;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
buffer_update <= '0';
capture_epoch <= '0';
timer_clear <= '0';
 
if( Wr_En = '1' )then
case( Reg_Addr_q )is
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
when "000" =>
setpt_buffer_b0 <= Wr_Data_q;
buffer_pending <= '1';
185,10 → 191,10
end case;
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "000" =>
Rd_Data <= epoch_setpt_b0;
when "001" =>
/VHDL/o8_epoch_timer_ii.vhd
38,6 → 38,8
-- 0x5 AAAAAAAA B1 of Current Epoch Time(RO)
-- 0x6 AAAAAAAA B2 of Current Epoch Time(RO)
-- 0x7 AAAAAAAA B3 of Current Epoch Time(RO)
-- Note that any write to 0x04,0x05, 0x06, or 0x07 will copy
-- the current epoch time to a readable output buffer
-- 0x8 xxxxxxxx (not used - returns 0x00)
-- 0x9 xxxxxxxx (not used - returns 0x00)
-- 0xA xxxxxxxx (not used - returns 0x00)
51,8 → 53,6
-- B = Alarm status (R)
-- Note that any write will update the internal set point
-- and clear the alarm
-- Note that any write to 0x04,0x05, or 0x06 will copy the
-- current epoch time to a readable output buffer
--
-- Revision History
-- Author Date Change
60,6 → 60,7
-- Seth Henry 04/15/20 Created from o8_epoch_timer due to requirement
-- change.
-- Seth Henry 04/16/20 Modifiefd to make use of Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
76,6 → 77,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
93,13 → 95,14
alias Comp_Addr is Open8_Bus.Address(15 downto 4);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Open8_Bus.Address(3 downto 0);
signal Reg_Addr_q : std_logic_vector(3 downto 0) :=
(others => '0');
 
signal Wr_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(3 downto 0);
signal Reg_Sel_q : std_logic_vector(3 downto 0) := "0000";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal setpt_buffer : std_logic_vector(31 downto 0) :=
(others => '0');
142,15 → 145,18
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_Data_q <= (others => '0');
Reg_Addr_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Reg_Sel_q <= "0000";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
setpt_buffer <= (others => '0');
buffer_pending <= '0';
buffer_update <= '0';
158,16 → 164,17
timer_clear <= '0';
elsif( rising_edge( Clock ) )then
 
Reg_Addr_q <= Reg_Addr;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
buffer_update <= '0';
timer_clear <= '0';
capture_epoch <= '0';
 
if( Wr_En = '1' )then
case( Reg_Addr_q )is
if( Wr_En_q = '1' and Write_Qual = '1' )then
case( Reg_Sel_q )is
when x"0" =>
setpt_buffer_b0 <= Wr_Data_q;
buffer_pending <= '1';
199,9 → 206,9
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when x"0" =>
Rd_Data <= epoch_setpt_b0;
when x"1" =>
/VHDL/o8_gpin.vhd
60,8 → 60,10
constant User_Addr : std_logic_vector(15 downto 0) := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Rd_En : std_logic;
 
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal GPIN_q1 : DATA_TYPE;
signal GPIN_q2 : DATA_TYPE;
signal User_In : DATA_TYPE;
68,13 → 70,13
 
begin
 
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
'0';
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
GPIN_q1 <= x"00";
GPIN_q2 <= x"00";
85,8 → 87,8
User_In <= GPIN_q2;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match;
if( Rd_En = '1' )then
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
Rd_Data <= User_In;
end if;
end if;
/VHDL/o8_gpio.vhd
38,6 → 38,7
-- Also removed "input only" generic, as there is a
-- separate module for that
-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
53,6 → 54,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
--
GPIO : inout DATA_TYPE
67,12 → 69,16
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Addr_Match : std_logic;
 
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal User_Out : DATA_TYPE := x"00";
signal User_En : DATA_TYPE := x"00";
81,24 → 87,27
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Rd_En <= '0';
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Wr_En <= '0';
Wr_Data_q <= x"00";
 
User_Out <= Default_Out;
User_En <= Default_En;
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
case( Reg_Sel )is
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
User_Out <= Wr_Data_q;
when "01" =>
109,11 → 118,10
 
User_In <= GPIO;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
Rd_Data <= User_In;
case( Reg_Sel )is
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= User_Out;
when "01" =>
/VHDL/o8_gpout.vhd
40,6 → 40,7
-- Seth Henry 12/19/19 Renamed to "o8_gpout" to fit "theme"
-- Seth Henry 04/10/20 Code Cleanup and comments
-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
56,6 → 57,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
--
GPO : out DATA_TYPE
70,12 → 72,15
constant User_Addr : std_logic_vector(15 downto 1)
:= Address(15 downto 1);
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
alias Reg_Addr is Open8_Bus.Address(0);
signal Reg_Sel : std_logic := '0';
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(0);
signal Reg_Sel_q : std_logic := '0';
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal User_Out : DATA_TYPE := x"00";
signal User_En : DATA_TYPE := x"00";
87,10 → 92,10
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel <= '0';
Wr_En <= '0';
Reg_Sel_q <= '0';
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
User_Out <= Default_Out;
if( not Disable_Tristate)then
97,14 → 102,15
User_En <= Default_En;
end if;
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
if( Wr_En_q = '1' )then
if( Disable_Tristate )then
User_Out <= Wr_Data_q;
else
if( Reg_Sel = '0' )then
if( Reg_Sel_q = '0' )then
User_Out <= Wr_Data_q;
else
User_En <= Wr_Data_q;
112,11 → 118,11
end if;
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
if( Rd_En_q = '1' )then
Rd_Data <= User_Out;
if( (Reg_Sel = '1') and (not Disable_Tristate) )then
if( (Reg_Sel_q = '1') and (not Disable_Tristate) )then
Rd_Data <= User_En;
end if;
end if;
/VHDL/o8_hd44780_4b.vhd
73,6 → 73,7
-- Seth Henry 01/22/13 Design Start
-- Seth Henry 04/10/20 Code & comment cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
93,6 → 94,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
114,14 → 116,16
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic := '0';
signal Addr_Match : std_logic;
 
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
 
signal Wr_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Reg_Valid : std_logic := '0';
signal Reg_Sel : std_logic := '0';
191,14 → 195,16
--------------------------------------------------------------------------------
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Addr_q <= (others => '0');
Wr_Data_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
Reg_Valid <= '0';
208,18 → 214,16
LCD_Contrast <= Default_Contrast;
LCD_Bright <= Default_Brightness;
elsif( rising_edge( Clock ) )then
Reg_Addr_q <= Reg_Addr;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
 
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
Reg_Valid <= '0';
 
if( Wr_En = '1' )then
case( Reg_Addr_q )is
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
when "00" | "01" =>
Reg_Valid <= '1';
Reg_Sel <= Reg_Addr_q(0);
Reg_Sel <= Reg_Sel_q(0);
Reg_Data <= Wr_Data_q;
when "10" =>
LCD_Contrast <= Wr_Data_q;
229,10 → 233,10
end case;
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" | "01" =>
Rd_Data(7) <= Tx_Ready;
when "10" =>
/VHDL/o8_hd44780_8b.vhd
73,6 → 73,7
-- Seth Henry 01/22/13 Design Start
-- Seth Henry 04/10/20 Code & comment cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
93,6 → 94,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
114,14 → 116,16
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic := '0';
signal Addr_Match : std_logic;
 
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Addr_q : std_logic_vector(1 downto 0) := (others => '0');
 
signal Wr_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Reg_Valid : std_logic := '0';
signal Reg_Sel : std_logic := '0';
187,14 → 191,16
--------------------------------------------------------------------------------
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Addr_q <= (others => '0');
Wr_Data_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
Reg_Valid <= '0';
204,18 → 210,16
LCD_Contrast <= Default_Contrast;
LCD_Bright <= Default_Brightness;
elsif( rising_edge( Clock ) )then
Reg_Addr_q <= Reg_Addr;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
 
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
Reg_Valid <= '0';
 
if( Wr_En = '1' )then
case( Reg_Addr_q )is
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
when "00" | "01" =>
Reg_Valid <= '1';
Reg_Sel <= Reg_Addr_q(0);
Reg_Sel <= Reg_Sel_q(0);
Reg_Data <= Wr_Data_q;
when "10" =>
LCD_Contrast <= Wr_Data_q;
225,10 → 229,10
end case;
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" | "01" =>
Rd_Data(7) <= Tx_Ready;
when "10" =>
/VHDL/o8_lfsr32.vhd
61,10 → 61,11
constant User_Addr : std_logic_vector(15 downto 1)
:= Address(15 downto 1);
alias Comp_Addr is Open8_Bus.Address(15 downto 1);
alias Reg_Sel is Open8_Bus.Address(0);
signal Addr_Match : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(0);
signal Reg_Sel_q : std_logic := '0';
signal Addr_Match : std_logic := '0';
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal d0 : std_logic := '0';
signal lfsr : std_logic_vector(31 downto 0) := x"00000000";
72,8 → 73,9
 
begin
 
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else
'0';
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
d0 <= lfsr(31) xnor lfsr(21) xnor lfsr(1) xnor lfsr(0);
 
lfsr_proc: process( Clock, Reset )
80,15 → 82,16
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= '0';
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= x"00";
lfsr <= Init_Seed;
lfsr_q <= x"00000000";
elsif( rising_edge(Clock) )then
Rd_Data <= x"00";
Reg_Sel_q <= Reg_Sel;
Rd_En <= Addr_Match;
if( Rd_En = '1' )then
Reg_Sel_q <= Reg_Sel_d;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En_q = '1' )then
Rd_Data <= lfsr_q(31 downto 24);
lfsr_q <= lfsr_q(23 downto 0) & x"00";
if( Reg_Sel_q = '1' )then
/VHDL/o8_ltc2355_2p.vhd
75,13 → 75,15
 
constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
alias Reg_Sel is Open8_Bus.Address(2 downto 0);
signal Addr_Match : std_logic;
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0);
signal Wr_Data_q : DATA_TYPE;
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Rd_En : std_logic;
signal User_In : DATA_TYPE;
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal User_Trig : std_logic;
 
104,23 → 106,27
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= (others => '0');
Reg_Sel_q <= "000";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Wr_En <= '0';
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
User_Trig <= '0';
Timer_Int <= x"00";
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
User_Trig <= '0';
if( Wr_En = '1' )then
if( Wr_En_q = '1' )then
if( Reg_Sel_q = "110" )then
Timer_Int <= Wr_Data_q;
end if;
129,10 → 135,9
end if;
end if;
 
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
 
if( Rd_En = '1' )then
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
-- Channel 1, Full resolution, lower byte
when "000" =>
/VHDL/o8_max7221.vhd
30,6 → 30,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 01/22/20 Design Start
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
48,6 → 49,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
--
Mx_Data : out std_logic;
Mx_Clock : out std_logic;
65,19 → 67,22
constant User_Addr : std_logic_vector(15 downto 4) :=
Address(15 downto 4);
alias Comp_Addr is Open8_Bus.Address(15 downto 4);
signal Addr_Match : std_logic := '0';
 
signal FIFO_Wr_En : std_logic;
signal FIFO_Wr_Data : std_logic_vector(11 downto 0);
signal FIFO_Wr_En : std_logic := '0';
signal FIFO_Wr_Data : std_logic_vector(11 downto 0) :=
(others => '0');
 
signal FIFO_Rd_En : std_logic;
signal FIFO_Empty : std_logic;
signal FIFO_Rd_Data : std_logic_vector(11 downto 0);
signal FIFO_Rd_En : std_logic := '0';
signal FIFO_Empty : std_logic := '0';
signal FIFO_Rd_Data : std_logic_vector(11 downto 0) :=
(others => '0');
 
type TX_CTRL_STATES is (IDLE, TX_BYTE, TX_START, TX_WAIT );
signal TX_Ctrl : TX_CTRL_STATES;
signal TX_Ctrl : TX_CTRL_STATES := IDLE;
 
signal TX_En : std_logic;
signal TX_Idle : std_logic;
signal TX_En : std_logic := '0';
signal TX_Idle : std_logic := '0';
 
constant BAUD_DLY_RATIO : real := (Clock_Frequency / Bitclock_Frequency);
constant BAUD_DLY_VAL : integer := integer(BAUD_DLY_RATIO * 0.5);
87,18 → 92,20
 
signal Baud_Cntr : std_logic_vector( BAUD_DLY_WDT - 1 downto 0 )
:= (others => '0');
signal Baud_Tick : std_logic;
signal Baud_Tick : std_logic := '0';
 
type IO_STATES is ( IDLE, SYNC_CLK, SCLK_L, SCLK_H, ADV_BIT, DONE );
signal io_state : IO_STATES;
signal bit_cntr : std_logic_vector(3 downto 0);
signal tx_buffer : std_logic_vector(15 downto 0);
signal io_state : IO_STATES := IDLE;
signal bit_cntr : std_logic_vector(3 downto 0) := (others => '0');
signal tx_buffer : std_logic_vector(15 downto 0) :=
(others => '0');
 
begin
 
FIFO_Wr_En <= Open8_Bus.Wr_En when Comp_Addr = User_Addr else
'0';
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
 
FIFO_Wr_En <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
 
FIFO_Wr_Data <= Open8_Bus.Address(3 downto 0) &
Open8_Bus.Wr_Data;
 
/VHDL/o8_pwm16.vhd
56,6 → 56,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
75,12 → 76,14
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Open8_Bus.Address(2 downto 0);
signal Reg_Addr_q : std_logic_vector(2 downto 0) := (others => '0');
 
signal Wr_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0) := (others => '0');
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal PWM_Enable : std_logic := '0';
signal PWM_Period : std_logic_vector(15 downto 0) := (others => '0');
97,15 → 100,18
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
PWM_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_Data_q <= (others => '0');
Reg_Addr_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Rd_Data <= x"00";
Reg_Sel_q <= "000";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
Interrupt <= '0';
 
PWM_Enable <= '0';
116,12 → 122,12
Width_Ctr <= (others => '0');
PWM_Out <= '0';
elsif( rising_edge(Clock) )then
Reg_Addr_q <= Reg_Addr;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Reg_Sel_q <= Reg_Sel_d;
 
if( Wr_En = '1' )then
case( Reg_Addr_q )is
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
when "000" =>
PWM_Period_l <= Wr_Data_q;
when "001" =>
136,10 → 142,10
end case;
end if;
 
Rd_Data <= (others => '0');
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "000" =>
Rd_Data <= PWM_Period_l;
when "001" =>
/VHDL/o8_pwm_adc.vhd
60,7 → 60,8
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
 
signal Addr_Match : std_logic := '0';
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Sample : DATA_TYPE := x"00";
signal RAM_Addr : std_logic_vector(9 downto 0) := (others => '0');
69,20 → 70,20
signal Average : DATA_TYPE := x"00";
begin
 
Addr_Match <= Open8_Bus.Rd_En when Comp_Addr = User_Addr else '0';
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
elsif( rising_edge( Clock ) )then
 
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
 
if( Rd_En = '1' )then
if( Rd_En_q = '1' )then
Rd_Data <= Average;
end if;
end if;
/VHDL/o8_ram_1k.vhd
82,10 → 82,10
signal WPR_Addr_Match : std_logic := '0';
 
alias WPR_Reg_Sel_d is Open8_Bus.Address(0);
signal WPR_Reg_Sel : std_logic := '0';
signal WPR_Reg_Sel_q : std_logic := '0';
 
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data : DATA_TYPE := x"00";
signal WPR_Wr_Data_q : DATA_TYPE := x"00";
 
signal Write_Mask : std_logic_vector(15 downto 0) :=
x"0000";
92,8 → 92,10
alias Write_Mask_0 is Write_Mask(7 downto 0);
alias Write_Mask_1 is Write_Mask(15 downto 8);
 
signal WPR_Wr_En : std_logic := '0';
signal WPR_Rd_En : std_logic := '0';
signal WPR_Wr_En_d : std_logic := '0';
signal WPR_Wr_En_q : std_logic := '0';
signal WPR_Rd_En_d : std_logic := '0';
signal WPR_Rd_En_q : std_logic := '0';
 
alias RAM_Base_Addr is Open8_Bus.Address(15 downto 10);
alias RAM_Addr is Open8_Bus.Address(9 downto 0);
103,8 → 105,9
signal RAM_Region_Match : std_logic := '0';
signal RAM_Addr_Match : std_logic := '0';
 
signal RAM_Wr_En : std_logic := '0';
signal RAM_Rd_En : std_logic := '0';
signal RAM_Wr_En_d : std_logic := '0';
signal RAM_Rd_En_d : std_logic := '0';
signal RAM_Rd_En_q : std_logic := '0';
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
begin
112,6 → 115,8
Write_Protect_On : if( Write_Protect )generate
 
WPR_Addr_Match <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
WPR_Wr_En_d <= WPR_Addr_Match and Wr_En and ISR_En;
WPR_Rd_En_d <= WPR_Addr_Match and Rd_En;
 
RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
118,44 → 123,46
RAM_Region_Match <= Write_Mask(conv_integer(RAM_Rgn_Addr)) or
ISR_En;
 
RAM_Wr_En <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
RAM_Rd_En_d <= RAM_Addr_Match and Rd_En;
RAM_Wr_En_d <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
Write_Mask <= Default_Mask;
WPR_Reg_Sel_q <= '0';
WPR_Wr_Data_q <= x"00";
 
WPR_Reg_Sel <= '0';
WPR_Wr_En_q <= '0';
WPR_Rd_En_q <= '0';
 
WPR_Wr_En <= '0';
WPR_Rd_En <= '0';
Write_Mask <= Default_Mask;
 
RAM_Rd_En <= '0';
RAM_Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
WPR_Reg_Sel <= WPR_Reg_Sel_d;
WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
 
WPR_Wr_En <= WPR_Addr_Match and Wr_En and ISR_En;
Wr_Data <= Wr_Data_d;
if( WPR_Wr_En = '1' )then
case( WPR_Reg_Sel )is
WPR_Wr_En_q <= WPR_Wr_En_d;
WPR_Wr_Data_q <= Wr_Data_d;
if( WPR_Wr_En_q = '1' )then
case( WPR_Reg_Sel_q )is
when '0' =>
Write_Mask_0 <= Wr_Data;
Write_Mask_0 <= WPR_Wr_Data_q;
when '1' =>
Write_Mask_1 <= Wr_Data;
Write_Mask_1 <= WPR_Wr_Data_q;
when others =>
null;
end case;
end if;
 
WPR_Rd_En <= WPR_Addr_Match and Rd_En;
RAM_Rd_En <= RAM_Addr_Match and Rd_En;
WPR_Rd_En_q <= WPR_Rd_En_d;
RAM_Rd_En_q <= RAM_Rd_En_d;
 
Rd_Data <= OPEN8_NULLBUS;
if( RAM_Rd_En = '1' )then
if( RAM_Rd_En_q = '1' )then
Rd_Data <= RAM_Rd_Data;
elsif( WPR_Rd_En = '1' )then
case( WPR_Reg_Sel )is
elsif( WPR_Rd_En_q = '1' )then
case( WPR_Reg_Sel_q )is
when '0' =>
Rd_Data <= Write_Mask_0;
when '1' =>
173,17 → 180,18
 
RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
RAM_Wr_En <= RAM_Addr_Match and Open8_Bus.Wr_En;
RAM_Rd_En_d <= RAM_Addr_Match and Open8_Bus.Rd_En;
RAM_Wr_En_d <= RAM_Addr_Match and Open8_Bus.Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
RAM_Rd_En <= '0';
RAM_Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
RAM_Rd_En <= RAM_Addr_Match and Open8_Bus.Rd_En;
RAM_Rd_En_q <= RAM_Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
if( RAM_Rd_En = '1' )then
if( RAM_Rd_En_q = '1' )then
Rd_Data <= RAM_Rd_Data;
end if;
end if;
197,7 → 205,7
address => RAM_Addr,
clock => Clock,
data => Wr_Data_d,
wren => RAM_Wr_En,
wren => RAM_Wr_En_d,
q => RAM_Rd_Data
);
 
/VHDL/o8_ram_4k.vhd
84,11 → 84,11
signal WPR_Addr_Match : std_logic := '0';
 
alias WPR_Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal WPR_Reg_Sel : std_logic_vector(1 downto 0) :=
signal WPR_Reg_Sel_q : std_logic_vector(1 downto 0) :=
(others => '0');
 
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data : DATA_TYPE := x"00";
signal WPR_Wr_Data_q : DATA_TYPE := x"00";
 
signal Write_Mask : std_logic_vector(31 downto 0) :=
x"00000000";
98,9 → 98,9
alias Write_Mask_3 is Write_Mask(31 downto 24);
 
signal WPR_Wr_En_d : std_logic := '0';
signal WPR_Wr_En : std_logic := '0';
signal WPR_Wr_En_q : std_logic := '0';
signal WPR_Rd_En_d : std_logic := '0';
signal WPR_Rd_En : std_logic := '0';
signal WPR_Rd_En_q : std_logic := '0';
 
alias RAM_Base_Addr is Open8_Bus.Address(15 downto 12);
alias RAM_Addr is Open8_Bus.Address(11 downto 0);
110,8 → 110,9
signal RAM_Region_Match : std_logic := '0';
signal RAM_Addr_Match : std_logic := '0';
 
signal RAM_Wr_En : std_logic := '0';
signal RAM_Rd_En : std_logic := '0';
signal RAM_Wr_En_d : std_logic := '0';
signal RAM_Rd_En_d : std_logic := '0';
signal RAM_Rd_En_q : std_logic := '0';
signal RAM_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
begin
119,6 → 120,8
Write_Protect_On : if( Write_Protect )generate
 
WPR_Addr_Match <= '1' when WPR_Comp_Addr = WPR_User_Addr else '0';
WPR_Wr_En_d <= WPR_Addr_Match and Wr_En and ISR_En;
WPR_Rd_En_d <= WPR_Addr_Match and Rd_En;
 
RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
125,48 → 128,51
RAM_Region_Match <= Write_Mask(conv_integer(RAM_Rgn_Addr)) or
ISR_En;
 
RAM_Wr_En <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
RAM_Rd_En_d <= RAM_Addr_Match and Rd_En;
RAM_Wr_En_d <= RAM_Addr_Match and RAM_Region_Match and Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
Write_Mask <= Default_Mask;
 
WPR_Reg_Sel <= (others => '0');
WPR_Reg_Sel_q <= (others => '0');
WPR_Wr_Data_q <= x"00";
 
WPR_Wr_En <= '0';
WPR_Rd_En <= '0';
WPR_Wr_En_q <= '0';
WPR_Rd_En_q <= '0';
 
RAM_Rd_En <= '0';
Write_Mask <= Default_Mask;
 
RAM_Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
WPR_Reg_Sel <= WPR_Reg_Sel_d;
WPR_Reg_Sel_q <= WPR_Reg_Sel_d;
 
WPR_Wr_En <= WPR_Addr_Match and Wr_En and ISR_En;
Wr_Data <= Wr_Data_d;
if( WPR_Wr_En = '1' )then
case( WPR_Reg_Sel )is
WPR_Wr_En_q <= WPR_Wr_En_d;
WPR_Wr_Data_q <= Wr_Data_d;
if( WPR_Wr_En_q = '1' )then
case( WPR_Reg_Sel_q )is
when "00" =>
Write_Mask_0 <= Wr_Data;
Write_Mask_0 <= WPR_Wr_Data_q;
when "01" =>
Write_Mask_1 <= Wr_Data;
Write_Mask_1 <= WPR_Wr_Data_q;
when "10" =>
Write_Mask_2 <= Wr_Data;
Write_Mask_2 <= WPR_Wr_Data_q;
when "11" =>
Write_Mask_3 <= Wr_Data;
Write_Mask_3 <= WPR_Wr_Data_q;
when others =>
null;
end case;
end if;
 
WPR_Rd_En <= WPR_Addr_Match and Rd_En;
RAM_Rd_En <= RAM_Addr_Match and Rd_En;
WPR_Rd_En_q <= WPR_Rd_En_d;
RAM_Rd_En_q <= RAM_Rd_En_d;
 
Rd_Data <= OPEN8_NULLBUS;
if( RAM_Rd_En = '1' )then
if( RAM_Rd_En_q = '1' )then
Rd_Data <= RAM_Rd_Data;
elsif( WPR_Rd_En = '1' )then
case( WPR_Reg_Sel )is
elsif( WPR_Rd_En_q = '1' )then
case( WPR_Reg_Sel_q )is
when "00" =>
Rd_Data <= Write_Mask_0;
when "01" =>
188,17 → 194,18
 
RAM_Addr_Match <= '1' when RAM_Base_Addr = RAM_User_Addr else '0';
 
RAM_Wr_En <= RAM_Addr_Match and Open8_Bus.Wr_En;
RAM_Rd_En_d <= RAM_Addr_Match and Open8_Bus.Rd_En;
RAM_Wr_En_d <= RAM_Addr_Match and Open8_Bus.Wr_En;
 
RAM_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
RAM_Rd_En <= '0';
RAM_Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge(Clock) )then
RAM_Rd_En <= RAM_Addr_Match and Open8_Bus.Rd_En;
RAM_Rd_En_q <= RAM_Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
if( RAM_Rd_En = '1' )then
if( RAM_Rd_En_q = '1' )then
Rd_Data <= RAM_Rd_Data;
end if;
end if;
212,7 → 219,7
address => RAM_Addr,
clock => Clock,
data => Wr_Data_d,
wren => RAM_Wr_En,
wren => RAM_Wr_En_d,
q => RAM_Rd_Data
);
 
/VHDL/o8_register.vhd
33,6 → 33,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 12/20/19 Design Start
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
50,6 → 51,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
--
Register_Out : out DATA_TYPE
65,33 → 67,40
:= Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
signal Reg_Out : DATA_TYPE;
signal Rd_En : std_logic;
 
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Reg_Out : DATA_TYPE := x"00";
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_En <= '0';
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Reg_Out <= Default_Value;
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
if( Wr_En_q = '1' and Write_Qual = '1' )then
Reg_Out <= Wr_Data_q;
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
Rd_Data <= Reg_Out;
end if;
end if;
/VHDL/o8_rtc.vhd
47,6 → 47,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
63,6 → 64,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
--
Interrupt_PIT : out std_logic;
76,18 → 78,21
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
 
constant User_Addr : std_logic_vector(15 downto 3)
:= Address(15 downto 3);
constant User_Addr : std_logic_vector(15 downto 3) :=
Address(15 downto 3);
 
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
signal Addr_Match : std_logic;
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Open8_Bus.Address(2 downto 0);
signal Reg_Addr_q : std_logic_vector(2 downto 0);
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0) := (others => '0');
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
signal Rd_En : std_logic;
 
type PIT_TYPE is record
timer_cnt : DATA_TYPE;
timer_ro : std_logic;
147,6 → 152,8
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
Interrupt_PIT <= pit.timer_ro;
Interrupt_RTC <= rtc.frac_ro;
154,6 → 161,12
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= "000";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
pit.timer_cnt <= x"00";
pit.timer_ro <= '0';
 
199,12 → 212,6
interval <= x"00";
update_interval <= '0';
 
Wr_Data_q <= (others => '0');
Reg_Addr_q <= (others => '0');
Wr_En <= '0';
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
 
elsif( rising_edge( Clock ) )then
 
-- Periodic Interval Timer
329,13 → 336,14
 
update_interval <= '0';
 
Reg_Addr_q <= Reg_Addr;
Wr_Data_q <= Open8_Bus.Wr_Data;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
update_rtc <= '0';
if( Wr_En = '1' )then
case( Reg_Addr_q )is
if( Wr_En_q = '1' )then
case( Reg_Sel_q )is
when "000" =>
interval <= Wr_Data_q;
update_interval <= '1';
373,10 → 381,10
update_ctmr <= (others => '1');
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Addr_q )is
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "000" =>
Rd_Data <= interval;
when "001" =>
/VHDL/o8_sdlc_if.vhd
64,6 → 64,7
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
89,6 → 90,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
-- Serial IO
110,10 → 112,11
alias CPU_Upper_Addr is Open8_Bus.Address(15 downto 9);
signal Base_Addr_Match : std_logic := '0';
 
alias DP_A_Addr is Open8_Bus.Address(8 downto 0);
alias DP_A_Addr is Open8_Bus.Address(8 downto 0);
signal DP_A_Wr_En : std_logic := '0';
alias DP_A_Wr_Data is Open8_Bus.Wr_Data;
signal DP_A_Rd_En : std_logic := '0';
signal DP_A_Rd_En_d : std_logic := '0';
signal DP_A_Rd_En_q : std_logic := '0';
signal DP_A_Rd_Data : DATA_TYPE := OPEN8_NULLBUS;
 
constant Reg_Sub_Addr : std_logic_vector(8 downto 1) := x"7F";
122,7 → 125,8
 
signal Reg_Addr : std_logic_vector(8 downto 1) := (others => '0');
signal Reg_Sel : std_logic := '0';
signal Reg_Wr_En : std_logic := '0';
signal Reg_Wr_En_d : std_logic := '0';
signal Reg_Wr_En_q : std_logic := '0';
signal Reg_Clk_Sel : std_logic := '0';
signal Reg_TxS_Sel : std_logic := '0';
 
185,33 → 189,41
-- This decode needs to happen immediately, to give the RAM a chance to
-- do the lookup before we have to set Rd_Data
Base_Addr_Match <= '1' when Base_Addr = CPU_Upper_Addr else '0';
DP_A_Wr_En <= Base_Addr_Match and Open8_Bus.Wr_En;
Reg_Wr_En_d <= Base_Addr_Match and
Open8_Bus.Wr_En and
Write_Qual;
 
DP_A_Wr_En <= Base_Addr_Match and
Open8_Bus.Wr_En and
Write_Qual;
 
DP_A_Rd_En_d <= Base_Addr_Match and Open8_Bus.Rd_En;
 
CPU_IF_proc: process( Reset, Clock )
begin
if( Reset = Reset_Level )then
Reg_Addr <= (others => '0');
Reg_Wr_En <= '0';
Reg_Wr_En_q <= '0';
Reg_Clk_Sel <= '0';
Reg_TxS_Sel <= '0';
DP_A_Rd_En <= '0';
DP_A_Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Interrupt <= '0';
elsif( rising_edge(Clock) )then
Reg_Addr <= Reg_Upper_Addr;
Reg_Sel <= Reg_Lower_Addr;
Reg_Wr_En <= Base_Addr_Match and Open8_Bus.Wr_En;
Reg_Wr_En_q <= Reg_Wr_En_d;
 
Reg_Clk_Sel <= '0';
Reg_TxS_Sel <= '0';
if( Reg_Addr = Reg_Sub_Addr )then
Reg_Clk_Sel <= Reg_Wr_En and not Reg_Sel;
Reg_TxS_Sel <= Reg_Wr_En and Reg_Sel;
Reg_Clk_Sel <= Reg_Wr_En_q and not Reg_Sel;
Reg_TxS_Sel <= Reg_Wr_En_q and Reg_Sel;
end if;
 
DP_A_Rd_En <= Base_Addr_Match and Open8_Bus.Rd_En;
DP_A_Rd_En_q <= DP_A_Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
if( DP_A_Rd_En = '1' )then
if( DP_A_Rd_En_q = '1' )then
Rd_Data <= DP_A_Rd_Data;
end if;
 
/VHDL/o8_status_led.vhd
40,6 → 40,7
------------------ -------- ---------------------------------------------------
-- Seth Henry 12/20/19 Design Start
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
56,6 → 57,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
--
LED_Out : out std_logic
71,10 → 73,15
:= Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : std_logic_vector(2 downto 0);
 
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal LED_Mode : std_logic_vector(2 downto 0);
signal Rd_En : std_logic;
 
signal Dim50Pct_Out : std_logic;
 
92,25 → 99,27
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_En <= '0';
Wr_Data_q <= (others => '0');
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
LED_Mode <= (others => '0');
Rd_En <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data(2 downto 0);
if( Wr_En = '1' )then
LED_Mode <= Wr_Data_q;
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
if( Wr_En_q = '1' and Write_Qual = '1' )then
LED_Mode <= Wr_Data_q(2 downto 0);
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
if( Rd_En_q = '1' )then
Rd_Data <= "00000" & LED_Mode;
end if;
 
/VHDL/o8_sys_timer.vhd
38,6 → 38,7
-- Seth Henry 04/09/20 Modified timer update logic to reset the timer on
-- interval write.
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
50,11 → 51,11
 
entity o8_sys_timer is
generic(
Write_Protect : boolean := FALSE;
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
65,19 → 66,16
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
alias ISR_En is Open8_Bus.GP_Flags(EXT_ISR);
 
signal Wr_En_d : std_logic;
signal Rd_En_d : std_logic;
 
alias Wr_Data is Open8_Bus.Wr_Data;
 
constant User_Addr : ADDRESS_TYPE := Address;
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
 
signal Wr_En_d : std_logic;
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Interval : DATA_TYPE := x"00";
87,41 → 85,30
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
 
-- If the Write_Protect generic is set only allow the memory to be written
-- if the ISR bit is set. Otherwise, the memory should be read-only
 
Write_Protect_On : if( Write_Protect )generate
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and ISR_En;
end generate;
 
Write_Protect_Off : if( not Write_Protect )generate
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
end generate;
 
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_En <= '0';
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Interval <= x"00";
Update_Interval <= '0';
elsif( rising_edge( Clock ) )then
Wr_En <= Wr_En_d;
Wr_Data_q <= Wr_Data;
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
Update_Interval <= Wr_En;
if( Wr_En = '1' )then
Update_Interval <= Wr_En_q and Write_Qual;
if( Wr_En_q = '1' and Write_Qual = '1' )then
Interval <= Wr_Data_q;
end if;
 
Rd_Data <= (others => '0');
Rd_En <= Rd_En_d;
if( Rd_En = '1' )then
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
Rd_Data <= Interval;
end if;
end if;
/VHDL/o8_sys_timer_ii.vhd
46,6 → 46,7
-- interval write.
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 04/17/20 Altered interval to be a 24-bit counter
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
62,6 → 63,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic
);
76,13 → 78,15
constant User_Addr : std_logic_vector(15 downto 2) :=
Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Addr_Match : std_logic := '0';
 
signal Addr_Match : std_logic := '0';
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
signal Wr_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Wr_En_d : std_logic;
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Req_Interval : std_logic_vector(23 downto 0) := x"000000";
100,14 → 104,16
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Wr_En <= '0';
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Req_Interval <= x"000000";
Update_Interval <= '0';
114,13 → 120,13
Update_Pending <= '0';
Output_Enable <= '0';
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
Update_Interval <= '0';
if( Wr_En = '1' )then
case( Reg_Sel )is
if( Wr_En_q = '1' and Write_Qual = '1' )then
case( Reg_Sel_q )is
when "00" =>
Req_Interval_B0 <= Wr_Data_q;
Update_Pending <= '1';
142,9 → 148,9
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Sel )is
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= Req_Interval_B0;
when "01" =>
/VHDL/o8_trig_delay.vhd
0,0 → 1,401
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Entity: o8_trig_delay
-- Description: Receives a 6-bit vector command and 16-bit argument from the
-- vector_tx entity. Issues interrupt to the CPU on receipt of
-- three bytes.
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x0 AAAAAAAA Delay Time Byte 0 (RW)
-- 0x1 AAAAAAAA Delay Time Byte 1 (RW)
-- 0x2 AAAAAAAA Delay Time Byte 2 (RW)
-- 0x3 AAAAAAAA Pulse Width Byte 0 (RW)
-- 0x4 AAAAAAAA Pulse Width Byte 1 (RW)
-- 0x5 AAAAAAAA Pulse Width Byte 2 (RW)
-- 0x6 EDCBAA-- Time Configuration (RW*)
-- A: Interrupt Select
-- 00 - Disabled
-- 01 - Interrupt on trigger event
-- 10 - Interrupt on delay done
-- 11 - Interrupt on pulse done
-- B: Trigger Edge
-- 0 - Trigger on falling edge
-- 1 - Trigger on rising edge
-- C: Automatic Re-Arm (enabled if 1)
-- D: Time base locked (okay if 1) (read-only)
-- E: Time base source
-- 0 - Use the internal uSec_Tick pulse
-- 1 - Use an external clock source
-- 0x7 DCBA---- Timer Control (RW*)
-- A: Current output level (read-only)
-- B: Clear/Re-Arm on '1' (one-shot)
-- Trigger event status on read
-- C: Disable/Safe Trigger (one-shot)
-- Returns '0' on read
-- D: Enable/Arm Trigger (one-shot)
-- Trigger armed status on read
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/14/20 Design start
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.open8_pkg.all;
 
entity o8_trig_delay is
generic(
Default_Delay : std_logic_vector(23 downto 0) := x"000000";
Default_Width : std_logic_vector(23 downto 0) := x"000000";
Default_Timebase : std_logic := '0';
Default_Auto_ReArm : std_logic := '0';
Default_Trigger_Edge : std_logic := '1';
Default_Int_Source : std_logic_vector(1 downto 0) := "00";
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
Time_Base_Clock : in std_logic := '0';
Time_Base_Locked : in std_logic := '1';
--
Ext_Trig : in std_logic;
Timer_Out : out std_logic
);
end entity;
 
architecture behave of o8_trig_delay is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
alias uSec_Tick is Open8_Bus.uSec_Tick;
alias Wr_Data_d is Open8_Bus.Wr_Data;
 
constant User_Addr : std_logic_vector(15 downto 3) :=
Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
 
signal Addr_Match : std_logic := '0';
signal Reg_Sel_q : std_logic_vector(2 downto 0) := "000";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
-- Configuration Registers
 
signal Pulse_Delay : std_logic_vector(23 downto 0) := x"000000";
alias Pulse_Delay_B0 is Pulse_Delay( 7 downto 0);
alias Pulse_Delay_B1 is Pulse_Delay(15 downto 8);
alias Pulse_Delay_B2 is Pulse_Delay(23 downto 16);
 
signal Pulse_Width : std_logic_vector(23 downto 0) := x"000000";
alias Pulse_Width_B0 is Pulse_Width( 7 downto 0);
alias Pulse_Width_B1 is Pulse_Width(15 downto 8);
alias Pulse_Width_B2 is Pulse_Width(23 downto 16);
 
signal Time_Base_Source : std_logic := '0';
signal Time_Base_Status : std_logic := '0';
signal Auto_ReArm : std_logic := '0';
signal Trigger_Edge : std_logic := '0';
signal Interrupt_Select : std_logic_vector(1 downto 0);
 
signal Arm_Timer : std_logic := '0';
signal Safe_Timer : std_logic := '0';
signal Clear_Trigd : std_logic := '0';
 
-- Time Base signals
signal Ext_TBC_SR : std_logic_vector(3 downto 0) := "0000";
signal Ext_TBL_SR : std_logic_vector(3 downto 0) := "0000";
 
signal Timer_Tick : std_logic := '0';
 
-- Trigger signals
signal Ext_Trig_SR : std_logic_vector(3 downto 0) := "0000";
signal Trig_RE : std_logic := '0';
signal Trig_FE : std_logic := '0';
signal Delay_Trig : std_logic := '0';
signal Trigger_Armed : std_logic := '0';
signal Trigger_Event : std_logic := '0';
 
-- Delay Timer signals
signal Delay_Pending : std_logic := '0';
signal Delay_Tmr : std_logic_vector(23 downto 0) := x"000000";
signal Delay_Tmr_SR : std_logic_vector(1 downto 0);
signal Width_Trig : std_logic := '0';
 
-- Pulse Timer signals
signal Width_Tmr : std_logic_vector(23 downto 0) := x"000000";
signal Width_Tmr_SR : std_logic_vector(1 downto 0);
signal Pulse_Out : std_logic := '0';
signal Pulse_Done : std_logic := '0';
 
begin
 
Timer_Out <= Pulse_Out;
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel_q <= (others => '0');
Wr_En_q <= '0';
Wr_Data_q <= (others => '0');
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Pulse_Delay <= Default_Delay;
Pulse_Width <= Default_Width;
Time_Base_Source <= Default_Timebase;
Auto_ReArm <= Default_Auto_ReArm;
Trigger_Edge <= Default_Trigger_Edge;
Interrupt_Select <= Default_Int_Source;
Arm_Timer <= '0';
Safe_Timer <= '0';
Clear_Trigd <= '0';
Interrupt <= '0';
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
 
Arm_Timer <= '0';
Safe_Timer <= '0';
Clear_Trigd <= '0';
 
if( Wr_En_q = '1' and Write_Qual = '1' )then
case( Reg_Sel_q )is
when "000" =>
Pulse_Delay_B0 <= Wr_Data_q;
when "001" =>
Pulse_Delay_B1 <= Wr_Data_q;
when "010" =>
Pulse_Delay_B2 <= Wr_Data_q;
 
when "011" =>
Pulse_Width_B0 <= Wr_Data_q;
when "100" =>
Pulse_Width_B1 <= Wr_Data_q;
when "101" =>
Pulse_Width_B2 <= Wr_Data_q;
 
when "110" =>
Time_Base_Source <= Wr_Data_q(7);
-- Reserved for status bit
Auto_ReArm <= Wr_Data_q(5);
Trigger_Edge <= Wr_Data_q(4);
Interrupt_Select <= Wr_Data_q(3 downto 2);
 
when "111" =>
Arm_Timer <= Wr_Data_q(7);
Safe_Timer <= Wr_Data_q(6);
Clear_Trigd <= Wr_Data_q(5);
when others => null;
end case;
end if;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "000" =>
Rd_Data <= Pulse_Delay_B0;
when "001" =>
Rd_Data <= Pulse_Delay_B1;
when "010" =>
Rd_Data <= Pulse_Delay_B2;
 
when "011" =>
Rd_Data <= Pulse_Width_B0;
when "100" =>
Rd_Data <= Pulse_Width_B1;
when "101" =>
Rd_Data <= Pulse_Width_B2;
 
when "110" =>
Rd_Data <= Time_Base_Source & -- Bit 7
Time_Base_Status & -- Bit 6
Auto_ReArm & -- Bit 5
Trigger_Edge & -- Bit 4
Interrupt_Select & -- Bits 3:2
"00"; -- Bits 1:0
when "111" =>
Rd_Data <= Trigger_Armed & -- Bit 7
'0' & -- Bit 6
Trigger_Event & -- Bit 5
Pulse_Out & -- Bit 4
"0000"; -- Bits 3:0
when others => null;
end case;
end if;
 
case( Interrupt_Select )is
when "00" =>
Interrupt <= '0';
when "01" =>
Interrupt <= Delay_Trig;
when "10" =>
Interrupt <= Width_Trig;
when "11" =>
Interrupt <= Pulse_Done;
when others =>
null;
end case;
 
end if;
end process;
 
Time_Base_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Ext_TBC_SR <= (others => '0');
Ext_TBL_SR <= (others => '0');
Time_Base_Status <= '0';
Timer_Tick <= '0';
elsif( rising_edge(Clock) )then
Ext_TBC_SR <= Ext_TBC_SR(2 downto 0) & Time_Base_Clock;
Ext_TBL_SR <= Ext_TBL_SR(2 downto 0) & Time_Base_Locked;
 
Time_Base_Status <= '1';
Timer_Tick <= uSec_Tick;
if( Time_Base_Source = '1' )then
Time_Base_Status <= Ext_TBL_SR(3);
Timer_Tick <= Ext_TBC_SR(2) and not Ext_TBC_SR(3);
end if;
 
end if;
end process;
 
Trigger_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Ext_Trig_SR <= (others => '0');
Trig_RE <= '0';
Trig_FE <= '0';
Delay_Trig <= '0';
Trigger_Armed <= '0';
Trigger_Event <= '0';
elsif( rising_edge(Clock) )then
Ext_Trig_SR <= Ext_Trig_SR(2 downto 0) & Ext_Trig;
 
Trig_RE <= Ext_Trig_SR(2) and not Ext_Trig_SR(3);
Trig_FE <= Ext_Trig_SR(3) and not Ext_Trig_SR(2);
 
Delay_Trig <= ((Trig_FE and not Trigger_Edge) or
(Trig_RE and Trigger_Edge)) and
Trigger_Armed and (not Trigger_Event);
 
if( Arm_Timer = '1' )then
Trigger_Armed <= '1';
elsif( Safe_Timer = '1' )then
Trigger_Armed <= '0';
end if;
 
if( Delay_Trig = '1' )then
Trigger_Event <= '1';
elsif( Clear_Trigd = '1' or Auto_ReArm = '1' )then
Trigger_Event <= '0';
end if;
 
end if;
end process;
 
Delay_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Delay_Pending <= '0';
Delay_Tmr <= (others => '0');
Delay_Tmr_SR <= (others => '0');
Width_Trig <= '0';
elsif( rising_edge(Clock) )then
 
if( Delay_Trig = '1' )then
Delay_Pending <= '1';
elsif( Timer_Tick = '1' and Delay_Pending = '1' )then
Delay_Pending <= '0';
end if;
 
Delay_Tmr <= Delay_Tmr - Timer_Tick;
if( Timer_Tick = '1' and Delay_Pending = '1' )then
Delay_Tmr <= Pulse_Delay;
elsif( Delay_Tmr = 0 )then
Delay_Tmr <= (others => '0');
end if;
 
Delay_Tmr_SR <= Delay_Tmr_SR(0) & nor_reduce(Delay_Tmr);
 
-- If the pulse delay is set to zero, trigger the pulse output
-- immediately (overriding the timer logic) otherwise, trigger when
-- the delay timer crosses from 1 to 0
Width_Trig <= (Delay_Trig and nor_reduce(Pulse_Delay)) or
(Delay_Tmr_SR(0) and not Delay_Tmr_SR(1));
 
end if;
end process;
 
Timer_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Width_Tmr <= (others => '0');
Pulse_Done <= '0';
Pulse_Out <= '0';
elsif( rising_edge(Clock) )then
Width_Tmr <= Width_Tmr - Timer_Tick;
if( Width_Trig = '1' )then
Width_Tmr <= Pulse_Width;
elsif( Width_Tmr = 0 )then
Width_Tmr <= (others => '0');
end if;
 
Width_Tmr_SR <= Width_Tmr_SR(0) & nor_reduce(Width_Tmr);
 
Pulse_Done <= (Width_Trig and nor_reduce(Pulse_Width)) or
(Width_Tmr_SR(0) and not Width_Tmr_SR(1));
 
if( Width_Trig = '1' )then
Pulse_Out <= '1';
elsif( Pulse_Done = '1' )then
Pulse_Out <= '0';
end if;
 
end if;
end process;
 
end architecture;
/VHDL/o8_vdsm12.vhd
37,6 → 37,7
-- Seth Henry 12/18/19 Design start
-- Seth Henry 04/10/20 Code Cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
53,6 → 54,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
--
DACOut : out std_logic
67,12 → 69,16
constant User_Addr : std_logic_vector(15 downto 2)
:= Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
signal Addr_Match : std_logic := '0';
signal Wr_En : std_logic := '0';
signal Addr_Match : std_logic;
 
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En : std_logic := '0';
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
constant DAC_Width : integer := 12;
 
188,25 → 194,28
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Reg_Sel <= "00";
Rd_En <= '0';
Reg_Sel_q <= "00";
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
Wr_En <= '0';
Wr_Data_q <= x"00";
 
DAC_Val_LB <= x"00";
DAC_Val_UB <= x"0";
DAC_Val <= Default_Value;
elsif( rising_edge( Clock ) )then
Reg_Sel <= Reg_Addr;
Reg_Sel_q <= Reg_Sel_d;
 
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
case( Reg_Sel )is
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
if( Wr_En_q = '1' and Write_Qual = '1' )then
case( Reg_Sel_q )is
when "00" =>
DAC_Val_LB <= Wr_Data_q;
when "01" =>
219,10 → 228,10
end case;
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
case( Reg_Sel )is
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= DAC_Val_LB;
when "01" =>
/VHDL/o8_vdsm8.vhd
34,6 → 34,8
-- Seth Henry 06/23/16 Design start
-- Seth Henry 04/10/20 Code Cleanup
-- Seth Henry 04/16/20 Modified to use Open8 bus record
-- Seth Henry 05/18/20 Added write qualification input
-- Seth Henry 05/18/20 Added write qualification input
 
library ieee;
use ieee.std_logic_1164.all;
50,6 → 52,7
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Write_Qual : in std_logic := '1';
Rd_Data : out DATA_TYPE;
--
DACout : out std_logic
65,33 → 68,39
:= Address(15 downto 0);
alias Comp_Addr is Open8_Bus.Address(15 downto 0);
signal Addr_Match : std_logic;
signal Wr_En : std_logic;
signal Wr_Data_q : DATA_TYPE;
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
signal Wr_Data_q : DATA_TYPE := x"00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal Reg_Out : DATA_TYPE;
signal Rd_En : std_logic;
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En and Write_Qual;
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Wr_En <= '0';
Wr_En_q <= '0';
Wr_Data_q <= x"00";
Reg_Out <= Default_Value;
Rd_En <= '0';
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Wr_En <= Addr_Match and Open8_Bus.Wr_En;
Wr_Data_q <= Open8_Bus.Wr_Data;
if( Wr_En = '1' )then
Wr_En_q <= Wr_En_d;
Wr_Data_q <= Wr_Data_d;
if( Wr_En_q = '1' )then
Reg_Out <= Wr_Data_q;
end if;
 
Rd_En_q <= Rd_En_d;
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
if( Rd_En = '1' )then
if( Rd_En_q = '1' )then
Rd_Data <= Reg_Out;
end if;
end if;
/VHDL/o8_vector_rx.vhd
77,9 → 77,10
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
signal Rd_En : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0);
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00";
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
constant BAUD_RATE_DIV : integer := integer(Clock_Frequency / Bit_Rate);
 
113,19 → 114,21
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En;
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Reg_Sel <= (others => '0');
Reg_Sel_q <= (others => '0');
Rd_En_q <= '0';
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Reg_Sel_q <= Reg_Sel_d;
 
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Reg_Sel <= Reg_Addr;
if( Rd_En = '1' )then
case( Reg_Sel )is
Rd_En_q <= Rd_En_d;
if( Rd_En_q = '1' )then
case( Reg_Sel_q )is
when "00" =>
Rd_Data <= Vector_Cmd;
when "01" =>

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