URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc/trunk
- from Rev 295 to Rev 296
- ↔ Reverse comparison
Rev 295 → Rev 296
/VHDL/o8_elapsed_usec.vhd
123,12 → 123,8
Timer_Reset <= '0'; |
if( Wr_En_q = '1' and Write_Qual = '1' )then |
case( Reg_Sel_q )is |
when "00" => |
when "00" | "01" | "10" => |
Update_Shadow <= '1'; |
when "01" => |
Update_Shadow <= '1'; |
when "10" => |
Update_Shadow <= '1'; |
when "11" => |
Timer_Reset <= Wr_Data_q(6); |
Timer_En_Req <= Wr_Data_q(7); |
/VHDL/o8_vector_rx.vhd
1,4 → 1,4
-- Copyright (c)2020 Jeremy Seth Henry |
-- Copyright (c)2021 Jeremy Seth Henry |
-- All rights reserved. |
-- |
-- Redistribution and use in source and binary forms, with or without |
42,6 → 42,8
-- conditions instead |
-- Seth Henry 05/23/20 Added the parallel interface |
-- Seth Henry 04/07/21 Added checksum to prevent glitching on serial noise |
-- Seth Henry 09/15/21 Removed parallel interface and increased checksum |
-- to 16-bits. Also made the magic number a generic. |
|
library ieee; |
use ieee.std_logic_1164.all; |
54,6 → 56,7
|
entity o8_vector_rx is |
generic( |
Magic_Num : DATA_TYPE; |
Bit_Rate : real; |
Enable_Parity : boolean; |
Parity_Odd_Even_n : std_logic; |
64,12 → 67,9
Open8_Bus : in OPEN8_BUS_TYPE; |
Rd_Data : out DATA_TYPE; |
Interrupt : out std_logic; |
-- Parallel Interface |
Vec_Req : in std_logic; |
Vec_Index : in std_logic_vector(5 downto 0); |
Vec_Data : in std_logic_vector(15 downto 0); |
-- Serial Interface |
Vec_Rx : in std_logic |
Rx_In : in std_logic; |
RX_FC : out std_logic |
); |
end entity; |
|
85,6 → 85,10
|
alias Reg_Sel_d is Open8_Bus.Address(1 downto 0); |
signal Reg_Sel_q : std_logic_vector(1 downto 0) := "00"; |
|
signal Wr_En_d : std_logic := '0'; |
signal Wr_En_q : std_logic := '0'; |
|
signal Rd_En_d : std_logic := '0'; |
signal Rd_En_q : std_logic := '0'; |
|
99,12 → 103,12
|
signal Rx_Baud_Cntr : std_logic_vector(Baud_Bits - 1 downto 0) := |
(others => '0'); |
signal Rx_Baud_Tick : std_logic; |
signal Rx_Baud_Tick : std_logic := '0'; |
|
signal Vec_Rx_SR : std_logic_vector(2 downto 0); |
signal Vec_Rx_SR : std_logic_vector(2 downto 0) := "000"; |
alias Vec_Rx_MS is Vec_Rx_SR(2); |
signal Rx_Idle_Cntr : std_logic_vector(3 downto 0); |
signal RX_Idle : std_logic; |
signal Rx_Idle_Cntr : std_logic_vector(3 downto 0) := "0000"; |
signal Rx_Idle : std_logic := '0'; |
signal Rx_Data : DATA_TYPE := x"00"; |
signal Rx_Valid : std_logic; |
|
112,25 → 116,31
GET_VECTOR_CMD, |
GET_VECTOR_ARG_LB, |
GET_VECTOR_ARG_UB, |
GET_VECTOR_SUM, |
GET_VECTOR_SUM_LB, |
GET_VECTOR_SUM_UB, |
SEND_INTERRUPT ); |
signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD; |
|
signal Vec_Req_SR : std_logic_vector(2 downto 0); |
alias Vec_Req_MS is Vec_Req_SR(2); |
signal Vec_Req_SR : std_logic_vector(2 downto 0) := "000"; |
alias Vec_Req_MS is Vec_Req_SR(2); |
|
signal Vector_Index : DATA_TYPE := x"00"; |
signal Vector_Index : DATA_TYPE := x"00"; |
signal Vector_Data : ADDRESS_TYPE := x"0000"; |
alias Vector_Data_LB is Vector_Data(7 downto 0); |
alias Vector_Data_UB is Vector_Data(15 downto 8); |
signal Vector_RX_Sum : DATA_TYPE := x"00"; |
signal Vector_RX_Sum : ADDRESS_TYPE := x"0000"; |
alias Vector_RX_Sum_LB is Vector_RX_Sum(7 downto 0); |
alias Vector_RX_Sum_UB is Vector_RX_Sum(15 downto 8); |
|
constant MAGIC_NUM : DATA_TYPE := x"4D"; |
signal Checksum : DATA_TYPE := x"00"; |
signal Checksum : ADDRESS_TYPE := x"0000"; |
|
signal Interrupt_Req : std_logic := '0'; |
signal Interrupt_Pending : std_logic := '0'; |
|
begin |
|
Addr_Match <= '1' when Comp_Addr = User_Addr else '0'; |
Wr_En_d <= Addr_Match and Open8_Bus.Wr_En; |
Rd_En_d <= Addr_Match and Open8_Bus.Rd_En; |
|
io_reg: process( Clock, Reset ) |
137,11 → 147,14
begin |
if( Reset = Reset_Level )then |
Reg_Sel_q <= (others => '0'); |
Wr_En_q <= '0'; |
Rd_En_q <= '0'; |
Rd_Data <= OPEN8_NULLBUS; |
Interrupt <= '0'; |
Interrupt_Pending <= '0'; |
elsif( rising_edge( Clock ) )then |
Reg_Sel_q <= Reg_Sel_d; |
|
Wr_En_q <= Wr_En_d; |
Rd_Data <= OPEN8_NULLBUS; |
Rd_En_q <= Rd_En_d; |
if( Rd_En_q = '1' )then |
152,10 → 165,22
Rd_Data <= Vector_Data_LB; |
when "10" => |
Rd_Data <= Vector_Data_UB; |
when "11" => |
Rd_Data <= Interrupt_Pending & "0000000"; |
when others => |
null; |
end case; |
end case; |
end if; |
|
Interrupt <= Interrupt_Req; |
if( Interrupt_Req = '1' )then |
Interrupt_Pending <= '1'; |
elsif( Wr_En_q = '1' )then |
Interrupt_Pending <= '0'; |
end if; |
|
RX_FC <= not Interrupt_Pending; |
|
end if; |
end process; |
|
175,7 → 200,7
Rx_Baud_Tick <= '1'; |
end if; |
|
Vec_Rx_SR <= Vec_Rx_SR(1 downto 0) & Vec_Rx; |
Vec_Rx_SR <= Vec_Rx_SR(1 downto 0) & Rx_In; |
Rx_Idle_Cntr <= Rx_Idle_Cntr - Rx_Baud_Tick; |
if( Vec_Rx_MS = '0' )then |
Rx_Idle_Cntr <= (others => '1'); |
182,7 → 207,6
elsif( Rx_Idle_Cntr = 0 )then |
Rx_Idle_Cntr <= (others => '0'); |
end if; |
|
Rx_Idle <= nor_reduce(Rx_Idle_Cntr); |
end if; |
end process; |
198,7 → 222,7
Clock => Clock, |
Reset => Reset, |
-- |
RX_In => Vec_Rx, |
RX_In => Rx_In, |
-- |
Rx_Data => RX_Data, |
Rx_Valid => RX_Valid, |
212,33 → 236,26
Vector_State <= CHECKSUM_INIT; |
Vector_Index <= x"00"; |
Vector_Data <= x"0000"; |
Interrupt <= '0'; |
Checksum <= x"0000"; |
Interrupt_Req <= '0'; |
elsif( rising_edge(Clock) )then |
Vec_Req_SR <= Vec_Req_SR(1 downto 0) & Vec_Req; |
Interrupt_Req <= '0'; |
|
Interrupt <= '0'; |
|
if( Vec_Req_MS = '1' )then |
Vector_Index <= "00" & Vec_Index; |
Vector_Data <= Vec_Data; |
Interrupt <= '1'; |
end if; |
|
case( Vector_State )is |
when CHECKSUM_INIT => |
Checksum <= MAGIC_NUM; |
Checksum <= x"00" & Magic_Num; |
Vector_State <= GET_VECTOR_CMD; |
|
when GET_VECTOR_CMD => |
if( Rx_Valid = '1' )then |
Checksum <= Checksum + Rx_Data; |
Vector_Index <= "00" & Rx_Data(5 downto 0); |
Checksum <= Checksum + (x"00" & Rx_Data); |
Vector_Index <= Rx_Data; |
Vector_State <= GET_VECTOR_ARG_LB; |
end if; |
|
when GET_VECTOR_ARG_LB => |
if( Rx_Valid = '1' )then |
Checksum <= Checksum + Rx_Data; |
Checksum <= Checksum + (x"00" & Rx_Data); |
Vector_Data_LB <= Rx_Data; |
Vector_State <= GET_VECTOR_ARG_UB; |
end if; |
245,26 → 262,32
|
when GET_VECTOR_ARG_UB => |
if( Rx_Valid = '1' )then |
Checksum <= Checksum + Rx_Data; |
Checksum <= Checksum + (x"00" & Rx_Data); |
Vector_Data_UB <= Rx_Data; |
Vector_State <= GET_VECTOR_SUM; |
Vector_State <= GET_VECTOR_SUM_LB; |
end if; |
|
when GET_VECTOR_SUM => |
when GET_VECTOR_SUM_LB => |
if( Rx_Valid = '1' )then |
Vector_RX_Sum <= Rx_Data; |
Vector_RX_Sum_LB <= Rx_Data; |
Vector_State <= GET_VECTOR_SUM_UB; |
end if; |
|
when GET_VECTOR_SUM_UB => |
if( Rx_Valid = '1' )then |
Vector_RX_Sum_UB <= Rx_Data; |
Vector_State <= SEND_INTERRUPT; |
end if; |
|
when SEND_INTERRUPT => |
if( Checksum = Vector_RX_Sum )then |
Interrupt <= '1'; |
Interrupt_Req <= '1'; |
end if; |
Vector_State <= CHECKSUM_INIT; |
when others => null; |
end case; |
|
if( Rx_Idle = '1' )then |
if( Rx_Idle = '1' or Interrupt_Pending = '1' )then |
Vector_State <= CHECKSUM_INIT; |
end if; |
|
/VHDL/vector_tx.vhd
1,4 → 1,4
-- Copyright (c)2020 Jeremy Seth Henry |
-- Copyright (c)2021 Jeremy Seth Henry |
-- All rights reserved. |
-- |
-- Redistribution and use in source and binary forms, with or without |
32,6 → 32,7
-- Seth Henry 05/06/20 Added version block |
-- Seth Henry 04/07/21 Modified to replace hard-coded blocks with true |
-- argument inputs. |
-- Seth Henry 09/15/21 Added flow control and made the Magic_Num a generic |
|
library ieee; |
use ieee.std_logic_1164.all; |
44,11 → 45,11
|
entity vector_tx is |
generic( |
Button_Level : std_logic; |
Magic_Num : DATA_TYPE := x"4D"; |
Bit_Rate : real; |
Enable_Parity : boolean; |
Parity_Odd_Even_n : std_logic; |
Sys_Freq : real; |
Clock_Frequency : real; |
Reset_Level : std_logic |
); |
port( |
73,17 → 74,19
signal Arg_Lower_Buffer : DATA_TYPE := x"00"; |
signal Arg_Upper_Buffer : DATA_TYPE := x"00"; |
|
type VECTOR_TX_STATES is (IDLE, |
type VECTOR_TX_STATES is (IDLE, WAIT_FC, |
SEND_CMD, WAIT_CMD, |
SEND_ARG_LB, WAIT_ARG_LB, |
SEND_ARG_UB, WAIT_ARG_UB, |
SEND_SUM, WAIT_SUM ); |
SEND_SUM_LB, WAIT_SUM_LB, |
SEND_SUM_UB, WAIT_SUM_UB ); |
signal Vector_State : VECTOR_TX_STATES := IDLE; |
|
constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate); |
constant BAUD_RATE_DIV : integer := integer(Clock_Frequency / Bit_Rate); |
|
constant MAGIC_NUM : DATA_TYPE := x"4D"; |
signal Checksum : DATA_TYPE := x"00"; |
signal Checksum : ADDRESS_TYPE := x"0000"; |
alias Checksum_LB is Checksum(7 downto 0); |
alias Checksum_UB is Checksum(15 downto 8); |
|
signal Tx_Data : DATA_TYPE := x"00"; |
signal Tx_Valid : std_logic := '0'; |
108,11 → 111,16
case( Vector_State )is |
when IDLE => |
Tx_Busy <= '0'; |
Checksum <= MAGIC_NUM; |
Checksum <= x"00" & MAGIC_NUM; |
if( Tx_Enable = '1' )then |
Command_Buffer <= Tx_Command; |
Arg_Lower_Buffer <= Tx_Arg_Lower; |
Arg_Upper_Buffer <= Tx_Arg_Upper; |
Vector_State <= WAIT_FC; |
end if; |
|
when WAIT_FC => |
if( Tx_FC = '1' )then |
Vector_State <= SEND_CMD; |
end if; |
|
146,16 → 154,26
|
when WAIT_ARG_UB => |
if( Tx_Done = '1' )then |
Vector_State <= SEND_SUM; |
Vector_State <= SEND_SUM_LB; |
end if; |
|
when SEND_SUM => |
Tx_Data <= Checksum; |
when SEND_SUM_LB => |
Tx_Data <= Checksum_LB; |
Tx_Valid <= '1'; |
Vector_State <= WAIT_SUM; |
Vector_State <= WAIT_SUM_LB; |
|
when WAIT_SUM => |
when WAIT_SUM_LB => |
if( Tx_Done = '1' )then |
Vector_State <= SEND_SUM_UB; |
end if; |
|
when SEND_SUM_UB => |
Tx_Data <= Checksum_UB; |
Tx_Valid <= '1'; |
Vector_State <= WAIT_SUM_UB; |
|
when WAIT_SUM_UB => |
if( Tx_Done = '1' )then |
Vector_State <= IDLE; |
end if; |
|