URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
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- This comparison shows the changes necessary to convert path
/open8_urisc/trunk
- from Rev 313 to Rev 314
- ↔ Reverse comparison
Rev 313 → Rev 314
/VHDL/o8_cpu.vhd
109,7 → 109,7
-- : Setting this generic to TRUE will switch to unsigned offsets, |
-- : switching the range to 0 to 255 instead. |
-- : |
-- : Rotate_Ignores_Carry alters the ROL and ROR instructions to |
-- : Rotate_Ignores_Carry alters the ROL and ROR instructions to |
-- : not rotate through, or alter, the carry bit. When enabled, |
-- : ROL performs Rn <= Rn<<1 and ROR performs Rn <= 1>>Rn. Note |
-- : that unlike the original instructions, the C bit is not |
556,9 → 556,6
signal IDX_Sel_l : std_logic_vector(2 downto 0) := "000"; |
signal IDX_Sel_h : std_logic_vector(2 downto 0) := "000"; |
|
signal IDX_Reg_l : integer := 0; |
signal IDX_Reg_h : integer := 0; |
|
signal IDX_NoOffset_Calc : ADDRESS_TYPE := x"0000"; |
signal IDX_Offset_Calc : ADDRESS_TYPE := x"0000"; |
|
601,6 → 598,39
-- Address bus selection/generation logic |
------------------------------------------------------------------------------- |
|
-- The original model treated the offset to LDO/STO as a signed value |
-- allowing access to locations -128 to +127 from [Rn+1:Rn]. This isn't |
-- always helpful, so the generic allows the CPU to use unsigned math |
-- for the offsets. This makes the range 0 to +255 instead. |
|
IDX_Offset_SX <= '0' when Unsigned_Index_Offsets else Operand1(7); |
|
IDX_Offset(15 downto 8) <= (others => IDX_Offset_SX); |
IDX_Offset(7 downto 0) <= Operand1; |
|
-- Enable_Auto_Increment uses the LSB to determine whether or not to |
-- do the auto-increment, so we need to lock the LSB for each operand |
-- if it is enabled. This forces [ODD:EVEN] pairing. |
|
IDX_Sel_l <= (SubOp(2 downto 1) & '0') when Enable_Auto_Increment else |
SubOp; |
|
IDX_Sel_h <= (SubOp(2 downto 1) & '1') when Enable_Auto_Increment else |
SubOp_p1; |
|
-- Pipeline registers for the indexed and indexed with offset addresses. |
Idx_Addr_Calc_proc: process( Clock ) |
variable IDX_Reg_l, IDX_Reg_h : integer range 0 to 7 := 0; |
begin |
IDX_Reg_l := conv_integer(IDX_Sel_l); |
IDX_Reg_h := conv_integer(IDX_Sel_h); |
if( rising_edge(Clock))then |
IDX_NoOffset_Calc <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)); |
IDX_Offset_Calc <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)) + |
IDX_Offset; |
end if; |
end process; |
|
-- Address selection logic based on current CPU state. This is combinatorial, |
-- as adding pipeline registration would add a clock cycle to every instr, |
-- without really adding the Fmax to compensate. |
633,43 → 663,6
end case; |
end process; |
|
-- The original model treated the offset to LDO/STO as a signed value |
-- allowing access to locations -128 to +127 from [Rn+1:Rn]. This isn't |
-- always helpful, so the generic allows the CPU to use unsigned math |
-- for the offsets. This makes the range 0 to +255 instead. |
|
IDX_Offset_SX <= '0' when Unsigned_Index_Offsets else Operand1(7); |
|
IDX_Offset(15 downto 8) <= (others => IDX_Offset_SX); |
IDX_Offset(7 downto 0) <= Operand1; |
|
-- Enable_Auto_Increment uses the LSB to determine whether or not to |
-- do the auto-increment, so we need to lock the LSB for each operand |
-- if it is enabled. This forces [ODD:EVEN] pairing. |
|
IDX_Sel_l <= (SubOp(2 downto 1) & '0') when Enable_Auto_Increment else |
SubOp; |
|
IDX_Sel_h <= (SubOp(2 downto 1) & '1') when Enable_Auto_Increment else |
SubOp_p1; |
|
IDX_Reg_l <= conv_integer(IDX_Sel_l); |
IDX_Reg_h <= conv_integer(IDX_Sel_h); |
|
-- Pipeline registers for the indexed and indexed with offset addresses. |
Idx_Addr_Calc_proc: process( Clock, Reset ) |
variable Reg, Reg_1 : integer range 0 to 7 := 0; |
begin |
if( Reset = Reset_Level )then |
IDX_NoOffset_Calc <= x"0000"; |
IDX_Offset_Calc <= x"0000"; |
elsif( rising_edge(Clock))then |
IDX_NoOffset_Calc <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)); |
IDX_Offset_Calc <= (Regfile(IDX_Reg_h) & Regfile(IDX_Reg_l)) + |
IDX_Offset; |
end if; |
end process; |
|
------------------------------------------------------------------------------- |
-- Combinatorial portion of CPU finite state machine |
-- State Logic / Instruction Decoding & Execution |
764,25 → 757,28
case SubOp is |
when SOP_RSP => |
PC_Ctrl.Offset <= PC_NEXT; |
if( not Allow_Stack_Address_Move )then |
-- The behavior of RSP is controlled by the |
-- Allow_Stack_Address_Move generic. If it is TRUE, then RSP |
-- can read/write the SP arbitrarily based on R1:R0. Otherwise |
-- it will use the default behavior of resetting it to the |
-- HDL generic address. |
if( Allow_Stack_Address_Move )then |
if( Flags(STACK_XFER_FLAG) = '1' )then |
-- If RSP is set to allow SP moves, and the specified flag |
-- is true, then signal the stack pointer logic to load |
-- from R1:R0 |
SP_Ctrl.Oper <= SP_SET; |
else -- Flags(STACK_XFER_FLAG = '0' |
-- If RSP is set to allow SP moves, and the specified flag |
-- is false, then signal the ALU to copy the stack pointer |
-- to R1:R0 |
ALU_Ctrl.Oper <= ALU_RSP; |
end if; |
else |
-- The default behavior for this instruction is to simply |
-- repoint the SP to the HDL default |
SP_Ctrl.Oper <= SP_CLR; |
end if; |
if( Allow_Stack_Address_Move and |
Flags(STACK_XFER_FLAG) = '1' )then |
-- If RSP is set to allow SP moves, and the specified flag |
-- is true, then signal the stack pointer logic to load |
-- from R1:R0 |
SP_Ctrl.Oper <= SP_SET; |
end if; |
if( Allow_Stack_Address_Move and |
Flags(STACK_XFER_FLAG) = '0')then |
-- If RSP is set to allow SP moves, and the specified flag |
-- is false, then signal the ALU to copy the stack pointer |
-- to R1:R0 |
ALU_Ctrl.Oper <= ALU_RSP; |
end if; |
|
when SOP_RTS | SOP_RTI => |
CPU_Next_State <= RTS_C1; |
1102,7 → 1098,7
ALU_Ctrl.Reg <= SubOp_p1; |
|
------------------------------------------------------------------------------- |
-- Basic Stack Manipulation (PSH, POP, RSP) |
-- Basic Stack Manipulation (PSH, POP) |
------------------------------------------------------------------------------- |
when PSH_C1 => |
CPU_Next_State <= IPF_C1; |