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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc/trunk
    from Rev 321 to Rev 322
    ↔ Reverse comparison
  •

Rev 321 → Rev 322

/VHDL/hd44780_4b.vhd
38,10 → 38,10
 
entity hd44780_4b is
generic(
Tsu : integer := 40; -- ns
Tpw : integer := 250; -- nS
Tcyc : integer := 500; -- nS
Clock_Frequency : real := 50000000.0; -- Hz
Tas : integer := 40; -- ns
Tpwe : integer := 250; -- nS
Tcyce : integer := 1000; -- nS
Clock_Frequency : real := 100000000.0; -- Hz
Reset_Level : std_logic := '1'
);
port(
77,9 → 77,9
 
constant CONV_NANOSECS : real := 0.000000001;
 
constant Tsu_r : real := CONV_NANOSECS * real(Tsu);
constant Tpw_r : real := CONV_NANOSECS * real(Tpw);
constant Tcyc_r : real := CONV_NANOSECS * real(Tcyc);
constant Tas_r : real := CONV_NANOSECS * real(Tas);
constant Tpwe_r : real := CONV_NANOSECS * real(Tpwe + Tas);
constant Tcyc_r : real := CONV_NANOSECS * real(Tcyce + Tas);
 
constant TCYC_i : integer := integer(Clock_Frequency * Tcyc_r);
constant TCYC_BITS : integer := ceil_log2(TCYC_i);
86,22 → 86,20
 
constant TCYC_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
conv_std_logic_vector(TCYC_i-1, TCYC_BITS);
 
constant TAS_i : integer := integer(Clock_Frequency * Tas_r);
constant TAS_DELAY : std_logic_vector(TCYC_BITS - 1 downto 0) :=
conv_std_logic_vector(TAS_i-1,TCYC_BITS);
 
constant TPWE_i : integer := integer(Clock_Frequency * Tpwe_r);
constant TPWE_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
conv_std_logic_vector(TPWE_i-1, TCYC_BITS);
 
signal tcyc_timer : std_logic_vector(TCYC_BITS - 1 downto 0) :=
(others => '0');
 
constant TPW_i : integer := integer(Clock_Frequency * Tpw_r);
constant TPW_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
conv_std_logic_vector(TPW_i-1, TCYC_BITS);
 
constant TSU_i : integer := integer(Clock_Frequency * Tsu_r);
constant TSU_BITS : integer := ceil_log2(TSU_i);
constant TSU_DELAY : std_logic_vector(TSU_BITS - 1 downto 0) :=
conv_std_logic_vector(TSU_i-1,TSU_BITS);
signal tsnh_timer : std_logic_vector(TSU_BITS-1 downto 0) :=
(others => '0');
 
type IO_STATES is (IDLE,
INIT_UB, TAS_UB, TPW_UB, TCYC_UB,
TAS_UB, TPW_UB, TCYC_UB,
INIT_LB, TPW_LB, TCYC_LB,
DONE );
signal io_state : IO_STATES;
123,7 → 121,6
io_state <= IDLE;
fn_set <= '0';
tcyc_timer <= (others => '0');
tsnh_timer <= (others => '0');
Wr_Buffer <= (others => '0');
IO_Done <= '0';
LCD_RS <= '0';
131,44 → 128,46
LCD_DQ <= (others => '0');
elsif( rising_edge(Clock) )then
IO_Done <= '0';
LCD_RS <= '0';
LCD_E <= '0';
LCD_DQ_U <= (others => '0');
LCD_DQ_L <= (others => '0');
tcyc_timer <= tcyc_timer + 1;
 
case( io_state )is
when IDLE =>
tcyc_timer <= (others => '0');
if( Wr_En = '1' )then
Wr_Buffer <= Wr_Reg & Wr_Data;
fn_set <= Wr_Fnset;
io_state <= INIT_UB;
io_state <= TAS_UB;
end if;
 
when INIT_UB =>
tsnh_timer <= TSU_DELAY;
tcyc_timer <= (others => '0');
when TAS_UB =>
LCD_RS <= Wr_Buffer_A;
io_state <= TAS_UB;
 
when TAS_UB =>
tsnh_timer <= tsnh_timer - 1;
if( or_reduce(tsnh_timer) = '0' )then
if( tcyc_timer >= TAS_DELAY )then
io_state <= TPW_UB;
end if;
 
when TPW_UB =>
tcyc_timer <= tcyc_timer + 1;
LCD_RS <= Wr_Buffer_A;
LCD_E <= '1';
LCD_DQ_U <= Wr_Buffer_U;
if( tcyc_timer = TPW_DELAY )then
if( tcyc_timer >= TPWE_DELAY )then
io_state <= TCYC_UB;
end if;
 
when TCYC_UB =>
tcyc_timer <= tcyc_timer + 1;
LCD_RS <= Wr_Buffer_A;
LCD_DQ_U <= Wr_Buffer_U;
if( tcyc_timer >= TCYC_DELAY )then
io_state <= INIT_LB;
end if;
 
when INIT_LB =>
tcyc_timer <= (others => '0');
tcyc_timer <= TAS_DELAY;
LCD_RS <= Wr_Buffer_A;
LCD_DQ_U <= Wr_Buffer_U;
io_state <= TPW_LB;
if( fn_set = '1' )then
fn_set <= '0';
176,25 → 175,21
end if;
 
when TPW_LB =>
tcyc_timer <= tcyc_timer + 1;
LCD_RS <= Wr_Buffer_A;
LCD_E <= '1';
LCD_DQ_U <= Wr_Buffer_L;
if( tcyc_timer = TPW_DELAY )then
if( tcyc_timer >= TPWE_DELAY )then
io_state <= TCYC_LB;
end if;
 
when TCYC_LB =>
tcyc_timer <= tcyc_timer + 1;
LCD_RS <= Wr_Buffer_A;
LCD_DQ_U <= Wr_Buffer_L;
if( tcyc_timer >= TCYC_DELAY )then
io_state <= DONE;
IO_Done <= '1';
io_state <= IDLE;
end if;
 
when DONE =>
IO_Done <= '1';
LCD_RS <= '0';
LCD_DQ_U <= (others => '0');
io_state <= IDLE;
 
when others =>
null;
end case;
/VHDL/hd44780_8b.vhd
25,10 → 25,17
-- Description: Provides low-level timing of the control signals in 8-bit mode
-- (required by o8_hd44780_if)
--
-- Note: This code attempts to implement the timing diagram in the HD44780U
-- LCD II datasheet with a few simplifications. Chiefly, DQ is updated
-- at the start of E, rather than attempting to assert within Tds of
-- the falling edge of E. Further, both RS and DQ are asserted until
-- the end of Tcycle, where Tcycle is defined as TcycleE + Tas
 
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/12/21 Design Start
-- Seth Henry 09/19/23 Rewrote IF to use a single cycle timer
 
library ieee;
use ieee.std_logic_1164.all;
38,10 → 45,10
 
entity hd44780_8b is
generic(
Tsu : integer := 40; -- ns
Tpw : integer := 250; -- nS
Tcyc : integer := 500; -- nS
Clock_Frequency : real := 50000000.0; -- Hz
Tas : integer := 50; -- ns
Tpwe : integer := 450; -- ns
Tcyce : integer := 1000; -- ns
Clock_Frequency : real := 100000000.0; -- Hz
Reset_Level : std_logic := '1'
);
port(
76,9 → 83,9
 
constant CONV_NANOSECS : real := 0.000000001;
 
constant Tsu_r : real := CONV_NANOSECS * real(Tsu);
constant Tpw_r : real := CONV_NANOSECS * real(Tpw);
constant Tcyc_r : real := CONV_NANOSECS * real(Tcyc);
constant Tas_r : real := CONV_NANOSECS * real(Tas);
constant Tpwe_r : real := CONV_NANOSECS * real(Tpwe + Tas);
constant Tcyc_r : real := CONV_NANOSECS * real(Tcyce + Tas);
 
constant TCYC_i : integer := integer(Clock_Frequency * Tcyc_r);
constant TCYC_BITS : integer := ceil_log2(TCYC_i);
88,18 → 95,15
signal tcyc_timer : std_logic_vector(TCYC_BITS - 1 downto 0) :=
(others => '0');
 
constant TPW_i : integer := integer(Clock_Frequency * Tpw_r);
constant TPW_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
conv_std_logic_vector(TPW_i-1, TCYC_BITS);
constant TAS_i : integer := integer(Clock_Frequency * Tas_r);
constant TAS_DELAY : std_logic_vector(TCYC_BITS - 1 downto 0) :=
conv_std_logic_vector(TAS_i-1,TCYC_BITS);
 
constant TSU_i : integer := integer(Clock_Frequency * Tsu_r);
constant TSU_BITS : integer := ceil_log2(TSU_i);
constant TSU_DELAY : std_logic_vector(TSU_BITS - 1 downto 0) :=
conv_std_logic_vector(TSU_i-1,TSU_BITS);
signal tsnh_timer : std_logic_vector(TSU_BITS-1 downto 0) :=
(others => '0');
constant TPWE_i : integer := integer(Clock_Frequency * Tpwe_r);
constant TPWE_DELAY : std_logic_vector(TCYC_BITS-1 downto 0) :=
conv_std_logic_vector(TPWE_i-1, TCYC_BITS);
 
type IO_STATES is (IDLE, INIT, IO_TAS, IO_TPW, IO_TCYC, DONE );
type IO_STATES is (IDLE, IO_TAS, IO_TPWE, IO_TCYC );
signal io_state : IO_STATES;
 
signal Wr_Buffer : std_logic_vector(8 downto 0);
113,7 → 117,6
if( Reset = Reset_Level )then
io_state <= IDLE;
tcyc_timer <= (others => '0');
tsnh_timer <= (others => '0');
Wr_Buffer <= (others => '0');
IO_Done <= '0';
LCD_RS <= '0';
121,46 → 124,41
LCD_DQ <= (others => '0');
elsif( rising_edge(Clock) )then
IO_Done <= '0';
LCD_RS <= '0';
LCD_E <= '0';
LCD_DQ <= x"00";
tcyc_timer <= tcyc_timer + 1;
 
case( io_state )is
when IDLE =>
tcyc_timer <= (others => '0');
if( Wr_En = '1' )then
Wr_Buffer <= Wr_Reg & Wr_Data;
io_state <= INIT;
io_state <= IO_TAS;
end if;
 
when INIT =>
tsnh_timer <= TSU_DELAY;
tcyc_timer <= (others => '0');
when IO_TAS =>
LCD_RS <= Wr_Buffer_A;
io_state <= IO_TAS;
 
when IO_TAS =>
tsnh_timer <= tsnh_timer - 1;
if( or_reduce(tsnh_timer) = '0' )then
io_state <= IO_TPW;
if( tcyc_timer >= TAS_DELAY )then
io_state <= IO_TPWE;
end if;
 
when IO_TPW =>
tcyc_timer <= tcyc_timer + 1;
when IO_TPWE =>
LCD_RS <= Wr_Buffer_A;
LCD_E <= '1';
LCD_DQ <= Wr_Buffer_D;
if( tcyc_timer = TPW_DELAY )then
if( tcyc_timer >= TPWE_DELAY )then
io_state <= IO_TCYC;
end if;
 
when IO_TCYC =>
tcyc_timer <= tcyc_timer + 1;
LCD_RS <= Wr_Buffer_A;
LCD_DQ <= Wr_Buffer_D;
if( tcyc_timer >= TCYC_DELAY )then
io_state <= DONE;
IO_Done <= '1';
io_state <= IDLE;
end if;
 
when DONE =>
IO_Done <= '1';
LCD_RS <= '0';
LCD_DQ <= (others => '0');
io_state <= IDLE;
 
when others =>
null;
end case;
/VHDL/o8_hd44780_8b.vhd
136,7 → 136,7
 
signal Tx_Ready : std_logic := '0';
 
constant LCD_CONFIG1 : std_logic_vector(7 downto 0) := x"38"; -- Set 4-bit, 2-line mode
constant LCD_CONFIG1 : std_logic_vector(7 downto 0) := x"38"; -- Set 8-bit, 2-line mode
constant LCD_CONFIG2 : std_logic_vector(7 downto 0) := x"0C"; -- Turn display on, no cursor
constant LCD_CONFIG3 : std_logic_vector(7 downto 0) := x"01"; -- Clear display
constant LCD_CONFIG4 : std_logic_vector(7 downto 0) := x"06"; -- Positive increment, no shift
/VHDL/o8_hd44780_if.vhd
99,17 → 99,18
entity o8_hd44780_if is
generic(
Use_4Bit_IF : boolean := FALSE;
-- Bus IF timing
Tsu : integer := 40; -- ns
Tpw : integer := 250; -- nS
Tcyc : integer := 500; -- nS
-- Panel command timing
-- LCD bus IF timing
Tas : integer := 20; -- ns
Tpwe : integer := 450; -- nS
Tcyce : integer := 1000; -- nS
-- LCD command timing
Tpwrdly : integer := 40000; -- uS
Tcldsp : integer := 2000; -- uS
Tbusy : integer := 50; -- uS
-- Contrast/Backlight
-- Backlight
Use_Backlight : boolean := FALSE;
Default_Brightness : std_logic_vector(7 downto 0) := x"00";
-- System clock & address
Clock_Frequency : real;
Address : ADDRESS_TYPE
);
338,9 → 339,9
 
U_IO : entity work.hd44780_4b
generic map(
Tsu => Tsu,
Tpw => Tpw,
Tcyc => Tcyc,
Tas => Tas,
Tpwe => Tpwe,
Tcyce => Tcyce,
Clock_Frequency => Clock_Frequency,
Reset_Level => Reset_Level
)
366,9 → 367,9
 
U_IO : entity work.hd44780_8b
generic map(
Tsu => Tsu,
Tpw => Tpw,
Tcyc => Tcyc,
Tas => Tas,
Tpwe => Tpwe,
Tcyce => Tcyce,
Clock_Frequency => Clock_Frequency,
Reset_Level => Reset_Level
)
/VHDL/o8_ltc2355_2p.vhd
21,7 → 21,7
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-- THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL units : ltc2355_2p
-- VHDL units : o8_ltc2355_2p
-- Description: Reads out a pair of LTC2355 14-bit ADCs which are wired with
-- : common clock and CONVERT START inputs. Because they are
-- : synchronized, this entity provides simultaneously updated
34,10 → 34,21
-- : Works best when the clock frequency is 96MHz or lower. Module
-- : will divide the clock by 2 if it is greater than this.
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x0 AAAAAAAA ADC Channel 1 Data(7:0) (RO)
-- 0x1 --AAAAAA ADC Channel 1 Data(13:8) (RO)
-- 0x2 AAAAAAAA ADC Channel 2 Data(7:0) (RO)
-- 0x3 --AAAAAA ADC Channel 2 Data(13:8) (reduced) (RO)
-- 0x4 AAAAAAAA ADC Channel 1 Data(13:6) (reduced) (RO)
-- 0x5 AAAAAAAA ADC Channel 2 Data(13:6) (RO)
-- 0x6 AAAAAAAA Update / Sample Rate (in uS) (RW)
-- 0x7 A------- Force Trigger / Status (RW)
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/16/20 Revision block added
-- Seth Henry 12/14/20 Forked
 
library ieee;
use ieee.std_logic_1164.all;
75,9 → 86,9
 
constant User_Addr : std_logic_vector(15 downto 3) := Address(15 downto 3);
alias Comp_Addr is Open8_Bus.Address(15 downto 3);
signal Addr_Match : std_logic;
signal Addr_Match : std_logic := '0';
alias Reg_Sel_d is Open8_Bus.Address(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0);
signal Reg_Sel_q : std_logic_vector(2 downto 0) := (others => '0');
signal Wr_En_d : std_logic := '0';
signal Wr_En_q : std_logic := '0';
alias Wr_Data_d is Open8_Bus.Wr_Data;
85,24 → 96,25
signal Rd_En_d : std_logic := '0';
signal Rd_En_q : std_logic := '0';
 
signal User_Trig : std_logic;
signal User_Trig : std_logic := '0';
 
signal Timer_Int : DATA_TYPE;
signal Timer_Cnt : DATA_TYPE;
signal Timer_Trig : std_logic;
signal Timer_Int : DATA_TYPE := (others => '0');
signal Timer_Cnt : DATA_TYPE := (others => '0');
signal Timer_Trig : std_logic := '0';
 
type ADC_STATES is ( IDLE, START, CLK_HIGH, CLK_HIGH2, CLK_LOW, CLK_LOW2, UPDATE );
signal ad_state : ADC_STATES;
 
signal rx_buffer1 : std_logic_vector(16 downto 0);
signal rx_buffer2 : std_logic_vector(16 downto 0);
signal bit_cntr : std_logic_vector(4 downto 0);
signal rx_buffer1 : std_logic_vector(16 downto 0) := (others => '0');
signal rx_buffer2 : std_logic_vector(16 downto 0) := (others => '0');
signal bit_cntr : std_logic_vector(4 downto 0) := (others => '0');
constant BIT_COUNT : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(16,5);
 
signal ADC1_Data : std_logic_vector(13 downto 0);
signal ADC2_Data : std_logic_vector(13 downto 0);
signal ADC_Ready : std_logic;
signal ADC1_Data : std_logic_vector(13 downto 0) := (others => '0');
signal ADC2_Data : std_logic_vector(13 downto 0) := (others => '0');
signal ADC_Ready : std_logic := '0';
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
263,4 → 275,4
end if;
end process;
 
end architecture;
end architecture;

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