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Rev 125 → Rev 126

/trunk/gnu/binutils/gas/testsuite/gas/sh/sh4al-dsp.d
0,0 → 1,104
#as: -dsp
#objdump: -fdr --prefix-addresses --show-raw-insn
#name: SH4al DSP constructs
 
.*: file format elf.*sh.*
architecture: sh4al-dsp, flags 0x00000010:
HAS_SYMS
start address 0x00000000
 
Disassembly of section \.text:
0x00000000 43 34 ldrc r3
0x00000002 4c 34 ldrc r12
0x00000004 8a 0a ldrc #10
0x00000006 8a f3 ldrc #-13
0x00000008 00 98 setdmx
0x0000000a 00 c8 setdmy
0x0000000c 00 88 clrdmxy
 
0x0000000e f1 16 movx\.w @r4,x0 movy\.w a0,@r7\+
0x00000010 f1 84 movx\.w @r0,x1
0x00000012 f3 48 movx\.w @r1\+,y0
0x00000014 f2 cc movx\.w @r5\+r8,y1
0x00000016 f2 94 movx\.l @r5,x1
0x00000018 f1 14 movx\.l @r0,x0
0x0000001a f3 58 movx\.l @r1\+,y0
0x0000001c f0 dc movx\.l @r4\+r8,y1
 
0x0000001e f0 2b movx\.w a0,@r4\+ movy\.w @r6\+r9,y0
0x00000020 f3 64 movx\.w x0,@r1
0x00000022 f1 a8 movx\.w a1,@r0\+
0x00000024 f2 ec movx\.w x1,@r5\+r8
0x00000026 f2 34 movx\.l a0,@r5
0x00000028 f1 74 movx\.l x0,@r0
0x0000002a f3 f8 movx\.l x1,@r1\+
0x0000002c f0 bc movx\.l a1,@r4\+r8
 
0x0000002e f1 ed movx\.w a1,@r4\+r8 movy\.w @r7,y1
0x00000030 f3 01 movy\.w @r3,y0
0x00000032 f2 c2 movy\.w @r2\+,x1
0x00000034 f0 83 movy\.w @r6\+r9,x0
0x00000036 f0 61 movy\.l @r6,y1
0x00000038 f2 21 movy\.l @r2,y0
0x0000003a f3 a2 movy\.l @r3\+,x0
0x0000003c f1 e3 movy\.l @r7\+r9,x1
 
0x0000003e f2 de movx\.w @r5\+r8,x1 movy\.w a1,@r6\+
0x00000040 f2 d1 movy\.w y1,@r2
0x00000042 f3 12 movy\.w a0,@r3\+
0x00000044 f1 93 movy\.w y0,@r7\+r9
0x00000046 f1 71 movy\.l a1,@r7
0x00000048 f3 b1 movy\.l y0,@r3
0x0000004a f2 f2 movy\.l y1,@r2\+
0x0000004c f0 33 movy\.l a0,@r6\+r9
 
0x0000004e f8 00 88 47 pabs x1,a0
0x00000052 f8 00 a8 0e pabs y0,m1
0x00000056 f8 00 8a dc dct pabs a1,m0
0x0000005a f8 00 8a 19 dct pabs x0,x1
0x0000005e f8 00 8b 9b dcf pabs a0,y1
0x00000062 f8 00 8b 57 dcf pabs x1,a0
0x00000066 f8 00 aa 58 dct pabs y1,x0
0x0000006a f8 00 aa 6e dct pabs m0,m1
0x0000006e f8 00 ab 7a dcf pabs m1,y0
0x00000072 f8 00 ab 45 dcf pabs y0,a1
0x00000076 f8 00 4e 00 pmuls a1,x0,m0
0x0000007a f8 00 4b 04 pmuls y0,a1,m1
0x0000007e f8 00 8d 07 pclr a0
0x00000082 f8 00 8e 05 dct pclr a1
0x00000086 f8 00 4e 10 pclr x0 pmuls a1,x0,m0
0x0000008a f8 00 40 1b pclr a1 pmuls x0,y0,a0
0x0000008e f8 00 45 1e pclr a0 pmuls x1,y1,a1
0x00000092 f8 00 4b 15 pclr y0 pmuls y0,a1,m1
0x00000096 f8 00 a1 a8 psub a0,m0,x0
0x0000009a f8 00 85 79 psub m1,x1,x1
0x0000009e f8 00 85 8a psub y0,a0,y0
0x000000a2 f8 00 a2 db dct psub a1,y1,y1
0x000000a6 f8 00 86 67 dct psub m0,x1,a0
0x000000aa f8 00 86 95 dct psub y1,a0,a1
0x000000ae f8 00 a3 7c dcf psub x1,m1,m0
0x000000b2 f8 00 87 4e dcf psub y0,x1,m1
0x000000b6 f8 00 87 b5 dcf psub m1,a0,a1
0x000000ba f8 00 9d de pswap a1,m1
0x000000be f8 00 9d 17 pswap x0,a0
0x000000c2 f8 00 bd 7a pswap m1,y0
0x000000c6 f8 00 bd 49 pswap y0,x1
0x000000ca f8 00 9e 9b dct pswap a0,y1
0x000000ce f8 00 9e 58 dct pswap x1,x0
0x000000d2 f8 00 be 55 dct pswap y1,a1
0x000000d6 f8 00 be 6c dct pswap m0,m0
0x000000da f8 00 9f 97 dcf pswap a0,a0
0x000000de f8 00 9f 5e dcf pswap x1,m1
0x000000e2 f8 00 bf 78 dcf pswap m1,x0
0x000000e6 f8 00 bf 4b dcf pswap y0,y1
0x000000ea f8 00 98 85 prnd a0,a1
0x000000ee f8 00 b8 1c prnd y1,m0
0x000000f2 f8 00 9a d8 dct prnd a1,x0
0x000000f6 f8 00 9a 1b dct prnd x0,y1
0x000000fa f8 00 ba 77 dct prnd m1,a0
0x000000fe f8 00 ba 49 dct prnd y0,x1
0x00000102 f8 00 9b 9a dcf prnd a0,y0
0x00000106 f8 00 9b 5e dcf prnd x1,m1
0x0000010a f8 00 bb 57 dcf prnd y1,a0
0x0000010e f8 00 bb 65 dcf prnd m0,a1
0x00000112 00 09 nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/err.exp
0,0 → 1,28
# Copyright (C) 2000, 2005, 2007 Free Software Foundation, Inc.
 
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
# Please email any bugs, comments, and/or additions to this file to:
# binutils@sources.redhat.com
 
load_lib gas-dg.exp
dg-init
 
if [istarget sh-*-*] then {
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/warn-*.s]] "" ""
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/err-*.s]] "" ""
}
 
dg-finish
/trunk/gnu/binutils/gas/testsuite/gas/sh/fdpic.s
0,0 → 1,8
.text
 
.long foo@PCREL
.long foo@FUNCDESC
.long foo@GOT
.long foo@GOTOFF
.long foo@GOTFUNCDESC
.long foo@GOTOFFFUNCDESC
/trunk/gnu/binutils/gas/testsuite/gas/sh/err-sh4a.s
0,0 → 1,29
! { dg-do assemble }
 
.text
.p2align 2
 
movli.l @r7,r13 ! { dg-error "invalid operands" }
movco.l r1,@r0 ! { dg-error "invalid operands" }
 
movli.l r0,@r0 ! { dg-error "invalid operands" }
movco.l @r0,r0 ! { dg-error "invalid operands" }
 
movli.l r1 ! { dg-error "invalid operands|missing operand" }
movco.l r0 ! { dg-error "invalid operands|missing operand" }
 
movli.l @r1,r0,r2 ! { dg-error "excess operands" }
movco.l r0,@r1,r2 ! { dg-error "excess operands" }
 
movua.l @r0,r1 ! { dg-error "invalid operands" }
movua.l @r0,r1,r2 ! { dg-error "invalid operands" }
movua.l @r1+ ! { dg-error "invalid operands|missing operand" }
movua.l r0,@r1 ! { dg-error "invalid operands" }
movua.l @(r0,r1),r2 ! { dg-error "invalid operands" }
movua.l @-r5,r1 ! { dg-error "invalid operands" }
 
icbi r0 ! { dg-error "invalid operands" }
 
prefi r7 ! { dg-error "invalid operands" }
 
synco r0 ! { dg-error "excess operands" }
/trunk/gnu/binutils/gas/testsuite/gas/sh/err-le.s
0,0 → 1,10
! { dg-do assemble { target sh*-*-elf} }
! { dg-options "-big" }
! { dg-error "-little required" "" { target sh*-*-elf } 0 }
 
! Check that a mismatch between command-line options and the .big
! directive is identified.
 
.little
start:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/dsp.s
0,0 → 1,27
# Test file for SH/GAS -- dsp instructions
 
.text
.align
.globl dsp_tests
dsp_tests:
movs.w @-r2, x0
movs.w @r3, x1
movs.w @r4+, y0
movs.w @r5+r8, y1
movs.w m0, @-r5
movs.w m1, @r4
movs.w a0, @r3+
movs.w a1, @r2+r8
 
movs.l @-r2, a0g
movs.l @r3, a1g
movs.l @r4+, x0
movs.l @r5+r8, x1
movs.l y0, @-r5
movs.l y1, @r4
movs.l m0, @r3+
movs.l m1, @r2+r8
 
padd x0,y0,a0
plds a0,mach
padd x0,y0,a0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh2a-pic.d
0,0 → 1,16
#objdump: -dr --prefix-addresses --show-raw-insn
#name: SH2a PIC relocations
#as: -isa=sh2a
#skip: sh*-*-symbian*
 
dump.o: file format elf32-sh.*
 
Disassembly of section .text:
0x00000000 01 00 00 00 movi20 #0,r1
0: R_SH_GOT20 foo
0x00000004 01 00 00 00 movi20 #0,r1
4: R_SH_GOTOFF20 foo
0x00000008 01 00 00 00 movi20 #0,r1
8: R_SH_GOTFUNCDESC20 foo
0x0000000c 01 00 00 00 movi20 #0,r1
c: R_SH_GOTOFFFUNCDESC20 foo
/trunk/gnu/binutils/gas/testsuite/gas/sh/err-sh4a-fp.s
0,0 → 1,15
! { dg-do assemble }
 
.text
.p2align 2
 
fpchg fpul ! { dg-error "excess operands" }
 
fsrra fr1, fr2 ! { dg-error "excess operands" }
fsrra ! { dg-error "invalid operands|missing operand" }
fsrra fpul ! { dg-error "invalid operands" }
fsrra dr0, dr2 ! { dg-error "invalid operands" }
 
fsca dr0, fpul ! { dg-error "invalid operands" }
fsca fpul, fr0 ! { dg-error "invalid operands" }
fsca fpul ! { dg-error "invalid operands|missing operand" }
/trunk/gnu/binutils/gas/testsuite/gas/sh/err-mova.s
0,0 → 1,20
! { dg-do assemble }
 
! Check that an error occurs on mova instructions with an unaligned or
! negative offset.
 
negative:
.word 0
 
.align 2
start:
mova start, r0 ! { dg-error "negative offset|pcrel too far" }
mova negative, r0 ! { dg-error "negative offset|pcrel too far" }
mova aligned, r0 ! ok
mova unaligned, r0 ! { dg-error "unaligned destination" }
 
.align 2
aligned:
.word 1
unaligned:
.word 2
/trunk/gnu/binutils/gas/testsuite/gas/sh/sign-extension.d
0,0 → 1,11
#as: -little
#objdump: -drj.text
#name: Sign-extended immediate
 
.*: file format .*sh.*
 
Disassembly of section \.text:
 
00000000 <foo>:
0: f0 e0 mov #-16,r0
2: 09 00 nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/too_large.d
0,0 → 1,9
#name: Check for bogus overflow errors in .byte directives
#as: -big -relax -isa=sh4a
#nm: -n
 
[ ]*U \.L318
[ ]*U \.L319
[ ]*U \.L320
[ ]*U \.L321
0+00100 t \.L307
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh4al-dsp.s
0,0 → 1,104
.text
.p2align 2
 
ldrc r3
ldrc r12
ldrc #10
ldrc #243
setdmx
setdmy
clrdmxy
 
movx.w @r4,x0 movy.w a0,@r7+
movx.w @r0,x1
movx.w @r1+,y0 nopy
nopy movx.w @r5+r8,y1
 
movx.l @r5,x1
movx.l @r0,x0
movx.l @r1+,y0 nopy
nopy movx.l @r4+r8,y1
 
movx.w a0,@r4+ movy.w @r6+r9,y0
movx.w x0,@r1
movx.w a1,@r0+ nopy
nopy movx.w x1,@r5+r8
 
movx.l a0,@r5
movx.l x0,@r0
movx.l x1,@r1+ nopy
nopy movx.l a1,@r4+r8
 
movy.w @r7,y1 movx.w a1,@r4+r8
movy.w @r3,y0
movy.w @r2+,x1 nopx
nopx movy.w @r6+r9,x0
 
movy.l @r6,y1
movy.l @r2,y0
movy.l @r3+,x0 nopx
nopx movy.l @r7+r9,x1
 
movy.w a1,@r6+ movx.w @r5+r8,x1
movy.w y1,@r2
movy.w a0,@r3+ nopx
nopx movy.w y0,@r7+r9
 
movy.l a1,@r7
movy.l y0,@r3
movy.l y1,@r2+ nopx
nopx movy.l a0,@r6+r9
 
pabs x1,a0
pabs y0,m1
dct pabs a1,m0
dct pabs x0,x1
dcf pabs a0,y1
dcf pabs x1,a0
dct pabs y1,x0
dct pabs m0,m1
dcf pabs m1,y0
dcf pabs y0,a1
 
pmuls a1,x0,m0
pmuls y0,a1,m1
pclr a0
dct pclr a1
pclr x0 pmuls a1,x0,m0
pclr a1 pmuls x0,y0,a0
pclr a0 pmuls x1,y1,a1
pclr y0 pmuls y0,a1,m1
 
psub a0,m0,x0
psub m1,x1,x1
psub y0,a0,y0
dct psub a1,y1,y1
dct psub m0,x1,a0
dct psub y1,a0,a1
dcf psub x1,m1,m0
dcf psub y0,x1,m1
dcf psub m1,a0,a1
 
pswap a1,m1
pswap x0,a0
pswap m1,y0
pswap y0,x1
dct pswap a0,y1
dct pswap x1,x0
dct pswap y1,a1
dct pswap m0,m0
dcf pswap a0,a0
dcf pswap x1,m1
dcf pswap m1,x0
dcf pswap y0,y1
 
prnd a0,a1
prnd y1,m0
dct prnd a1,x0
dct prnd x0,y1
dct prnd m1,a0
dct prnd y0,x1
dcf prnd a0,y0
dcf prnd x1,m1
dcf prnd y1,a0
dcf prnd m0,a1
/trunk/gnu/binutils/gas/testsuite/gas/sh/pcrel-coff.d
0,0 → 1,27
#as: -big
#objdump: -d -EB
#name: PC-relative loads
 
.*: file format .*sh.*
 
Disassembly of section .text:
 
00000000 <code>:
0: d1 03 mov\.l 10 <litpool>,r1 ! fffffff0
2: d1 03 mov\.l 10 <litpool>,r1 ! fffffff0
4: c7 02 mova 10 <litpool>,r0
6: 61 02 mov\.l @r0,r1
8: d1 01 mov\.l 10 <litpool>,r1 ! fffffff0
a: 01 03 bsrf r1
c: 00 09 nop
e: 00 09 nop
 
00000010 <litpool>:
10: ff ff \.word 0xffff
12: ff f0 fadd fr15,fr15
14: 00 09 nop
16: 00 09 nop
18: 00 09 nop
1a: 00 09 nop
1c: 00 09 nop
1e: 00 09 nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh4a-dsp.d
0,0 → 1,40
#as: -dsp
#objdump: -fdr --prefix-addresses --show-raw-insn
#name: SH4al-dsp constructs shared with sh4a (and sh4)
 
.*: file format elf.*sh.*
architecture: sh4a-nofpu, flags 0x00000010:
HAS_SYMS
start address 0x00000000
 
Disassembly of section \.text:
0x00000000 01 63 movli\.l @r1,r0
0x00000002 00 73 movco\.l r0,@r0
0x00000004 06 63 movli\.l @r6,r0
0x00000006 03 73 movco\.l r0,@r3
0x00000008 0a 63 movli\.l @r10,r0
0x0000000a 0c 73 movco\.l r0,@r12
0x0000000c 40 a9 movua\.l @r0,r0
0x0000000e 4d a9 movua\.l @r13,r0
0x00000010 47 a9 movua\.l @r7,r0
0x00000012 45 e9 movua\.l @r5\+,r0
0x00000014 42 e9 movua\.l @r2\+,r0
0x00000016 4b e9 movua\.l @r11\+,r0
0x00000018 04 e3 icbi @r4
0x0000001a 0f e3 icbi @r15
0x0000001c 02 e3 icbi @r2
0x0000001e 05 d3 prefi @r5
0x00000020 0a d3 prefi @r10
0x00000022 00 ab synco
0x00000024 45 fa ldc r5,dbr
0x00000026 4a f6 ldc.l @r10\+,dbr
0x00000028 0b 3a stc sgr,r11
0x0000002a 49 32 stc.l sgr,@-r9
0x0000002c 02 fa stc dbr,r2
0x0000002e 46 f2 stc.l dbr,@-r6
0x00000030 03 c3 movca.l r0,@r3
0x00000032 0c 93 ocbi @r12
0x00000034 07 a3 ocbp @r7
0x00000036 0d b3 ocbwb @r13
0x00000038 0e 83 pref @r14
0x0000003a 00 09 nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh2a-pic.s
0,0 → 1,6
.text
 
movi20 #foo@GOT, r1
movi20 #foo@GOTOFF, r1
movi20 #foo@GOTFUNCDESC, r1
movi20 #foo@GOTOFFFUNCDESC, r1
/trunk/gnu/binutils/gas/testsuite/gas/sh/pcrel2.d
0,0 → 1,23
#as: -big
#objdump: -drj.text
#name: PC-relative loads
 
.*: file format .*sh.*
 
Disassembly of section \.text:
 
00000000 <code>:
0: 8b 01 bf 6 <foo>
2: d0 02 mov\.l c <bar>,r0 ! 6 .*
4: 90 02 mov\.w c <bar>,r0 ! 0 .*
 
00000006 <foo>:
6: af fe bra 6 <foo>
8: 00 09 nop
a: 00 09 nop
 
0000000c <bar>:
c: 00 00 .*[ ]*.*
e: 00 06 .*[ ]*.*
10: 00 0a .*[ ]*.*
12: 0c 00 .*[ ]*.*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sign-extension.s
0,0 → 1,3
.align 2
foo:
mov #0xfffffff0, r0
/trunk/gnu/binutils/gas/testsuite/gas/sh/too_large.s
0,0 → 1,39
.file "too_large.c"
.text
nop
.align 8
.L307:
.byte .L302-.L307
.byte .L303-.L307
.byte .L304-.L307
.byte .L305-.L307
.L304:
mov.l .L318,r1
jsr @r1
mov r8,r4
lds r0,fpul
fsts fpul,fr1
flds fr1,fpul
sts fpul,r0
mov r14,r15
lds.l @r15+,pr
mov.l @r15+,r14
mov.l @r15+,r8
rts
nop
.L305:
mov.l .L319,r7
jsr @r7
mov r8,r4
lds r0,fpul
bra .L307
fsts fpul,fr1
.L303:
mov.l .L320,r6
jsr @r6
mov r8,r4
lds r0,fpul
bra .L307
fsts fpul,fr1
.L302:
mov.l .L321,r5
/trunk/gnu/binutils/gas/testsuite/gas/sh/pcrel-hms.d
0,0 → 1,29
#as: -big
#source: pcrel.s
#objdump: -d -EB
#name: PC-relative loads
#stderr: pcrel.l
 
.*: file format .*sh.*
 
Disassembly of section .text:
 
00000000 <code>:
0: d0 04 mov\.l 14 <litpool>,r0 ! ffffffec
2: d1 05 mov\.l 18 <litpool\+0x4>,r1 ! 90009
4: d1 03 mov\.l 14 <litpool>,r1 ! ffffffec
6: d1 03 mov\.l 14 <litpool>,r1 ! ffffffec
8: c7 02 mova 14 <litpool>,r0
a: 61 02 mov\.l @r0,r1
c: d1 01 mov\.l 14 <litpool>,r1 ! ffffffec
e: 01 03 bsrf r1
10: 00 09 nop
12: 00 09 nop
 
00000014 <litpool>:
14: ff ff \.word 0xffff
16: ff ec fmov fr14,fr15
18: 00 09 nop
1a: 00 09 nop
1c: 00 09 nop
1e: 00 09 nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/tlsnopic.d
0,0 → 1,20
#objdump: -dr
#as: -big
#name: sh non-pic tls
 
.*: +file format .*
 
Disassembly of section .text:
 
0+000 <fn>:
0: 2f e6 [ ]*mov\.l r14,@-r15
2: 6e f3 [ ]*mov r15,r14
4: 01 12 [ ]*stc gbr,r1
6: d0 02 [ ]*mov\.l 10 <fn\+0x10>,r0[ ]+! 0 .*
8: 30 1c [ ]*add r1,r0
a: 6f e3 [ ]*mov r14,r15
c: 00 0b [ ]*rts
e: 6e f6 [ ]*mov\.l @r15\+,r14
10: 00 00 [ ]*\.word 0x0+0
[ ]+10: R_SH_TLS_LE_32 foo
\.\.\.
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh3-dsp.s
0,0 → 1,287
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh3-dsp but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh3-dsp.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh3-dsp.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh3_dsp:
! Instructions introduced into sh3-dsp
 
! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
0,0 → 1,221
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh2a-nofpu but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh2a-nofpu.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh2a_nofpu:
! Instructions introduced into sh2a-nofpu
ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
mov.b R0,@r4+ ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}
mov.b @-r5,R0 ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}
mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
mov.l R0,@r4+ ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}
mov.l @-r5,R0 ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}
mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
mov.w R0,@r4+ ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}
mov.w @-r5,R0 ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}
mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
stc TBR,r4 ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
bclr #4, r4 ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bld #4, r4 ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bset #4, r4 ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bst #4, r4 ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
bst.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
clips.b r4 ;!/* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}
clips.w r4 ;!/* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}
clipu.b r4 ;!/* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}
clipu.w r4 ;!/* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}
divs R0,r4 ;!/* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}
divu R0,r4 ;!/* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}
jsr/n @r5 ;!/* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}
jsr/n @@(8,TBR) ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}
ldbank @r5,R0 ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}
movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
movrt r4 ;!/* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}
mulr R0,r4 ;!/* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}
nott ;!/* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}
resbank ;!/* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}
rts/n ;!/* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}
rtv/n r5 ;!/* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}
stbank R0,@r4 ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}
band.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */ {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bandnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bldnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bornot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bxor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
movi20 #4,r4 ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */ {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}
movi20s #1024,r4 ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */ {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh4-nofpu.s
0,0 → 1,194
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh4-nofpu but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh4-nofpu.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh4-nofpu.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh4_nofpu:
! Instructions introduced into sh4-nofpu
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
0,0 → 1,201
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh4a-nofpu but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh4a-nofpu.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh4a-nofpu.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh4a_nofpu:
! Instructions introduced into sh4a-nofpu
icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
0,0 → 1,168
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh2a-nofpu-or-sh3-nommu but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh2a-nofpu-or-sh3-nommu.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh2a_nofpu_or_sh3_nommu:
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
 
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh3-nommu.s
0,0 → 1,180
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh3-nommu but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh3-nommu.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh3-nommu.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh3_nommu:
! Instructions introduced into sh3-nommu
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh2.s
0,0 → 1,166
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh2 but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh2.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh2.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh2:
! Instructions introduced into sh2
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
 
! Instructions inherited from ancestors: sh
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh2a.s
0,0 → 1,289
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh2a but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh2a.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh2a:
! Instructions introduced into sh2a
fmov.d xd4,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}
fmov.d @(2048,r5),xd2 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),<DX_REG_N> */ {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32}
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.b R0,@r4+ ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}
mov.b @-r5,R0 ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}
mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.l R0,@r4+ ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}
mov.l @-r5,R0 ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}
mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
mov.w R0,@r4+ ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}
mov.w @-r5,R0 ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}
mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc TBR,r4 ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
bclr #4, r4 ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bld #4, r4 ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bset #4, r4 ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bst #4, r4 ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
bst.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
clips.b r4 ;!/* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}
clips.w r4 ;!/* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}
clipu.b r4 ;!/* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}
clipu.w r4 ;!/* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}
divs R0,r4 ;!/* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}
divu R0,r4 ;!/* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}
jsr/n @r5 ;!/* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}
jsr/n @@(8,TBR) ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}
ldbank @r5,R0 ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}
movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
movrt r4 ;!/* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}
mulr R0,r4 ;!/* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}
nott ;!/* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}
resbank ;!/* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}
rts/n ;!/* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}
rtv/n r5 ;!/* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}
stbank R0,@r4 ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}
band.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */ {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bandnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bldnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bornot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
bxor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
movi20 #4,r4 ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */ {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}
movi20s #1024,r4 ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */ {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh3.s
0,0 → 1,181
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh3 but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh3.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh3.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh3:
! Instructions introduced into sh3
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh4.s
0,0 → 1,263
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh4 but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh4.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh4.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh4:
! Instructions introduced into sh4
fipr fv4,fv0 ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}
frchg ;!/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}
fsca FPUL,dr2 ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh-dsp.s
0,0 → 1,272
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh-dsp but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh-dsp.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh-dsp.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh_dsp:
! Instructions introduced into sh-dsp
ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
 
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh4a.s
0,0 → 1,271
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh4a but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh4a.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh4a.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh4a:
! Instructions introduced into sh4a
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
fipr fv4,fv0 ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
frchg ;!/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}
fsca FPUL,dr2 ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}
fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh4al-dsp.s
0,0 → 1,343
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh4al-dsp but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh4al-dsp.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh4al-dsp.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh4al_dsp:
! Instructions introduced into sh4al-dsp
clrdmxy ;!/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up}
ldrc r5 ;!/* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up}
ldrc #4 ;!/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up}
setdmx ;!/* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up}
setdmy ;!/* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up}
movx.w @r1,y1 ;!/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up}
movx.w @r1+,y1 ;!/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up}
movx.w @r1+r8,y1 ;!/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up}
movx.w a0,@r1 ;!/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up}
movx.w a0,@r1+ ;!/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up}
movx.w a0,@r1+r8 ;!/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up}
movx.l @r1,y1 ;!/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up}
movx.l @r1+,y1 ;!/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up}
movx.l @r1+r8,y1 ;!/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up}
movx.l a0,@r1 ;!/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up}
movx.l a0,@r1+ ;!/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up}
movx.l a0,@r1+r8 ;!/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up}
movy.w @r3,y1 ;!/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up}
movy.w @r3+,y1 ;!/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up}
movy.w @r3+r9,y1 ;!/* nnmm000011 movy.w @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up}
movy.w a0,@r3 ;!/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up}
movy.w a0,@r3+ ;!/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up}
movy.w a0,@r3+r9 ;!/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up}
movy.l @r3,y1 ;!/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up}
movy.l @r3+,y1 ;!/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up}
movy.l @r3+r9,y1 ;!/* nnmm100011 movy.l @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up}
movy.l a0,@r3 ;!/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up}
movy.l a0,@r3+ ;!/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up}
movy.l a0,@r3+r9 ;!/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up}
dct pabs x1,m0 ;!/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up}
dct pabs y0,m0 ;!/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up}
dct prnd x1,m0 ;!/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up}
dct prnd y0,m0 ;!/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up}
dct psub y0,x1,m0 ;!/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */ {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up}
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
 
! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh2e.s
0,0 → 1,202
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh2e but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh2e.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh2e.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh2e:
! Instructions introduced into sh2e
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
 
! Instructions inherited from ancestors: sh sh2
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh3e.s
0,0 → 1,218
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh3e but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh3e.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh3e.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh3e:
! Instructions introduced into sh3e
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/arch.exp
0,0 → 1,522
# Copyright (C) 2004, 2005, 2007, 2008
# Free Software Foundation, Inc.
 
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
# Please email any bugs, comments, and/or additions to this file to:
# binutils@sources.redhat.com
 
# This scripts tests all available SH architectures with all the assembler
# options related to the architecture. It ensures that those combinations
# which should not work do not work, and that those that should work
# produce the correct output architecture.
#
# It looks for files in the same directory as this file named sh*.s .
# Each file must contain all the instructions available within
# that architecture. The architecture name is inferred from the file name.
#
# The sh*.s files should NOT be hand edited. Whenever the script is run
# (e.g. with 'make check') it creates a set of new (usually identical) files
# in the <objdir>/gas/testsuite directory. These are compared against the
# old ones in the testsuite. When the expected results change (or new
# architectures are added) these new files can be used to replace the old
# ones with no modification required.
#
# The script generates the architecture/option permutations automatically,
# but it reads the expected results from the file arch_expected.txt (also
# found in the same directory as this script).
#
# The arch_expected.txt file should NOT be hand edited. Whenever the script
# is run (e.g. with 'make check') it creates a new (usually identical) file
# named arch_results.txt in the <objdir>/gas/testsuite directory. When the
# expected results change (or new architectures are added) this new file
# can be used to replace arch_expected.txt with no modification required.
 
if {[istarget sh*-*-*]} then {
 
 
# This procedure extracts the architecture name from the objdump output.
# If there is no architecture name (or objdump output changes significantly)
# then the behaviour is undefined, but it will most likely return junk.
 
proc get_sh_arch { ofile } {
global comp_output
 
objdump "-f $ofile"
send_log $comp_output
 
set comp_output [string replace $comp_output 0 \
[expr [string first "architecture:" $comp_output] + 13] ""]
 
return [string range $comp_output 0 [expr [string first "," $comp_output] - 1]]
}
 
 
# This procedure runs two tests:
# Test 1: Check the assembler can assemble the given file with
# given options.
# Test 2: Check that the resultant architecture is as expected.
# It also writes an entry to the arch_results.txt file.
 
proc test_arch { file opt arch resultfile } {
global comp_output
 
set name [file tail $file]
set rootname [file rootname $name]
 
if [string equal $opt "default-options"] then {
gas_run $name "-o ${rootname}-#${opt}#.o" ""
} else {
gas_run $name "$opt -o ${rootname}-#${opt}#.o" ""
}
 
if [want_no_output "$rootname file should assemble with $opt"] then {
set result [get_sh_arch "${rootname}-#${opt}#.o"]
puts $resultfile [format "%-20s %-25s %s" $file $opt $result]
 
if {$result == $arch} then {
pass "$rootname file with $opt should assemble to arch $arch"
file delete "${rootname}-#${opt}#.o"
} else {
send_log $comp_output
fail "$rootname file with $opt should assemble to arch $arch"
}
} else {
puts $resultfile [format "%-20s %-25s ERROR" $file $opt]
untested "$rootname file with $opt should assemble to arch $arch"
}
 
}
 
 
# This procedure tests that a file that is not suposed to assemble
# with a given option does, in fact, not assemble.
# It also writes an entry to the arch_results.txt file.
 
proc test_arch_error { file opt resultfile} {
global comp_output
 
set name [file tail $file]
set rootname [file rootname $name]
 
if [string equal $opt "default-options"] then {
gas_run $name "-o ${rootname}-#${opt}#.o" ""
} else {
gas_run $name "$opt -o ${rootname}-#${opt}#.o" ""
}
 
if [string match "" $comp_output] then {
fail "$rootname file with $opt should not assemble"
puts $resultfile [format "%-20s %-25s [get_sh_arch ${rootname}-#${opt}#.o]" $file $opt]
} else {
pass "$rootname file with $opt should not assemble"
puts $resultfile [format "%-20s %-25s ERROR" $file $opt]
}
}
 
# These tests are not suitable for sh-coff because
# coff does not store the architecture information.
 
if [istarget sh*-*-elf] then {
global subdir srcdir
 
# Find all the architectures and generate the
# list of options we will test.
 
set filelist [lsort -ascii [glob "$srcdir/$subdir/sh*.s"]]
set optlist {"default-options" "-dsp" "-isa=any" "-isa=dsp" "-isa=fp"}
foreach file $filelist {
set arch [file rootname [file tail $file]]
lappend optlist "-isa=$arch" "-isa=${arch}-up"
}
 
# Initialise the results file
 
set outfile [open "arch_results.txt" w 0666]
puts $outfile "# Generated file. DO NOT EDIT"
puts $outfile "#"
puts $outfile "# This file is generated by gas/testsuite/gas/sh/arch/arch.exp ."
puts $outfile "# It contains the expected results of the tests."
puts $outfile "# If the tests are failing because the expected results"
puts $outfile "# have changed then run 'make check' and copy the new file"
puts $outfile "# from <objdir>/gas/testsuite/arch_results.txt"
puts $outfile "# to <srcdir>/gas/testsuite/gas/sh/arch/arch_expected.txt ."
puts $outfile "# Make sure the new expected results are ALL correct."
puts $outfile "#"
puts $outfile [format "# %-18s %-25s %s" "FILE" "OPTION" "OUTPUT"]
puts $outfile [format "# %-18s %-25s %s" "----" "------" "------"]
 
# Open the expected results file and skip the header
 
set infile [open "$srcdir/$subdir/arch_expected.txt" r]
while {[gets $infile line] >= 0 && [string match {\#*} $line]} {send_log "reading '$line'\n"}
 
foreach file $filelist {
foreach opt $optlist {
set name [file tail $file]
set rootname [file rootname $name]
 
# Decode the expected result from the file
 
scan $line "%s %s %s" exfile exopt exarch
send_log "exfile = '$exfile', exopt = '$exopt', exarch = '$exarch'\n"
send_log " name = '$name', opt = '$opt'\n"
 
if {[string equal $exfile $name] && [string equal $exopt $opt]} then {
# The expected result file makes sense and
# appears up-to-date (the file and options match)
 
if {[string equal $exarch "ERROR"]} then {
test_arch_error $name $opt $outfile
} else {
test_arch $name $opt $exarch $outfile
}
} else {
# The expected result file isn't right somehow
# so just try any old test. This will cause
# many failures, but will generate the results file.
 
test_arch $name $opt $rootname $outfile
}
 
# Read the next line from the expected result file.
# This is at the end because the process of skipping
# the header reads the first real line
 
if [gets $infile line] then {
send_log "reading '$line'\n"
}
}
}
 
close $infile
close $outfile
}
 
return
 
#########################################################################
# Generate one sh*.s file for each architecture defined in sh-opc.h
# This will contain all the instructions valid on that platform
#
# This code produces pass or fail reports for each instruction
# in order to ensure that problems are visible to the developer,
# rather than just warnings hidden in the log file.
 
# These variables will contains the architecture
# and instruction data extracted from sh-opc.h
array set arches {}
set archcount 0
array set insns {}
set insncount 0
 
# Pull the architecture inheritance macros out of sh-opc.h
# Pull all the insns out of the sh-opc.h file.
send_log "Reading sh-opc.h\n"
send_log "========================================================\n"
spawn -noecho cat "$srcdir/../../opcodes/sh-opc.h" ;# -open doesn't seem to be reliable
expect {
-re {#define\s+arch_([^ ]*)_up\s*\(([^)]*)\)} {
set arches($archcount) [string map {_ -} $expect_out(1,string)]
set arches($archcount,descendents) [string map {_ -} $expect_out(2,string)]
incr archcount
pass "Architecture arch_$expect_out(1,string) read OK"
exp_continue
}
# Match all 32 bit opcodes
-re {(?x) # enable expanded regexp syntax
^/\* # open C comment at start of input
(?:\s*\S+){2} # 2 binary words (for 32 bit opcodes)
\s+ ([^*]+?) # instruction mnemonics (must not leave comment)
\s* \*/ # close C comment
\s* \{ # open brace of data initialiser
(?:[^\}]+\}){2}# 2 brace pairs (operands and nibbles)
\s* , # comma
\s* arch_(\S+)_up # architecture name
\s* \| # literal or
\s* arch_op32 # 32 bit opcode indicator
\s* \} # close brace of data initialiser
} {
set insns(insn,$insncount) $expect_out(1,string)
set insns(arch,$insncount) [string map {_ -} $expect_out(2,string)]
set insns(context,$insncount) $expect_out(0,string)
incr insncount
pass "Instruction '$expect_out(1,string)' read OK"
exp_continue
}
# Special case: Match the repeat pseudo op
-re {(?x) # enable expanded regexp syntax
^/\* # open C comment at start of input
\s* repeat # repeat does not have a bit pattern
\s+ start\s+end # don't read fake operands as such (replaced below)
\s+ ([^*]+?) # instruction operand
\s* \*/ # close C comment
\s* \{ # open brace of data initialiser
(?:[^\}]+\}){2}# 2 brace pairs (operands and nibbles)
\s* , # comma
\s* arch_(\S+)_up # architecture name
\s* \} # close brace of data initialiser
} {
set insns(insn,$insncount) "repeat 10 20 $expect_out(1,string)"
set insns(arch,$insncount) [string map {_ -} $expect_out(2,string)]
set insns(context,$insncount) $expect_out(0,string)
incr insncount
pass "Instruction '$expect_out(1,string)' read OK"
exp_continue
}
# Match all 16 bit opcodes
-re {(?x) # enable expanded regexp syntax
^/\* # open C comment at start of input
\s* \S+ # 1 binary word (for 16 bit opcodes)
\s+ ([^*]+?) # instruction mnemonics (must not leave comment)
\s* \*/ # close C comment
\s* \{ # open brace of data initialiser
(?:[^\}]+\}){2}# 2 brace pairs (operands and nibbles)
\s* , # comma
\s* arch_(\S+)_up # architecture name
\s* \} # close brace of data initialiser
} {
set insns(insn,$insncount) $expect_out(1,string)
set insns(arch,$insncount) [string map {_ -} $expect_out(2,string)]
set insns(context,$insncount) $expect_out(0,string)
incr insncount
pass "Instruction '$expect_out(1,string)' read OK"
exp_continue
}
# Match all remaining possible instructions (error detection)
-re {(?x) # enable expanded regexp syntax
^/\* # open C comment at start of input
(?:[^*]*(?:\*[^/])?)+ # match contents of comment allowing *
\*/ # close C comment
\s* \{ # open brace of data initialiser
(?:[^\}]+\}){2}# 2 brace pairs (operands and nibbles)
\s* , # comma
[^\}]*
arch # look for 'arch' anywhere before closing brace
[^\}]*
\} # close brace of data initialiser
} {
fail "Found something that looks like an instruction but cannot be decoded:\n\t$expect_out(0,string)"
exp_continue
}
# No match so move to next (possible) comment
-re {^.+?((?=/\*)|(?=\#\s*define))} exp_continue
}
send_log "--------------------------------------------------------\n"
 
if {$archcount == 0} then {
fail "Unable to read any architectures from sh-opc.h"
} else {
pass "Read architecture data from sh-opc.h"
}
if {$insncount == 0} then {
fail "Unable to read any instructions from sh-opc.h"
} else {
pass "Read instruction data from sh-opc.h"
}
 
# Munge the insns such that they will assemble
# Each instruction in sh-opc.h has an example format
# with placeholders for the parameters. These placeholders
# need to be replaced with real registers and constants
# as appropriate in order to assemble correctly.
for {set i 0} {$i < $insncount} {incr i} {
set out $insns(insn,$i)
if {[regexp {AY_.{3,4}_N} $insns(context,$i)] == 1} then {
regsub -nocase {<REG_N>} $out {r6} out
} else {
regsub -nocase {<REG_N>} $out {r4} out
}
regsub -nocase {<REG_M>} $out {r5} out
if {[regexp {IMM0_20BY8} $insns(context,$i)] == 1} then {
regsub -nocase {<imm>} $out {1024} out
} else {
regsub -nocase {<imm>} $out {4} out
}
regsub -nocase {<bdisp\d*>} $out {.+8} out
regsub -nocase {<disp12>} $out {2048} out
regsub -nocase {<disp\d*>} $out {8} out
regsub -nocase {Rn_BANK} $out {r1_bank} out
regsub -nocase {Rm_BANK} $out {r2_bank} out
regsub -nocase {<F_REG_N>} $out {fr1} out
regsub -nocase {<F_REG_M>} $out {fr2} out
regsub -nocase {<D_REG_N>} $out {dr2} out
regsub -nocase {<D_REG_M>} $out {dr4} out
regsub -nocase {<V_REG_N>} $out {fv0} out
regsub -nocase {<V_REG_M>} $out {fv4} out
regsub -nocase {<DX_REG_N>} $out {xd2} out
regsub -nocase {<DX_REG_M>} $out {xd4} out
regsub -nocase (XMTRX_M4) $out {xmtrx} out
regsub -nocase (<DSP_REG_X>) $out {x1} out
regsub -nocase (<DSP_REG_Y>) $out {y0} out
regsub -nocase (<DSP_REG_M>) $out {a1} out
regsub -nocase (<DSP_REG_N>) $out {m0} out
regsub -nocase (<REG_Axy>) $out {r1} out
regsub -nocase (<REG_Ayx>) $out {r3} out
regsub -nocase (<DSP_REG_XY>) $out {y1} out
regsub -nocase (<DSP_REG_YX>) $out {y1} out
regsub -nocase (<DSP_REG_AX>) $out {a0} out
regsub -nocase (<DSP_REG_AY>) $out {a0} out
regsub (Se) $out {x0} out
regsub (Sf) $out {y0} out
regsub (Dg) $out {m0} out
# Put in a dct in order to differentiate between
# conditional and non-conditional pabs and prnd
# i.e. between sh-dsp and sh4al-dsp
if {[regexp {PPIC} $insns(context,$i)] == 1} then {
set out "dct $out"
}
# Make sure the proper alignments are ok.
if [regexp {i8p4} $insns(context,$i)] {
set out ".align 2\n\t$out"
}
 
# Write back the results.
set insns(insn,$i) $out
set insns(context,$i) [string map {\n " " \r " "} $insns(context,$i)]
}
 
# Initialise the data structure for the inheritance
array set archtree {}
for {set a 0} {$a < $archcount} {incr a} {
set archtree($arches($a)) {}
}
 
# For each architecture, extract its immediate parents
for {set a 0} {$a < $archcount} {incr a} {
set s $arches($a,descendents)
regsub -all {[\s|]+} $s { } s
foreach word [split $s { }] {
# Word should be one of arch-..., | (or), or arch-...-up
# We only want the -up information
# Note that the _ -> - translation was done above
if {[regexp {^arch-(.*)-up$} $word match arch] == 1} then {
# $arch is the descendent of $arches($a),
# so $arches($a) is the parent of $arch
lappend archtree($arch) $arches($a)
}
}
}
 
# Propagate the inhertances through the list
# Iterate to ensure all inheritances are found (necessary?)
set changesmade 1
while {$changesmade == 1} {
set changesmade 0
foreach a [array names archtree] {
foreach b [array names archtree] {
# If arch 'a' is a parent of arch 'b' then b inherits from a
if {[lsearch -exact $archtree($b) $a] != -1} then {
# Only add each arch if it is not already present
foreach arch $archtree($a) {
if {[lsearch -exact $archtree($b) $arch] == -1} then {
lappend archtree($b) $arch
set changesmade 1
}
}
}
}
}
}
 
# Generate the assembler file for each architecture
# Also count up how many instructions should be valid for each architecture
array set insns_valid {}
for {set arch 0} {$arch < $archcount} {incr arch} {
set insns_valid($arches($arch)) 0
set fd [open $arches($arch).s w 0666]
puts $fd "! Generated file. DO NOT EDIT.\n!"
puts $fd "! This file was generated by gas/testsuite/gas/sh/arch/arch.exp ."
puts $fd "! This file should contain every instruction valid on"
puts $fd "! architecture $arches($arch) but no more."
puts $fd "! If the tests are failing because the expected results"
puts $fd "! have changed then run 'make check' and copy the new file"
puts $fd "! from <objdir>/gas/testsuite/$arches($arch).s"
puts $fd "! to <srcdir>/gas/testsuite/gas/sh/arch/$arches($arch).s ."
puts $fd "! Make sure there are no unexpected or missing instructions."
puts $fd "\n\t.section .text"
puts $fd "[string map {- _} $arches($arch)]:"
puts $fd "! Instructions introduced into $arches($arch)"
for {set i 0} {$i < $insncount} {incr i} {
if [string equal $arches($arch) $insns(arch,$i)] then {
puts $fd [format "\t%-25s ;!%s" $insns(insn,$i) $insns(context,$i)]
incr insns_valid($arches($arch))
}
}
puts $fd "\n! Instructions inherited from ancestors: [lsort -increasing $archtree($arches($arch))]"
for {set i 0} {$i < $insncount} {incr i} {
if {[string equal $arches($arch) $insns(arch,$i)] != 1 && [lsearch -exact $archtree($arches($arch)) $insns(arch,$i)] != -1} then {
puts $fd [format "\t%-25s ;!%s" $insns(insn,$i) $insns(context,$i)]
incr insns_valid($arches($arch))
}
}
close $fd
}
 
 
###################################################################
# Compare the newly created sh*.s files with the existing
# ones in the testsuite
 
for {set arch 0} {$arch < $archcount} {incr arch} {
send_log "diff $srcdir/$subdir/$arches($arch).s $arches($arch).s\n"
catch "exec diff $srcdir/$subdir/$arches($arch).s $arches($arch).s" diff_output
if {[string equal $diff_output ""] == 0} then {
send_log $diff_output
fail "Check $arches($arch) architecture has not changed"
} else {
pass "Check $arches($arch) architecture has not changed"
}
}
 
 
###################################################################
# Generate an assembler file with every instruction
# Then use it to test how many failures there are for
# each architecture. If this does not match the predicted value
# then the assembler accepts too many instructions for a given
# architecture.
 
 
set fd [open "all_insns.s" w 0666]
for {set i 0} {$i < $insncount} {incr i} {
puts $fd [format "\t%-25s ;!%s" $insns(insn,$i) $insns(context,$i)]
}
close $fd
 
# Assemble the all_insns.s file for each isa and count how many failures there are
foreach arch [array names insns_valid] {
set errormessages 0
set expected [expr $insncount - $insns_valid($arch)]
 
# The -Z option ensures that all error messages are output,
# even those from later phases of assembly (such as offset range errors)
send_log "$AS -Z -isa=$arch all_insns.s -o /dev/null\n"
spawn $AS -Z -isa=$arch all_insns.s -o /dev/null
expect Error: {incr errormessages; exp_continue}
 
if {$errormessages == $expected} then {
pass "$expected insns should not assemble on $arch"
} else {
if {([istarget sh*-*-coff] || [istarget sh*-hms]) && [string match {*dsp} $arch]} {
xfail "$expected insns should not assemble on $arch ($errormessages did not)"
} else {
fail "$expected insns should not assemble on $arch ($errormessages did not)"
}
}
}
 
 
} ;# istarget sh*-*-*
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
0,0 → 1,233
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh2a-or-sh4 but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh2a-or-sh4.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh2a_or_sh4:
! Instructions introduced into sh2a-or-sh4
fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
0,0 → 1,169
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh2a-nofpu-or-sh4-nommu-nofpu but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh2a-nofpu-or-sh4-nommu-nofpu.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh2a_nofpu_or_sh4_nommu_nofpu:
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh.s
0,0 → 1,155
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh:
! Instructions introduced into sh
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
 
! Instructions inherited from ancestors:
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
0,0 → 1,205
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh2a-or-sh3e but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh2a-or-sh3e.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh2a_or_sh3e:
! Instructions introduced into sh2a-or-sh3e
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/arch_expected.txt
0,0 → 1,912
# Generated file. DO NOT EDIT
#
# This file is generated by gas/testsuite/gas/sh/arch/arch.exp .
# It contains the expected results of the tests.
# If the tests are failing because the expected results
# have changed then run 'make check' and copy the new file
# from <objdir>/gas/testsuite/arch_results.txt
# to <srcdir>/gas/testsuite/gas/sh/arch/arch_expected.txt .
# Make sure the new expected results are ALL correct.
#
# FILE OPTION OUTPUT
# ---- ------ ------
sh-dsp.s default-options ERROR
sh-dsp.s -dsp sh-dsp
sh-dsp.s -isa=any sh-dsp
sh-dsp.s -isa=dsp sh-dsp
sh-dsp.s -isa=fp ERROR
sh-dsp.s -isa=sh-dsp sh-dsp
sh-dsp.s -isa=sh-dsp-up sh-dsp
sh-dsp.s -isa=sh ERROR
sh-dsp.s -isa=sh-up sh-dsp
sh-dsp.s -isa=sh2 ERROR
sh-dsp.s -isa=sh2-up sh-dsp
sh-dsp.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh-dsp.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3-dsp
sh-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp
sh-dsp.s -isa=sh2a-nofpu ERROR
sh-dsp.s -isa=sh2a-nofpu-up ERROR
sh-dsp.s -isa=sh2a-or-sh3e ERROR
sh-dsp.s -isa=sh2a-or-sh3e-up ERROR
sh-dsp.s -isa=sh2a-or-sh4 ERROR
sh-dsp.s -isa=sh2a-or-sh4-up ERROR
sh-dsp.s -isa=sh2a ERROR
sh-dsp.s -isa=sh2a-up ERROR
sh-dsp.s -isa=sh2e ERROR
sh-dsp.s -isa=sh2e-up ERROR
sh-dsp.s -isa=sh3-dsp sh3-dsp
sh-dsp.s -isa=sh3-dsp-up sh3-dsp
sh-dsp.s -isa=sh3-nommu ERROR
sh-dsp.s -isa=sh3-nommu-up sh3-dsp
sh-dsp.s -isa=sh3 ERROR
sh-dsp.s -isa=sh3-up sh3-dsp
sh-dsp.s -isa=sh3e ERROR
sh-dsp.s -isa=sh3e-up ERROR
sh-dsp.s -isa=sh4-nofpu ERROR
sh-dsp.s -isa=sh4-nofpu-up sh4al-dsp
sh-dsp.s -isa=sh4-nommu-nofpu ERROR
sh-dsp.s -isa=sh4-nommu-nofpu-up sh4al-dsp
sh-dsp.s -isa=sh4 ERROR
sh-dsp.s -isa=sh4-up ERROR
sh-dsp.s -isa=sh4a-nofpu ERROR
sh-dsp.s -isa=sh4a-nofpu-up sh4al-dsp
sh-dsp.s -isa=sh4a ERROR
sh-dsp.s -isa=sh4a-up ERROR
sh-dsp.s -isa=sh4al-dsp sh4al-dsp
sh-dsp.s -isa=sh4al-dsp-up sh4al-dsp
sh.s default-options sh
sh.s -dsp sh
sh.s -isa=any sh
sh.s -isa=dsp sh
sh.s -isa=fp sh
sh.s -isa=sh-dsp sh-dsp
sh.s -isa=sh-dsp-up sh-dsp
sh.s -isa=sh sh
sh.s -isa=sh-up sh
sh.s -isa=sh2 sh2
sh.s -isa=sh2-up sh2
sh.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu
sh.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu
sh.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
sh.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu
sh.s -isa=sh2a-nofpu sh2a-nofpu
sh.s -isa=sh2a-nofpu-up sh2a-nofpu
sh.s -isa=sh2a-or-sh3e sh2a-or-sh3e
sh.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e
sh.s -isa=sh2a-or-sh4 sh2a-or-sh4
sh.s -isa=sh2a-or-sh4-up sh2a-or-sh4
sh.s -isa=sh2a sh2a
sh.s -isa=sh2a-up sh2a
sh.s -isa=sh2e sh2e
sh.s -isa=sh2e-up sh2e
sh.s -isa=sh3-dsp sh3-dsp
sh.s -isa=sh3-dsp-up sh3-dsp
sh.s -isa=sh3-nommu sh3-nommu
sh.s -isa=sh3-nommu-up sh3-nommu
sh.s -isa=sh3 sh3
sh.s -isa=sh3-up sh3
sh.s -isa=sh3e sh3e
sh.s -isa=sh3e-up sh3e
sh.s -isa=sh4-nofpu sh4-nofpu
sh.s -isa=sh4-nofpu-up sh4-nofpu
sh.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu
sh.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu
sh.s -isa=sh4 sh4
sh.s -isa=sh4-up sh4
sh.s -isa=sh4a-nofpu sh4a-nofpu
sh.s -isa=sh4a-nofpu-up sh4a-nofpu
sh.s -isa=sh4a sh4a
sh.s -isa=sh4a-up sh4a
sh.s -isa=sh4al-dsp sh4al-dsp
sh.s -isa=sh4al-dsp-up sh4al-dsp
sh2.s default-options sh2
sh2.s -dsp sh2
sh2.s -isa=any sh2
sh2.s -isa=dsp sh2
sh2.s -isa=fp sh2
sh2.s -isa=sh-dsp sh-dsp
sh2.s -isa=sh-dsp-up sh-dsp
sh2.s -isa=sh ERROR
sh2.s -isa=sh-up sh2
sh2.s -isa=sh2 sh2
sh2.s -isa=sh2-up sh2
sh2.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu
sh2.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu
sh2.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
sh2.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu
sh2.s -isa=sh2a-nofpu sh2a-nofpu
sh2.s -isa=sh2a-nofpu-up sh2a-nofpu
sh2.s -isa=sh2a-or-sh3e sh2a-or-sh3e
sh2.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e
sh2.s -isa=sh2a-or-sh4 sh2a-or-sh4
sh2.s -isa=sh2a-or-sh4-up sh2a-or-sh4
sh2.s -isa=sh2a sh2a
sh2.s -isa=sh2a-up sh2a
sh2.s -isa=sh2e sh2e
sh2.s -isa=sh2e-up sh2e
sh2.s -isa=sh3-dsp sh3-dsp
sh2.s -isa=sh3-dsp-up sh3-dsp
sh2.s -isa=sh3-nommu sh3-nommu
sh2.s -isa=sh3-nommu-up sh3-nommu
sh2.s -isa=sh3 sh3
sh2.s -isa=sh3-up sh3
sh2.s -isa=sh3e sh3e
sh2.s -isa=sh3e-up sh3e
sh2.s -isa=sh4-nofpu sh4-nofpu
sh2.s -isa=sh4-nofpu-up sh4-nofpu
sh2.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu
sh2.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu
sh2.s -isa=sh4 sh4
sh2.s -isa=sh4-up sh4
sh2.s -isa=sh4a-nofpu sh4a-nofpu
sh2.s -isa=sh4a-nofpu-up sh4a-nofpu
sh2.s -isa=sh4a sh4a
sh2.s -isa=sh4a-up sh4a
sh2.s -isa=sh4al-dsp sh4al-dsp
sh2.s -isa=sh4al-dsp-up sh4al-dsp
sh2a-nofpu-or-sh3-nommu.s default-options sh2a-nofpu-or-sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -dsp sh2a-nofpu-or-sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=any sh2a-nofpu-or-sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=dsp sh2a-nofpu-or-sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=fp sh2a-nofpu-or-sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=sh-dsp ERROR
sh2a-nofpu-or-sh3-nommu.s -isa=sh-dsp-up sh3-dsp
sh2a-nofpu-or-sh3-nommu.s -isa=sh ERROR
sh2a-nofpu-or-sh3-nommu.s -isa=sh-up sh2a-nofpu-or-sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=sh2 ERROR
sh2a-nofpu-or-sh3-nommu.s -isa=sh2-up sh2a-nofpu-or-sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu sh2a-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-up sh2a-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh3e sh2a-or-sh3e
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh4 sh2a-or-sh4
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-or-sh4-up sh2a-or-sh4
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a sh2a
sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-up sh2a
sh2a-nofpu-or-sh3-nommu.s -isa=sh2e ERROR
sh2a-nofpu-or-sh3-nommu.s -isa=sh2e-up sh2a-or-sh3e
sh2a-nofpu-or-sh3-nommu.s -isa=sh3-dsp sh3-dsp
sh2a-nofpu-or-sh3-nommu.s -isa=sh3-dsp-up sh3-dsp
sh2a-nofpu-or-sh3-nommu.s -isa=sh3-nommu sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=sh3-nommu-up sh3-nommu
sh2a-nofpu-or-sh3-nommu.s -isa=sh3 sh3
sh2a-nofpu-or-sh3-nommu.s -isa=sh3-up sh3
sh2a-nofpu-or-sh3-nommu.s -isa=sh3e sh3e
sh2a-nofpu-or-sh3-nommu.s -isa=sh3e-up sh3e
sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nofpu sh4-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nofpu-up sh4-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh4 sh4
sh2a-nofpu-or-sh3-nommu.s -isa=sh4-up sh4
sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-nofpu sh4a-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-nofpu-up sh4a-nofpu
sh2a-nofpu-or-sh3-nommu.s -isa=sh4a sh4a
sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-up sh4a
sh2a-nofpu-or-sh3-nommu.s -isa=sh4al-dsp sh4al-dsp
sh2a-nofpu-or-sh3-nommu.s -isa=sh4al-dsp-up sh4al-dsp
sh2a-nofpu-or-sh4-nommu-nofpu.s default-options sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -dsp sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=any sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=dsp sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=fp sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-dsp ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-dsp-up sh4al-dsp
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-up sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2 ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2-up sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu sh2a-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-up sh2a-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh3e ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh3e-up sh2a-or-sh4
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh4 sh2a-or-sh4
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh4-up sh2a-or-sh4
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a sh2a
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-up sh2a
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2e ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2e-up sh2a-or-sh4
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-dsp ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-dsp-up sh4al-dsp
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-nommu ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-nommu-up sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3 ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-up sh4-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3e ERROR
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3e-up sh4
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nofpu sh4-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nofpu-up sh4-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4 sh4
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-up sh4
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-nofpu sh4a-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-nofpu-up sh4a-nofpu
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a sh4a
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-up sh4a
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4al-dsp sh4al-dsp
sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4al-dsp-up sh4al-dsp
sh2a-nofpu.s default-options sh2a-nofpu
sh2a-nofpu.s -dsp sh2a-nofpu
sh2a-nofpu.s -isa=any sh2a-nofpu
sh2a-nofpu.s -isa=dsp sh2a-nofpu
sh2a-nofpu.s -isa=fp sh2a-nofpu
sh2a-nofpu.s -isa=sh-dsp ERROR
sh2a-nofpu.s -isa=sh-dsp-up ERROR
sh2a-nofpu.s -isa=sh ERROR
sh2a-nofpu.s -isa=sh-up sh2a-nofpu
sh2a-nofpu.s -isa=sh2 ERROR
sh2a-nofpu.s -isa=sh2-up sh2a-nofpu
sh2a-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh2a-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu
sh2a-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh2a-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu
sh2a-nofpu.s -isa=sh2a-nofpu sh2a-nofpu
sh2a-nofpu.s -isa=sh2a-nofpu-up sh2a-nofpu
sh2a-nofpu.s -isa=sh2a-or-sh3e ERROR
sh2a-nofpu.s -isa=sh2a-or-sh3e-up sh2a
sh2a-nofpu.s -isa=sh2a-or-sh4 ERROR
sh2a-nofpu.s -isa=sh2a-or-sh4-up sh2a
sh2a-nofpu.s -isa=sh2a sh2a
sh2a-nofpu.s -isa=sh2a-up sh2a
sh2a-nofpu.s -isa=sh2e ERROR
sh2a-nofpu.s -isa=sh2e-up sh2a
sh2a-nofpu.s -isa=sh3-dsp ERROR
sh2a-nofpu.s -isa=sh3-dsp-up ERROR
sh2a-nofpu.s -isa=sh3-nommu ERROR
sh2a-nofpu.s -isa=sh3-nommu-up ERROR
sh2a-nofpu.s -isa=sh3 ERROR
sh2a-nofpu.s -isa=sh3-up ERROR
sh2a-nofpu.s -isa=sh3e ERROR
sh2a-nofpu.s -isa=sh3e-up ERROR
sh2a-nofpu.s -isa=sh4-nofpu ERROR
sh2a-nofpu.s -isa=sh4-nofpu-up ERROR
sh2a-nofpu.s -isa=sh4-nommu-nofpu ERROR
sh2a-nofpu.s -isa=sh4-nommu-nofpu-up ERROR
sh2a-nofpu.s -isa=sh4 ERROR
sh2a-nofpu.s -isa=sh4-up ERROR
sh2a-nofpu.s -isa=sh4a-nofpu ERROR
sh2a-nofpu.s -isa=sh4a-nofpu-up ERROR
sh2a-nofpu.s -isa=sh4a ERROR
sh2a-nofpu.s -isa=sh4a-up ERROR
sh2a-nofpu.s -isa=sh4al-dsp ERROR
sh2a-nofpu.s -isa=sh4al-dsp-up ERROR
sh2a-or-sh3e.s default-options sh2a-or-sh3e
sh2a-or-sh3e.s -dsp ERROR
sh2a-or-sh3e.s -isa=any sh2a-or-sh3e
sh2a-or-sh3e.s -isa=dsp ERROR
sh2a-or-sh3e.s -isa=fp sh2a-or-sh3e
sh2a-or-sh3e.s -isa=sh-dsp ERROR
sh2a-or-sh3e.s -isa=sh-dsp-up ERROR
sh2a-or-sh3e.s -isa=sh ERROR
sh2a-or-sh3e.s -isa=sh-up sh2a-or-sh3e
sh2a-or-sh3e.s -isa=sh2 ERROR
sh2a-or-sh3e.s -isa=sh2-up sh2a-or-sh3e
sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e
sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh2a-or-sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4
sh2a-or-sh3e.s -isa=sh2a-nofpu ERROR
sh2a-or-sh3e.s -isa=sh2a-nofpu-up sh2a
sh2a-or-sh3e.s -isa=sh2a-or-sh3e sh2a-or-sh3e
sh2a-or-sh3e.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e
sh2a-or-sh3e.s -isa=sh2a-or-sh4 sh2a-or-sh4
sh2a-or-sh3e.s -isa=sh2a-or-sh4-up sh2a-or-sh4
sh2a-or-sh3e.s -isa=sh2a sh2a
sh2a-or-sh3e.s -isa=sh2a-up sh2a
sh2a-or-sh3e.s -isa=sh2e ERROR
sh2a-or-sh3e.s -isa=sh2e-up sh2a-or-sh3e
sh2a-or-sh3e.s -isa=sh3-dsp ERROR
sh2a-or-sh3e.s -isa=sh3-dsp-up ERROR
sh2a-or-sh3e.s -isa=sh3-nommu ERROR
sh2a-or-sh3e.s -isa=sh3-nommu-up sh3e
sh2a-or-sh3e.s -isa=sh3 ERROR
sh2a-or-sh3e.s -isa=sh3-up sh3e
sh2a-or-sh3e.s -isa=sh3e sh3e
sh2a-or-sh3e.s -isa=sh3e-up sh3e
sh2a-or-sh3e.s -isa=sh4-nofpu ERROR
sh2a-or-sh3e.s -isa=sh4-nofpu-up sh4
sh2a-or-sh3e.s -isa=sh4-nommu-nofpu ERROR
sh2a-or-sh3e.s -isa=sh4-nommu-nofpu-up sh4
sh2a-or-sh3e.s -isa=sh4 sh4
sh2a-or-sh3e.s -isa=sh4-up sh4
sh2a-or-sh3e.s -isa=sh4a-nofpu ERROR
sh2a-or-sh3e.s -isa=sh4a-nofpu-up sh4a
sh2a-or-sh3e.s -isa=sh4a sh4a
sh2a-or-sh3e.s -isa=sh4a-up sh4a
sh2a-or-sh3e.s -isa=sh4al-dsp ERROR
sh2a-or-sh3e.s -isa=sh4al-dsp-up ERROR
sh2a-or-sh4.s default-options sh2a-or-sh4
sh2a-or-sh4.s -dsp ERROR
sh2a-or-sh4.s -isa=any sh2a-or-sh4
sh2a-or-sh4.s -isa=dsp ERROR
sh2a-or-sh4.s -isa=fp sh2a-or-sh4
sh2a-or-sh4.s -isa=sh-dsp ERROR
sh2a-or-sh4.s -isa=sh-dsp-up ERROR
sh2a-or-sh4.s -isa=sh ERROR
sh2a-or-sh4.s -isa=sh-up sh2a-or-sh4
sh2a-or-sh4.s -isa=sh2 ERROR
sh2a-or-sh4.s -isa=sh2-up sh2a-or-sh4
sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh4
sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh2a-or-sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4
sh2a-or-sh4.s -isa=sh2a-nofpu ERROR
sh2a-or-sh4.s -isa=sh2a-nofpu-up sh2a
sh2a-or-sh4.s -isa=sh2a-or-sh3e ERROR
sh2a-or-sh4.s -isa=sh2a-or-sh3e-up sh2a-or-sh4
sh2a-or-sh4.s -isa=sh2a-or-sh4 sh2a-or-sh4
sh2a-or-sh4.s -isa=sh2a-or-sh4-up sh2a-or-sh4
sh2a-or-sh4.s -isa=sh2a sh2a
sh2a-or-sh4.s -isa=sh2a-up sh2a
sh2a-or-sh4.s -isa=sh2e ERROR
sh2a-or-sh4.s -isa=sh2e-up sh2a-or-sh4
sh2a-or-sh4.s -isa=sh3-dsp ERROR
sh2a-or-sh4.s -isa=sh3-dsp-up ERROR
sh2a-or-sh4.s -isa=sh3-nommu ERROR
sh2a-or-sh4.s -isa=sh3-nommu-up sh4
sh2a-or-sh4.s -isa=sh3 ERROR
sh2a-or-sh4.s -isa=sh3-up sh4
sh2a-or-sh4.s -isa=sh3e ERROR
sh2a-or-sh4.s -isa=sh3e-up sh4
sh2a-or-sh4.s -isa=sh4-nofpu ERROR
sh2a-or-sh4.s -isa=sh4-nofpu-up sh4
sh2a-or-sh4.s -isa=sh4-nommu-nofpu ERROR
sh2a-or-sh4.s -isa=sh4-nommu-nofpu-up sh4
sh2a-or-sh4.s -isa=sh4 sh4
sh2a-or-sh4.s -isa=sh4-up sh4
sh2a-or-sh4.s -isa=sh4a-nofpu ERROR
sh2a-or-sh4.s -isa=sh4a-nofpu-up sh4a
sh2a-or-sh4.s -isa=sh4a sh4a
sh2a-or-sh4.s -isa=sh4a-up sh4a
sh2a-or-sh4.s -isa=sh4al-dsp ERROR
sh2a-or-sh4.s -isa=sh4al-dsp-up ERROR
sh2a.s default-options sh2a
sh2a.s -dsp ERROR
sh2a.s -isa=any sh2a
sh2a.s -isa=dsp ERROR
sh2a.s -isa=fp sh2a
sh2a.s -isa=sh-dsp ERROR
sh2a.s -isa=sh-dsp-up ERROR
sh2a.s -isa=sh ERROR
sh2a.s -isa=sh-up sh2a
sh2a.s -isa=sh2 ERROR
sh2a.s -isa=sh2-up sh2a
sh2a.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh2a.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a
sh2a.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh2a.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a
sh2a.s -isa=sh2a-nofpu ERROR
sh2a.s -isa=sh2a-nofpu-up sh2a
sh2a.s -isa=sh2a-or-sh3e ERROR
sh2a.s -isa=sh2a-or-sh3e-up sh2a
sh2a.s -isa=sh2a-or-sh4 ERROR
sh2a.s -isa=sh2a-or-sh4-up sh2a
sh2a.s -isa=sh2a sh2a
sh2a.s -isa=sh2a-up sh2a
sh2a.s -isa=sh2e ERROR
sh2a.s -isa=sh2e-up sh2a
sh2a.s -isa=sh3-dsp ERROR
sh2a.s -isa=sh3-dsp-up ERROR
sh2a.s -isa=sh3-nommu ERROR
sh2a.s -isa=sh3-nommu-up ERROR
sh2a.s -isa=sh3 ERROR
sh2a.s -isa=sh3-up ERROR
sh2a.s -isa=sh3e ERROR
sh2a.s -isa=sh3e-up ERROR
sh2a.s -isa=sh4-nofpu ERROR
sh2a.s -isa=sh4-nofpu-up ERROR
sh2a.s -isa=sh4-nommu-nofpu ERROR
sh2a.s -isa=sh4-nommu-nofpu-up ERROR
sh2a.s -isa=sh4 ERROR
sh2a.s -isa=sh4-up ERROR
sh2a.s -isa=sh4a-nofpu ERROR
sh2a.s -isa=sh4a-nofpu-up ERROR
sh2a.s -isa=sh4a ERROR
sh2a.s -isa=sh4a-up ERROR
sh2a.s -isa=sh4al-dsp ERROR
sh2a.s -isa=sh4al-dsp-up ERROR
sh2e.s default-options sh2e
sh2e.s -dsp ERROR
sh2e.s -isa=any sh2e
sh2e.s -isa=dsp ERROR
sh2e.s -isa=fp sh2e
sh2e.s -isa=sh-dsp ERROR
sh2e.s -isa=sh-dsp-up ERROR
sh2e.s -isa=sh ERROR
sh2e.s -isa=sh-up sh2e
sh2e.s -isa=sh2 ERROR
sh2e.s -isa=sh2-up sh2e
sh2e.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh2e.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e
sh2e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh2e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4
sh2e.s -isa=sh2a-nofpu ERROR
sh2e.s -isa=sh2a-nofpu-up sh2a
sh2e.s -isa=sh2a-or-sh3e sh2a-or-sh3e
sh2e.s -isa=sh2a-or-sh3e-up sh2a-or-sh3e
sh2e.s -isa=sh2a-or-sh4 sh2a-or-sh4
sh2e.s -isa=sh2a-or-sh4-up sh2a-or-sh4
sh2e.s -isa=sh2a sh2a
sh2e.s -isa=sh2a-up sh2a
sh2e.s -isa=sh2e sh2e
sh2e.s -isa=sh2e-up sh2e
sh2e.s -isa=sh3-dsp ERROR
sh2e.s -isa=sh3-dsp-up ERROR
sh2e.s -isa=sh3-nommu ERROR
sh2e.s -isa=sh3-nommu-up sh3e
sh2e.s -isa=sh3 ERROR
sh2e.s -isa=sh3-up sh3e
sh2e.s -isa=sh3e sh3e
sh2e.s -isa=sh3e-up sh3e
sh2e.s -isa=sh4-nofpu ERROR
sh2e.s -isa=sh4-nofpu-up sh4
sh2e.s -isa=sh4-nommu-nofpu ERROR
sh2e.s -isa=sh4-nommu-nofpu-up sh4
sh2e.s -isa=sh4 sh4
sh2e.s -isa=sh4-up sh4
sh2e.s -isa=sh4a-nofpu ERROR
sh2e.s -isa=sh4a-nofpu-up sh4a
sh2e.s -isa=sh4a sh4a
sh2e.s -isa=sh4a-up sh4a
sh2e.s -isa=sh4al-dsp ERROR
sh2e.s -isa=sh4al-dsp-up ERROR
sh3-dsp.s default-options ERROR
sh3-dsp.s -dsp sh3-dsp
sh3-dsp.s -isa=any sh3-dsp
sh3-dsp.s -isa=dsp sh3-dsp
sh3-dsp.s -isa=fp ERROR
sh3-dsp.s -isa=sh-dsp ERROR
sh3-dsp.s -isa=sh-dsp-up sh3-dsp
sh3-dsp.s -isa=sh ERROR
sh3-dsp.s -isa=sh-up sh3-dsp
sh3-dsp.s -isa=sh2 ERROR
sh3-dsp.s -isa=sh2-up sh3-dsp
sh3-dsp.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh3-dsp.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3-dsp
sh3-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh3-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp
sh3-dsp.s -isa=sh2a-nofpu ERROR
sh3-dsp.s -isa=sh2a-nofpu-up ERROR
sh3-dsp.s -isa=sh2a-or-sh3e ERROR
sh3-dsp.s -isa=sh2a-or-sh3e-up ERROR
sh3-dsp.s -isa=sh2a-or-sh4 ERROR
sh3-dsp.s -isa=sh2a-or-sh4-up ERROR
sh3-dsp.s -isa=sh2a ERROR
sh3-dsp.s -isa=sh2a-up ERROR
sh3-dsp.s -isa=sh2e ERROR
sh3-dsp.s -isa=sh2e-up ERROR
sh3-dsp.s -isa=sh3-dsp sh3-dsp
sh3-dsp.s -isa=sh3-dsp-up sh3-dsp
sh3-dsp.s -isa=sh3-nommu ERROR
sh3-dsp.s -isa=sh3-nommu-up sh3-dsp
sh3-dsp.s -isa=sh3 ERROR
sh3-dsp.s -isa=sh3-up sh3-dsp
sh3-dsp.s -isa=sh3e ERROR
sh3-dsp.s -isa=sh3e-up ERROR
sh3-dsp.s -isa=sh4-nofpu ERROR
sh3-dsp.s -isa=sh4-nofpu-up sh4al-dsp
sh3-dsp.s -isa=sh4-nommu-nofpu ERROR
sh3-dsp.s -isa=sh4-nommu-nofpu-up sh4al-dsp
sh3-dsp.s -isa=sh4 ERROR
sh3-dsp.s -isa=sh4-up ERROR
sh3-dsp.s -isa=sh4a-nofpu ERROR
sh3-dsp.s -isa=sh4a-nofpu-up sh4al-dsp
sh3-dsp.s -isa=sh4a ERROR
sh3-dsp.s -isa=sh4a-up ERROR
sh3-dsp.s -isa=sh4al-dsp sh4al-dsp
sh3-dsp.s -isa=sh4al-dsp-up sh4al-dsp
sh3-nommu.s default-options sh3-nommu
sh3-nommu.s -dsp sh3-nommu
sh3-nommu.s -isa=any sh3-nommu
sh3-nommu.s -isa=dsp sh3-nommu
sh3-nommu.s -isa=fp sh3-nommu
sh3-nommu.s -isa=sh-dsp ERROR
sh3-nommu.s -isa=sh-dsp-up sh3-dsp
sh3-nommu.s -isa=sh ERROR
sh3-nommu.s -isa=sh-up sh3-nommu
sh3-nommu.s -isa=sh2 ERROR
sh3-nommu.s -isa=sh2-up sh3-nommu
sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3-nommu
sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nommu-nofpu
sh3-nommu.s -isa=sh2a-nofpu ERROR
sh3-nommu.s -isa=sh2a-nofpu-up ERROR
sh3-nommu.s -isa=sh2a-or-sh3e ERROR
sh3-nommu.s -isa=sh2a-or-sh3e-up sh3e
sh3-nommu.s -isa=sh2a-or-sh4 ERROR
sh3-nommu.s -isa=sh2a-or-sh4-up sh4
sh3-nommu.s -isa=sh2a ERROR
sh3-nommu.s -isa=sh2a-up ERROR
sh3-nommu.s -isa=sh2e ERROR
sh3-nommu.s -isa=sh2e-up sh3e
sh3-nommu.s -isa=sh3-dsp sh3-dsp
sh3-nommu.s -isa=sh3-dsp-up sh3-dsp
sh3-nommu.s -isa=sh3-nommu sh3-nommu
sh3-nommu.s -isa=sh3-nommu-up sh3-nommu
sh3-nommu.s -isa=sh3 sh3
sh3-nommu.s -isa=sh3-up sh3
sh3-nommu.s -isa=sh3e sh3e
sh3-nommu.s -isa=sh3e-up sh3e
sh3-nommu.s -isa=sh4-nofpu sh4-nofpu
sh3-nommu.s -isa=sh4-nofpu-up sh4-nofpu
sh3-nommu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu
sh3-nommu.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu
sh3-nommu.s -isa=sh4 sh4
sh3-nommu.s -isa=sh4-up sh4
sh3-nommu.s -isa=sh4a-nofpu sh4a-nofpu
sh3-nommu.s -isa=sh4a-nofpu-up sh4a-nofpu
sh3-nommu.s -isa=sh4a sh4a
sh3-nommu.s -isa=sh4a-up sh4a
sh3-nommu.s -isa=sh4al-dsp sh4al-dsp
sh3-nommu.s -isa=sh4al-dsp-up sh4al-dsp
sh3.s default-options sh3
sh3.s -dsp sh3
sh3.s -isa=any sh3
sh3.s -isa=dsp sh3
sh3.s -isa=fp sh3
sh3.s -isa=sh-dsp ERROR
sh3.s -isa=sh-dsp-up sh3-dsp
sh3.s -isa=sh ERROR
sh3.s -isa=sh-up sh3
sh3.s -isa=sh2 ERROR
sh3.s -isa=sh2-up sh3
sh3.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh3.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3
sh3.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh3.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nofpu
sh3.s -isa=sh2a-nofpu ERROR
sh3.s -isa=sh2a-nofpu-up ERROR
sh3.s -isa=sh2a-or-sh3e ERROR
sh3.s -isa=sh2a-or-sh3e-up sh3e
sh3.s -isa=sh2a-or-sh4 ERROR
sh3.s -isa=sh2a-or-sh4-up sh4
sh3.s -isa=sh2a ERROR
sh3.s -isa=sh2a-up ERROR
sh3.s -isa=sh2e ERROR
sh3.s -isa=sh2e-up sh3e
sh3.s -isa=sh3-dsp sh3-dsp
sh3.s -isa=sh3-dsp-up sh3-dsp
sh3.s -isa=sh3-nommu ERROR
sh3.s -isa=sh3-nommu-up sh3
sh3.s -isa=sh3 sh3
sh3.s -isa=sh3-up sh3
sh3.s -isa=sh3e sh3e
sh3.s -isa=sh3e-up sh3e
sh3.s -isa=sh4-nofpu sh4-nofpu
sh3.s -isa=sh4-nofpu-up sh4-nofpu
sh3.s -isa=sh4-nommu-nofpu ERROR
sh3.s -isa=sh4-nommu-nofpu-up sh4-nofpu
sh3.s -isa=sh4 sh4
sh3.s -isa=sh4-up sh4
sh3.s -isa=sh4a-nofpu sh4a-nofpu
sh3.s -isa=sh4a-nofpu-up sh4a-nofpu
sh3.s -isa=sh4a sh4a
sh3.s -isa=sh4a-up sh4a
sh3.s -isa=sh4al-dsp sh4al-dsp
sh3.s -isa=sh4al-dsp-up sh4al-dsp
sh3e.s default-options sh3e
sh3e.s -dsp ERROR
sh3e.s -isa=any sh3e
sh3e.s -isa=dsp ERROR
sh3e.s -isa=fp sh3e
sh3e.s -isa=sh-dsp ERROR
sh3e.s -isa=sh-dsp-up ERROR
sh3e.s -isa=sh ERROR
sh3e.s -isa=sh-up sh3e
sh3e.s -isa=sh2 ERROR
sh3e.s -isa=sh2-up sh3e
sh3e.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh3e.s -isa=sh2a-nofpu-or-sh3-nommu-up sh3e
sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh3e.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4
sh3e.s -isa=sh2a-nofpu ERROR
sh3e.s -isa=sh2a-nofpu-up ERROR
sh3e.s -isa=sh2a-or-sh3e ERROR
sh3e.s -isa=sh2a-or-sh3e-up sh3e
sh3e.s -isa=sh2a-or-sh4 ERROR
sh3e.s -isa=sh2a-or-sh4-up sh4
sh3e.s -isa=sh2a ERROR
sh3e.s -isa=sh2a-up ERROR
sh3e.s -isa=sh2e ERROR
sh3e.s -isa=sh2e-up sh3e
sh3e.s -isa=sh3-dsp ERROR
sh3e.s -isa=sh3-dsp-up ERROR
sh3e.s -isa=sh3-nommu ERROR
sh3e.s -isa=sh3-nommu-up sh3e
sh3e.s -isa=sh3 ERROR
sh3e.s -isa=sh3-up sh3e
sh3e.s -isa=sh3e sh3e
sh3e.s -isa=sh3e-up sh3e
sh3e.s -isa=sh4-nofpu ERROR
sh3e.s -isa=sh4-nofpu-up sh4
sh3e.s -isa=sh4-nommu-nofpu ERROR
sh3e.s -isa=sh4-nommu-nofpu-up sh4
sh3e.s -isa=sh4 sh4
sh3e.s -isa=sh4-up sh4
sh3e.s -isa=sh4a-nofpu ERROR
sh3e.s -isa=sh4a-nofpu-up sh4a
sh3e.s -isa=sh4a sh4a
sh3e.s -isa=sh4a-up sh4a
sh3e.s -isa=sh4al-dsp ERROR
sh3e.s -isa=sh4al-dsp-up ERROR
sh4-nofpu.s default-options sh4-nofpu
sh4-nofpu.s -dsp sh4-nofpu
sh4-nofpu.s -isa=any sh4-nofpu
sh4-nofpu.s -isa=dsp sh4-nofpu
sh4-nofpu.s -isa=fp sh4-nofpu
sh4-nofpu.s -isa=sh-dsp ERROR
sh4-nofpu.s -isa=sh-dsp-up sh4al-dsp
sh4-nofpu.s -isa=sh ERROR
sh4-nofpu.s -isa=sh-up sh4-nofpu
sh4-nofpu.s -isa=sh2 ERROR
sh4-nofpu.s -isa=sh2-up sh4-nofpu
sh4-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh4-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4-nofpu
sh4-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh4-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nofpu
sh4-nofpu.s -isa=sh2a-nofpu ERROR
sh4-nofpu.s -isa=sh2a-nofpu-up ERROR
sh4-nofpu.s -isa=sh2a-or-sh3e ERROR
sh4-nofpu.s -isa=sh2a-or-sh3e-up sh4
sh4-nofpu.s -isa=sh2a-or-sh4 ERROR
sh4-nofpu.s -isa=sh2a-or-sh4-up sh4
sh4-nofpu.s -isa=sh2a ERROR
sh4-nofpu.s -isa=sh2a-up ERROR
sh4-nofpu.s -isa=sh2e ERROR
sh4-nofpu.s -isa=sh2e-up sh4
sh4-nofpu.s -isa=sh3-dsp ERROR
sh4-nofpu.s -isa=sh3-dsp-up sh4al-dsp
sh4-nofpu.s -isa=sh3-nommu ERROR
sh4-nofpu.s -isa=sh3-nommu-up sh4-nofpu
sh4-nofpu.s -isa=sh3 ERROR
sh4-nofpu.s -isa=sh3-up sh4-nofpu
sh4-nofpu.s -isa=sh3e ERROR
sh4-nofpu.s -isa=sh3e-up sh4
sh4-nofpu.s -isa=sh4-nofpu sh4-nofpu
sh4-nofpu.s -isa=sh4-nofpu-up sh4-nofpu
sh4-nofpu.s -isa=sh4-nommu-nofpu ERROR
sh4-nofpu.s -isa=sh4-nommu-nofpu-up sh4-nofpu
sh4-nofpu.s -isa=sh4 sh4
sh4-nofpu.s -isa=sh4-up sh4
sh4-nofpu.s -isa=sh4a-nofpu sh4a-nofpu
sh4-nofpu.s -isa=sh4a-nofpu-up sh4a-nofpu
sh4-nofpu.s -isa=sh4a sh4a
sh4-nofpu.s -isa=sh4a-up sh4a
sh4-nofpu.s -isa=sh4al-dsp sh4al-dsp
sh4-nofpu.s -isa=sh4al-dsp-up sh4al-dsp
sh4-nommu-nofpu.s default-options sh4-nommu-nofpu
sh4-nommu-nofpu.s -dsp sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=any sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=dsp sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=fp sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=sh-dsp ERROR
sh4-nommu-nofpu.s -isa=sh-dsp-up sh4al-dsp
sh4-nommu-nofpu.s -isa=sh ERROR
sh4-nommu-nofpu.s -isa=sh-up sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=sh2 ERROR
sh4-nommu-nofpu.s -isa=sh2-up sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=sh2a-nofpu ERROR
sh4-nommu-nofpu.s -isa=sh2a-nofpu-up ERROR
sh4-nommu-nofpu.s -isa=sh2a-or-sh3e ERROR
sh4-nommu-nofpu.s -isa=sh2a-or-sh3e-up sh4
sh4-nommu-nofpu.s -isa=sh2a-or-sh4 ERROR
sh4-nommu-nofpu.s -isa=sh2a-or-sh4-up sh4
sh4-nommu-nofpu.s -isa=sh2a ERROR
sh4-nommu-nofpu.s -isa=sh2a-up ERROR
sh4-nommu-nofpu.s -isa=sh2e ERROR
sh4-nommu-nofpu.s -isa=sh2e-up sh4
sh4-nommu-nofpu.s -isa=sh3-dsp ERROR
sh4-nommu-nofpu.s -isa=sh3-dsp-up sh4al-dsp
sh4-nommu-nofpu.s -isa=sh3-nommu ERROR
sh4-nommu-nofpu.s -isa=sh3-nommu-up sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=sh3 ERROR
sh4-nommu-nofpu.s -isa=sh3-up sh4-nofpu
sh4-nommu-nofpu.s -isa=sh3e ERROR
sh4-nommu-nofpu.s -isa=sh3e-up sh4
sh4-nommu-nofpu.s -isa=sh4-nofpu sh4-nofpu
sh4-nommu-nofpu.s -isa=sh4-nofpu-up sh4-nofpu
sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu-up sh4-nommu-nofpu
sh4-nommu-nofpu.s -isa=sh4 sh4
sh4-nommu-nofpu.s -isa=sh4-up sh4
sh4-nommu-nofpu.s -isa=sh4a-nofpu sh4a-nofpu
sh4-nommu-nofpu.s -isa=sh4a-nofpu-up sh4a-nofpu
sh4-nommu-nofpu.s -isa=sh4a sh4a
sh4-nommu-nofpu.s -isa=sh4a-up sh4a
sh4-nommu-nofpu.s -isa=sh4al-dsp sh4al-dsp
sh4-nommu-nofpu.s -isa=sh4al-dsp-up sh4al-dsp
sh4.s default-options sh4
sh4.s -dsp ERROR
sh4.s -isa=any sh4
sh4.s -isa=dsp ERROR
sh4.s -isa=fp sh4
sh4.s -isa=sh-dsp ERROR
sh4.s -isa=sh-dsp-up ERROR
sh4.s -isa=sh ERROR
sh4.s -isa=sh-up sh4
sh4.s -isa=sh2 ERROR
sh4.s -isa=sh2-up sh4
sh4.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh4.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4
sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh4.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4
sh4.s -isa=sh2a-nofpu ERROR
sh4.s -isa=sh2a-nofpu-up ERROR
sh4.s -isa=sh2a-or-sh3e ERROR
sh4.s -isa=sh2a-or-sh3e-up sh4
sh4.s -isa=sh2a-or-sh4 ERROR
sh4.s -isa=sh2a-or-sh4-up sh4
sh4.s -isa=sh2a ERROR
sh4.s -isa=sh2a-up ERROR
sh4.s -isa=sh2e ERROR
sh4.s -isa=sh2e-up sh4
sh4.s -isa=sh3-dsp ERROR
sh4.s -isa=sh3-dsp-up ERROR
sh4.s -isa=sh3-nommu ERROR
sh4.s -isa=sh3-nommu-up sh4
sh4.s -isa=sh3 ERROR
sh4.s -isa=sh3-up sh4
sh4.s -isa=sh3e ERROR
sh4.s -isa=sh3e-up sh4
sh4.s -isa=sh4-nofpu ERROR
sh4.s -isa=sh4-nofpu-up sh4
sh4.s -isa=sh4-nommu-nofpu ERROR
sh4.s -isa=sh4-nommu-nofpu-up sh4
sh4.s -isa=sh4 sh4
sh4.s -isa=sh4-up sh4
sh4.s -isa=sh4a-nofpu ERROR
sh4.s -isa=sh4a-nofpu-up sh4a
sh4.s -isa=sh4a sh4a
sh4.s -isa=sh4a-up sh4a
sh4.s -isa=sh4al-dsp ERROR
sh4.s -isa=sh4al-dsp-up ERROR
sh4a-nofpu.s default-options sh4a-nofpu
sh4a-nofpu.s -dsp sh4a-nofpu
sh4a-nofpu.s -isa=any sh4a-nofpu
sh4a-nofpu.s -isa=dsp sh4a-nofpu
sh4a-nofpu.s -isa=fp sh4a-nofpu
sh4a-nofpu.s -isa=sh-dsp ERROR
sh4a-nofpu.s -isa=sh-dsp-up sh4al-dsp
sh4a-nofpu.s -isa=sh ERROR
sh4a-nofpu.s -isa=sh-up sh4a-nofpu
sh4a-nofpu.s -isa=sh2 ERROR
sh4a-nofpu.s -isa=sh2-up sh4a-nofpu
sh4a-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh4a-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4a-nofpu
sh4a-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh4a-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4a-nofpu
sh4a-nofpu.s -isa=sh2a-nofpu ERROR
sh4a-nofpu.s -isa=sh2a-nofpu-up ERROR
sh4a-nofpu.s -isa=sh2a-or-sh3e ERROR
sh4a-nofpu.s -isa=sh2a-or-sh3e-up sh4a
sh4a-nofpu.s -isa=sh2a-or-sh4 ERROR
sh4a-nofpu.s -isa=sh2a-or-sh4-up sh4a
sh4a-nofpu.s -isa=sh2a ERROR
sh4a-nofpu.s -isa=sh2a-up ERROR
sh4a-nofpu.s -isa=sh2e ERROR
sh4a-nofpu.s -isa=sh2e-up sh4a
sh4a-nofpu.s -isa=sh3-dsp ERROR
sh4a-nofpu.s -isa=sh3-dsp-up sh4al-dsp
sh4a-nofpu.s -isa=sh3-nommu ERROR
sh4a-nofpu.s -isa=sh3-nommu-up sh4a-nofpu
sh4a-nofpu.s -isa=sh3 ERROR
sh4a-nofpu.s -isa=sh3-up sh4a-nofpu
sh4a-nofpu.s -isa=sh3e ERROR
sh4a-nofpu.s -isa=sh3e-up sh4a
sh4a-nofpu.s -isa=sh4-nofpu ERROR
sh4a-nofpu.s -isa=sh4-nofpu-up sh4a-nofpu
sh4a-nofpu.s -isa=sh4-nommu-nofpu ERROR
sh4a-nofpu.s -isa=sh4-nommu-nofpu-up sh4a-nofpu
sh4a-nofpu.s -isa=sh4 ERROR
sh4a-nofpu.s -isa=sh4-up sh4a
sh4a-nofpu.s -isa=sh4a-nofpu sh4a-nofpu
sh4a-nofpu.s -isa=sh4a-nofpu-up sh4a-nofpu
sh4a-nofpu.s -isa=sh4a sh4a
sh4a-nofpu.s -isa=sh4a-up sh4a
sh4a-nofpu.s -isa=sh4al-dsp sh4al-dsp
sh4a-nofpu.s -isa=sh4al-dsp-up sh4al-dsp
sh4a.s default-options sh4a
sh4a.s -dsp ERROR
sh4a.s -isa=any sh4a
sh4a.s -isa=dsp ERROR
sh4a.s -isa=fp sh4a
sh4a.s -isa=sh-dsp ERROR
sh4a.s -isa=sh-dsp-up ERROR
sh4a.s -isa=sh ERROR
sh4a.s -isa=sh-up sh4a
sh4a.s -isa=sh2 ERROR
sh4a.s -isa=sh2-up sh4a
sh4a.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh4a.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4a
sh4a.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh4a.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4a
sh4a.s -isa=sh2a-nofpu ERROR
sh4a.s -isa=sh2a-nofpu-up ERROR
sh4a.s -isa=sh2a-or-sh3e ERROR
sh4a.s -isa=sh2a-or-sh3e-up sh4a
sh4a.s -isa=sh2a-or-sh4 ERROR
sh4a.s -isa=sh2a-or-sh4-up sh4a
sh4a.s -isa=sh2a ERROR
sh4a.s -isa=sh2a-up ERROR
sh4a.s -isa=sh2e ERROR
sh4a.s -isa=sh2e-up sh4a
sh4a.s -isa=sh3-dsp ERROR
sh4a.s -isa=sh3-dsp-up ERROR
sh4a.s -isa=sh3-nommu ERROR
sh4a.s -isa=sh3-nommu-up sh4a
sh4a.s -isa=sh3 ERROR
sh4a.s -isa=sh3-up sh4a
sh4a.s -isa=sh3e ERROR
sh4a.s -isa=sh3e-up sh4a
sh4a.s -isa=sh4-nofpu ERROR
sh4a.s -isa=sh4-nofpu-up sh4a
sh4a.s -isa=sh4-nommu-nofpu ERROR
sh4a.s -isa=sh4-nommu-nofpu-up sh4a
sh4a.s -isa=sh4 ERROR
sh4a.s -isa=sh4-up sh4a
sh4a.s -isa=sh4a-nofpu ERROR
sh4a.s -isa=sh4a-nofpu-up sh4a
sh4a.s -isa=sh4a sh4a
sh4a.s -isa=sh4a-up sh4a
sh4a.s -isa=sh4al-dsp ERROR
sh4a.s -isa=sh4al-dsp-up ERROR
sh4al-dsp.s default-options ERROR
sh4al-dsp.s -dsp sh4al-dsp
sh4al-dsp.s -isa=any sh4al-dsp
sh4al-dsp.s -isa=dsp sh4al-dsp
sh4al-dsp.s -isa=fp ERROR
sh4al-dsp.s -isa=sh-dsp ERROR
sh4al-dsp.s -isa=sh-dsp-up sh4al-dsp
sh4al-dsp.s -isa=sh ERROR
sh4al-dsp.s -isa=sh-up sh4al-dsp
sh4al-dsp.s -isa=sh2 ERROR
sh4al-dsp.s -isa=sh2-up sh4al-dsp
sh4al-dsp.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
sh4al-dsp.s -isa=sh2a-nofpu-or-sh3-nommu-up sh4al-dsp
sh4al-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
sh4al-dsp.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp
sh4al-dsp.s -isa=sh2a-nofpu ERROR
sh4al-dsp.s -isa=sh2a-nofpu-up ERROR
sh4al-dsp.s -isa=sh2a-or-sh3e ERROR
sh4al-dsp.s -isa=sh2a-or-sh3e-up ERROR
sh4al-dsp.s -isa=sh2a-or-sh4 ERROR
sh4al-dsp.s -isa=sh2a-or-sh4-up ERROR
sh4al-dsp.s -isa=sh2a ERROR
sh4al-dsp.s -isa=sh2a-up ERROR
sh4al-dsp.s -isa=sh2e ERROR
sh4al-dsp.s -isa=sh2e-up ERROR
sh4al-dsp.s -isa=sh3-dsp ERROR
sh4al-dsp.s -isa=sh3-dsp-up sh4al-dsp
sh4al-dsp.s -isa=sh3-nommu ERROR
sh4al-dsp.s -isa=sh3-nommu-up sh4al-dsp
sh4al-dsp.s -isa=sh3 ERROR
sh4al-dsp.s -isa=sh3-up sh4al-dsp
sh4al-dsp.s -isa=sh3e ERROR
sh4al-dsp.s -isa=sh3e-up ERROR
sh4al-dsp.s -isa=sh4-nofpu ERROR
sh4al-dsp.s -isa=sh4-nofpu-up sh4al-dsp
sh4al-dsp.s -isa=sh4-nommu-nofpu ERROR
sh4al-dsp.s -isa=sh4-nommu-nofpu-up sh4al-dsp
sh4al-dsp.s -isa=sh4 ERROR
sh4al-dsp.s -isa=sh4-up ERROR
sh4al-dsp.s -isa=sh4a-nofpu ERROR
sh4al-dsp.s -isa=sh4a-nofpu-up sh4al-dsp
sh4al-dsp.s -isa=sh4a ERROR
sh4al-dsp.s -isa=sh4a-up ERROR
sh4al-dsp.s -isa=sh4al-dsp sh4al-dsp
sh4al-dsp.s -isa=sh4al-dsp-up sh4al-dsp
/trunk/gnu/binutils/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
0,0 → 1,193
! Generated file. DO NOT EDIT.
!
! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
! This file should contain every instruction valid on
! architecture sh4-nommu-nofpu but no more.
! If the tests are failing because the expected results
! have changed then run 'make check' and copy the new file
! from <objdir>/gas/testsuite/sh4-nommu-nofpu.s
! to <srcdir>/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s .
! Make sure there are no unexpected or missing instructions.
 
.section .text
sh4_nommu_nofpu:
! Instructions introduced into sh4-nommu-nofpu
ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
 
! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
.align 2
mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
.align 2
mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh2a.d
0,0 → 1,68
#objdump: -dr --prefix-addresses --show-raw-insn
#name: SH2a new instructions
#as: -isa=sh2a
 
dump.o: file format elf32-sh.*
 
Disassembly of section .text:
0x00000000 33 79 4f ff band.b #7,@\(4095,r3\)
0x00000004 33 79 cf ff bandnot.b #7,@\(4095,r3\)
0x00000008 33 79 0f ff bclr.b #7,@\(4095,r3\)
0x0000000c 86 37 bclr #7,r3
0x0000000e 33 79 3f ff bld.b #7,@\(4095,r3\)
0x00000012 87 3f bld #7,r3
0x00000014 33 79 bf ff bldnot.b #7,@\(4095,r3\)
0x00000018 33 79 5f ff bor.b #7,@\(4095,r3\)
0x0000001c 33 79 df ff bornot.b #7,@\(4095,r3\)
0x00000020 33 79 1f ff bset.b #7,@\(4095,r3\)
0x00000024 86 3f bset #7,r3
0x00000026 33 79 2f ff bst.b #7,@\(4095,r3\)
0x0000002a 87 37 bst #7,r3
0x0000002c 33 79 6f ff bxor.b #7,@\(4095,r3\)
0x00000030 43 91 clips.b r3
0x00000032 43 95 clips.w r3
0x00000034 43 81 clipu.b r3
0x00000036 43 85 clipu.w r3
0x00000038 43 94 divs r0,r3
0x0000003a 43 84 divu r0,r3
0x0000003c 33 31 3f ff fmov.s fr3,@\(16380,r3\)
0x00000040 33 21 3f ff fmov.d dr2,@\(32760,r3\)
0x00000044 33 31 7f ff fmov.s @\(16380,r3\),fr3
0x00000048 32 31 7f ff fmov.d @\(32760,r3\),dr2
0x0000004c 43 4b jsr/n @r3
0x0000004e 83 ff jsr/n @@\(1020,tbr\)
0x00000050 43 e5 ldbank @r3,r0
0x00000052 43 4a ldc r3,tbr
0x00000054 34 31 0f ff mov.b r3,@\(4095,r4\)
0x00000058 34 31 1f ff mov.w r3,@\(8190,r4\)
0x0000005c 34 31 2f ff mov.l r3,@\(16380,r4\)
0x00000060 35 41 4f ff mov.b @\(4095,r4\),r5
0x00000064 35 41 5f ff mov.w @\(8190,r4\),r5
0x00000068 35 41 6f ff mov.l @\(16380,r4\),r5
0x0000006c 43 8b mov.b r0,@r3\+
0x0000006e 43 9b mov.w r0,@r3\+
0x00000070 43 ab mov.l r0,@r3\+
0x00000072 43 cb mov.b @-r3,r0
0x00000074 43 db mov.w @-r3,r0
0x00000076 43 eb mov.l @-r3,r0
0x00000078 03 70 ff ff movi20 #524287,r3
0x0000007c 03 80 00 00 movi20 #-524288,r3
0x00000080 03 71 ff ff movi20s #134217472,r3
0x00000084 03 81 00 00 movi20s #-134217728,r3
0x00000088 43 f1 movml.l r3,@-r15
0x0000008a 43 f5 movml.l @r15\+,r3
0x0000008c 43 f0 movmu.l r3,@-r15
0x0000008e 43 f4 movmu.l @r15\+,r3
0x00000090 03 39 movrt r3
0x00000092 34 31 8f ff movu.b @\(4095,r3\),r4
0x00000096 34 31 9f ff movu.w @\(8190,r3\),r4
0x0000009a 44 80 mulr r0,r4
0x0000009c 00 68 nott
0x0000009e 05 83 pref @r5
0x000000a0 00 5b resbank
0x000000a2 00 6b rts/n
0x000000a4 03 7b rtv/n r3
0x000000a6 44 3c shad r3,r4
0x000000a8 44 3d shld r3,r4
0x000000aa 45 e1 stbank r0,@r5
0x000000ac 04 4a stc tbr,r4
/trunk/gnu/binutils/gas/testsuite/gas/sh/renesas-1.d
0,0 → 1,11
#objdump: -dr
#as: -renesas
 
.*: +file format .*
 
Disassembly of section .text:
 
00000000 <foo-0x4>:
0: 00 00 [ ]*\.word 0x0000
[ ]+0: R_SH_DIR32 foo
\.\.\.
/trunk/gnu/binutils/gas/testsuite/gas/sh/tlspic.d
0,0 → 1,33
#objdump: -dr
#as: -big
#name: sh pic tls
 
.*: +file format .*
 
Disassembly of section .text:
 
0+000 <fn>:
0: 2f c6 [ ]*mov\.l r12,@-r15
2: 2f e6 [ ]*mov\.l r14,@-r15
4: 6e f3 [ ]*mov r15,r14
6: c7 08 [ ]*mova 28 <fn\+0x28>,r0
8: dc 07 [ ]*mov\.l 28 <fn\+0x28>,r12[ ]+! 0 .*
a: 3c 0c [ ]*add r0,r12
c: d0 02 [ ]*mov\.l 18 <fn\+0x18>,r0[ ]+! 0 .*
e: 01 12 [ ]*stc gbr,r1
10: 00 ce [ ]*mov\.l @\(r0,r12\),r0
12: a0 03 [ ]*bra 1c <fn\+0x1c>
14: 31 0c [ ]*add r0,r1
16: 00 09 [ ]*nop
18: 00 00 [ ]*\.word 0x0000
[ ]+18: R_SH_TLS_IE_32 foo
1a: 00 00 [ ]*\.word 0x0000
1c: 60 13 [ ]*mov r1,r0
1e: 6f e3 [ ]*mov r14,r15
20: 6e f6 [ ]*mov\.l @r15\+,r14
22: 00 0b [ ]*rts
24: 6c f6 [ ]*mov\.l @r15\+,r12
26: 00 09 [ ]*nop
28: 00 00 [ ]*\.word 0x0+0
[ ]+28: R_SH_GOTPC _GLOBAL_OFFSET_TABLE_
\.\.\.
/trunk/gnu/binutils/gas/testsuite/gas/sh/pcrel-coff.s
0,0 → 1,14
.text
 
.p2align 2
code:
mov.l litpool, r1
mov.l @(14,pc), r1
mova @(litpool-.,pc), r0
mov.l @r0,r1
mov.l @(litpool-.,pc), r1
bsrf r1
nop
nop
litpool:
.long code - .
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh4a.d
0,0 → 1,27
#objdump: -fdr --prefix-addresses --show-raw-insn
#name: SH4a non-FP constructs
 
.*: file format elf.*sh.*
architecture: sh4a-nofpu, flags 0x00000010:
HAS_SYMS
start address 0x00000000
 
Disassembly of section \.text:
0x00000000 01 63 movli\.l @r1,r0
0x00000002 00 73 movco\.l r0,@r0
0x00000004 06 63 movli\.l @r6,r0
0x00000006 03 73 movco\.l r0,@r3
0x00000008 0a 63 movli\.l @r10,r0
0x0000000a 0c 73 movco\.l r0,@r12
0x0000000c 40 a9 movua\.l @r0,r0
0x0000000e 4d a9 movua\.l @r13,r0
0x00000010 47 a9 movua\.l @r7,r0
0x00000012 45 e9 movua\.l @r5\+,r0
0x00000014 42 e9 movua\.l @r2\+,r0
0x00000016 4b e9 movua\.l @r11\+,r0
0x00000018 04 e3 icbi @r4
0x0000001a 0f e3 icbi @r15
0x0000001c 02 e3 icbi @r2
0x0000001e 05 d3 prefi @r5
0x00000020 0a d3 prefi @r10
0x00000022 00 ab synco
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh4a-fp.d
0,0 → 1,15
#objdump: -fdr --prefix-addresses --show-raw-insn
#name: SH4a FP constructs
 
.*: file format elf.*sh.*
architecture: sh4a, flags 0x00000010:
HAS_SYMS
start address 0x00000000
 
Disassembly of section \.text:
0x00000000 f7 fd fpchg
0x00000002 f1 7d fsrra fr1
0x00000004 f9 7d fsrra fr9
0x00000006 f6 7d fsrra fr6
0x00000008 f2 fd fsca fpul,dr2
0x0000000a fc fd fsca fpul,dr12
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh4a-dsp.s
0,0 → 1,42
.text
.p2align 2
 
movli.l @r1,r0
movco.l r0,@r0
 
movli.l @r6,r0
movco.l r0,@r3
 
movli.l @r10,r0
movco.l r0,@r12
 
movua.l @r0,r0
movua.l @r13,r0
movua.l @r7,r0
 
movua.l @r5+,r0
movua.l @r2+,r0
movua.l @r11+,r0
 
icbi @r4
icbi @r15
icbi @r2
 
prefi @r5
prefi @r10
 
synco
 
# Instructions present in SH4 but not in SH3-DSP
ldc r5,dbr
ldc.l @r10+,dbr
stc sgr,r11
stc.l sgr,@-r9
stc dbr,r2
stc.l dbr,@-r6
movca.l r0,@r3
ocbi @r12
ocbp @r7
ocbwb @r13
pref @r14
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/datal64-1.d
0,0 → 1,50
#as: --abi=64
#objdump: -sr
#source: datal-1.s
#name: DataLabel redundant local use, SHmedia 64-bit ABI
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET TYPE VALUE
0+20 R_SH_IMM_MEDLOW16 \.data\+0x0+3a
0+24 R_SH_IMM_LOW16 myrodata3
0+28 R_SH_IMM_LOW16 \.rodata\+0x0+10
0+2c R_SH_IMM_LOW16 \.rodata\+0x0+3a
0+00 R_SH_IMM_HI16 \.data\+0x0+4
0+04 R_SH_IMM_MEDHI16 \.data\+0x0+4
0+08 R_SH_IMM_MEDLOW16 \.data\+0x0+4
0+0c R_SH_IMM_LOW16 \.data\+0x0+4
0+10 R_SH_IMM_HI16 \.data\+0x0+32
0+14 R_SH_IMM_MEDHI16 \.data\+0x0+32
0+18 R_SH_IMM_MEDLOW16 \.data\+0x0+32
0+1c R_SH_IMM_LOW16 \.data\+0x0+32
 
RELOCATION RECORDS FOR \[\.data\]:
OFFSET TYPE VALUE
0+00 R_SH_DIR32 \.rodata
0+04 R_SH_DIR32 \.rodata
0+08 R_SH_DIR32 \.data
0+0c R_SH_DIR32 \.data
0+10 R_SH_DIR32 \.data
0+14 R_SH_DIR32 myrodata3
0+18 R_SH_DIR32 foo6
 
RELOCATION RECORDS FOR \[\.rodata\]:
OFFSET TYPE VALUE
0+00 R_SH_DIR32 \.data
0+04 R_SH_DIR32 \.data
0+08 R_SH_DIR32 \.rodata
0+0c R_SH_DIR32 \.rodata
0+10 R_SH_DIR32 \.rodata
 
Contents of section \.text:
0000 cc000030 c8000030 c8000030 c8000030 .*
0010 cc000030 c8000030 c8000030 c8000030 .*
0020 cc000030 cc0002d0 cc0002d0 cc0002d0 .*
Contents of section \.data:
0000 00000004 00000026 00000004 0000000c .*
0010 00000038 00000000 0000002a .*
Contents of section \.rodata:
0000 00000010 0000004c 00000008 00000020 .*
0010 00000104 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/endian-2.d
0,0 → 1,10
#as: --isa=shmedia --abi=64 --no-exp -big
#objdump: -s
#name: SH64 Big Endian
 
.*: file format elf64-sh64.*
 
Contents of section .text:
0000 cc48d000 12345678 12340000.*
 
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptc64-1.d
0,0 → 1,19
#as: --abi=64
#objdump: -dr
#source: ptc-1.s
#name: PT constant, 64-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <start>:
[ ]+0:[ ]+cc000190[ ]+movi 0,r25
[ ]+0:[ ]+R_SH_IMM_HI16_PCREL \*ABS\*\+0xf0
[ ]+4:[ ]+c8000190[ ]+shori 0,r25
[ ]+4:[ ]+R_SH_IMM_MEDHI16_PCREL \*ABS\*\+0xf4
[ ]+8:[ ]+c8000190[ ]+shori 0,r25
[ ]+8:[ ]+R_SH_IMM_MEDLOW16_PCREL \*ABS\*\+0xf8
[ ]+c:[ ]+c8000190[ ]+shori 0,r25
[ ]+c:[ ]+R_SH_IMM_LOW16_PCREL \*ABS\*\+0xfc
[ ]+10:[ ]+6bf56610[ ]+ptrel/l r25,tr1
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel-2.s
0,0 → 1,138
! Like rel-1.s, but using "$", not "datalabel $" as self expression. It's
! not as useful, but should emit the obvious output.
 
.mode SHmedia
.text
start:
movi data1 - $,r10
movi (data2 - $) & 65535,r10
movi ((data3 - $) >> 0) & 65535,r10
movi ((data4 - $) >> 16) & 65535,r10
movi data5 + 8 - $,r10
movi (data6 + 16 - $) & 65535,r10
movi ((data7 + 12 - $) >> 0) & 65535,r10
movi ((data8 + 4 - $) >> 16) & 65535,r10
 
movi othertext1 - $,r10
movi (othertext2 - $) & 65535,r10
movi ((othertext3 - $) >> 0) & 65535,r10
movi ((othertext4 - $) >> 16) & 65535,r10
movi othertext5 + 8 - $,r10
movi (othertext6 + 16 - $) & 65535,r10
movi ((othertext7 + 12 - $) >> 0) & 65535,r10
movi ((othertext8 + 4 - $) >> 16) & 65535,r10
 
movi extern1 - $,r10
movi (extern2 - $) & 65535,r10
movi ((extern3 - $) >> 0) & 65535,r10
movi ((extern4 - $) >> 16) & 65535,r10
movi extern5 + 8 - $,r10
movi (extern6 + 16 - $) & 65535,r10
movi ((extern7 + 12 - $) >> 0) & 65535,r10
movi ((extern8 + 4 - $) >> 16) & 65535,r10
 
movi gdata1 - $,r10
movi (gdata2 - $) & 65535,r10
movi ((gdata3 - $) >> 0) & 65535,r10
movi ((gdata4 - $) >> 16) & 65535,r10
movi gdata5 + 8 - $,r10
movi (gdata6 + 16 - $) & 65535,r10
movi ((gdata7 + 12 - $) >> 0) & 65535,r10
movi ((gdata8 + 4 - $) >> 16) & 65535,r10
 
movi gothertext1 - $,r10
movi (gothertext2 - $) & 65535,r10
movi ((gothertext3 - $) >> 0) & 65535,r10
movi ((gothertext4 - $) >> 16) & 65535,r10
movi gothertext5 + 8 - $,r10
movi (gothertext6 + 16 - $) & 65535,r10
movi ((gothertext7 + 12 - $) >> 0) & 65535,r10
movi ((gothertext8 + 4 - $) >> 16) & 65535,r10
 
.section .othertext,"ax"
x:
nop
othertext1:
nop
othertext2:
nop
othertext3:
nop
othertext4:
nop
othertext5:
nop
othertext6:
nop
othertext7:
nop
othertext8:
nop
.global gothertext1
gothertext1:
nop
.global gothertext2
gothertext2:
nop
.global gothertext3
gothertext3:
nop
.global gothertext4
gothertext4:
nop
.global gothertext5
gothertext5:
nop
.global gothertext6
gothertext6:
nop
.global gothertext7
gothertext7:
nop
.global gothertext8
gothertext8:
nop
 
.data
y:
.long 0
data1:
.long 0
data2:
.long 0
data3:
.long 0
data4:
.long 0
data5:
.long 0
data6:
.long 0
data7:
.long 0
data8:
.long 0
.global gdata1
gdata1:
.long 0
.global gdata2
gdata2:
.long 0
.global gdata3
gdata3:
.long 0
.global gdata4
gdata4:
.long 0
.global gdata5
gdata5:
.long 0
.global gdata6
gdata6:
.long 0
.global gdata7
gdata7:
.long 0
.global gdata8
gdata8:
.long 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/case-noexp-1.d
0,0 → 1,18
#as: --abi=32 -no-expand
#objdump: -dr
#source: case-1.s
#name: Case-insensitive registers and opcodes with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
[ ]+4:[ ]+6ff0fff0[ ]+nop
[ ]+8:[ ]+e8000040[ ]+pta/u 8 <start\+0x8>,tr4
[ ]+8:[ ]+R_SH_PT_16 foo
[ ]+c:[ ]+e8000630[ ]+pta/l 10 <start\+0x10>,tr3
[ ]+c:[ ]+R_SH_PT_16 bar
[ ]+10:[ ]+cc00a820[ ]+movi 42,r2
[ ]+14:[ ]+ebffee20[ ]+pta/l 0 <start>,tr2
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt-2.s
0,0 → 1,22
! Check inter-segment pt and pta
.text
start:
nop
start1:
nop
start4:
pt start1,tr5
nop
 
pt start2,tr7
nop
 
.section .text.other,"ax"
dummylabel: ! Needed to hang a marker that this is SHmedia.
nop
start2:
pta start3,tr4
nop
start3:
pta start4,tr3
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/syntax-2.s
0,0 → 1,10
.text
start:
 
! pseudo-ops
 
pt .L4,tr0
pt .L5,tr0
.L4:
.mode shcompact
.L5:
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ua32-1.d
0,0 → 1,23
#as: --abi=32
#objdump: -sr
#source: ua-1.s
#name: Unaligned pseudos, 32-bit ABI.
 
# Note that the relocs for externsym0 + 3 and externsym2 + 42 are
# partial-in-place, i.e. REL-like, and are not displayed correctly.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.rodata\]:
OFFSET *TYPE *VALUE
0+0f R_SH_DIR32 externsym0
0+1b R_SH_64 externsym1\+0x0+29
0+2c R_SH_DIR32 externsym2
0+30 R_SH_64 externsym3\+0x0+2b
 
 
Contents of section \.rodata:
0000 01234567 89abcdef 2a4a2143 b1abcd00 .*
0010 00000301 2c456d89 ab1d0f00 00000000 .*
0020 00000002 01a34b67 c9ab0d4f 0000002a .*
0030 00000000 00000000 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/endian-2.s
0,0 → 1,7
.text
.mode shmedia
start:
 
movi 0x1234,r0
.long 0x12345678
.word 0x1234, 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/basic-1.d
0,0 → 1,234
#as: --isa=shmedia
#objdump: -dr
#name: Basic SHmedia instructions.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
[0]+ <start>:
[ ]+0:[ ]+003966b0[ ]+add r3,r25,r43
[ ]+4:[ ]+00d80be0[ ]+add\.l r13,r2,r62
[ ]+8:[ ]+d2c7d210[ ]+addi r44,500,r33
[ ]+c:[ ]+d55832b0[ ]+addi\.l r21,-500,r43
[ ]+10:[ ]+033ca9e0[ ]+addz\.l r51,r42,r30
[ ]+14:[ ]+e1347bf0[ ]+alloco r19,960
[ ]+18:[ ]+048be4c0[ ]+and r8,r57,r12
[ ]+1c:[ ]+070f8d20[ ]+andc r48,r35,r18
[ ]+20:[ ]+d987f660[ ]+andi r24,509,r38
[ ]+24:[ ]+65719620[ ]+beq/l r23,r37,tr2
[ ]+28:[ ]+65716e40[ ]+beq/l r23,r27,tr4
[ ]+2c:[ ]+6431bc60[ ]+beq/u r3,r47,tr6
[ ]+30:[ ]+e4417a50[ ]+beqi/l r4,30,tr5
[ ]+34:[ ]+e4418600[ ]+beqi/l r4,-31,tr0
[ ]+38:[ ]+e761a420[ ]+beqi/u r54,-23,tr2
[ ]+3c:[ ]+6403fe70[ ]+bge/l r0,r63,tr7
[ ]+40:[ ]+64a31a40[ ]+bge/l r10,r6,tr4
[ ]+44:[ ]+64b39010[ ]+bge/u r11,r36,tr1
[ ]+48:[ ]+65ebae30[ ]+bgeu/l r30,r43,tr3
[ ]+4c:[ ]+64ab6a50[ ]+bgeu/l r10,r26,tr5
[ ]+50:[ ]+673b9020[ ]+bgeu/u r51,r36,tr2
[ ]+54:[ ]+6617b270[ ]+bgt/l r33,r44,tr7
[ ]+58:[ ]+6517fa40[ ]+bgt/l r17,r62,tr4
[ ]+5c:[ ]+64f71810[ ]+bgt/u r15,r6,tr1
[ ]+60:[ ]+662f6e60[ ]+bgtu/l r34,r27,tr6
[ ]+64:[ ]+65cffa00[ ]+bgtu/l r28,r62,tr0
[ ]+68:[ ]+652f6450[ ]+bgtu/u r18,r25,tr5
[ ]+6c:[ ]+4411fe60[ ]+blink tr1,r38
[ ]+70:[ ]+67e5be00[ ]+bne/l r62,r47,tr0
[ ]+74:[ ]+65d55a10[ ]+bne/l r29,r22,tr1
[ ]+78:[ ]+6675bc60[ ]+bne/u r39,r47,tr6
[ ]+7c:[ ]+e4e5ce70[ ]+bnei/l r14,-13,tr7
[ ]+80:[ ]+e5857e30[ ]+bnei/l r24,31,tr3
[ ]+84:[ ]+e765a820[ ]+bnei/u r54,-22,tr2
[ ]+88:[ ]+6ff5fff0[ ]+brk
[ ]+8c:[ ]+015ffcc0[ ]+byterev r21,r12
[ ]+90:[ ]+00a12d50[ ]+cmpeq r10,r11,r21
[ ]+94:[ ]+01e37f30[ ]+cmpgt r30,r31,r51
[ ]+98:[ ]+017786d0[ ]+cmpgtu r23,r33,r45
[ ]+9c:[ ]+22010ec0[ ]+cmveq r32,r3,r44
[ ]+a0:[ ]+20d5f040[ ]+cmvne r13,r60,r4
[ ]+a4:[ ]+19615be0[ ]+fabs\.d dr22,dr62
[ ]+a8:[ ]+1bb0ed90[ ]+fabs\.s fr59,fr25
[ ]+ac:[ ]+3681f140[ ]+fadd\.d dr40,dr60,dr20
[ ]+b0:[ ]+3690ed30[ ]+fadd\.s fr41,fr59,fr19
[ ]+b4:[ ]+3049cb90[ ]+fcmpeq\.d dr4,dr50,r57
[ ]+b8:[ ]+32f87910[ ]+fcmpeq\.s fr47,fr30,r17
[ ]+bc:[ ]+32cfd140[ ]+fcmpge\.d dr44,dr52,r20
[ ]+c0:[ ]+325e5e00[ ]+fcmpge\.s fr37,fr23,r32
[ ]+c4:[ ]+314d7330[ ]+fcmpgt\.d dr20,dr28,r51
[ ]+c8:[ ]+32fc5560[ ]+fcmpgt\.s fr47,fr21,r22
[ ]+cc:[ ]+320beaf0[ ]+fcmpun\.d dr32,dr58,r47
[ ]+d0:[ ]+315aa8c0[ ]+fcmpun\.s fr21,fr42,r12
[ ]+d4:[ ]+3a87a150[ ]+fcnv\.ds dr40,fr21
[ ]+d8:[ ]+3ab6ae00[ ]+fcnv\.sd fr43,dr32
[ ]+dc:[ ]+3625e140[ ]+fdiv\.d dr34,dr56,dr20
[ ]+e0:[ ]+34d46930[ ]+fdiv\.s fr13,fr26,fr19
[ ]+e4:[ ]+1ff2fe70[ ]+fgetscr fr39
[ ]+e8:[ ]+14062270[ ]+fipr\.s fv0,fv8,fr39
[ ]+ec:[ ]+9df3eb00[ ]+fld\.d r31,2000,dr48
[ ]+f0:[ ]+9b5a2660[ ]+fld\.p r53,-3000,fp38
[ ]+f4:[ ]+9757f750[ ]+fld\.s r53,2036,fr53
[ ]+f8:[ ]+1d79a820[ ]+fldx\.d r23,r42,dr2
[ ]+fc:[ ]+1c2d5a00[ ]+fldx\.p r2,r22,fp32
[ ]+100:[ ]+1db8e8c0[ ]+fldx\.s r27,r58,fr12
[ ]+104:[ ]+385e15c0[ ]+float\.ld fr5,dr28
[ ]+108:[ ]+3b7cde40[ ]+float\.ls fr55,fr36
[ ]+10c:[ ]+3acdb100[ ]+float\.qd dr44,dr16
[ ]+110:[ ]+39ef78b0[ ]+float\.qs dr30,fr11
[ ]+114:[ ]+368e9440[ ]+fmac\.s fr40,fr37,fr4
[ ]+118:[ ]+38812280[ ]+fmov\.d dr8,dr40
[ ]+11c:[ ]+33a1ea20[ ]+fmov\.dq dr58,r34
[ ]+120:[ ]+1d90ff40[ ]+fmov\.ls r25,fr52
[ ]+124:[ ]+1ed1ff20[ ]+fmov\.qd r45,dr50
[ ]+128:[ ]+38401370[ ]+fmov\.s fr4,fr55
[ ]+12c:[ ]+30e038f0[ ]+fmov\.sl fr14,r15
[ ]+130:[ ]+3587eaa0[ ]+fmul\.d dr24,dr58,dr42
[ ]+134:[ ]+35b68220[ ]+fmul\.s fr27,fr32,fr34
[ ]+138:[ ]+18230800[ ]+fneg\.d dr2,dr0
[ ]+13c:[ ]+18020210[ ]+fneg\.s fr0,fr33
[ ]+140:[ ]+32c2b3f0[ ]+fputscr fr44
[ ]+144:[ ]+39e57ac0[ ]+fsqrt\.d dr30,dr44
[ ]+148:[ ]+38340d70[ ]+fsqrt\.s fr3,fr23
[ ]+14c:[ ]+bc37d020[ ]+fst\.d r3,4000,dr2
[ ]+150:[ ]+bb682cc0[ ]+fst\.p r54,-4008,fp12
[ ]+154:[ ]+b5282570[ ]+fst\.s r18,-2012,fr23
[ ]+158:[ ]+3d29b8c0[ ]+fstx\.d r18,r46,dr12
[ ]+15c:[ ]+3e6d6b40[ ]+fstx\.p r38,r26,fp52
[ ]+160:[ ]+3c785da0[ ]+fstx\.s r7,r23,fr26
[ ]+164:[ ]+3403b200[ ]+fsub\.d dr0,dr44,dr32
[ ]+168:[ ]+3432f830[ ]+fsub\.s fr3,fr62,fr3
[ ]+16c:[ ]+3a6b9b50[ ]+ftrc\.dl dr38,fr53
[ ]+170:[ ]+3ba8eb10[ ]+ftrc\.sl fr58,fr49
[ ]+174:[ ]+38e939a0[ ]+ftrc\.dq dr14,dr26
[ ]+178:[ ]+3bcaf160[ ]+ftrc\.sq fr60,dr22
[ ]+17c:[ ]+150e81c0[ ]+ftrv\.s mtrx16,fv32,fv28
[ ]+180:[ ]+c05fd7e0[ ]+getcfg r5,-11,r62
[ ]+184:[ ]+274ffd00[ ]+getcon cr52,r16
[ ]+188:[ ]+4465fda0[ ]+gettr tr6,r26
[ ]+18c:[ ]+e3058bf0[ ]+icbi r48,-960
[ ]+190:[ ]+83200fe0[ ]+ld\.b r50,3,r62
[ ]+194:[ ]+885da560[ ]+ld\.l r5,-604,r22
[ ]+198:[ ]+8e3cdea0[ ]+ld\.q r35,-1608,r42
[ ]+19c:[ ]+935cdc20[ ]+ld\.ub r53,-201,r2
[ ]+1a0:[ ]+b17cdea0[ ]+ld\.uw r23,-402,r42
[ ]+1a4:[ ]+86e25cb0[ ]+ld\.w r46,302,r11
[ ]+1a8:[ ]+c0668a90[ ]+ldhi\.l r6,-30,r41
[ ]+1ac:[ ]+c2477df0[ ]+ldhi\.q r36,31,r31
[ ]+1b0:[ ]+c1325300[ ]+ldlo\.l r19,20,r48
[ ]+1b4:[ ]+c09381d0[ ]+ldlo\.q r9,-32,r29
[ ]+1b8:[ ]+40500ef0[ ]+ldx\.b r5,r3,r47
[ ]+1bc:[ ]+4192ace0[ ]+ldx\.l r25,r43,r14
[ ]+1c0:[ ]+40c3f290[ ]+ldx\.q r12,r60,r41
[ ]+1c4:[ ]+40d40010[ ]+ldx\.ub r13,r0,r1
[ ]+1c8:[ ]+40d50910[ ]+ldx\.uw r13,r2,r17
[ ]+1cc:[ ]+40a15bc0[ ]+ldx\.w r10,r22,r60
[ ]+1d0:[ ]+287afe10[ ]+mabs\.l r7,r33
[ ]+1d4:[ ]+2a59fe20[ ]+mabs\.w r37,r34
[ ]+1d8:[ ]+0a228070[ ]+madd\.l r34,r32,r7
[ ]+1dc:[ ]+0971d510[ ]+madd\.w r23,r53,r17
[ ]+1e0:[ ]+09865c90[ ]+madds\.l r24,r23,r9
[ ]+1e4:[ ]+0a245f10[ ]+madds\.ub r34,r23,r49
[ ]+1e8:[ ]+08450bb0[ ]+madds\.w r4,r2,r59
[ ]+1ec:[ ]+2960e1f0[ ]+mcmpeq\.b r22,r56,r31
[ ]+1f0:[ ]+2952b7d0[ ]+mcmpeq\.l r21,r45,r61
[ ]+1f4:[ ]+2a01d810[ ]+mcmpeq\.w r32,r54,r1
[ ]+1f8:[ ]+28361130[ ]+mcmpgt\.l r3,r4,r19
[ ]+1fc:[ ]+2a24d8d0[ ]+mcmpgt\.ub r34,r54,r13
[ ]+200:[ ]+29751430[ ]+mcmpgt\.w r23,r5,r3
[ ]+204:[ ]+4be3c9e0[ ]+mcmv r62,r50,r30
[ ]+208:[ ]+4c2d1400[ ]+mcnvs\.lw r2,r5,r0
[ ]+20c:[ ]+4d581ca0[ ]+mcnvs\.wb r21,r7,r10
[ ]+210:[ ]+4d7cbcd0[ ]+mcnvs\.wub r23,r47,r13
[ ]+214:[ ]+2847a470[ ]+mextr1 r4,r41,r7
[ ]+218:[ ]+2a0b12f0[ ]+mextr2 r32,r4,r47
[ ]+21c:[ ]+299fb9b0[ ]+mextr3 r25,r46,r27
[ ]+220:[ ]+2f431820[ ]+mextr4 r52,r6,r2
[ ]+224:[ ]+2d574150[ ]+mextr5 r21,r16,r21
[ ]+228:[ ]+2d8bfaa0[ ]+mextr6 r24,r62,r42
[ ]+22c:[ ]+2f9fb970[ ]+mextr7 r57,r46,r23
[ ]+230:[ ]+48511020[ ]+mmacfx\.wl r5,r4,r2
[ ]+234:[ ]+48b5b160[ ]+mmacnfx\.wl r11,r44,r22
[ ]+238:[ ]+4d6286c0[ ]+mmul\.l r22,r33,r44
[ ]+23c:[ ]+4cc18ef0[ ]+mmul\.w r12,r35,r47
[ ]+240:[ ]+4fd69700[ ]+mmulfx\.l r61,r37,r48
[ ]+244:[ ]+4c151c50[ ]+mmulfx\.w r1,r7,r5
[ ]+248:[ ]+4ca99720[ ]+mmulfxrp\.w r10,r37,r50
[ ]+24c:[ ]+4c0e1f70[ ]+mmulhi\.wl r0,r7,r55
[ ]+250:[ ]+4caa6e30[ ]+mmullo\.wl r10,r27,r35
[ ]+254:[ ]+4a998250[ ]+mmulsum\.wq r41,r32,r37
[ ]+258:[ ]+cffe16b0[ ]+movi -123,r43
[ ]+25c:[ ]+2b9d8040[ ]+mperm\.w r57,r32,r4
[ ]+260:[ ]+48505d40[ ]+msad\.ubq r5,r23,r20
[ ]+264:[ ]+0e363140[ ]+mshalds\.l r35,r12,r20
[ ]+268:[ ]+0eb5d1e0[ ]+mshalds\.w r43,r52,r30
[ ]+26c:[ ]+0c4a5e80[ ]+mshard\.l r4,r23,r40
[ ]+270:[ ]+0d89f8a0[ ]+mshard\.w r24,r62,r10
[ ]+274:[ ]+0c2b4320[ ]+mshards\.q r2,r16,r50
[ ]+278:[ ]+2ea41bc0[ ]+mshfhi\.b r42,r6,r60
[ ]+27c:[ ]+2f464bb0[ ]+mshfhi\.l r52,r18,r59
[ ]+280:[ ]+2c857ee0[ ]+mshfhi\.w r8,r31,r46
[ ]+284:[ ]+2dc09e90[ ]+mshflo\.b r28,r39,r41
[ ]+288:[ ]+2dd29ab0[ ]+mshflo\.l r29,r38,r43
[ ]+28c:[ ]+2de196c0[ ]+mshflo\.w r30,r37,r44
[ ]+290:[ ]+0df292e0[ ]+mshlld\.l r31,r36,r46
[ ]+294:[ ]+0e018ef0[ ]+mshlld\.w r32,r35,r47
[ ]+298:[ ]+0e1e8b10[ ]+mshlrd\.l r33,r34,r49
[ ]+29c:[ ]+0e2d8720[ ]+mshlrd\.w r34,r33,r50
[ ]+2a0:[ ]+0a3a8340[ ]+msub\.l r35,r32,r52
[ ]+2a4:[ ]+0a497f50[ ]+msub\.w r36,r31,r53
[ ]+2a8:[ ]+0a5e7b70[ ]+msubs\.l r37,r30,r55
[ ]+2ac:[ ]+0a6c7780[ ]+msubs\.ub r38,r29,r56
[ ]+2b0:[ ]+0a7d73a0[ ]+msubs\.w r39,r28,r58
[ ]+2b4:[ ]+03dea5a0[ ]+mulu\.l r61,r41,r26
[ ]+2b8:[ ]+6ff0fff0[ ]+nop
[ ]+2bc:[ ]+03cdfea0[ ]+nsb r60,r42
[ ]+2c0:[ ]+e2b987f0[ ]+ocbi r43,-992
[ ]+2c4:[ ]+e28883f0[ ]+ocbp r40,-1024
[ ]+2c8:[ ]+e2cc7ff0[ ]+ocbwb r44,992
[ ]+2cc:[ ]+07b90e80[ ]+or r59,r3,r40
[ ]+2d0:[ ]+dfa4e680[ ]+ori r58,313,r40
[ ]+2d4:[ ]+e391fff0[ ]+prefi r57,-32
[ ]+2d8:[ ]+6bf1e260[ ]+ptabs/l r56,tr6
[ ]+2dc:[ ]+6bf1fe60[ ]+ptabs/l r63,tr6
[ ]+2e0:[ ]+6bf1f060[ ]+ptabs/u r60,tr6
[ ]+2e4:[ ]+6bf5de30[ ]+ptrel/l r55,tr3
[ ]+2e8:[ ]+6bf53e30[ ]+ptrel/l r15,tr3
[ ]+2ec:[ ]+6bf5fc30[ ]+ptrel/u r63,tr3
[ ]+2f0:[ ]+e29fd7e0[ ]+putcfg r41,-11,r62
[ ]+2f4:[ ]+6e8ffde0[ ]+putcon r40,cr30
[ ]+2f8:[ ]+6ff3fff0[ ]+rte
[ ]+2fc:[ ]+0727a930[ ]+shard r50,r42,r19
[ ]+300:[ ]+0746a540[ ]+shard\.l r52,r41,r20
[ ]+304:[ ]+c757a150[ ]+shari r53,40,r21
[ ]+308:[ ]+c7769d60[ ]+shari\.l r55,39,r22
[ ]+30c:[ ]+07819970[ ]+shlld r56,r38,r23
[ ]+310:[ ]+07909580[ ]+shlld\.l r57,r37,r24
[ ]+314:[ ]+c7c19190[ ]+shlli r60,36,r25
[ ]+318:[ ]+c7d07da0[ ]+shlli\.l r61,31,r26
[ ]+31c:[ ]+07f389b0[ ]+shlrd r63,r34,r27
[ ]+320:[ ]+040285c0[ ]+shlrd\.l r0,r33,r28
[ ]+324:[ ]+c42381d0[ ]+shlri r2,32,r29
[ ]+328:[ ]+c4327de0[ ]+shlri\.l r3,31,r30
[ ]+32c:[ ]+cbff70d0[ ]+shori 65500,r13
[ ]+330:[ ]+6ff7fff0[ ]+sleep
[ ]+334:[ ]+a057d5d0[ ]+st\.b r5,501,r29
[ ]+338:[ ]+a867cdf0[ ]+st\.l r6,1996,r31
[ ]+33c:[ ]+ac77d600[ ]+st\.q r7,4008,r32
[ ]+340:[ ]+a497d610[ ]+st\.w r9,1002,r33
[ ]+344:[ ]+e0a6b2b0[ ]+sthi\.l r10,-20,r43
[ ]+348:[ ]+e0c75ec0[ ]+sthi\.q r12,23,r44
[ ]+34c:[ ]+e0d296d0[ ]+stlo\.l r13,-27,r45
[ ]+350:[ ]+e0f356e0[ ]+stlo\.q r15,21,r46
[ ]+354:[ ]+610076f0[ ]+stx\.b r16,r29,r47
[ ]+358:[ ]+6112cb00[ ]+stx\.l r17,r50,r48
[ ]+35c:[ ]+6133c710[ ]+stx\.q r19,r49,r49
[ ]+360:[ ]+61413f20[ ]+stx\.w r20,r15,r50
[ ]+364:[ ]+016b7730[ ]+sub r22,r29,r51
[ ]+368:[ ]+017a7340[ ]+sub\.l r23,r28,r52
[ ]+36c:[ ]+21936f50[ ]+swap\.q r25,r27,r53
[ ]+370:[ ]+6ff2fff0[ ]+synci
[ ]+374:[ ]+6ff6fff0[ ]+synco
[ ]+378:[ ]+6da1fff0[ ]+trapa r26
[ ]+37c:[ ]+05cd6b60[ ]+xor r28,r26,r54
[ ]+380:[ ]+c5dd7f70[ ]+xori r29,31,r55
[ ]+384:[ ]+047ed510[ ]+muls\.l r7,r53,r17
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange2-1.d
0,0 → 1,43
#as: --abi=32
#objdump: -dr
#source: crange2.s
#name: PT to SHcompact
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <shmedia>:
[ ]+0:[ ]+e8000a30[ ]+pta/l 8 <shmedia1>,tr3
[ ]+4:[ ]+ec001240[ ]+ptb/l 14 <shcompact1>,tr4
 
0+8 <shmedia1>:
[ ]+8:[ ]+ec001250[ ]+ptb/l 18 <shcompact2>,tr5
 
0+c <shmedia2>:
[ ]+c:[ ]+6ff0fff0[ ]+nop
 
0+10[ ]+<shcompact>:
[ ]+10:[ ]+00[ ]+09[ ]+nop
[ ]+12:[ ]+00[ ]+09[ ]+nop
 
0+14 <shcompact1>:
[ ]+14:[ ]+00[ ]+09[ ]+nop
[ ]+16:[ ]+00[ ]+09[ ]+nop
 
0+18 <shcompact2>:
[ ]+18:[ ]+00[ ]+09[ ]+nop
[ ]+1a:[ ]+00[ ]+09[ ]+nop
 
0+1c <shcompact3>:
[ ]+1c:[ ]+00[ ]+09[ ]+nop
[ ]+1e:[ ]+00[ ]+09[ ]+nop
 
0+20[ ]+<shcompact4>:
[ ]+20:[ ]+00[ ]+09[ ]+nop
[ ]+22:[ ]+00[ ]+09[ ]+nop
 
0+24 <shmedia3>:
[ ]+24:[ ]+effffa60[ ]+ptb/l 1c <shcompact3>,tr6
[ ]+28:[ ]+effffa70[ ]+ptb/l 20[ ]+<shcompact4>,tr7
[ ]+2c:[ ]+ebffe200[ ]+pta/l c <shmedia2>,tr0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange4-1.d
0,0 → 1,19
#as: --abi=32
#objdump: -sr
#source: crange4.s
#name: .cranges descriptors with final variant.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.cranges\]:
OFFSET *TYPE *VALUE
0+ R_SH_DIR32 \.text
0+a R_SH_DIR32 \.text
 
 
Contents of section \.text:
0000 6ff0fff0 00000000 00000000 00000000 .*
0010 00000000 00000000 .*
Contents of section \.cranges:
0000 00000000 00000004 00030000 00040000 .*
0010 00140001 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/immexpr2.s
0,0 → 1,16
! This expression and the associated resolved-expression case is new for SH64.
 
.data
.uaquad end-start
.uaquad .Lend-.Lstart
 
.text
.mode SHmedia
start:
nop
end:
.Lstart:
nop
nop
.Lend:
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift64-1.d
0,0 → 1,58
#as: --abi=64
#objdump: -dr
#source: shift-1.s
#name: Shift expressions, 64-bit ABI, 32-bit subset.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000040[ ]+movi 0,r4
[ ]+0:[ ]+R_SH_IMM_LOW16 \.data\+0x4
[ ]+4:[ ]+cc000040[ ]+movi 0,r4
[ ]+4:[ ]+R_SH_IMM_LOW16 \.data\+0x4
[ ]+8:[ ]+cc000040[ ]+movi 0,r4
[ ]+8:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x4
[ ]+c:[ ]+cc000040[ ]+movi 0,r4
[ ]+c:[ ]+R_SH_IMM_LOW16 externsym
[ ]+10:[ ]+cc000040[ ]+movi 0,r4
[ ]+10:[ ]+R_SH_IMM_LOW16 externsym
[ ]+14:[ ]+cc000040[ ]+movi 0,r4
[ ]+14:[ ]+R_SH_IMM_MEDLOW16 externsym
[ ]+18:[ ]+c8000040[ ]+shori 0,r4
[ ]+18:[ ]+R_SH_IMM_LOW16 \.data\+0x4
[ ]+1c:[ ]+c8000040[ ]+shori 0,r4
[ ]+1c:[ ]+R_SH_IMM_LOW16 \.data\+0x4
[ ]+20:[ ]+c8000040[ ]+shori 0,r4
[ ]+20:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x4
[ ]+24:[ ]+c8000040[ ]+shori 0,r4
[ ]+24:[ ]+R_SH_IMM_LOW16 externsym
[ ]+28:[ ]+c8000040[ ]+shori 0,r4
[ ]+28:[ ]+R_SH_IMM_LOW16 externsym
[ ]+2c:[ ]+c8000040[ ]+shori 0,r4
[ ]+2c:[ ]+R_SH_IMM_MEDLOW16 externsym
[ ]+30:[ ]+cc000040[ ]+movi 0,r4
[ ]+30:[ ]+R_SH_IMM_LOW16 \.data\+0x2e
[ ]+34:[ ]+cc000040[ ]+movi 0,r4
[ ]+34:[ ]+R_SH_IMM_LOW16 \.data\+0x2f
[ ]+38:[ ]+cc000040[ ]+movi 0,r4
[ ]+38:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x30
[ ]+3c:[ ]+cc000040[ ]+movi 0,r4
[ ]+3c:[ ]+R_SH_IMM_LOW16 externsym\+0x2d
[ ]+40:[ ]+cc000040[ ]+movi 0,r4
[ ]+40:[ ]+R_SH_IMM_LOW16 externsym\+0x2e
[ ]+44:[ ]+cc000040[ ]+movi 0,r4
[ ]+44:[ ]+R_SH_IMM_MEDLOW16 externsym\+0x2f
[ ]+48:[ ]+c8000040[ ]+shori 0,r4
[ ]+48:[ ]+R_SH_IMM_LOW16 \.data\+0x2e
[ ]+4c:[ ]+c8000040[ ]+shori 0,r4
[ ]+4c:[ ]+R_SH_IMM_LOW16 \.data\+0x2f
[ ]+50:[ ]+c8000040[ ]+shori 0,r4
[ ]+50:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x30
[ ]+54:[ ]+c8000040[ ]+shori 0,r4
[ ]+54:[ ]+R_SH_IMM_LOW16 externsym\+0x2d
[ ]+58:[ ]+c8000040[ ]+shori 0,r4
[ ]+58:[ ]+R_SH_IMM_LOW16 externsym\+0x2e
[ ]+5c:[ ]+c8000040[ ]+shori 0,r4
[ ]+5c:[ ]+R_SH_IMM_MEDLOW16 externsym\+0x2f
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/immexpr32-2.d
0,0 → 1,11
#as: --abi=32
#objdump: -sr
#source: immexpr2.s
#name: Resolved 64-bit operand, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Contents of section \.text:
0000 6ff0fff0 6ff0fff0 6ff0fff0 .*
Contents of section .data:
0000 00000000 00000004 00000000 00000008 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/datal32-1.d
0,0 → 1,45
#as: --abi=32
#objdump: -sr
#source: datal-1.s
#name: DataLabel redundant local use, SHmedia 32-bit ABI
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET *TYPE *VALUE
0+10 R_SH_IMM_MEDLOW16 \.data\+0x0+3a
0+14 R_SH_IMM_LOW16 myrodata3
0+18 R_SH_IMM_LOW16 \.rodata\+0x0+10
0+1c R_SH_IMM_LOW16 \.rodata\+0x0+3a
0+00 R_SH_IMM_MEDLOW16 \.data\+0x0+4
0+04 R_SH_IMM_LOW16 \.data\+0x0+4
0+08 R_SH_IMM_MEDLOW16 \.data\+0x0+32
0+0c R_SH_IMM_LOW16 \.data\+0x0+32
 
RELOCATION RECORDS FOR \[\.data\]:
OFFSET *TYPE *VALUE
0+00 R_SH_DIR32 \.rodata
0+04 R_SH_DIR32 \.rodata
0+08 R_SH_DIR32 \.data
0+0c R_SH_DIR32 \.data
0+10 R_SH_DIR32 \.data
0+14 R_SH_DIR32 myrodata3
0+18 R_SH_DIR32 foo6
 
RELOCATION RECORDS FOR \[\.rodata\]:
OFFSET *TYPE *VALUE
0+00 R_SH_DIR32 \.data
0+04 R_SH_DIR32 \.data
0+08 R_SH_DIR32 \.rodata
0+0c R_SH_DIR32 \.rodata
0+10 R_SH_DIR32 \.rodata
 
Contents of section \.text:
0000 cc000030 c8000030 cc000030 c8000030 .*
0010 cc000030 cc0002d0 cc0002d0 cc0002d0 .*
Contents of section \.data:
0000 00000004 00000026 00000004 0000000c .*
0010 00000038 00000000 0000002a .*
Contents of section \.rodata:
0000 00000010 0000004c 00000008 00000020 .*
0010 00000104 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptc32-1.d
0,0 → 1,15
#as: --abi=32
#objdump: -dr
#source: ptc-1.s
#name: PT constant, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000190[ ]+movi 0,r25
[ ]+0:[ ]+R_SH_IMM_MEDLOW16_PCREL \*ABS\*\+0xf8
[ ]+4:[ ]+c8000190[ ]+shori 0,r25
[ ]+4:[ ]+R_SH_IMM_LOW16_PCREL \*ABS\*\+0xfc
[ ]+8:[ ]+6bf56610[ ]+ptrel/l r25,tr1
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel64-3.d
0,0 → 1,111
#as: --abi=64
#objdump: -sr
#source: rel-3.s
#name: MOVI: PC-relative datalabel relocs, 64-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET TYPE VALUE
0+10 R_SH_IMM_LOW16_PCREL \.data\+0x0+8
0+14 R_SH_IMM_LOW16_PCREL \.data\+0x0+c
0+18 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+10
0+2c R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+30 R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+34 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+24
0+48 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+8
0+4c R_SH_IMM_LOW16_PCREL \.othertext\+0x0+c
0+50 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+10
0+64 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+68 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+6c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+24
0+80 R_SH_IMM_LOW16_PCREL extern2
0+84 R_SH_IMM_LOW16_PCREL extern3
0+88 R_SH_IMM_MEDLOW16_PCREL extern4
0+9c R_SH_IMM_LOW16_PCREL extern6\+0x0+10
0+a0 R_SH_IMM_LOW16_PCREL extern7\+0x0+c
0+a4 R_SH_IMM_MEDLOW16_PCREL extern8\+0x0+4
0+b8 R_SH_IMM_LOW16_PCREL gdata2
0+bc R_SH_IMM_LOW16_PCREL gdata3
0+c0 R_SH_IMM_MEDLOW16_PCREL gdata4
0+d4 R_SH_IMM_LOW16_PCREL gdata6\+0x0+10
0+d8 R_SH_IMM_LOW16_PCREL gdata7\+0x0+c
0+dc R_SH_IMM_MEDLOW16_PCREL gdata8\+0x0+4
0+f0 R_SH_IMM_LOW16_PCREL gothertext2
0+f4 R_SH_IMM_LOW16_PCREL gothertext3
0+f8 R_SH_IMM_MEDLOW16_PCREL gothertext4
0+10c R_SH_IMM_LOW16_PCREL gothertext6\+0x0+10
0+110 R_SH_IMM_LOW16_PCREL gothertext7\+0x0+c
0+114 R_SH_IMM_MEDLOW16_PCREL gothertext8\+0x0+4
0+ R_SH_IMM_HI16_PCREL \.data\+0x0+4
0+4 R_SH_IMM_MEDHI16_PCREL \.data\+0x0+8
0+8 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+c
0+c R_SH_IMM_LOW16_PCREL \.data\+0x0+10
0+1c R_SH_IMM_HI16_PCREL \.data\+0x0+1c
0+20 R_SH_IMM_MEDHI16_PCREL \.data\+0x0+20
0+24 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+24
0+28 R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+38 R_SH_IMM_HI16_PCREL \.othertext\+0x0+4
0+3c R_SH_IMM_MEDHI16_PCREL \.othertext\+0x0+8
0+40 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+c
0+44 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+10
0+54 R_SH_IMM_HI16_PCREL \.othertext\+0x0+1c
0+58 R_SH_IMM_MEDHI16_PCREL \.othertext\+0x0+20
0+5c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+24
0+60 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+70 R_SH_IMM_HI16_PCREL extern1
0+74 R_SH_IMM_MEDHI16_PCREL extern1\+0x0+4
0+78 R_SH_IMM_MEDLOW16_PCREL extern1\+0x0+8
0+7c R_SH_IMM_LOW16_PCREL extern1\+0x0+c
0+8c R_SH_IMM_HI16_PCREL extern5\+0x0+8
0+90 R_SH_IMM_MEDHI16_PCREL extern5\+0x0+c
0+94 R_SH_IMM_MEDLOW16_PCREL extern5\+0x0+10
0+98 R_SH_IMM_LOW16_PCREL extern5\+0x0+14
0+a8 R_SH_IMM_HI16_PCREL gdata1
0+ac R_SH_IMM_MEDHI16_PCREL gdata1\+0x0+4
0+b0 R_SH_IMM_MEDLOW16_PCREL gdata1\+0x0+8
0+b4 R_SH_IMM_LOW16_PCREL gdata1\+0x0+c
0+c4 R_SH_IMM_HI16_PCREL gdata5\+0x0+8
0+c8 R_SH_IMM_MEDHI16_PCREL gdata5\+0x0+c
0+cc R_SH_IMM_MEDLOW16_PCREL gdata5\+0x0+10
0+d0 R_SH_IMM_LOW16_PCREL gdata5\+0x0+14
0+e0 R_SH_IMM_HI16_PCREL gothertext1
0+e4 R_SH_IMM_MEDHI16_PCREL gothertext1\+0x0+4
0+e8 R_SH_IMM_MEDLOW16_PCREL gothertext1\+0x0+8
0+ec R_SH_IMM_LOW16_PCREL gothertext1\+0x0+c
0+fc R_SH_IMM_HI16_PCREL gothertext5\+0x0+8
0+100 R_SH_IMM_MEDHI16_PCREL gothertext5\+0x0+c
0+104 R_SH_IMM_MEDLOW16_PCREL gothertext5\+0x0+10
0+108 R_SH_IMM_LOW16_PCREL gothertext5\+0x0+14
 
Contents of section \.text:
0000 cc0000a0 c80000a0 c80000a0 c80000a0 .*
0010 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0020 c80000a0 c80000a0 c80000a0 cc0000a0 .*
0030 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0040 c80000a0 c80000a0 cc0000a0 cc0000a0 .*
0050 cc0000a0 cc0000a0 c80000a0 c80000a0 .*
0060 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
0070 cc0000a0 c80000a0 c80000a0 c80000a0 .*
0080 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0090 c80000a0 c80000a0 c80000a0 cc0000a0 .*
00a0 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
00b0 c80000a0 c80000a0 cc0000a0 cc0000a0 .*
00c0 cc0000a0 cc0000a0 c80000a0 c80000a0 .*
00d0 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
00e0 cc0000a0 c80000a0 c80000a0 c80000a0 .*
00f0 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0100 c80000a0 c80000a0 c80000a0 cc0000a0 .*
0110 cc0000a0 cc0000a0 .*
Contents of section \.data:
0000 00000000 00000000 00000000 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 00000000 00000000 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 .*
Contents of section \.othertext:
0000 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0040 6ff0fff0 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/basic-1.s
0,0 → 1,233
! Various straightforward insn tests, one per insns basic insn format.
! No insns with strange relocs. The insns are from the alphabetical list
! in SH-5/ST50-023-04.
 
.text
start:
add r3,r25,r43
add.l r13,r2,r62
addi r44,500,r33
addi.l r21,-500,r43
addz.l r51,r42,r30
alloco r19,960
and r8,r57,r12
andc r48,r35,r18
andi r24,509,r38
beq r23,r37,tr2
beq/l r23,r27,tr4
beq/u r3,r47,tr6
beqi r4,30,tr5
beqi/l r4,-31,tr0
beqi/u r54,-23,tr2
bge r0,r63,tr7
bge/l r10,r6,tr4
bge/u r11,r36,tr1
bgeu r30,r43,tr3
bgeu/l r10,r26,tr5
bgeu/u r51,r36,tr2
bgt r33,r44,tr7
bgt/l r17,r62,tr4
bgt/u r15,r6,tr1
bgtu r34,r27,tr6
bgtu/l r28,r62,tr0
bgtu/u r18,r25,tr5
blink tr1,r38
bne r62,r47,tr0
bne/l r29,r22,tr1
bne/u r39,r47,tr6
bnei r14,-13,tr7
bnei/l r24,31,tr3
bnei/u r54,-22,tr2
brk
byterev r21,r12
cmpeq r10,r11,r21
cmpgt r30,r31,r51
cmpgtu r23,r33,r45
cmveq r32,r3,r44
cmvne r13,r60,r4
fabs.d dr22,dr62
fabs.s fr59,fr25
fadd.d dr40,dr60,dr20
fadd.s fr41,fr59,fr19
fcmpeq.d dr4,dr50,r57
fcmpeq.s fr47,fr30,r17
fcmpge.d dr44,dr52,r20
fcmpge.s fr37,fr23,r32
fcmpgt.d dr20,dr28,r51
fcmpgt.s fr47,fr21,r22
fcmpun.d dr32,dr58,r47
fcmpun.s fr21,fr42,r12
fcnv.ds dr40,fr21
fcnv.sd fr43,dr32
fdiv.d dr34,dr56,dr20
fdiv.s fr13,fr26,fr19
fgetscr fr39
fipr.s fv0,fv8,fr39
fld.d r31,2000,dr48
fld.p r53,-3000,fp38
fld.s r53,2036,fr53
fldx.d r23,r42,dr2
fldx.p r2,r22,fp32
fldx.s r27,r58,fr12
float.ld fr5,dr28
float.ls fr55,fr36
float.qd dr44,dr16
float.qs dr30,fr11
fmac.s fr40,fr37,fr4
fmov.d dr8,dr40
fmov.dq dr58,r34
fmov.ls r25,fr52
fmov.qd r45,dr50
fmov.s fr4,fr55
fmov.sl fr14,r15
fmul.d dr24,dr58,dr42
fmul.s fr27,fr32,fr34
fneg.d dr2,dr0
fneg.s fr0,fr33
fputscr fr44
fsqrt.d dr30,dr44
fsqrt.s fr3,fr23
fst.d r3,4000,dr2
fst.p r54,-4008,fp12
fst.s r18,-2012,fr23
fstx.d r18,r46,dr12
fstx.p r38,r26,fp52
fstx.s r7,r23,fr26
fsub.d dr0,dr44,dr32
fsub.s fr3,fr62,fr3
ftrc.dl dr38,fr53
ftrc.sl fr58,fr49
ftrc.dq dr14,dr26
ftrc.sq fr60,dr22
ftrv.s mtrx16,fv32,fv28
getcfg r5,-11,r62
getcon cr52,r16
gettr tr6,r26
icbi r48,-960
ld.b r50,3,r62
ld.l r5,-604,r22
ld.q r35,-1608,r42
ld.ub r53,-201,r2
ld.uw r23,-402,r42
ld.w r46,302,r11
ldhi.l r6,-30,r41
ldhi.q r36,31,r31
ldlo.l r19,20,r48
ldlo.q r9,-32,r29
ldx.b r5,r3,r47
ldx.l r25,r43,r14
ldx.q r12,r60,r41
ldx.ub r13,r0,r1
ldx.uw r13,r2,r17
ldx.w r10,r22,r60
mabs.l r7,r33
mabs.w r37,r34
madd.l r34,r32,r7
madd.w r23,r53,r17
madds.l r24,r23,r9
madds.ub r34,r23,r49
madds.w r4,r2,r59
mcmpeq.b r22,r56,r31
mcmpeq.l r21,r45,r61
mcmpeq.w r32,r54,r1
mcmpgt.l r3,r4,r19
mcmpgt.ub r34,r54,r13
mcmpgt.w r23,r5,r3
mcmv r62,r50,r30
mcnvs.lw r2,r5,r0
mcnvs.wb r21,r7,r10
mcnvs.wub r23,r47,r13
mextr1 r4,r41,r7
mextr2 r32,r4,r47
mextr3 r25,r46,r27
mextr4 r52,r6,r2
mextr5 r21,r16,r21
mextr6 r24,r62,r42
mextr7 r57,r46,r23
mmacfx.wl r5,r4,r2
mmacnfx.wl r11,r44,r22
mmul.l r22,r33,r44
mmul.w r12,r35,r47
mmulfx.l r61,r37,r48
mmulfx.w r1,r7,r5
mmulfxrp.w r10,r37,r50
mmulhi.wl r0,r7,r55
mmullo.wl r10,r27,r35
mmulsum.wq r41,r32,r37
movi -123,r43
mperm.w r57,r32,r4
msad.ubq r5,r23,r20
mshalds.l r35,r12,r20
mshalds.w r43,r52,r30
mshard.l r4,r23,r40
mshard.w r24,r62,r10
mshards.q r2,r16,r50
mshfhi.b r42,r6,r60
mshfhi.l r52,r18,r59
mshfhi.w r8,r31,r46
mshflo.b r28,r39,r41
mshflo.l r29,r38,r43
mshflo.w r30,r37,r44
mshlld.l r31,r36,r46
mshlld.w r32,r35,r47
mshlrd.l r33,r34,r49
mshlrd.w r34,r33,r50
msub.l r35,r32,r52
msub.w r36,r31,r53
msubs.l r37,r30,r55
msubs.ub r38,r29,r56
msubs.w r39,r28,r58
mulu.l r61,r41,r26
nop
nsb r60,r42
ocbi r43,-992
ocbp r40,-1024
ocbwb r44,992
or r59,r3,r40
ori r58,313,r40
prefi r57,-32
! Note: pta, ptb are not here.
ptabs r56,tr6
ptabs/l r63,tr6
ptabs/u r60,tr6
ptrel r55,tr3
ptrel/l r15,tr3
ptrel/u r63,tr3
putcfg r41,-11,r62
putcon r40,cr30
rte
shard r50,r42,r19
shard.l r52,r41,r20
shari r53,40,r21
shari.l r55,39,r22
shlld r56,r38,r23
shlld.l r57,r37,r24
shlli r60,36,r25
shlli.l r61,31,r26
shlrd r63,r34,r27
shlrd.l r0,r33,r28
shlri r2,32,r29
shlri.l r3,31,r30
shori 65500,r13
sleep
st.b r5,501,r29
st.l r6,1996,r31
st.q r7,4008,r32
st.w r9,1002,r33
sthi.l r10,-20,r43
sthi.q r12,23,r44
stlo.l r13,-27,r45
stlo.q r15,21,r46
stx.b r16,r29,r47
stx.l r17,r50,r48
stx.q r19,r49,r49
stx.w r20,r15,r50
sub r22,r29,r51
sub.l r23,r28,r52
swap.q r25,r27,r53
synci
synco
trapa r26
xor r28,r26,r54
xori r29,31,r55
muls.l r7,r53,r17
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptext32-noexp-1.d
0,0 → 1,22
#as: --isa=shmedia --abi=32 -no-expand
#source: ptext-1.s
#objdump: -dr
#name: PT, PTA, PTB non-expansion for external symbols, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+e8000250[ ]+pta/l 0 <start>,tr5
[ ]+0:[ ]+R_SH_PT_16 externalsym1\+0x28
[ ]+4:[ ]+e8000640[ ]+pta/l 8 <start\+0x8>,tr4
[ ]+4:[ ]+R_SH_PT_16 externalsym2\+0x2c
[ ]+8:[ ]+ec000630[ ]+ptb/l c <start\+0xc>,tr3
[ ]+8:[ ]+R_SH_PT_16 externalsym3\+0x30
[ ]+c:[ ]+e8000050[ ]+pta/u c <start\+0xc>,tr5
[ ]+c:[ ]+R_SH_PT_16 externalsym4\+0x34
[ ]+10:[ ]+e8000440[ ]+pta/u 14 <start\+0x14>,tr4
[ ]+10:[ ]+R_SH_PT_16 externalsym5\+0x38
[ ]+14:[ ]+ec000430[ ]+ptb/u 18 <start\+0x18>,tr3
[ ]+14:[ ]+R_SH_PT_16 externalsym6\+0x3c
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange2.s
0,0 → 1,34
! Check PT to SHcompact within same section as SHmedia, and that PT to
! nearby SHmedia still gets the right offset.
.text
.mode SHmedia
shmedia:
pt shmedia1,tr3
pt shcompact1,tr4
shmedia1:
ptb shcompact2,tr5
shmedia2:
nop
 
.mode SHcompact
shcompact: ! Have a label, so disassembling unrelocated code works.
nop
nop
shcompact1:
nop
nop
shcompact2:
nop
nop
shcompact3:
nop
nop
shcompact4:
nop
nop
 
.mode SHmedia
shmedia3:
pt shcompact3,tr6
ptb shcompact4,tr7
pt shmedia2,tr0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptc-1.s
0,0 → 1,5
! Check that simple constants get expected results.
.mode SHmedia
.text
start:
pta 0x100, tr1
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-movi-noexp-1.s
0,0 → 1,24
! Check that we get errors for MOVI operands out-of-range with -no-expand.
 
! { dg-do assemble }
! { dg-options "--abi=32 --isa=shmedia -no-expand" }
 
.text
start:
movi externalsym + 123,r3
movi 65535,r3 ! { dg-error "not a 16-bit signed value" }
movi 65536,r3 ! { dg-error "not a 16-bit signed value" }
movi 65535 << 16,r3 ! { dg-error "not a 16-bit signed value" }
movi 32767,r3
movi 32768,r3 ! { dg-error "not a 16-bit signed value" }
movi 32767 << 16,r3 ! { dg-error "not a 16-bit signed value" }
movi -32768,r3
movi -32769,r3 ! { dg-error "not a 16-bit signed value" }
movi -32768 << 16,r3 ! { dg-error "not a 16-bit signed value" }
movi localsym + 73,r4
movi forwardsym - 42,r4
.set forwardsym,47
 
.data
localsym:
.long 1
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-1.s
0,0 → 1,47
! { dg-do assemble }
 
! Various operand errors experienced during the creation of basic-1.s;
! some are redundant.
!
addz.l r51,-42,r30 ! { dg-error "invalid operand" }
beqi r4,-33,tr5 ! { dg-error "not a 6-bit signed value" }
fadd.s dr41,dr59,dr19 ! { dg-error "invalid operand" }
fdiv.s fr13,dr26,fr19 ! { dg-error "invalid operand" }
fld.p r53,-3000,fp39 ! { dg-error "invalid operand" }
fld.s r53,1010,fr53 ! { dg-error "not a multiple of 4" }
float.qd dr45,dr16 ! { dg-error "invalid operand" }
float.qs dr31,fr11 ! { dg-error "invalid operand" }
fmov.d dr8,dr43 ! { dg-error "invalid operand" }
fmov.qd r45,dr5 ! { dg-error "invalid operand" }
fmul.d dr7,dr57,dr42 ! { dg-error "invalid operand" }
fneg.s fr0,dr33 ! { dg-error "invalid operand" }
fsqrt.d dr31,dr43 ! { dg-error "invalid operand" }
fst.p r54,-4008,fp11 ! { dg-error "invalid operand" }
fstx.p r38,r26,dr52 ! { dg-error "invalid operand" }
ftrc.dq dr15,dr29 ! { dg-error "invalid operand" }
ftrv.s mtrx16,fv32,fv7 ! { dg-error "invalid operand" }
icbi r48,12000 ! { dg-error "not a 11-bit signed value" }
ld.w r46,301,r11 ! { dg-error "not an even value" }
ldhi.l r6,302,r41 ! { dg-error "not a 6-bit signed value" }
ldlo.l r19,334,r48 ! { dg-error "not a 6-bit signed value" }
ldlo.q r9,311,r29 ! { dg-error "not a 6-bit signed value" }
ocbi r43,11008 ! { dg-error "not a 11-bit signed value" }
ocbp r40,-11008 ! { dg-error "not a 11-bit signed value" }
ocbwb r44,-10016 ! { dg-error "not a 11-bit signed value" }
prefi r57,16000 ! { dg-error "not a 11-bit signed value" }
putcfg r41,-511,r62 ! { dg-error "not a 6-bit signed value" }
shlld r56,38,r23 ! { dg-error "invalid operand" }
shlli.l r61,r35,r26 ! { dg-error "invalid operand" }
shlli r60,r36,r25 ! { dg-error "invalid operand" }
shlri r2,r32,r29 ! { dg-error "invalid operand" }
shlri.l r3,r31,r30 ! { dg-error "invalid operand" }
st.w r9,2002,r33 ! { dg-error "not a 11-bit signed value" }
sthi.l r10,-201,r43 ! { dg-error "not a 6-bit signed value" }
sthi.q r12,203,r44 ! { dg-error "not a 6-bit signed value" }
stlo.l r13,-207,r45 ! { dg-error "not a 6-bit signed value" }
stlo.q r15,217,r46 ! { dg-error "not a 6-bit signed value" }
stx.b r16,219,r47 ! { dg-error "invalid operand" }
stx.l r17,-500,r48 ! { dg-error "invalid operand" }
stx.q r19,-50,r49 ! { dg-error "invalid operand" }
stx.w r20,-150,r50 ! { dg-error "invalid operand" }
xori r29,-51,r55 ! { dg-error "not a 6-bit signed value" }
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/case-1.d
0,0 → 1,23
#as: --abi=32
#objdump: -dr
#name: Case-insensitive registers and opcodes.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
[ ]+4:[ ]+6ff0fff0[ ]+nop
[ ]+8:[ ]+cc000190[ ]+movi 0,r25
[ ]+8:[ ]+R_SH_IMM_MEDLOW16_PCREL foo\+0xf*ff8
[ ]+c:[ ]+c8000190[ ]+shori 0,r25
[ ]+c:[ ]+R_SH_IMM_LOW16_PCREL foo\+0xf*ffc
[ ]+10:[ ]+6bf56440[ ]+ptrel/u r25,tr4
[ ]+14:[ ]+cc000190[ ]+movi 0,r25
[ ]+14:[ ]+R_SH_IMM_MEDLOW16_PCREL bar\+0xf*ff8
[ ]+18:[ ]+c8000190[ ]+shori 0,r25
[ ]+18:[ ]+R_SH_IMM_LOW16_PCREL bar\+0xf*ffc
[ ]+1c:[ ]+6bf56630[ ]+ptrel/l r25,tr3
[ ]+20:[ ]+cc00a820[ ]+movi 42,r2
[ ]+24:[ ]+ebffde20[ ]+pta/l 0 <start>,tr2
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi64-noexp-2.d
0,0 → 1,28
#as: --isa=shmedia --abi=64 -no-expand
#objdump: -dr
#source: movi-2.s
#name: MOVI non-expansion of local symbols with relocs, 64-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <start>:
[ ]+0:[ ]+cc000210[ ]+movi 0,r33
[ ]+0:[ ]+R_SH_IMMS16 \.text\+0x2d
[ ]+4:[ ]+cc000360[ ]+movi 0,r54
[ ]+4:[ ]+R_SH_IMMS16 \.data\+0x2c
[ ]+8:[ ]+cc0000f0[ ]+movi 0,r15
[ ]+8:[ ]+R_SH_IMMS16 \.text\.other\+0x35
 
0+c <forw>:
[ ]+c:[ ]+cc000190[ ]+movi 0,r25
[ ]+c:[ ]+R_SH_IMMS16 \.data\.other\+0x38
Disassembly of section \.text\.other:
 
0+ <forwdummylabel>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
0+8 <forwothertext>:
[ ]+8:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/relax-2.d
0,0 → 1,30
#as: --abi=64
#objdump: -dr
#source: relax-2.s
#name: Assembler PTB relaxation limit, from first to second state.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start2>:
[ ]+4:[ ]+cc000990[ ]+movi 2,r25
[ ]+8:[ ]+c8000190[ ]+shori 0,r25
[ ]+c:[ ]+6bf56630[ ]+ptrel/l r25,tr3
 
0+10 <[ax]1>:
[ ]+10:[ ]+edfffe40[ ]+ptb/l 2000c <[ax]0>,tr4
[ ]+\.\.\.
 
0+2000c <[ax]0>:
[ ]+2000c:[ ]+ee000650[ ]+ptb/l 10 <[ax]1>,tr5
[ ]+20010:[ ]+ee000260[ ]+ptb/l 10 <[ax]1>,tr6
[ ]+20014:[ ]+cffff590[ ]+movi -3,r25
[ ]+20018:[ ]+cbffd190[ ]+shori 65524,r25
[ ]+2001c:[ ]+6bf56660[ ]+ptrel/l r25,tr6
[ ]+20020:[ ]+cffff590[ ]+movi -3,r25
[ ]+20024:[ ]+cbffa190[ ]+shori 65512,r25
[ ]+20028:[ ]+6bf56670[ ]+ptrel/l r25,tr7
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/abi-32.d
0,0 → 1,10
#as: --abi=32
#objdump: -dr
#name: Assertion .abi 32.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/creg-1.d
0,0 → 1,77
#as: --abi=32
#objdump: -dr
#name: Predefined control register names.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+240ffd50[ ]+getcon sr,r21
[ ]+4:[ ]+241ffdf0[ ]+getcon ssr,r31
[ ]+8:[ ]+242ffd60[ ]+getcon pssr,r22
[ ]+c:[ ]+244ffd50[ ]+getcon intevt,r21
[ ]+10:[ ]+245ffd50[ ]+getcon expevt,r21
[ ]+14:[ ]+246ffd50[ ]+getcon pexpevt,r21
[ ]+18:[ ]+247ffcc0[ ]+getcon tra,r12
[ ]+1c:[ ]+248ffd50[ ]+getcon spc,r21
[ ]+20:[ ]+249ffe90[ ]+getcon pspc,r41
[ ]+24:[ ]+24affd50[ ]+getcon resvec,r21
[ ]+28:[ ]+24bffd30[ ]+getcon vbr,r19
[ ]+2c:[ ]+24dffd50[ ]+getcon tea,r21
[ ]+30:[ ]+250ffe30[ ]+getcon dcr,r35
[ ]+34:[ ]+251ffd50[ ]+getcon kcr0,r21
[ ]+38:[ ]+252ffd50[ ]+getcon kcr1,r21
[ ]+3c:[ ]+27effd60[ ]+getcon ctc,r22
[ ]+40:[ ]+27fffd50[ ]+getcon usr,r21
[ ]+44:[ ]+240ffc20[ ]+getcon sr,r2
[ ]+48:[ ]+241ffd50[ ]+getcon ssr,r21
[ ]+4c:[ ]+242ffd50[ ]+getcon pssr,r21
[ ]+50:[ ]+244ffd50[ ]+getcon intevt,r21
[ ]+54:[ ]+245ffe60[ ]+getcon expevt,r38
[ ]+58:[ ]+246ffd50[ ]+getcon pexpevt,r21
[ ]+5c:[ ]+247ffd50[ ]+getcon tra,r21
[ ]+60:[ ]+248ffc10[ ]+getcon spc,r1
[ ]+64:[ ]+249ffd50[ ]+getcon pspc,r21
[ ]+68:[ ]+24affd50[ ]+getcon resvec,r21
[ ]+6c:[ ]+24bffef0[ ]+getcon vbr,r47
[ ]+70:[ ]+24dffd50[ ]+getcon tea,r21
[ ]+74:[ ]+250ffd50[ ]+getcon dcr,r21
[ ]+78:[ ]+251ffe30[ ]+getcon kcr0,r35
[ ]+7c:[ ]+252ffd50[ ]+getcon kcr1,r21
[ ]+80:[ ]+27effd50[ ]+getcon ctc,r21
[ ]+84:[ ]+27fffd50[ ]+getcon usr,r21
[ ]+88:[ ]+6d5ffc00[ ]+putcon r21,sr
[ ]+8c:[ ]+6dfffc10[ ]+putcon r31,ssr
[ ]+90:[ ]+6d6ffc20[ ]+putcon r22,pssr
[ ]+94:[ ]+6d5ffc40[ ]+putcon r21,intevt
[ ]+98:[ ]+6d5ffc50[ ]+putcon r21,expevt
[ ]+9c:[ ]+6d5ffc60[ ]+putcon r21,pexpevt
[ ]+a0:[ ]+6ccffc70[ ]+putcon r12,tra
[ ]+a4:[ ]+6d5ffc80[ ]+putcon r21,spc
[ ]+a8:[ ]+6e9ffc90[ ]+putcon r41,pspc
[ ]+ac:[ ]+6d5ffca0[ ]+putcon r21,resvec
[ ]+b0:[ ]+6d3ffcb0[ ]+putcon r19,vbr
[ ]+b4:[ ]+6d5ffcd0[ ]+putcon r21,tea
[ ]+b8:[ ]+6e3ffd00[ ]+putcon r35,dcr
[ ]+bc:[ ]+6d5ffd10[ ]+putcon r21,kcr0
[ ]+c0:[ ]+6d5ffd20[ ]+putcon r21,kcr1
[ ]+c4:[ ]+6d6fffe0[ ]+putcon r22,ctc
[ ]+c8:[ ]+6d5ffff0[ ]+putcon r21,usr
[ ]+cc:[ ]+6c2ffc00[ ]+putcon r2,sr
[ ]+d0:[ ]+6d5ffc10[ ]+putcon r21,ssr
[ ]+d4:[ ]+6d5ffc20[ ]+putcon r21,pssr
[ ]+d8:[ ]+6d5ffc40[ ]+putcon r21,intevt
[ ]+dc:[ ]+6e6ffc50[ ]+putcon r38,expevt
[ ]+e0:[ ]+6d5ffc60[ ]+putcon r21,pexpevt
[ ]+e4:[ ]+6d5ffc70[ ]+putcon r21,tra
[ ]+e8:[ ]+6c1ffc80[ ]+putcon r1,spc
[ ]+ec:[ ]+6d5ffc90[ ]+putcon r21,pspc
[ ]+f0:[ ]+6d5ffca0[ ]+putcon r21,resvec
[ ]+f4:[ ]+6efffcb0[ ]+putcon r47,vbr
[ ]+f8:[ ]+6d5ffcd0[ ]+putcon r21,tea
[ ]+fc:[ ]+6d5ffd00[ ]+putcon r21,dcr
[ ]+100:[ ]+6e3ffd10[ ]+putcon r35,kcr0
[ ]+104:[ ]+6d5ffd20[ ]+putcon r21,kcr1
[ ]+108:[ ]+6d5fffe0[ ]+putcon r21,ctc
[ ]+10c:[ ]+6d5ffff0[ ]+putcon r21,usr
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift32-1.d
0,0 → 1,58
#as: --abi=32
#objdump: -dr
#source: shift-1.s
#name: Shift expressions, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000040[ ]+movi 0,r4
[ ]+0:[ ]+R_SH_IMM_LOW16 \.data\+0x4
[ ]+4:[ ]+cc000040[ ]+movi 0,r4
[ ]+4:[ ]+R_SH_IMM_LOW16 \.data\+0x4
[ ]+8:[ ]+cc000040[ ]+movi 0,r4
[ ]+8:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x4
[ ]+c:[ ]+cc000040[ ]+movi 0,r4
[ ]+c:[ ]+R_SH_IMM_LOW16 externsym
[ ]+10:[ ]+cc000040[ ]+movi 0,r4
[ ]+10:[ ]+R_SH_IMM_LOW16 externsym
[ ]+14:[ ]+cc000040[ ]+movi 0,r4
[ ]+14:[ ]+R_SH_IMM_MEDLOW16 externsym
[ ]+18:[ ]+c8000040[ ]+shori 0,r4
[ ]+18:[ ]+R_SH_IMM_LOW16 \.data\+0x4
[ ]+1c:[ ]+c8000040[ ]+shori 0,r4
[ ]+1c:[ ]+R_SH_IMM_LOW16 \.data\+0x4
[ ]+20:[ ]+c8000040[ ]+shori 0,r4
[ ]+20:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x4
[ ]+24:[ ]+c8000040[ ]+shori 0,r4
[ ]+24:[ ]+R_SH_IMM_LOW16 externsym
[ ]+28:[ ]+c8000040[ ]+shori 0,r4
[ ]+28:[ ]+R_SH_IMM_LOW16 externsym
[ ]+2c:[ ]+c8000040[ ]+shori 0,r4
[ ]+2c:[ ]+R_SH_IMM_MEDLOW16 externsym
[ ]+30:[ ]+cc000040[ ]+movi 0,r4
[ ]+30:[ ]+R_SH_IMM_LOW16 \.data\+0x2e
[ ]+34:[ ]+cc000040[ ]+movi 0,r4
[ ]+34:[ ]+R_SH_IMM_LOW16 \.data\+0x2f
[ ]+38:[ ]+cc000040[ ]+movi 0,r4
[ ]+38:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x30
[ ]+3c:[ ]+cc000040[ ]+movi 0,r4
[ ]+3c:[ ]+R_SH_IMM_LOW16 externsym\+0x2d
[ ]+40:[ ]+cc000040[ ]+movi 0,r4
[ ]+40:[ ]+R_SH_IMM_LOW16 externsym\+0x2e
[ ]+44:[ ]+cc000040[ ]+movi 0,r4
[ ]+44:[ ]+R_SH_IMM_MEDLOW16 externsym\+0x2f
[ ]+48:[ ]+c8000040[ ]+shori 0,r4
[ ]+48:[ ]+R_SH_IMM_LOW16 \.data\+0x2e
[ ]+4c:[ ]+c8000040[ ]+shori 0,r4
[ ]+4c:[ ]+R_SH_IMM_LOW16 \.data\+0x2f
[ ]+50:[ ]+c8000040[ ]+shori 0,r4
[ ]+50:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x30
[ ]+54:[ ]+c8000040[ ]+shori 0,r4
[ ]+54:[ ]+R_SH_IMM_LOW16 externsym\+0x2d
[ ]+58:[ ]+c8000040[ ]+shori 0,r4
[ ]+58:[ ]+R_SH_IMM_LOW16 externsym\+0x2e
[ ]+5c:[ ]+c8000040[ ]+shori 0,r4
[ ]+5c:[ ]+R_SH_IMM_MEDLOW16 externsym\+0x2f
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-pt32-cmd3.s
0,0 → 1,10
! Check command-line error checking. The option -expand-pt32 is invalid with
! -abi=32 just as it is invalid with no SHmedia/SHcompact options.
 
! { dg-do assemble }
! { dg-options "-abi=32 -expand-pt32" }
! { dg-error ".* only valid with -abi=64" "" { target sh64-*-* } 0 }
 
.text
start:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel32-3.d
0,0 → 1,86
#as: --abi=32
#objdump: -sr
#source: rel-3.s
#name: MOVI: PC-relative datalabel relocs, 32-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET *TYPE *VALUE
0+8 R_SH_IMM_LOW16_PCREL \.data\+0x0+8
0+c R_SH_IMM_LOW16_PCREL \.data\+0x0+c
0+10 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+10
0+1c R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+20 R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+24 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+24
0+30 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+8
0+34 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+c
0+38 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+10
0+44 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+48 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+4c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+24
0+58 R_SH_IMM_LOW16_PCREL extern2
0+5c R_SH_IMM_LOW16_PCREL extern3
0+60 R_SH_IMM_MEDLOW16_PCREL extern4
0+6c R_SH_IMM_LOW16_PCREL extern6\+0x0+10
0+70 R_SH_IMM_LOW16_PCREL extern7\+0x0+c
0+74 R_SH_IMM_MEDLOW16_PCREL extern8\+0x0+4
0+80 R_SH_IMM_LOW16_PCREL gdata2
0+84 R_SH_IMM_LOW16_PCREL gdata3
0+88 R_SH_IMM_MEDLOW16_PCREL gdata4
0+94 R_SH_IMM_LOW16_PCREL gdata6\+0x0+10
0+98 R_SH_IMM_LOW16_PCREL gdata7\+0x0+c
0+9c R_SH_IMM_MEDLOW16_PCREL gdata8\+0x0+4
0+a8 R_SH_IMM_LOW16_PCREL gothertext2
0+ac R_SH_IMM_LOW16_PCREL gothertext3
0+b0 R_SH_IMM_MEDLOW16_PCREL gothertext4
0+bc R_SH_IMM_LOW16_PCREL gothertext6\+0x0+10
0+c0 R_SH_IMM_LOW16_PCREL gothertext7\+0x0+c
0+c4 R_SH_IMM_MEDLOW16_PCREL gothertext8\+0x0+4
0+ R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+4
0+4 R_SH_IMM_LOW16_PCREL \.data\+0x0+8
0+14 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+1c
0+18 R_SH_IMM_LOW16_PCREL \.data\+0x0+20
0+28 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+4
0+2c R_SH_IMM_LOW16_PCREL \.othertext\+0x0+8
0+3c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+1c
0+40 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+20
0+50 R_SH_IMM_MEDLOW16_PCREL extern1
0+54 R_SH_IMM_LOW16_PCREL extern1\+0x0+4
0+64 R_SH_IMM_MEDLOW16_PCREL extern5\+0x0+8
0+68 R_SH_IMM_LOW16_PCREL extern5\+0x0+c
0+78 R_SH_IMM_MEDLOW16_PCREL gdata1
0+7c R_SH_IMM_LOW16_PCREL gdata1\+0x0+4
0+8c R_SH_IMM_MEDLOW16_PCREL gdata5\+0x0+8
0+90 R_SH_IMM_LOW16_PCREL gdata5\+0x0+c
0+a0 R_SH_IMM_MEDLOW16_PCREL gothertext1
0+a4 R_SH_IMM_LOW16_PCREL gothertext1\+0x0+4
0+b4 R_SH_IMM_MEDLOW16_PCREL gothertext5\+0x0+8
0+b8 R_SH_IMM_LOW16_PCREL gothertext5\+0x0+c
 
Contents of section \.text:
0000 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
0010 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
0020 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0030 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0040 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
0050 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
0060 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
0070 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0080 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0090 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
00a0 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
00b0 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
00c0 cc0000a0 cc0000a0 .*
Contents of section \.data:
0000 00000000 00000000 00000000 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 00000000 00000000 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 .*
Contents of section \.othertext:
0000 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0040 6ff0fff0 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/case-1.s
0,0 → 1,12
! Tests that opcodes and common registers are recognized case-insensitive,
! and also that the option --isa=shmedia is optional.
 
.mode SHmedia
.text
start:
nOp
NOP
pt/U foo,tr4
PTA/l bar,Tr3
MOVI 42,R2
PTA/L start,TR2
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/relax-2.s
0,0 → 1,23
! Check relaxation for PTB. This is like relax-1.s, but presumably we can
! have bugs in the slight differences in limit-checking compared to PT and
! PTA.
 
.mode SHmedia
start:
nop
start2:
ptb x0,tr3
.mode SHcompact
x1:
.mode SHmedia
a1:
ptb x0,tr4
.space 32767*4-4,0
.mode SHcompact
x0:
.mode SHmedia
a0:
ptb x1,tr5
ptb x1,tr6
ptb x1,tr6
ptb x1,tr7
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-ptb-2.s
0,0 → 1,34
! Check that PTB to a assembly-time-resolvable SHcompact operand gets an
! error. Mostly like err-ptb-1.s, except we also specify --no-expand.
 
! { dg-do assemble }
! { dg-options "--abi=32 --no-expand" }
 
.text
.mode SHmedia
start:
ptb shmediasymbol1,tr1 ! { dg-error "PTB operand is a SHmedia symbol" }
shmediasymbol3:
ptb shcompactsymbol1,tr1
pta shcompactsymbol2,tr3 ! { dg-error "PTA operand is a SHcompact symbol" }
shmediasymbol1:
ptb shmediasymbol2,tr2 ! { dg-error "PTB operand is a SHmedia symbol" }
 
.mode SHcompact
shcompact:
nop
nop
shcompactsymbol2:
nop
nop
shcompactsymbol1:
nop
nop
 
.mode SHmedia
shmedia:
nop
shmediasymbol2:
nop
ptb shmediasymbol3,tr3 ! { dg-error "PTB operand is a SHmedia symbol" }
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/abi-32.s
0,0 → 1,7
! Check successful .abi assertion for 32-bit ABI.
 
.text
.abi 32
.mode SHmedia
start:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/creg-1.s
0,0 → 1,79
! Test recognition of predefined control register names, lower and upper
! case; getcon and putcon. Exhaustive test in those domain is small and
! simple enough. Note that basic-1.s has already tested non-predefined
! register names.
 
.mode SHmedia
.text
start:
getcon sr,r21
getcon ssr,r31
getcon pssr,r22
getcon intevt,r21
getcon expevt,r21
getcon pexpevt,r21
getcon tra,r12
getcon spc,r21
getcon pspc,r41
getcon resvec,r21
getcon vbr,r19
getcon tea,r21
getcon dcr,r35
getcon kcr0,r21
getcon kcr1,r21
getcon ctc,r22
getcon usr,r21
 
getcon SR,r2
getcon SSR,r21
getcon PSSR,r21
getcon INTEVT,r21
getcon EXPEVT,r38
getcon PEXPEVT,r21
getcon TRA,r21
getcon SPC,r1
getcon PSPC,r21
getcon RESVEC,r21
getcon VBR,r47
getcon TEA,r21
getcon DCR,r21
getcon KCR0,r35
getcon KCR1,r21
getcon CTC,r21
getcon USR,r21
 
putcon r21,sr
putcon r31,ssr
putcon r22,pssr
putcon r21,intevt
putcon r21,expevt
putcon r21,pexpevt
putcon r12,tra
putcon r21,spc
putcon r41,pspc
putcon r21,resvec
putcon r19,vbr
putcon r21,tea
putcon r35,dcr
putcon r21,kcr0
putcon r21,kcr1
putcon r22,ctc
putcon r21,usr
 
putcon r2,SR
putcon r21,SSR
putcon r21,PSSR
putcon r21,INTEVT
putcon r38,EXPEVT
putcon r21,PEXPEVT
putcon r21,TRA
putcon r1,SPC
putcon r21,PSPC
putcon r21,RESVEC
putcon r47,VBR
putcon r21,TEA
putcon r21,DCR
putcon r35,KCR0
putcon r21,KCR1
putcon r21,CTC
putcon r21,USR
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel-3.s
0,0 → 1,137
! Like rel-1, but references are marked "datalabel".
 
.mode SHmedia
.text
start:
movi datalabel data1 - datalabel $,r10
movi (datalabel data2 - datalabel $) & 65535,r10
movi ((datalabel data3 - datalabel $) >> 0) & 65535,r10
movi ((datalabel data4 - datalabel $) >> 16) & 65535,r10
movi datalabel data5 + 8 - datalabel $,r10
movi (datalabel data6 + 16 - datalabel $) & 65535,r10
movi ((datalabel data7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((datalabel data8 + 4 - datalabel $) >> 16) & 65535,r10
 
movi datalabel othertext1 - datalabel $,r10
movi (datalabel othertext2 - datalabel $) & 65535,r10
movi ((datalabel othertext3 - datalabel $) >> 0) & 65535,r10
movi ((datalabel othertext4 - datalabel $) >> 16) & 65535,r10
movi datalabel othertext5 + 8 - datalabel $,r10
movi (datalabel othertext6 + 16 - datalabel $) & 65535,r10
movi ((datalabel othertext7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((datalabel othertext8 + 4 - datalabel $) >> 16) & 65535,r10
 
movi datalabel extern1 - datalabel $,r10
movi (datalabel extern2 - datalabel $) & 65535,r10
movi ((datalabel extern3 - datalabel $) >> 0) & 65535,r10
movi ((datalabel extern4 - datalabel $) >> 16) & 65535,r10
movi datalabel extern5 + 8 - datalabel $,r10
movi (datalabel extern6 + 16 - datalabel $) & 65535,r10
movi ((datalabel extern7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((datalabel extern8 + 4 - datalabel $) >> 16) & 65535,r10
 
movi datalabel gdata1 - datalabel $,r10
movi (datalabel gdata2 - datalabel $) & 65535,r10
movi ((datalabel gdata3 - datalabel $) >> 0) & 65535,r10
movi ((datalabel gdata4 - datalabel $) >> 16) & 65535,r10
movi datalabel gdata5 + 8 - datalabel $,r10
movi (datalabel gdata6 + 16 - datalabel $) & 65535,r10
movi ((datalabel gdata7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((datalabel gdata8 + 4 - datalabel $) >> 16) & 65535,r10
 
movi datalabel gothertext1 - datalabel $,r10
movi (datalabel gothertext2 - datalabel $) & 65535,r10
movi ((datalabel gothertext3 - datalabel $) >> 0) & 65535,r10
movi ((datalabel gothertext4 - datalabel $) >> 16) & 65535,r10
movi datalabel gothertext5 + 8 - datalabel $,r10
movi (datalabel gothertext6 + 16 - datalabel $) & 65535,r10
movi ((datalabel gothertext7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((datalabel gothertext8 + 4 - datalabel $) >> 16) & 65535,r10
 
.section .othertext,"ax"
x:
nop
othertext1:
nop
othertext2:
nop
othertext3:
nop
othertext4:
nop
othertext5:
nop
othertext6:
nop
othertext7:
nop
othertext8:
nop
.global gothertext1
gothertext1:
nop
.global gothertext2
gothertext2:
nop
.global gothertext3
gothertext3:
nop
.global gothertext4
gothertext4:
nop
.global gothertext5
gothertext5:
nop
.global gothertext6
gothertext6:
nop
.global gothertext7
gothertext7:
nop
.global gothertext8
gothertext8:
nop
 
.data
y:
.long 0
data1:
.long 0
data2:
.long 0
data3:
.long 0
data4:
.long 0
data5:
.long 0
data6:
.long 0
data7:
.long 0
data8:
.long 0
.global gdata1
gdata1:
.long 0
.global gdata2
gdata2:
.long 0
.global gdata3
gdata3:
.long 0
.global gdata4
gdata4:
.long 0
.global gdata5
gdata5:
.long 0
.global gdata6
gdata6:
.long 0
.global gdata7
gdata7:
.long 0
.global gdata8
gdata8:
.long 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err.exp
0,0 → 1,9
load_lib gas-dg.exp
dg-init
 
if [istarget sh64-*-*] then {
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/warn-*.s]] "" "--isa=SHmedia"
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/err-*.s]] "" "--isa=SHmedia"
}
 
dg-finish
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt64-32-1.d
0,0 → 1,27
#as: --isa=shmedia --abi=64 -expand-pt32
#objdump: -dr
#source: pt-1.s
#name: Basic SHmedia PT and PTA instructions with -expand-pt32.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
[0]+4 <start1>:
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
[0]+8 <start4>:
[ ]+8:[ ]+ebfffe50[ ]+pta/l 4 <start1>,tr5
[ ]+c:[ ]+6ff0fff0[ ]+nop
[ ]+10:[ ]+e8000a70[ ]+pta/l 18 <start2>,tr7
[ ]+14:[ ]+6ff0fff0[ ]+nop
 
[0]+18 <start2>:
[ ]+18:[ ]+e8000a40[ ]+pta/l 20 <start3>,tr4
[ ]+1c:[ ]+6ff0fff0[ ]+nop
 
[0]+20 <start3>:
[ ]+20:[ ]+ebffea30[ ]+pta/l 8 <start4>,tr3
[ ]+24:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange2-2.d
0,0 → 1,22
#as: --abi=32
#objdump: -sr
#source: crange2.s
#name: .cranges descriptors for SHcompact and SHmedia in .text.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.cranges\]:
 
OFFSET *TYPE *VALUE
0+0 R_SH_DIR32 \.text
0+a R_SH_DIR32 \.text
0+14 R_SH_DIR32 \.text
 
 
Contents of section \.text:
0000 e8000a30 ec001240 ec001250 6ff0fff0 .*
0010 00090009 00090009 00090009 00090009 .*
0020 00090009 effffa60 effffa70 ebffe200 .*
Contents of section .cranges:
0000 00000000 00000010 00030000 00100000 .*
0010 00140002 00000024 0000000c 0003 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptext-1.s
0,0 → 1,8
! PT, PTA, PTB expansion for external symbols.
start:
pt externalsym1 + 40,tr5
pta externalsym2 + 44,tr4
ptb externalsym3 + 48,tr3
pt/u externalsym4 + 52,tr5
pta/u externalsym5 + 56,tr4
ptb/u externalsym6 + 60,tr3
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-abi-32.s
0,0 → 1,10
! Check .abi pseudo assertion.
 
! { dg-do assemble }
! { dg-options "-abi=64" }
 
.text
.abi 32 ! { dg-error "options do not specify 32-bit ABI" }
 
start:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi64-1.d
0,0 → 1,44
#as: --isa=shmedia --abi=64
#objdump: -dr
#source: movi-1.s
#name: MOVI expansion, 64-bit ABI, 32-bit subset.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000030[ ]+movi 0,r3
[ ]+0:[ ]+R_SH_IMM_HI16 externalsym\+0x7b
[ ]+4:[ ]+c8000030[ ]+shori 0,r3
[ ]+4:[ ]+R_SH_IMM_MEDHI16 externalsym\+0x7b
[ ]+8:[ ]+c8000030[ ]+shori 0,r3
[ ]+8:[ ]+R_SH_IMM_MEDLOW16 externalsym\+0x7b
[ ]+c:[ ]+c8000030[ ]+shori 0,r3
[ ]+c:[ ]+R_SH_IMM_LOW16 externalsym\+0x7b
[ ]+10:[ ]+cc000030[ ]+movi 0,r3
[ ]+14:[ ]+cbfffc30[ ]+shori 65535,r3
[ ]+18:[ ]+cc000430[ ]+movi 1,r3
[ ]+1c:[ ]+c8000030[ ]+shori 0,r3
[ ]+20:[ ]+cc000030[ ]+movi 0,r3
[ ]+24:[ ]+cbfffc30[ ]+shori 65535,r3
[ ]+28:[ ]+c8000030[ ]+shori 0,r3
[ ]+2c:[ ]+cdfffc30[ ]+movi 32767,r3
[ ]+30:[ ]+cc000030[ ]+movi 0,r3
[ ]+34:[ ]+ca000030[ ]+shori 32768,r3
[ ]+38:[ ]+cdfffc30[ ]+movi 32767,r3
[ ]+3c:[ ]+c8000030[ ]+shori 0,r3
[ ]+40:[ ]+ce000030[ ]+movi -32768,r3
[ ]+44:[ ]+cffffc30[ ]+movi -1,r3
[ ]+48:[ ]+c9fffc30[ ]+shori 32767,r3
[ ]+4c:[ ]+ce000030[ ]+movi -32768,r3
[ ]+50:[ ]+c8000030[ ]+shori 0,r3
[ ]+54:[ ]+cc000040[ ]+movi 0,r4
[ ]+54:[ ]+R_SH_IMM_HI16 \.data\+0x49
[ ]+58:[ ]+c8000040[ ]+shori 0,r4
[ ]+58:[ ]+R_SH_IMM_MEDHI16 \.data\+0x49
[ ]+5c:[ ]+c8000040[ ]+shori 0,r4
[ ]+5c:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x49
[ ]+60:[ ]+c8000040[ ]+shori 0,r4
[ ]+60:[ ]+R_SH_IMM_LOW16 \.data\+0x49
[ ]+64:[ ]+cc001440[ ]+movi 5,r4
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ua-1.s
0,0 → 1,16
! Check that unaligned pseudos emit the expected relocs and contents
! whether aligned or not.
 
.section .rodata,"a"
start:
.uaquad 0x123456789abcdef
.byte 42
.uaword 0x4a21
.ualong 0x43b1abcd
.ualong externsym0 + 3
.uaquad 0x12c456d89ab1d0f
.uaquad externsym1 + 41
.byte 2
.uaquad 0x1a34b67c9ab0d4f
.ualong externsym2 + 42
.uaquad externsym3 + 43
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/lineno.d
0,0 → 1,19
#as: --abi=32 --isa=shmedia -gdwarf2
#objdump: -dl
#source: lineno.s
#name: Dwarf2 line numbers vs macro opcodes
 
.*: file format .*-sh64.*
 
Disassembly of section .text:
 
[0]+ <start>:
start.*:
[ ]+0:[ ]+cc000410[ ]+movi[ ]+1,r1
.*:4
[ ]+4:[ ]+cc000410[ ]+movi[ ]+1,r1
.*:5
[ ]+8:[ ]+ca1a8010[ ]+shori[ ]+34464,r1
[ ]+c:[ ]+6ff0fff0[ ]+nop[ ]*
.*:6
[ ]+10:[ ]+6ff0fff0[ ]+nop[ ]*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift64-2.d
0,0 → 1,42
#as: --abi=64
#objdump: -dr
#source: shift-2.s
#name: Shift expressions, 64-bit ABI, 64-bit subset.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000040[ ]+movi 0,r4
[ ]+0:[ ]+R_SH_IMM_MEDHI16 \.data\+0x4
[ ]+4:[ ]+cc000040[ ]+movi 0,r4
[ ]+4:[ ]+R_SH_IMM_HI16 \.data\+0x4
[ ]+8:[ ]+cc000040[ ]+movi 0,r4
[ ]+8:[ ]+R_SH_IMM_MEDHI16 \.data\+0x30
[ ]+c:[ ]+cc000040[ ]+movi 0,r4
[ ]+c:[ ]+R_SH_IMM_HI16 \.data\+0x2f
[ ]+10:[ ]+cc000040[ ]+movi 0,r4
[ ]+10:[ ]+R_SH_IMM_MEDHI16 externsym
[ ]+14:[ ]+cc000040[ ]+movi 0,r4
[ ]+14:[ ]+R_SH_IMM_HI16 externsym
[ ]+18:[ ]+cc000040[ ]+movi 0,r4
[ ]+18:[ ]+R_SH_IMM_MEDHI16 externsym\+0x29
[ ]+1c:[ ]+cc000040[ ]+movi 0,r4
[ ]+1c:[ ]+R_SH_IMM_HI16 externsym\+0x2a
[ ]+20:[ ]+c8000040[ ]+shori 0,r4
[ ]+20:[ ]+R_SH_IMM_MEDHI16 \.data\+0x4
[ ]+24:[ ]+c8000040[ ]+shori 0,r4
[ ]+24:[ ]+R_SH_IMM_HI16 \.data\+0x4
[ ]+28:[ ]+c8000040[ ]+shori 0,r4
[ ]+28:[ ]+R_SH_IMM_MEDHI16 \.data\+0x30
[ ]+2c:[ ]+c8000040[ ]+shori 0,r4
[ ]+2c:[ ]+R_SH_IMM_HI16 \.data\+0x2f
[ ]+30:[ ]+c8000040[ ]+shori 0,r4
[ ]+30:[ ]+R_SH_IMM_MEDHI16 externsym
[ ]+34:[ ]+c8000040[ ]+shori 0,r4
[ ]+34:[ ]+R_SH_IMM_HI16 externsym
[ ]+38:[ ]+c8000040[ ]+shori 0,r4
[ ]+38:[ ]+R_SH_IMM_MEDHI16 externsym\+0x29
[ ]+3c:[ ]+c8000040[ ]+shori 0,r4
[ ]+3c:[ ]+R_SH_IMM_HI16 externsym\+0x2a
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-pt-1.s
0,0 → 1,18
! Check that we get errors for a PT operand out of range with -no-relax.
 
! { dg-do assemble }
! { dg-options "--abi=32 --no-expand" }
 
.mode SHmedia
start:
nop
start2:
pt x0,tr3 ! { dg-error "operand out of range" }
x1:
pt x0,tr4
.space 32767*4-4,0
x0:
pt x1,tr5
pt x1,tr6
pt x1,tr6 ! { dg-error "operand out of range" }
pt x1,tr7 ! { dg-error "operand out of range" }
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/localcom-1.d
0,0 → 1,30
#as: --abi=32
#objdump: -srt
#source: localcom-1.s
#name: Datalabel on local comm symbol and equated local comm symbol
 
.*: file format .*-sh64.*
 
SYMBOL TABLE:
0+0 l d \.text 0+ (|\.text)
0+0 l d \.data 0+ (|\.data)
0+0 l d \.bss 0+ (|\.bss)
0+0 l \.text 0+ start
0+c l O \.bss 0+4 dd
0+c l O \.bss 0+4 d
0+4 l O \.bss 0+4 b
0+0 l O \.bss 0+4 a
0+8 l O \.bss 0+4 c
 
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET *TYPE *VALUE
0+10 R_SH_DIR32 \.bss
0+14 R_SH_DIR32 \.bss
0+18 R_SH_DIR32 \.bss
 
 
Contents of section \.text:
0000 00090009 00090009 00090009 00090009 .*
0010 00000004 00000004 0000000c 12340009 .*
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel64-4.d
0,0 → 1,111
#as: --abi=64
#objdump: -sr
#source: rel-4.s
#name: MOVI: PC+1-relative datalabel relocs, 64-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET TYPE VALUE
0+10 R_SH_IMM_LOW16_PCREL \.data\+0x0+7
0+14 R_SH_IMM_LOW16_PCREL \.data\+0x0+b
0+18 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+f
0+2c R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+30 R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+34 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+23
0+48 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+7
0+4c R_SH_IMM_LOW16_PCREL \.othertext\+0x0+b
0+50 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+f
0+64 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+27
0+68 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+27
0+6c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+23
0+80 R_SH_IMM_LOW16_PCREL extern2\+0xffffffffffffffff
0+84 R_SH_IMM_LOW16_PCREL extern3\+0xffffffffffffffff
0+88 R_SH_IMM_MEDLOW16_PCREL extern4\+0xffffffffffffffff
0+9c R_SH_IMM_LOW16_PCREL extern6\+0x0+f
0+a0 R_SH_IMM_LOW16_PCREL extern7\+0x0+b
0+a4 R_SH_IMM_MEDLOW16_PCREL extern8\+0x0+3
0+b8 R_SH_IMM_LOW16_PCREL gdata2\+0xffffffffffffffff
0+bc R_SH_IMM_LOW16_PCREL gdata3\+0xffffffffffffffff
0+c0 R_SH_IMM_MEDLOW16_PCREL gdata4\+0xffffffffffffffff
0+d4 R_SH_IMM_LOW16_PCREL gdata6\+0x0+f
0+d8 R_SH_IMM_LOW16_PCREL gdata7\+0x0+b
0+dc R_SH_IMM_MEDLOW16_PCREL gdata8\+0x0+3
0+f0 R_SH_IMM_LOW16_PCREL gothertext2\+0xffffffffffffffff
0+f4 R_SH_IMM_LOW16_PCREL gothertext3\+0xffffffffffffffff
0+f8 R_SH_IMM_MEDLOW16_PCREL gothertext4\+0xffffffffffffffff
0+10c R_SH_IMM_LOW16_PCREL gothertext6\+0x0+f
0+110 R_SH_IMM_LOW16_PCREL gothertext7\+0x0+b
0+114 R_SH_IMM_MEDLOW16_PCREL gothertext8\+0x0+3
0+ R_SH_IMM_HI16_PCREL \.data\+0x0+3
0+4 R_SH_IMM_MEDHI16_PCREL \.data\+0x0+7
0+8 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+b
0+c R_SH_IMM_LOW16_PCREL \.data\+0x0+f
0+1c R_SH_IMM_HI16_PCREL \.data\+0x0+1b
0+20 R_SH_IMM_MEDHI16_PCREL \.data\+0x0+1f
0+24 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+23
0+28 R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+38 R_SH_IMM_HI16_PCREL \.othertext\+0x0+3
0+3c R_SH_IMM_MEDHI16_PCREL \.othertext\+0x0+7
0+40 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+b
0+44 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+f
0+54 R_SH_IMM_HI16_PCREL \.othertext\+0x0+1b
0+58 R_SH_IMM_MEDHI16_PCREL \.othertext\+0x0+1f
0+5c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+23
0+60 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+27
0+70 R_SH_IMM_HI16_PCREL extern1\+0xffffffffffffffff
0+74 R_SH_IMM_MEDHI16_PCREL extern1\+0x0+3
0+78 R_SH_IMM_MEDLOW16_PCREL extern1\+0x0+7
0+7c R_SH_IMM_LOW16_PCREL extern1\+0x0+b
0+8c R_SH_IMM_HI16_PCREL extern5\+0x0+7
0+90 R_SH_IMM_MEDHI16_PCREL extern5\+0x0+b
0+94 R_SH_IMM_MEDLOW16_PCREL extern5\+0x0+f
0+98 R_SH_IMM_LOW16_PCREL extern5\+0x0+13
0+a8 R_SH_IMM_HI16_PCREL gdata1\+0xffffffffffffffff
0+ac R_SH_IMM_MEDHI16_PCREL gdata1\+0x0+3
0+b0 R_SH_IMM_MEDLOW16_PCREL gdata1\+0x0+7
0+b4 R_SH_IMM_LOW16_PCREL gdata1\+0x0+b
0+c4 R_SH_IMM_HI16_PCREL gdata5\+0x0+7
0+c8 R_SH_IMM_MEDHI16_PCREL gdata5\+0x0+b
0+cc R_SH_IMM_MEDLOW16_PCREL gdata5\+0x0+f
0+d0 R_SH_IMM_LOW16_PCREL gdata5\+0x0+13
0+e0 R_SH_IMM_HI16_PCREL gothertext1\+0xffffffffffffffff
0+e4 R_SH_IMM_MEDHI16_PCREL gothertext1\+0x0+3
0+e8 R_SH_IMM_MEDLOW16_PCREL gothertext1\+0x0+7
0+ec R_SH_IMM_LOW16_PCREL gothertext1\+0x0+b
0+fc R_SH_IMM_HI16_PCREL gothertext5\+0x0+7
0+100 R_SH_IMM_MEDHI16_PCREL gothertext5\+0x0+b
0+104 R_SH_IMM_MEDLOW16_PCREL gothertext5\+0x0+f
0+108 R_SH_IMM_LOW16_PCREL gothertext5\+0x0+13
 
Contents of section \.text:
0000 cc0000a0 c80000a0 c80000a0 c80000a0 .*
0010 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0020 c80000a0 c80000a0 c80000a0 cc0000a0 .*
0030 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0040 c80000a0 c80000a0 cc0000a0 cc0000a0 .*
0050 cc0000a0 cc0000a0 c80000a0 c80000a0 .*
0060 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
0070 cc0000a0 c80000a0 c80000a0 c80000a0 .*
0080 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0090 c80000a0 c80000a0 c80000a0 cc0000a0 .*
00a0 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
00b0 c80000a0 c80000a0 cc0000a0 cc0000a0 .*
00c0 cc0000a0 cc0000a0 c80000a0 c80000a0 .*
00d0 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
00e0 cc0000a0 c80000a0 c80000a0 c80000a0 .*
00f0 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0100 c80000a0 c80000a0 c80000a0 cc0000a0 .*
0110 cc0000a0 cc0000a0 .*
Contents of section \.data:
0000 00000000 00000000 00000000 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 00000000 00000000 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 .*
Contents of section \.othertext:
0000 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0040 6ff0fff0 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange3.s
0,0 → 1,34
! There was a bug in which a .cranges data hunk could include a hunk of
! code in front of it. The following illustrates a function (start)
! followed by constants output into .rodata, followed by a function
! (continue), with a case-table (.L173) in it. The bug included code from
! the start of the function (continue) into the case-table range descriptor.
 
.text
.mode SHmedia
start:
nop
.section .rodata
.long 0xabcdef01
.long 0x12345678
.text
continue:
nop
nop
nop
.align 2
.align 2
.L173:
.word 0x0123
.word 0x5678
.word 0x1234
.word 0x5678
.word 0x1234
.word 0x5678
.word 0x1234
.word 0xfede
nop
nop
nop
nop
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/datal-1.s
0,0 → 1,41
! Check "datalabel" qualifier.
! This is the most simple use; references to local symbols where it is
! completely redundant. Code tests are for SHmedia mode.
 
.mode SHmedia
.text
start:
movi datalabel foo,r3
movi DataLabel foo2 + 42,r3
movi (datalabel (foo3 + 46) >> 16) & 65535,r3
movi datalabel myrodata3 & 65535, r45
movi datalabel myrodata4 & 65535, r45
movi DATALABEL (myrodata2 + 50) & 65535, r45
 
.section .rodata
.long datalabel foo4
myrodata1:
.long DATALABEL foo5 + 56
myrodata2:
.long datalabel $
.global myrodata3
myrodata3:
.long datalabel $+20
myrodata4:
.long datalabel myrodata1+0x100
 
.data
.long datalabel myrodata1
foo:
.long DATALABEL myrodata2+30
foo2:
.long DataLabel foo
foo3:
.long datalabel $
foo4:
.long datalabel $+40
foo5:
.long datalabel myrodata3
.global foo6
foo6:
.long datalabel foo6 + 42
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/lineno.s
0,0 → 1,7
.text
 
start:
movi 1,r1
movi 100000,r1
nop
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange2-noexp-1.d
0,0 → 1,43
#as: --abi=32 -no-expand
#objdump: -dr
#source: crange2.s
#name: PT to SHcompact with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <shmedia>:
[ ]+0:[ ]+e8000a30[ ]+pta/l 8 <shmedia1>,tr3
[ ]+4:[ ]+ec001240[ ]+ptb/l 14 <shcompact1>,tr4
 
0+8 <shmedia1>:
[ ]+8:[ ]+ec001250[ ]+ptb/l 18 <shcompact2>,tr5
 
0+c <shmedia2>:
[ ]+c:[ ]+6ff0fff0[ ]+nop
 
0+10[ ]+<shcompact>:
[ ]+10:[ ]+00[ ]+09[ ]+nop
[ ]+12:[ ]+00[ ]+09[ ]+nop
 
0+14 <shcompact1>:
[ ]+14:[ ]+00[ ]+09[ ]+nop
[ ]+16:[ ]+00[ ]+09[ ]+nop
 
0+18 <shcompact2>:
[ ]+18:[ ]+00[ ]+09[ ]+nop
[ ]+1a:[ ]+00[ ]+09[ ]+nop
 
0+1c <shcompact3>:
[ ]+1c:[ ]+00[ ]+09[ ]+nop
[ ]+1e:[ ]+00[ ]+09[ ]+nop
 
0+20[ ]+<shcompact4>:
[ ]+20:[ ]+00[ ]+09[ ]+nop
[ ]+22:[ ]+00[ ]+09[ ]+nop
 
0+24 <shmedia3>:
[ ]+24:[ ]+effffa60[ ]+ptb/l 1c <shcompact3>,tr6
[ ]+28:[ ]+effffa70[ ]+ptb/l 20[ ]+<shcompact4>,tr7
[ ]+2c:[ ]+ebffe200[ ]+pta/l c <shmedia2>,tr0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-2.s
0,0 → 1,16
! { dg-do assemble }
! { dg-options "--abi=32 --isa=shmedia" }
!
 
! This is a mainly a copy of movi64-2.s, but we check that out-of-range
! errors are emitted for the 32-bit ABI.
.text
start:
movi 65536 << 16,r3 ! { dg-error "not a 32-bit signed value" }
movi -32769 << 16,r3 ! { dg-error "not a 32-bit signed value" }
movi 32768 << 16,r3
movi -32768 << 16,r3
movi 32767 << 48,r3 ! { dg-error "not a 32-bit signed value" }
movi 32768 << 48,r3 ! { dg-error "not a 32-bit signed value" }
movi -32768 << 48,r3 ! { dg-error "not a 32-bit signed value" }
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/localcom-1.s
0,0 → 1,26
! The implicit equation from a datalabel to the main symbol was incorrect
! at one time. This is reasonably close to the original testcase.
 
.mode SHcompact
start:
nop
nop
nop
nop
nop
nop
nop
nop
.set dd,d
.long b
.long datalabel b
.long datalabel dd
.word 0x1234
.local a
.comm a,4,4
.local b
.comm b,4,4
.local c
.comm c,4,4
.local d
.comm d,4,4
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/relax-3.d
0,0 → 1,43
#as: --abi=64
#objdump: -dr
#source: relax-3.s
#name: Assembler PC-rel MOVI relaxation limit, from first to second state.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start2>:
[ ]+4:[ ]+cc000030[ ]+movi 0,r3
[ ]+8:[ ]+ca001030[ ]+shori 32772,r3
 
0+c <x1>:
[ ]+c:[ ]+cdfffc40[ ]+movi 32767,r4
[ ]+\.\.\.
 
0+800c <x0>:
[ ]+800c:[ ]+ce000050[ ]+movi -32768,r5
[ ]+8010:[ ]+cffffc60[ ]+movi -1,r6
[ ]+8014:[ ]+c9fffc60[ ]+shori 32767,r6
[ ]+8018:[ ]+cffffc70[ ]+movi -1,r7
[ ]+801c:[ ]+cbfffc70[ ]+shori 65535,r7
[ ]+8020:[ ]+cbfffc70[ ]+shori 65535,r7
[ ]+8024:[ ]+ca000070[ ]+shori 32768,r7
[ ]+8028:[ ]+cc000080[ ]+movi 0,r8
[ ]+802c:[ ]+c8000080[ ]+shori 0,r8
[ ]+8030:[ ]+c8000080[ ]+shori 0,r8
[ ]+8034:[ ]+c9fffc80[ ]+shori 32767,r8
[ ]+8038:[ ]+cc000080[ ]+movi 0,r8
[ ]+803c:[ ]+c8000080[ ]+shori 0,r8
[ ]+8040:[ ]+c8000080[ ]+shori 0,r8
[ ]+8044:[ ]+c8004080[ ]+shori 16,r8
Disassembly of section \.text\.another:
 
0+ <y0>:
[ ]+0:[ ]+cc000090[ ]+movi 0,r9
[ ]+4:[ ]+c8000090[ ]+shori 0,r9
[ ]+8:[ ]+c8000090[ ]+shori 0,r9
[ ]+c:[ ]+c8002090[ ]+shori 8,r9
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi32-1.d
0,0 → 1,35
#as: --isa=shmedia --abi=32
#objdump: -dr
#source: movi-1.s
#name: MOVI expansion, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000030[ ]+movi 0,r3
[ ]+0:[ ]+R_SH_IMM_MEDLOW16 externalsym\+0x7b
[ ]+4:[ ]+c8000030[ ]+shori 0,r3
[ ]+4:[ ]+R_SH_IMM_LOW16 externalsym\+0x7b
[ ]+8:[ ]+cc000030[ ]+movi 0,r3
[ ]+c:[ ]+cbfffc30[ ]+shori 65535,r3
[ ]+10:[ ]+cc000430[ ]+movi 1,r3
[ ]+14:[ ]+c8000030[ ]+shori 0,r3
[ ]+18:[ ]+cffffc30[ ]+movi -1,r3
[ ]+1c:[ ]+c8000030[ ]+shori 0,r3
[ ]+20:[ ]+cdfffc30[ ]+movi 32767,r3
[ ]+24:[ ]+cc000030[ ]+movi 0,r3
[ ]+28:[ ]+ca000030[ ]+shori 32768,r3
[ ]+2c:[ ]+cdfffc30[ ]+movi 32767,r3
[ ]+30:[ ]+c8000030[ ]+shori 0,r3
[ ]+34:[ ]+ce000030[ ]+movi -32768,r3
[ ]+38:[ ]+cffffc30[ ]+movi -1,r3
[ ]+3c:[ ]+c9fffc30[ ]+shori 32767,r3
[ ]+40:[ ]+ce000030[ ]+movi -32768,r3
[ ]+44:[ ]+c8000030[ ]+shori 0,r3
[ ]+48:[ ]+cc000040[ ]+movi 0,r4
[ ]+48:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x49
[ ]+4c:[ ]+c8000040[ ]+shori 0,r4
[ ]+4c:[ ]+R_SH_IMM_LOW16 \.data\+0x49
[ ]+50:[ ]+cc001440[ ]+movi 5,r4
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift64-noexp-3.d
0,0 → 1,14
#as: --abi=64 -no-expand
#objdump: -dr
#source: shift-3.s
#name: Shift expression, local but undefined symbol, 64-bit ABI with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000010[ ]+movi 0,r1
[ ]+0:[ ]+R_SH_IMM_LOW16 \.LC0
[ ]+4:[ ]+cc000030[ ]+movi 0,r3
[ ]+4:[ ]+R_SH_IMM_MEDLOW16 \.LC0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/creg-2.d
0,0 → 1,17
#as: --abi=32
#objdump: -dr
#name: Predefined control register names specified in crN syntax.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+240ffd50[ ]+getcon sr,r21
[ ]+4:[ ]+24dffd50[ ]+getcon tea,r21
[ ]+8:[ ]+27effd60[ ]+getcon ctc,r22
[ ]+c:[ ]+248ffd50[ ]+getcon spc,r21
[ ]+10:[ ]+244ffd50[ ]+getcon intevt,r21
[ ]+14:[ ]+6d3ffcb0[ ]+putcon r19,vbr
[ ]+18:[ ]+6e6ffc50[ ]+putcon r38,expevt
[ ]+1c:[ ]+6d5ffc10[ ]+putcon r21,ssr
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt64-noexp-2.d
0,0 → 1,34
#as: --isa=shmedia -abi=64 -no-expand
#objdump: -dr
#source: pt-2.s
#name: Inter-segment PT, 64-bit with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
0+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start1>:
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
0+8 <start4>:
[ ]+8:[ ]+ebfffe50[ ]+pta/l 4 <start1>,tr5
[ ]+c:[ ]+6ff0fff0[ ]+nop
[ ]+10:[ ]+e8000270[ ]+pta/l 10 <start4\+0x8>,tr7
[ ]+10:[ ]+R_SH_PT_16 \.text\.other\+0x5
[ ]+14:[ ]+6ff0fff0[ ]+nop
 
Disassembly of section \.text\.other:
 
0+ <dummylabel>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start2>:
[ ]+4:[ ]+e8000a40[ ]+pta/l c <start3>,tr4
[ ]+8:[ ]+6ff0fff0[ ]+nop
 
0+c <start3>:
[ ]+c:[ ]+e8000630[ ]+pta/l 10 <start3\+0x4>,tr3
[ ]+c:[ ]R_SH_PT_16 \.text\+0x9
[ ]+10:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi-1.s
0,0 → 1,20
! Check MOVI expansion. This one for the 32-bit subset.
.text
start:
movi externalsym + 123,r3
movi 65535,r3
movi 65536,r3
movi 65535 << 16,r3
movi 32767,r3
movi 32768,r3
movi 32767 << 16,r3
movi -32768,r3
movi -32769,r3
movi -32768 << 16,r3
movi localsym + 73,r4
movi forwardsym - 42,r4
.set forwardsym,47
 
.data
localsym:
.long 1
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel32-4.d
0,0 → 1,86
#as: --abi=32
#objdump: -sr
#source: rel-4.s
#name: MOVI: PC+1-relative datalabel relocs, 32-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET *TYPE *VALUE
0+8 R_SH_IMM_LOW16_PCREL \.data\+0x0+7
0+c R_SH_IMM_LOW16_PCREL \.data\+0x0+b
0+10 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+f
0+1c R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+20 R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+24 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+23
0+30 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+7
0+34 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+b
0+38 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+f
0+44 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+27
0+48 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+27
0+4c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+23
0+58 R_SH_IMM_LOW16_PCREL extern2\+0xf*ffffffff
0+5c R_SH_IMM_LOW16_PCREL extern3\+0xf*ffffffff
0+60 R_SH_IMM_MEDLOW16_PCREL extern4\+0xf*ffffffff
0+6c R_SH_IMM_LOW16_PCREL extern6\+0x0+f
0+70 R_SH_IMM_LOW16_PCREL extern7\+0x0+b
0+74 R_SH_IMM_MEDLOW16_PCREL extern8\+0x0+3
0+80 R_SH_IMM_LOW16_PCREL gdata2\+0xf*ffffffff
0+84 R_SH_IMM_LOW16_PCREL gdata3\+0xf*ffffffff
0+88 R_SH_IMM_MEDLOW16_PCREL gdata4\+0xf*ffffffff
0+94 R_SH_IMM_LOW16_PCREL gdata6\+0x0+f
0+98 R_SH_IMM_LOW16_PCREL gdata7\+0x0+b
0+9c R_SH_IMM_MEDLOW16_PCREL gdata8\+0x0+3
0+a8 R_SH_IMM_LOW16_PCREL gothertext2\+0xf*ffffffff
0+ac R_SH_IMM_LOW16_PCREL gothertext3\+0xf*ffffffff
0+b0 R_SH_IMM_MEDLOW16_PCREL gothertext4\+0xf*ffffffff
0+bc R_SH_IMM_LOW16_PCREL gothertext6\+0x0+f
0+c0 R_SH_IMM_LOW16_PCREL gothertext7\+0x0+b
0+c4 R_SH_IMM_MEDLOW16_PCREL gothertext8\+0x0+3
0+ R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+3
0+4 R_SH_IMM_LOW16_PCREL \.data\+0x0+7
0+14 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+1b
0+18 R_SH_IMM_LOW16_PCREL \.data\+0x0+1f
0+28 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+3
0+2c R_SH_IMM_LOW16_PCREL \.othertext\+0x0+7
0+3c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+1b
0+40 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+1f
0+50 R_SH_IMM_MEDLOW16_PCREL extern1\+0xf*ffffffff
0+54 R_SH_IMM_LOW16_PCREL extern1\+0x0+3
0+64 R_SH_IMM_MEDLOW16_PCREL extern5\+0x0+7
0+68 R_SH_IMM_LOW16_PCREL extern5\+0x0+b
0+78 R_SH_IMM_MEDLOW16_PCREL gdata1\+0xf*ffffffff
0+7c R_SH_IMM_LOW16_PCREL gdata1\+0x0+3
0+8c R_SH_IMM_MEDLOW16_PCREL gdata5\+0x0+7
0+90 R_SH_IMM_LOW16_PCREL gdata5\+0x0+b
0+a0 R_SH_IMM_MEDLOW16_PCREL gothertext1\+0xf*ffffffff
0+a4 R_SH_IMM_LOW16_PCREL gothertext1\+0x0+3
0+b4 R_SH_IMM_MEDLOW16_PCREL gothertext5\+0x0+7
0+b8 R_SH_IMM_LOW16_PCREL gothertext5\+0x0+b
 
Contents of section \.text:
0000 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
0010 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
0020 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0030 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0040 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
0050 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
0060 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
0070 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0080 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0090 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
00a0 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
00b0 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
00c0 cc0000a0 cc0000a0 .*
Contents of section \.data:
0000 00000000 00000000 00000000 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 00000000 00000000 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 .*
Contents of section \.othertext:
0000 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0040 6ff0fff0 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift-1.s
0,0 → 1,42
! Check that shift expressions translate to the proper reloc for MOVI and
! SHORI for local and external symbols. This is the 32-bit subset.
.text
.mode SHmedia
start:
movi localsym & 65535,r4
movi (localsym >> 0) & 65535,r4
movi (localsym >> 16) & 65535,r4
 
movi externsym & 65535,r4
movi (externsym >> 0) & 65535,r4
movi (externsym >> 16) & 65535,r4
 
shori localsym & 65535,r4
shori (localsym >> 0) & 65535,r4
shori (localsym >> 16) & 65535,r4
 
shori externsym & 65535,r4
shori (externsym >> 0) & 65535,r4
shori (externsym >> 16) & 65535,r4
 
movi (localsym + 42) & 65535,r4
movi ((localsym + 43) >> 0) & 65535,r4
movi ((localsym + 44) >> 16) & 65535,r4
 
movi (externsym + 45) & 65535,r4
movi ((externsym + 46) >> 0) & 65535,r4
movi ((externsym + 47) >> 16) & 65535,r4
 
shori (localsym + 42) & 65535,r4
shori ((localsym + 43) >> 0) & 65535,r4
shori ((localsym + 44) >> 16) & 65535,r4
 
shori (externsym + 45) & 65535,r4
shori ((externsym + 46) >> 0) & 65535,r4
shori ((externsym + 47) >> 16) & 65535,r4
 
.data
! Just make localsym have a non-zero offset into .data.
.long 0
localsym:
.long 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/relax-3.s
0,0 → 1,32
! Check relaxation for MOVI PC-relative expansions. Unfortunately, we
! can't check the 32 and 48 bit limit on a host with 32-bit longs, so we
! just check going from first state to the second state.
 
.mode SHmedia
.text
start:
nop
start2:
movi (x0-4-$),r3
x1:
movi (x0-1-$),r4
.space 32768-4,0
x0:
movi (x1-$),r5
movi (x1+3-$),r6
 
! These PC-relative expressions are here because of past bugs leading to
! premature symbol evaluation and assignment when they were exposed to
! relaxation.
! The expected result may need future tweaking if advances are done in
! relaxation. At the time of this writing the expressions are not
! relaxed although the numbers will be in the right range finally.
 
movi (x1-x0),r7
movi (x0-1-x1),r8
movi (y1-y0),r8
 
.section .text.another,"ax"
y0:
movi (x1-start2),r9
y1:
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/mix-1.d
0,0 → 1,42
#as: --abi=32
#objdump: -dr
#name: Mixed-ISA objects.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <start>:
[ ]+0:[ ]+89 01 bt 6 <forw>
[ ]+2:[ ]+c7 00[ ]+mova 4 <start2>,r0
 
0+4 <start2>:
[ ]+4:[ ]+00[ ]+09 nop
 
0+6 <forw>:
[ ]+6:[ ]+00[ ]+09 nop
Disassembly of section \.text\.media:
 
0+ <mediacode>:
[ ]+0:[ ]+cc000190[ ]+movi 0,r25
[ ]+0:[ ]+R_SH_IMM_MEDLOW16_PCREL \.text\+0xf*fffffffe
[ ]+4:[ ]+c8000190[ ]+shori 0,r25
[ ]+4:[ ]+R_SH_IMM_LOW16_PCREL \.text\+0x2
[ ]+8:[ ]+6bf56640[ ]+ptrel/l r25,tr4
[ ]+c:[ ]+cc000190[ ]+movi 0,r25
[ ]+c:[ ]+R_SH_IMM_MEDLOW16_PCREL \.text\+0xf*fffffffc
[ ]+10:[ ]+c8000190[ ]+shori 0,r25
[ ]+10:[ ]+R_SH_IMM_LOW16_PCREL \.text
[ ]+14:[ ]+6bf56650[ ]+ptrel/l r25,tr5
 
0+18 <mediacode2>:
[ ]+18:[ ]+cc000360[ ]+movi 0,r54
[ ]+18:[ ]+R_SH_IMM_MEDLOW16 \.text\+0x4
[ ]+1c:[ ]+c8000360[ ]+shori 0,r54
[ ]+1c:[ ]+R_SH_IMM_LOW16 \.text\+0x4
[ ]+20:[ ]+cc0002d0[ ]+movi 0,r45
[ ]+20:[ ]+R_SH_IMM_MEDLOW16 \.text\.media\+0x19
[ ]+24:[ ]+c80002d0[ ]+shori 0,r45
[ ]+24:[ ]+R_SH_IMM_LOW16 \.text\.media\+0x19
[ ]+28:[ ]+ebfff270[ ]+pta/l 18 <mediacode2>,tr7
[ ]+2c:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/creg-2.s
0,0 → 1,14
! Test recognition of predefined control register names specified as crN
! syntax, lower and upper case.
 
.mode SHmedia
.text
start:
getcon cr0,r21
getcon cr13,r21
getcon CR62,r22
getcon cr8,r21
getcon CR4,r21
putcon r19,cr11
putcon r38,CR5
putcon r21,CR1
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptext64-32-1.d
0,0 → 1,40
#as: --isa=shmedia --abi=64 -expand-pt32
#source: ptext-1.s
#objdump: -dr
#name: PT, PTA, PTB expansion for external symbols, 64-bit ABI with -expand-pt32.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000190[ ]+movi 0,r25
[ ]+0:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym1\+0x20
[ ]+4:[ ]+c8000190[ ]+shori 0,r25
[ ]+4:[ ]+R_SH_IMM_LOW16_PCREL externalsym1\+0x24
[ ]+8:[ ]+6bf56650[ ]+ptrel/l r25,tr5
[ ]+c:[ ]+cc000190[ ]+movi 0,r25
[ ]+c:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym2\+0x24
[ ]+10:[ ]+c8000190[ ]+shori 0,r25
[ ]+10:[ ]+R_SH_IMM_LOW16_PCREL externalsym2\+0x28
[ ]+14:[ ]+6bf56640[ ]+ptrel/l r25,tr4
[ ]+18:[ ]+cc000190[ ]+movi 0,r25
[ ]+18:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym3\+0x28
[ ]+1c:[ ]+c8000190[ ]+shori 0,r25
[ ]+1c:[ ]+R_SH_IMM_LOW16_PCREL externalsym3\+0x2c
[ ]+20:[ ]+6bf56630[ ]+ptrel/l r25,tr3
[ ]+24:[ ]+cc000190[ ]+movi 0,r25
[ ]+24:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym4\+0x2c
[ ]+28:[ ]+c8000190[ ]+shori 0,r25
[ ]+28:[ ]+R_SH_IMM_LOW16_PCREL externalsym4\+0x30
[ ]+2c:[ ]+6bf56450[ ]+ptrel/u r25,tr5
[ ]+30:[ ]+cc000190[ ]+movi 0,r25
[ ]+30:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym5\+0x30
[ ]+34:[ ]+c8000190[ ]+shori 0,r25
[ ]+34:[ ]+R_SH_IMM_LOW16_PCREL externalsym5\+0x34
[ ]+38:[ ]+6bf56440[ ]+ptrel/u r25,tr4
[ ]+3c:[ ]+cc000190[ ]+movi 0,r25
[ ]+3c:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym6\+0x34
[ ]+40:[ ]+c8000190[ ]+shori 0,r25
[ ]+40:[ ]+R_SH_IMM_LOW16_PCREL externalsym6\+0x38
[ ]+44:[ ]+6bf56430[ ]+ptrel/u r25,tr3
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/datal64-3.d
0,0 → 1,123
#as: --abi=64
#objdump: -xsr
#source: datal-3.s
#name: DataLabel local def/use, SHmedia 64-bit ABI
 
# We should have the st_type field of each symbol displayed too, so we can
# check that STT_DATALABEL is set, but objdump doesn't do that at present,
# and readelf isn't supported as a run_dump_test tool.
 
.*: file format .*-sh64.*
.*
architecture: sh5, flags 0x0+11:
HAS_RELOC, HAS_SYMS
start address 0x0+
 
Sections:
Idx Name Size VMA LMA File off Algn
0 \.text 0+c4 0+ 0+ 0+40 2\*\*0
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
1 \.data 0+ 0+ 0+ 0+104 2\*\*0
CONTENTS, ALLOC, LOAD, DATA
2 \.bss 0+ 0+ 0+ 0+104 2\*\*0
ALLOC
3 \.rodata 0+10 0+ 0+ 0+104 2\*\*2
CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
SYMBOL TABLE:
0+ l d \.text 0+ (|\.text)
0+ l d \.data 0+ (|\.data)
0+ l d \.bss 0+ (|\.bss)
0+ l \.text 0+ 0x04 start
0+58 l \.text 0+ 0x04 foo
0+68 l \.text 0+ 0x04 foo2
0+78 l \.text 0+ 0x04 foo3
0+ l d \.rodata 0+ (|\.rodata)
0+88 l \.text 0+ 0x04 foo4
0+4 l \.rodata 0+ myrodata1
0+98 l \.text 0+ 0x04 foo5
0+8 l \.rodata 0+ myrodata2
0+c g \.rodata 0+ myrodata3
0+b8 g \.text 0+ 0x04 foo7
0+b8 \*UND\* 0+ foo7
0+bc g \.text 0+ 0x04 foo8
0+bc \*UND\* 0+ foo8
0+c0 g \.text 0+ 0x04 foo9
0+c0 \*UND\* 0+ foo9
0+a8 g \.text 0+ 0x04 foo6
0+a8 \*UND\* 0+ foo6
 
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET TYPE VALUE
0+20 R_SH_IMM_MEDLOW16 \.text\+0x0+a6
0+44 R_SH_IMM_MEDLOW16 foo9\+0x0+40
0+ R_SH_IMM_HI16 \.text\+0x0+58
0+4 R_SH_IMM_MEDHI16 \.text\+0x0+58
0+8 R_SH_IMM_MEDLOW16 \.text\+0x0+58
0+c R_SH_IMM_LOW16 \.text\+0x0+58
0+10 R_SH_IMM_HI16 \.text\+0x0+92
0+14 R_SH_IMM_MEDHI16 \.text\+0x0+92
0+18 R_SH_IMM_MEDLOW16 \.text\+0x0+92
0+1c R_SH_IMM_LOW16 \.text\+0x0+92
0+24 R_SH_IMM_HI16 foo7\+0x0+2a
0+28 R_SH_IMM_MEDHI16 foo7\+0x0+2a
0+2c R_SH_IMM_MEDLOW16 foo7\+0x0+2a
0+30 R_SH_IMM_LOW16 foo7\+0x0+2a
0+34 R_SH_IMM_HI16 foo8
0+38 R_SH_IMM_MEDHI16 foo8
0+3c R_SH_IMM_MEDLOW16 foo8
0+40 R_SH_IMM_LOW16 foo8
0+48 R_SH_IMM_HI16 \.rodata\+0x0+4
0+4c R_SH_IMM_MEDHI16 \.rodata\+0x0+4
0+50 R_SH_IMM_MEDLOW16 \.rodata\+0x0+4
0+54 R_SH_IMM_LOW16 \.rodata\+0x0+4
0+58 R_SH_IMM_HI16 \.rodata\+0x0+26
0+5c R_SH_IMM_MEDHI16 \.rodata\+0x0+26
0+60 R_SH_IMM_MEDLOW16 \.rodata\+0x0+26
0+64 R_SH_IMM_LOW16 \.rodata\+0x0+26
0+68 R_SH_IMM_HI16 \.text\+0x0+58
0+6c R_SH_IMM_MEDHI16 \.text\+0x0+58
0+70 R_SH_IMM_MEDLOW16 \.text\+0x0+58
0+74 R_SH_IMM_LOW16 \.text\+0x0+58
0+78 R_SH_IMM_HI16 \.text\+0x0+78
0+7c R_SH_IMM_MEDHI16 \.text\+0x0+78
0+80 R_SH_IMM_MEDLOW16 \.text\+0x0+78
0+84 R_SH_IMM_LOW16 \.text\+0x0+78
0+88 R_SH_IMM_HI16 \.text\+0x0+b0
0+8c R_SH_IMM_MEDHI16 \.text\+0x0+b0
0+90 R_SH_IMM_MEDLOW16 \.text\+0x0+b0
0+94 R_SH_IMM_LOW16 \.text\+0x0+b0
0+98 R_SH_IMM_HI16 myrodata3
0+9c R_SH_IMM_MEDHI16 myrodata3
0+a0 R_SH_IMM_MEDLOW16 myrodata3
0+a4 R_SH_IMM_LOW16 myrodata3
0+a8 R_SH_IMM_HI16 foo6\+0x0+2a
0+ac R_SH_IMM_MEDHI16 foo6\+0x0+2a
0+b0 R_SH_IMM_MEDLOW16 foo6\+0x0+2a
0+b4 R_SH_IMM_LOW16 foo6\+0x0+2a
 
 
RELOCATION RECORDS FOR \[\.rodata\]:
OFFSET TYPE VALUE
0+ R_SH_DIR32 \.text
0+4 R_SH_DIR32 \.text
0+8 R_SH_DIR32 \.rodata
0+c R_SH_DIR32 \.rodata
 
 
Contents of section \.text:
0000 cc000030 c8000030 c8000030 c8000030 .*
0010 cc000030 c8000030 c8000030 c8000030 .*
0020 cc000030 cc0001e0 c80001e0 c80001e0 .*
0030 c80001e0 cc0001e0 c80001e0 c80001e0 .*
0040 c80001e0 cc000030 cc000380 c8000380 .*
0050 c8000380 c8000380 cc000150 c8000150 .*
0060 c8000150 c8000150 cc0000a0 c80000a0 .*
0070 c80000a0 c80000a0 cc000210 c8000210 .*
0080 c8000210 c8000210 cc000080 c8000080 .*
0090 c8000080 c8000080 cc0002c0 c80002c0 .*
00a0 c80002c0 c80002c0 cc0001e0 c80001e0 .*
00b0 c80001e0 c80001e0 6ff0fff0 6ff0fff0 .*
00c0 6ff0fff0 .*
Contents of section \.rodata:
0000 00000088 000000d0 00000008 00000020 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel-4.s
0,0 → 1,138
! Like rel-3.s, but as with rel-2 vs. rel-1, using "$", not "datalabel $"
! as self expression.
 
.mode SHmedia
.text
start:
movi datalabel data1 - $,r10
movi (datalabel data2 - $) & 65535,r10
movi ((datalabel data3 - $) >> 0) & 65535,r10
movi ((datalabel data4 - $) >> 16) & 65535,r10
movi datalabel data5 + 8 - $,r10
movi (datalabel data6 + 16 - $) & 65535,r10
movi ((datalabel data7 + 12 - $) >> 0) & 65535,r10
movi ((datalabel data8 + 4 - $) >> 16) & 65535,r10
 
movi datalabel othertext1 - $,r10
movi (datalabel othertext2 - $) & 65535,r10
movi ((datalabel othertext3 - $) >> 0) & 65535,r10
movi ((datalabel othertext4 - $) >> 16) & 65535,r10
movi datalabel othertext5 + 8 - $,r10
movi (datalabel othertext6 + 16 - $) & 65535,r10
movi ((datalabel othertext7 + 12 - $) >> 0) & 65535,r10
movi ((datalabel othertext8 + 4 - $) >> 16) & 65535,r10
 
movi datalabel extern1 - $,r10
movi (datalabel extern2 - $) & 65535,r10
movi ((datalabel extern3 - $) >> 0) & 65535,r10
movi ((datalabel extern4 - $) >> 16) & 65535,r10
movi datalabel extern5 + 8 - $,r10
movi (datalabel extern6 + 16 - $) & 65535,r10
movi ((datalabel extern7 + 12 - $) >> 0) & 65535,r10
movi ((datalabel extern8 + 4 - $) >> 16) & 65535,r10
 
movi datalabel gdata1 - $,r10
movi (datalabel gdata2 - $) & 65535,r10
movi ((datalabel gdata3 - $) >> 0) & 65535,r10
movi ((datalabel gdata4 - $) >> 16) & 65535,r10
movi datalabel gdata5 + 8 - $,r10
movi (datalabel gdata6 + 16 - $) & 65535,r10
movi ((datalabel gdata7 + 12 - $) >> 0) & 65535,r10
movi ((datalabel gdata8 + 4 - $) >> 16) & 65535,r10
 
movi datalabel gothertext1 - $,r10
movi (datalabel gothertext2 - $) & 65535,r10
movi ((datalabel gothertext3 - $) >> 0) & 65535,r10
movi ((datalabel gothertext4 - $) >> 16) & 65535,r10
movi datalabel gothertext5 + 8 - $,r10
movi (datalabel gothertext6 + 16 - $) & 65535,r10
movi ((datalabel gothertext7 + 12 - $) >> 0) & 65535,r10
movi ((datalabel gothertext8 + 4 - $) >> 16) & 65535,r10
 
.section .othertext,"ax"
x:
nop
othertext1:
nop
othertext2:
nop
othertext3:
nop
othertext4:
nop
othertext5:
nop
othertext6:
nop
othertext7:
nop
othertext8:
nop
.global gothertext1
gothertext1:
nop
.global gothertext2
gothertext2:
nop
.global gothertext3
gothertext3:
nop
.global gothertext4
gothertext4:
nop
.global gothertext5
gothertext5:
nop
.global gothertext6
gothertext6:
nop
.global gothertext7
gothertext7:
nop
.global gothertext8
gothertext8:
nop
 
.data
y:
.long 0
data1:
.long 0
data2:
.long 0
data3:
.long 0
data4:
.long 0
data5:
.long 0
data6:
.long 0
data7:
.long 0
data8:
.long 0
.global gdata1
gdata1:
.long 0
.global gdata2
gdata2:
.long 0
.global gdata3
gdata3:
.long 0
.global gdata4
gdata4:
.long 0
.global gdata5
gdata5:
.long 0
.global gdata6
gdata6:
.long 0
.global gdata7
gdata7:
.long 0
.global gdata8
gdata8:
.long 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi32-noexp-2.d
0,0 → 1,28
#as: --isa=shmedia --abi=32 -no-expand
#objdump: -dr
#source: movi-2.s
#name: MOVI non-expansion of local symbols with relocs, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <start>:
[ ]+0:[ ]+cc000210[ ]+movi 0,r33
[ ]+0:[ ]+R_SH_IMMS16 \.text\+0x2d
[ ]+4:[ ]+cc000360[ ]+movi 0,r54
[ ]+4:[ ]+R_SH_IMMS16 \.data\+0x2c
[ ]+8:[ ]+cc0000f0[ ]+movi 0,r15
[ ]+8:[ ]+R_SH_IMMS16 \.text\.other\+0x35
 
0+c <forw>:
[ ]+c:[ ]+cc000190[ ]+movi 0,r25
[ ]+c:[ ]+R_SH_IMMS16 \.data\.other\+0x38
Disassembly of section \.text\.other:
 
0+ <forwdummylabel>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
0+8 <forwothertext>:
[ ]+8:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt-noexp-1.d
0,0 → 1,27
#as: --isa=shmedia -no-expand
#objdump: -dr
#source: pt-1.s
#name: Basic SHmedia PT and PTA instructions with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
[0]+4 <start1>:
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
[0]+8 <start4>:
[ ]+8:[ ]+ebfffe50[ ]+pta/l 4 <start1>,tr5
[ ]+c:[ ]+6ff0fff0[ ]+nop
[ ]+10:[ ]+e8000a70[ ]+pta/l 18 <start2>,tr7
[ ]+14:[ ]+6ff0fff0[ ]+nop
 
[0]+18 <start2>:
[ ]+18:[ ]+e8000a40[ ]+pta/l 20 <start3>,tr4
[ ]+1c:[ ]+6ff0fff0[ ]+nop
 
[0]+20 <start3>:
[ ]+20:[ ]+ebffea30[ ]+pta/l 8 <start4>,tr3
[ ]+24:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/mix-1.s
0,0 → 1,21
! Check mixed-mode objects; different sections holding different ISA:s.
.mode SHcompact
.text
start:
bt forw
mova start2,r0
start2:
nop
forw:
nop
 
.section .text.media,"ax"
.mode SHmedia
mediacode:
ptb forw,tr4
pt start2,tr5
mediacode2:
movi start2,r54
movi mediacode2,r45
pta mediacode2,tr7
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt64-32-2.d
0,0 → 1,39
#as: --isa=shmedia -abi=64 -expand-pt32
#objdump: -dr
#source: pt-2.s
#name: Inter-segment PT, 64-bit with -expand-pt32.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
0+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start1>:
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
0+8 <start4>:
[ ]+8:[ ]+ebfffe50[ ]+pta/l 4 <start1>,tr5
[ ]+c:[ ]+6ff0fff0[ ]+nop
[ ]+10:[ ]+cc000190[ ]+movi 0,r25
[ ]+10:[ ]+R_SH_IMM_MEDLOW16_PCREL \.text\.other\+0xfffffffffffffffd
[ ]+14:[ ]+c8000190[ ]+shori 0,r25
[ ]+14:[ ]+R_SH_IMM_LOW16_PCREL \.text\.other\+0x1
[ ]+18:[ ]+6bf56670[ ]+ptrel/l r25,tr7
[ ]+1c:[ ]+6ff0fff0[ ]+nop
Disassembly of section \.text\.other:
 
0+ <dummylabel>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start2>:
[ ]+4:[ ]+e8000a40[ ]+pta/l c <start3>,tr4
[ ]+8:[ ]+6ff0fff0[ ]+nop
 
0+c <start3>:
[ ]+c:[ ]+cc000190[ ]+movi 0,r25
[ ]+c:[ ]+R_SH_IMM_MEDLOW16_PCREL \.text\+0x1
[ ]+10:[ ]+c8000190[ ]+shori 0,r25
[ ]+10:[ ]+R_SH_IMM_LOW16_PCREL \.text\+0x5
[ ]+14:[ ]+6bf56630[ ]+ptrel/l r25,tr3
[ ]+18:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange1-1.d
0,0 → 1,104
#as: --abi=32
#objdump: -sr
#source: crange1.s
#name: .cranges descriptors.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.cranges\]:
OFFSET *TYPE *VALUE
0+00 R_SH_DIR32 \.text\.shmediaanddata
0+0a R_SH_DIR32 \.text\.codemix
0+14 R_SH_DIR32 \.text\.codemixconst
0+1e R_SH_DIR32 \.text\.codemixconst
0+28 R_SH_DIR32 \.text\.codemixconst2
0+32 R_SH_DIR32 \.text\.codemixconst2
0+3c R_SH_DIR32 \.text\.codemixconst2
0+46 R_SH_DIR32 \.text\.codemixconst2
0+50 R_SH_DIR32 \.text\.codemixconst2
0+5a R_SH_DIR32 \.text\.shmediaanddata
0+64 R_SH_DIR32 \.text\.codemix
0+6e R_SH_DIR32 \.text\.codemixconst
0+78 R_SH_DIR32 \.text\.codemixconst2
 
 
Contents of section \.text:
0000 6ff0fff0 cc00aad0 cc0022e0 6ff0fff0 .*
Contents of section \.text\.compact:
0000 0009e02a 89000009 0009 .*
Contents of section \.text\.shmediaanddata:
0000 cc00aad0 cc0022e0 6ff0fff0 00000014 .*
0010 00000032 .*
Contents of section \.cranges:
0000 00000000 00000008 00030000 00000000 .*
0010 00180003 00000000 0000001c 00030000 .*
0020 001c0000 00200001 00000000 00000024 .*
0030 00030000 00240000 00280001 0000004c .*
0040 000000e8 00020000 01340000 002c0003 .*
0050 00000160 0000001c 00010000 00080000 .*
0060 000c0001 00000018 0000000e 00020000 .*
0070 003c0000 00800002 0000017c 00000154 .*
0080 0002 .*
Contents of section \.text\.codemix:
0000 cc00aad0 6ff0fff0 6ff0fff0 cc0062e0 .*
0010 6ff0fff0 6ff0fff0 0009e028 00090009 .*
0020 89000009 0009 .*
Contents of section \.text\.codemixconst:
0000 6ff0fff0 cc00aad0 6ff0fff0 6ff0fff0 .*
0010 cc00e2e0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff00000 0000fff0 6ff0fff0 .*
0030 6ff0fff0 00000000 000000b3 0009e02b .*
0040 00090009 89020009 00090009 00090000 .*
0050 00000000 00000000 00000000 00000000 .*
0060 00000000 00000000 00000000 00000000 .*
0070 00000000 00000000 00000000 00000000 .*
0080 00000000 00000000 00000000 00000000 .*
0090 00000000 00000000 00000000 00000000 .*
00a0 00000000 00000000 00000000 00000000 .*
00b0 00000000 00000000 0000007e .*
Contents of section \.text\.codemixconst2:
0000 6ff0fff0 cc00aad0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 cc0122e0 6ff0fff0 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 00000000 00000044 0009e02c .*
0050 00090009 89040009 00090009 00090009 .*
0060 00090009 09000000 00000000 00000000 .*
0070 00000000 00000000 00000000 00000000 .*
0080 00000000 00000000 00000000 00000000 .*
0090 00000000 00000000 00000000 00000000 .*
00a0 00000000 00000000 00000000 00000000 .*
00b0 00000000 00000000 00000000 00000000 .*
00c0 00000000 00000000 00000000 00000000 .*
00d0 00000000 00000000 00000000 00000000 .*
00e0 00000000 00000000 00000000 00000000 .*
00f0 00000000 00000000 00000000 00000000 .*
0100 00000000 00000000 00000000 00000000 .*
0110 00000000 00000000 00000000 00000000 .*
0120 00000000 00000000 00000000 00000000 .*
0130 000000e6 6ff0fff0 cc00aed0 6ff0fff0 .*
0140 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0150 6ff0fff0 6ff0fff0 6ff0fff0 cc0112e0 .*
0160 6ff0fff0 00000000 00000000 00000000 .*
0170 00000000 00000000 00000044 0009e00e .*
0180 00090009 890a0009 00090009 00090009 .*
0190 00090009 00090009 00090009 00090000 .*
01a0 00000000 00000000 00000000 00000000 .*
01b0 00000000 00000000 00000000 00000000 .*
01c0 00000000 00000000 00000000 00000000 .*
01d0 00000000 00000000 00000000 00000000 .*
01e0 00000000 00000000 00000000 00000000 .*
01f0 00000000 00000000 00000000 00000000 .*
0200 00000000 00000000 00000000 00000000 .*
0210 00000000 00000000 00000000 00000000 .*
0220 00000000 00000000 00000000 00000000 .*
0230 00000000 00000000 00000000 00000000 .*
0240 00000000 00000000 00000000 00000000 .*
0250 00000000 00000000 00000000 00000000 .*
0260 00000000 00000000 00000000 00000000 .*
0270 00000000 00000000 00000000 00000000 .*
0280 00000000 00000000 00000000 00000000 .*
0290 00000000 00000000 00000000 00000000 .*
02a0 00000000 00000000 00000000 00000000 .*
02b0 00000000 00000000 00000000 00000000 .*
02c0 00000000 00000000 00000000 00000152 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange3-1.d
0,0 → 1,24
#as: --abi=32
#objdump: -sr
#source: crange3.s
#name: .cranges descriptors, constant mix.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.cranges\]:
OFFSET *TYPE *VALUE
0+00 R_SH_DIR32 \.text
0+0a R_SH_DIR32 \.text
0+14 R_SH_DIR32 \.text
 
 
Contents of section \.text:
0000 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0010 01235678 12345678 12345678 1234fede .*
0020 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0030 6ff0fff0 .*
Contents of section \.rodata:
0000 abcdef01 12345678 .*
Contents of section \.cranges:
0000 00000000 00000010 00030000 00100000 .*
0010 00100001 00000020 00000014 0003 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptc64-32-1.d
0,0 → 1,15
#as: --abi=64 -expand-pt32
#objdump: -dr
#source: ptc-1.s
#name: PT constant, 64-bit ABI with -expand-pt32.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000190[ ]+movi 0,r25
[ ]+0:[ ]+R_SH_IMM_MEDLOW16_PCREL \*ABS\*\+0xf8
[ ]+4:[ ]+c8000190[ ]+shori 0,r25
[ ]+4:[ ]+R_SH_IMM_LOW16_PCREL \*ABS\*\+0xfc
[ ]+8:[ ]+6bf56610[ ]+ptrel/l r25,tr1
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange5-1.d
0,0 → 1,12
#as: --abi=32 --isa=SHmedia
#objdump: -sr
#source: crange5.s
#name: Avoid zero length .cranges range descriptor at .align in code.
 
.*: file format .*-sh64.*
 
Contents of section \.text:
0000 e8003a00 d4ff80f0 4455fc00 acf000e0 .*
0010 acf00c00 acf009c0 acf00520 00f8fce0 .*
0020 0029fc10 e4110200 ebffda50 d81201c0 .*
0030 e8000a00 cc000420 6ff0fff0 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi64-2.d
0,0 → 1,30
#as: --isa=shmedia --abi=64
#objdump: -dr
#name: MOVI expansion, 64-bit ABI, 64-bit subset.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000430[ ]+movi 1,r3
[ ]+4:[ ]+c8000030[ ]+shori 0,r3
[ ]+8:[ ]+c8000030[ ]+shori 0,r3
[ ]+c:[ ]+cffffc30[ ]+movi -1,r3
[ ]+10:[ ]+c9fffc30[ ]+shori 32767,r3
[ ]+14:[ ]+c8000030[ ]+shori 0,r3
[ ]+18:[ ]+cc000030[ ]+movi 0,r3
[ ]+1c:[ ]+ca000030[ ]+shori 32768,r3
[ ]+20:[ ]+c8000030[ ]+shori 0,r3
[ ]+24:[ ]+cdfffc30[ ]+movi 32767,r3
[ ]+28:[ ]+c8000030[ ]+shori 0,r3
[ ]+2c:[ ]+c8000030[ ]+shori 0,r3
[ ]+30:[ ]+c8000030[ ]+shori 0,r3
[ ]+34:[ ]+ce000030[ ]+movi -32768,r3
[ ]+38:[ ]+c8000030[ ]+shori 0,r3
[ ]+3c:[ ]+c8000030[ ]+shori 0,r3
[ ]+40:[ ]+c8000030[ ]+shori 0,r3
[ ]+44:[ ]+ce000030[ ]+movi -32768,r3
[ ]+48:[ ]+c8000030[ ]+shori 0,r3
[ ]+4c:[ ]+c8000030[ ]+shori 0,r3
[ ]+50:[ ]+c8000030[ ]+shori 0,r3
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/datal-2.d
0,0 → 1,44
#as: --abi=32
#objdump: -sr
#source: datal-2.s
#name: DataLabel redundant local use, SHcompact
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET *TYPE *VALUE
0+08 R_SH_DIR32 \.rodata
0+0c R_SH_DIR32 myrodata2
0+10 R_SH_DIR32 \.text
0+14 R_SH_DIR32 \.text
0+18 R_SH_DIR32 \.text
0+1c R_SH_DIR32 \.text
 
 
RELOCATION RECORDS FOR \[\.data\]:
OFFSET *TYPE *VALUE
0+00 R_SH_DIR32 myrodata2
0+04 R_SH_DIR32 \.data
0+08 R_SH_DIR32 \.data
0+0c R_SH_DIR32 foo2
0+10 R_SH_DIR32 foo3
0+14 R_SH_DIR32 \.text
0+18 R_SH_DIR32 \.text
 
 
RELOCATION RECORDS FOR \[\.rodata\]:
OFFSET *TYPE *VALUE
0+00 R_SH_DIR32 \.data
0+04 R_SH_DIR32 \.data
0+08 R_SH_DIR32 \.rodata
0+0c R_SH_DIR32 \.rodata
 
 
Contents of section \.text:
0000 c701c70d 00090009 00000004 00000014 .*
0010 00000002 0000002e 00000018 00000030 .*
Contents of section \.data:
0000 00000000 00000004 0000001c 00000000 .*
0010 00000014 00000002 00000018 .*
Contents of section \.rodata:
0000 00000010 0000004c 00000008 00000020 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptc64-noexp-1.d
0,0 → 1,13
#as: --abi=64 -no-expand
#objdump: -dr
#source: ptc-1.s
#name: PT constant, 64-bit ABI with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+e8000610[ ]+pta/l 4 <start\+0x4>,tr1
[ ]+0:[ ]+R_SH_PT_16 \*ABS\*\+0x100
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift64-3.d
0,0 → 1,14
#as: --abi=64
#objdump: -dr
#source: shift-3.s
#name: Shift expression, local but undefined symbol, 64-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000010[ ]+movi 0,r1
[ ]+0:[ ]+R_SH_IMM_LOW16 \.LC0
[ ]+4:[ ]+cc000030[ ]+movi 0,r3
[ ]+4:[ ]+R_SH_IMM_MEDLOW16 \.LC0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel64-1.d
0,0 → 1,111
#as: --abi=64
#objdump: -sr
#source: rel-1.s
#name: MOVI: PC-relative relocs, 64-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET TYPE VALUE
0+10 R_SH_IMM_LOW16_PCREL \.data\+0x0+8
0+14 R_SH_IMM_LOW16_PCREL \.data\+0x0+c
0+18 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+10
0+2c R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+30 R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+34 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+24
0+48 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+9
0+4c R_SH_IMM_LOW16_PCREL \.othertext\+0x0+d
0+50 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+11
0+64 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+29
0+68 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+29
0+6c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+25
0+80 R_SH_IMM_LOW16_PCREL extern2
0+84 R_SH_IMM_LOW16_PCREL extern3
0+88 R_SH_IMM_MEDLOW16_PCREL extern4
0+9c R_SH_IMM_LOW16_PCREL extern6\+0x0+10
0+a0 R_SH_IMM_LOW16_PCREL extern7\+0x0+c
0+a4 R_SH_IMM_MEDLOW16_PCREL extern8\+0x0+4
0+b8 R_SH_IMM_LOW16_PCREL gdata2
0+bc R_SH_IMM_LOW16_PCREL gdata3
0+c0 R_SH_IMM_MEDLOW16_PCREL gdata4
0+d4 R_SH_IMM_LOW16_PCREL gdata6\+0x0+10
0+d8 R_SH_IMM_LOW16_PCREL gdata7\+0x0+c
0+dc R_SH_IMM_MEDLOW16_PCREL gdata8\+0x0+4
0+f0 R_SH_IMM_LOW16_PCREL gothertext2
0+f4 R_SH_IMM_LOW16_PCREL gothertext3
0+f8 R_SH_IMM_MEDLOW16_PCREL gothertext4
0+10c R_SH_IMM_LOW16_PCREL gothertext6\+0x0+10
0+110 R_SH_IMM_LOW16_PCREL gothertext7\+0x0+c
0+114 R_SH_IMM_MEDLOW16_PCREL gothertext8\+0x0+4
0+ R_SH_IMM_HI16_PCREL \.data\+0x0+4
0+4 R_SH_IMM_MEDHI16_PCREL \.data\+0x0+8
0+8 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+c
0+c R_SH_IMM_LOW16_PCREL \.data\+0x0+10
0+1c R_SH_IMM_HI16_PCREL \.data\+0x0+1c
0+20 R_SH_IMM_MEDHI16_PCREL \.data\+0x0+20
0+24 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+24
0+28 R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+38 R_SH_IMM_HI16_PCREL \.othertext\+0x0+5
0+3c R_SH_IMM_MEDHI16_PCREL \.othertext\+0x0+9
0+40 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+d
0+44 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+11
0+54 R_SH_IMM_HI16_PCREL \.othertext\+0x0+1d
0+58 R_SH_IMM_MEDHI16_PCREL \.othertext\+0x0+21
0+5c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+25
0+60 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+29
0+70 R_SH_IMM_HI16_PCREL extern1
0+74 R_SH_IMM_MEDHI16_PCREL extern1\+0x0+4
0+78 R_SH_IMM_MEDLOW16_PCREL extern1\+0x0+8
0+7c R_SH_IMM_LOW16_PCREL extern1\+0x0+c
0+8c R_SH_IMM_HI16_PCREL extern5\+0x0+8
0+90 R_SH_IMM_MEDHI16_PCREL extern5\+0x0+c
0+94 R_SH_IMM_MEDLOW16_PCREL extern5\+0x0+10
0+98 R_SH_IMM_LOW16_PCREL extern5\+0x0+14
0+a8 R_SH_IMM_HI16_PCREL gdata1
0+ac R_SH_IMM_MEDHI16_PCREL gdata1\+0x0+4
0+b0 R_SH_IMM_MEDLOW16_PCREL gdata1\+0x0+8
0+b4 R_SH_IMM_LOW16_PCREL gdata1\+0x0+c
0+c4 R_SH_IMM_HI16_PCREL gdata5\+0x0+8
0+c8 R_SH_IMM_MEDHI16_PCREL gdata5\+0x0+c
0+cc R_SH_IMM_MEDLOW16_PCREL gdata5\+0x0+10
0+d0 R_SH_IMM_LOW16_PCREL gdata5\+0x0+14
0+e0 R_SH_IMM_HI16_PCREL gothertext1
0+e4 R_SH_IMM_MEDHI16_PCREL gothertext1\+0x0+4
0+e8 R_SH_IMM_MEDLOW16_PCREL gothertext1\+0x0+8
0+ec R_SH_IMM_LOW16_PCREL gothertext1\+0x0+c
0+fc R_SH_IMM_HI16_PCREL gothertext5\+0x0+8
0+100 R_SH_IMM_MEDHI16_PCREL gothertext5\+0x0+c
0+104 R_SH_IMM_MEDLOW16_PCREL gothertext5\+0x0+10
0+108 R_SH_IMM_LOW16_PCREL gothertext5\+0x0+14
 
Contents of section \.text:
0000 cc0000a0 c80000a0 c80000a0 c80000a0 .*
0010 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0020 c80000a0 c80000a0 c80000a0 cc0000a0 .*
0030 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0040 c80000a0 c80000a0 cc0000a0 cc0000a0 .*
0050 cc0000a0 cc0000a0 c80000a0 c80000a0 .*
0060 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
0070 cc0000a0 c80000a0 c80000a0 c80000a0 .*
0080 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0090 c80000a0 c80000a0 c80000a0 cc0000a0 .*
00a0 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
00b0 c80000a0 c80000a0 cc0000a0 cc0000a0 .*
00c0 cc0000a0 cc0000a0 c80000a0 c80000a0 .*
00d0 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
00e0 cc0000a0 c80000a0 c80000a0 c80000a0 .*
00f0 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0100 c80000a0 c80000a0 c80000a0 cc0000a0 .*
0110 cc0000a0 cc0000a0 .*
Contents of section \.data:
0000 00000000 00000000 00000000 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 00000000 00000000 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 .*
Contents of section \.othertext:
0000 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0040 6ff0fff0 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/datal32-3.d
0,0 → 1,94
#as: --abi=32
#objdump: -xsr
#source: datal-3.s
#name: DataLabel local def/use, SHmedia 32-bit ABI
 
# We should have the st_type field of each symbol displayed too, so we can
# check that STT_DATALABEL is set, but objdump doesn't do that at present,
# and readelf isn't supported as a run_dump_test tool.
 
.*: file format .*-sh64.*
.*
architecture: sh5, flags 0x0+11:
HAS_RELOC, HAS_SYMS
start address 0x0+
 
Sections:
Idx Name Size VMA LMA File off Algn
0 \.text 0+6c 0+ 0+ 0+34 2\*\*0
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
1 \.data 0+ 0+ 0+ 0+a0 2\*\*0
CONTENTS, ALLOC, LOAD, DATA
2 \.bss 0+ 0+ 0+ 0+a0 2\*\*0
ALLOC
3 \.rodata 0+10 0+ 0+ 0+a0 2\*\*2
CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
SYMBOL TABLE:
0+ l d \.text 0+ (|\.text)
0+ l d \.data 0+ (|\.data)
0+ l d \.bss 0+ (|\.bss)
0+ l \.text 0+ 0x04 start
0+30 l \.text 0+ 0x04 foo
0+38 l \.text 0+ 0x04 foo2
0+40 l \.text 0+ 0x04 foo3
0+ l d \.rodata 0+ (|\.rodata)
0+48 l \.text 0+ 0x04 foo4
0+4 l \.rodata 0+ myrodata1
0+50 l \.text 0+ 0x04 foo5
0+8 l \.rodata 0+ myrodata2
0+c g \.rodata 0+ myrodata3
0+60 g \.text 0+ 0x04 foo7
0+60 \*UND\* 0+ foo7
0+64 g \.text 0+ 0x04 foo8
0+64 \*UND\* 0+ foo8
0+68 g \.text 0+ 0x04 foo9
0+68 \*UND\* 0+ foo9
0+58 g \.text 0+ 0x04 foo6
0+58 \*UND\* 0+ foo6
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET *TYPE *VALUE
0+10 R_SH_IMM_MEDLOW16 \.text\+0x0+6e
0+24 R_SH_IMM_MEDLOW16 foo9\+0x0+40
0+00 R_SH_IMM_MEDLOW16 \.text\+0x0+30
0+04 R_SH_IMM_LOW16 \.text\+0x0+30
0+08 R_SH_IMM_MEDLOW16 \.text\+0x0+62
0+0c R_SH_IMM_LOW16 \.text\+0x0+62
0+14 R_SH_IMM_MEDLOW16 foo7\+0x0+2a
0+18 R_SH_IMM_LOW16 foo7\+0x0+2a
0+1c R_SH_IMM_MEDLOW16 foo8
0+20 R_SH_IMM_LOW16 foo8
0+28 R_SH_IMM_MEDLOW16 \.rodata\+0x0+4
0+2c R_SH_IMM_LOW16 \.rodata\+0x0+4
0+30 R_SH_IMM_MEDLOW16 \.rodata\+0x0+26
0+34 R_SH_IMM_LOW16 \.rodata\+0x0+26
0+38 R_SH_IMM_MEDLOW16 \.text\+0x0+30
0+3c R_SH_IMM_LOW16 \.text\+0x0+30
0+40 R_SH_IMM_MEDLOW16 \.text\+0x0+40
0+44 R_SH_IMM_LOW16 \.text\+0x0+40
0+48 R_SH_IMM_MEDLOW16 \.text\+0x0+70
0+4c R_SH_IMM_LOW16 \.text\+0x0+70
0+50 R_SH_IMM_MEDLOW16 myrodata3
0+54 R_SH_IMM_LOW16 myrodata3
0+58 R_SH_IMM_MEDLOW16 foo6\+0x0+2a
0+5c R_SH_IMM_LOW16 foo6\+0x0+2a
 
 
RELOCATION RECORDS FOR \[\.rodata\]:
OFFSET *TYPE *VALUE
0+ R_SH_DIR32 \.text
0+4 R_SH_DIR32 \.text
0+8 R_SH_DIR32 \.rodata
0+c R_SH_DIR32 \.rodata
 
 
Contents of section \.text:
0000 cc000030 c8000030 cc000030 c8000030 .*
0010 cc000030 cc0001e0 c80001e0 cc0001e0 .*
0020 c80001e0 cc000030 cc000380 c8000380 .*
0030 cc000150 c8000150 cc0000a0 c80000a0 .*
0040 cc000210 c8000210 cc000080 c8000080 .*
0050 cc0002c0 c80002c0 cc0001e0 c80001e0 .*
0060 6ff0fff0 6ff0fff0 6ff0fff0 .*
Contents of section \.rodata:
0000 00000048 00000088 00000008 00000020 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-dsp.s
0,0 → 1,15
! Check that we get errors when assembling DSP instructions.
 
! { dg-do assemble }
! { dg-options "-isa=SHcompact" }
 
! Regarding the opcode table, all insns are marked arch_sh_dsp_up; there are
! no insns marked arch_sh3_dsp_up. We check a few marked arch_sh_dsp_up:
! two have operands only recognized with -dsp; the other has an opcode not
! recognized without -dsp.
 
.text
start:
ldc r3,mod ! { dg-error "invalid operands" }
ldre @(16,pc) ! { dg-error "opcode not valid for this cpu variant" }
lds r4,a0 ! { dg-error "invalid operands" }
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/sh64.exp
0,0 → 1,27
# Copyright (C) 2000, 2002, 2005, 2007 Free Software Foundation, Inc.
 
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
# Please email any bugs, comments, and/or additions to this file to:
# dejagnu@gnu.org
 
if [istarget sh64-*-*] then {
set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
foreach rdtest $rd_test_list {
# We need to strip the ".d", but can leave the dirname.
verbose [file rootname $rdtest]
run_dump_test [file rootname $rdtest]
}
}
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel64-5.d
0,0 → 1,40
#as: --abi=64
#objdump: -sr
#source: rel-5.s
#name: MOVI: PC-relative reloc within .text, 64-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET TYPE VALUE
0+5c R_SH_IMM_LOW16_PCREL gstart6\+0x0+18
0+60 R_SH_IMM_MEDLOW16_PCREL gstart7\+0x0+20
0+1c R_SH_IMM_HI16_PCREL gstart2\+0x0+8
0+20 R_SH_IMM_MEDHI16_PCREL gstart2\+0x0+c
0+24 R_SH_IMM_MEDLOW16_PCREL gstart2\+0x0+10
0+28 R_SH_IMM_LOW16_PCREL gstart2\+0x0+14
0+2c R_SH_IMM_HI16_PCREL gstart3\+0x0+3
0+30 R_SH_IMM_MEDHI16_PCREL gstart3\+0x0+7
0+34 R_SH_IMM_MEDLOW16_PCREL gstart3\+0x0+b
0+38 R_SH_IMM_LOW16_PCREL gstart3\+0x0+f
0+3c R_SH_IMM_HI16_PCREL gstart4\+0x0+8
0+40 R_SH_IMM_MEDHI16_PCREL gstart4\+0x0+c
0+44 R_SH_IMM_MEDLOW16_PCREL gstart4\+0x0+10
0+48 R_SH_IMM_LOW16_PCREL gstart4\+0x0+14
0+4c R_SH_IMM_HI16_PCREL gstart5\+0x0+b
0+50 R_SH_IMM_MEDHI16_PCREL gstart5\+0x0+f
0+54 R_SH_IMM_MEDLOW16_PCREL gstart5\+0x0+13
0+58 R_SH_IMM_LOW16_PCREL gstart5\+0x0+17
 
Contents of section \.text:
0000 6ff0fff0 cc01a5e0 cc0191e0 cc01a1e0 .*
0010 cc01ade0 cc01e280 cc000320 cc0001e0 .*
0020 c80001e0 c80001e0 c80001e0 cc0001e0 .*
0030 c80001e0 c80001e0 c80001e0 cc0001e0 .*
0040 c80001e0 c80001e0 c80001e0 cc0001e0 .*
0050 c80001e0 c80001e0 c80001e0 cc000280 .*
0060 cc000320 6ff0fff0 6ff0fff0 6ff0fff0 .*
0070 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0080 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0090 6ff0fff0 .*
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange4.s
0,0 → 1,8
! This will be two .cranges. Original problem was that the second one was
! lost because .space just emitted a frag, without calling emit_expr as
! most other data-generating pseudos.
 
.mode SHmedia
start:
nop
.space 20,0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi64-2.s
0,0 → 1,10
! Check MOVI expansion. This one for the 64-bit ABI only.
.text
start:
movi 65536 << 16,r3
movi -32769 << 16,r3
movi 32768 << 16,r3
movi 32767 << 48,r3
movi 32768 << 48,r3 ! Perhaps a warning on this or the next,
movi -32768 << 48,r3 ! for being out of range?
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/datal-2.s
0,0 → 1,46
! Check "datalabel" qualifier.
! This is the most simple use; references to local symbols where it is
! completely redundant. Code tests are for SHcompact mode.
 
.mode SHcompact
.text
start:
mova datalabel litpool1,r0
start1:
mova datalabel litpool2 + 44,r0
start2:
nop
nop
litpool1:
.long datalabel myrodata1
litpool2:
.long datalabel myrodata2 + 20
.long DATALABEL start1
.long datalabel start2+42
.long DataLabel $
.long datalabel $+20
 
.section .rodata
.long datalabel foo4
myrodata1:
.long DataLabel foo5 + 56
.global myrodata2
myrodata2:
.long datalabel $
.long datalabel $+20
 
.data
.long DATALABEL myrodata2
foo:
.long datalabel $
.global foo2
foo2:
.long datalabel $+20
.global foo3
foo3:
.long DataLabel foo2
foo4:
.long datalabel foo3+20
foo5:
.long DATALABEL start1
.long datalabel start2+20
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-3.s
0,0 → 1,36
! { dg-do assemble }
! { dg-options "--abi=32" }
 
! Check that we get errors for immediate operands with expressions with
! resolvable differences between local symbols, but not in range for the
! operands, and no errors for nearby valid values.
 
.text
.mode SHmedia
start:
addi r50,.Lab500 - .Lab1,r40
addi r50,.Lab1000 - .Lab1,r40 ! { dg-error "not a 10-bit signed value" }
addi r50,.Lab500 - .Lab1 + 1,r40
addi r50,.Lab500 - .Lab1 + 2,r40
ld.uw r30,.Lab1000 - .Lab1,r40
ld.uw r30,.Lab500 - .Lab1 + 1,r40 ! { dg-error "not an even value" }
ld.uw r30,.Lab500 - .Lab1 + 2,r40
ld.uw r50,.Lab2000 - .Lab1,r20 ! { dg-error "not a 11-bit signed value" }
ld.l r50,.Lab2000 - .Lab1,r20
ld.l r50,.Lab2000 - .Lab1 + 1,r20 ! { dg-error "not a multiple of 4" }
ld.l r50,.Lab2000 - .Lab1 + 2,r20 ! { dg-error "not a multiple of 4" }
ld.l r50,.Lab4000 - .Lab1,r20 ! { dg-error "not a 12-bit signed value" }
nop
 
.data
.long 0
.Lab1:
.zero 500,0
.Lab500:
.zero 500,0
.Lab1000:
.zero 1000,0
.Lab2000:
.zero 2000,0
.Lab4000:
.long 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptext64-1.d
0,0 → 1,64
#as: --isa=shmedia --abi=64
#source: ptext-1.s
#objdump: -dr
#name: PT, PTA, PTB expansion for external symbols, 64-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000190[ ]+movi 0,r25
[ ]+0:[ ]+R_SH_IMM_HI16_PCREL externalsym1\+0x18
[ ]+4:[ ]+c8000190[ ]+shori 0,r25
[ ]+4:[ ]+R_SH_IMM_MEDHI16_PCREL externalsym1\+0x1c
[ ]+8:[ ]+c8000190[ ]+shori 0,r25
[ ]+8:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym1\+0x20
[ ]+c:[ ]+c8000190[ ]+shori 0,r25
[ ]+c:[ ]+R_SH_IMM_LOW16_PCREL externalsym1\+0x24
[ ]+10:[ ]+6bf56650[ ]+ptrel/l r25,tr5
[ ]+14:[ ]+cc000190[ ]+movi 0,r25
[ ]+14:[ ]+R_SH_IMM_HI16_PCREL externalsym2\+0x1c
[ ]+18:[ ]+c8000190[ ]+shori 0,r25
[ ]+18:[ ]+R_SH_IMM_MEDHI16_PCREL externalsym2\+0x20
[ ]+1c:[ ]+c8000190[ ]+shori 0,r25
[ ]+1c:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym2\+0x24
[ ]+20:[ ]+c8000190[ ]+shori 0,r25
[ ]+20:[ ]+R_SH_IMM_LOW16_PCREL externalsym2\+0x28
[ ]+24:[ ]+6bf56640[ ]+ptrel/l r25,tr4
[ ]+28:[ ]+cc000190[ ]+movi 0,r25
[ ]+28:[ ]+R_SH_IMM_HI16_PCREL externalsym3\+0x20
[ ]+2c:[ ]+c8000190[ ]+shori 0,r25
[ ]+2c:[ ]+R_SH_IMM_MEDHI16_PCREL externalsym3\+0x24
[ ]+30:[ ]+c8000190[ ]+shori 0,r25
[ ]+30:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym3\+0x28
[ ]+34:[ ]+c8000190[ ]+shori 0,r25
[ ]+34:[ ]+R_SH_IMM_LOW16_PCREL externalsym3\+0x2c
[ ]+38:[ ]+6bf56630[ ]+ptrel/l r25,tr3
[ ]+3c:[ ]+cc000190[ ]+movi 0,r25
[ ]+3c:[ ]+R_SH_IMM_HI16_PCREL externalsym4\+0x24
[ ]+40:[ ]+c8000190[ ]+shori 0,r25
[ ]+40:[ ]+R_SH_IMM_MEDHI16_PCREL externalsym4\+0x28
[ ]+44:[ ]+c8000190[ ]+shori 0,r25
[ ]+44:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym4\+0x2c
[ ]+48:[ ]+c8000190[ ]+shori 0,r25
[ ]+48:[ ]+R_SH_IMM_LOW16_PCREL externalsym4\+0x30
[ ]+4c:[ ]+6bf56450[ ]+ptrel/u r25,tr5
[ ]+50:[ ]+cc000190[ ]+movi 0,r25
[ ]+50:[ ]+R_SH_IMM_HI16_PCREL externalsym5\+0x28
[ ]+54:[ ]+c8000190[ ]+shori 0,r25
[ ]+54:[ ]+R_SH_IMM_MEDHI16_PCREL externalsym5\+0x2c
[ ]+58:[ ]+c8000190[ ]+shori 0,r25
[ ]+58:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym5\+0x30
[ ]+5c:[ ]+c8000190[ ]+shori 0,r25
[ ]+5c:[ ]+R_SH_IMM_LOW16_PCREL externalsym5\+0x34
[ ]+60:[ ]+6bf56440[ ]+ptrel/u r25,tr4
[ ]+64:[ ]+cc000190[ ]+movi 0,r25
[ ]+64:[ ]+R_SH_IMM_HI16_PCREL externalsym6\+0x2c
[ ]+68:[ ]+c8000190[ ]+shori 0,r25
[ ]+68:[ ]+R_SH_IMM_MEDHI16_PCREL externalsym6\+0x30
[ ]+6c:[ ]+c8000190[ ]+shori 0,r25
[ ]+6c:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym6\+0x34
[ ]+70:[ ]+c8000190[ ]+shori 0,r25
[ ]+70:[ ]+R_SH_IMM_LOW16_PCREL externalsym6\+0x38
[ ]+74:[ ]+6bf56430[ ]+ptrel/u r25,tr3
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi32-2.d
0,0 → 1,36
#as: --isa=shmedia --abi=32
#objdump: -dr
#source: movi-2.s
#name: MOVI expansion of local symbols with relocs, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <start>:
[ ]+0:[ ]+cc000210[ ]+movi 0,r33
[ ]+0:[ ]+R_SH_IMM_MEDLOW16 \.text\+0x39
[ ]+4:[ ]+c8000210[ ]+shori 0,r33
[ ]+4:[ ]+R_SH_IMM_LOW16 \.text\+0x39
[ ]+8:[ ]+cc000360[ ]+movi 0,r54
[ ]+8:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x2c
[ ]+c:[ ]+c8000360[ ]+shori 0,r54
[ ]+c:[ ]+R_SH_IMM_LOW16 \.data\+0x2c
[ ]+10:[ ]+cc0000f0[ ]+movi 0,r15
[ ]+10:[ ]+R_SH_IMM_MEDLOW16 \.text\.other\+0x35
[ ]+14:[ ]+c80000f0[ ]+shori 0,r15
[ ]+14:[ ]+R_SH_IMM_LOW16 \.text\.other\+0x35
 
0+18 <forw>:
[ ]+18:[ ]+cc000190[ ]+movi 0,r25
[ ]+18:[ ]+R_SH_IMM_MEDLOW16 \.data\.other\+0x38
[ ]+1c:[ ]+c8000190[ ]+shori 0,r25
[ ]+1c:[ ]+R_SH_IMM_LOW16 \.data\.other\+0x38
Disassembly of section \.text\.other:
 
0+ <forwdummylabel>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
0+8 <forwothertext>:
[ ]+8:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-pt32-cmd1.s
0,0 → 1,10
! Check command-line error checking. The option -expand-pt32 is only valid
! with -abi=64
 
! { dg-do assemble }
! { dg-options "-expand-pt32" }
! { dg-error ".* only valid with -abi=64" "" { target sh64-*-* } 0 }
 
.text
start:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-noexp-cmd1.s
0,0 → 1,10
! Check command-line error checking. The option -no-expand is not valid
! unless SHcompact/SHmedia is specified.
 
! { dg-do assemble }
! { dg-options "-no-expand" }
! { dg-error ".* only valid with SHcompact or SHmedia" "" { target sh64-*-elf* } 0 }
 
.text
start:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt-1.d
0,0 → 1,26
#as: --isa=shmedia
#objdump: -dr
#name: Basic SHmedia PT and PTA instructions.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
[0]+4 <start1>:
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
[0]+8 <start4>:
[ ]+8:[ ]+ebfffe50[ ]+pta/l 4 <start1>,tr5
[ ]+c:[ ]+6ff0fff0[ ]+nop
[ ]+10:[ ]+e8000a70[ ]+pta/l 18 <start2>,tr7
[ ]+14:[ ]+6ff0fff0[ ]+nop
 
[0]+18 <start2>:
[ ]+18:[ ]+e8000a40[ ]+pta/l 20 <start3>,tr4
[ ]+1c:[ ]+6ff0fff0[ ]+nop
 
[0]+20 <start3>:
[ ]+20:[ ]+ebffea30[ ]+pta/l 8 <start4>,tr3
[ ]+24:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift32-3.d
0,0 → 1,14
#as: --abi=32
#objdump: -dr
#source: shift-3.s
#name: Shift expression, local but undefined symbol, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000010[ ]+movi 0,r1
[ ]+0:[ ]+R_SH_IMM_LOW16 \.LC0
[ ]+4:[ ]+cc000030[ ]+movi 0,r3
[ ]+4:[ ]+R_SH_IMM_MEDLOW16 \.LC0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/syntax-1.d
0,0 → 1,157
#as: --isa=shmedia --abi=64 --no-exp
#objdump: -d
#name: Minimum SH64 Syntax Support.
 
.*: file format elf64-sh64.*
 
Disassembly of section .text:
 
0000000000000000 <.*>:
0: 88100410 ld.l r1,4,r1
4: 88100410 ld.l r1,4,r1
8: e8003a00 pta/l 40 <.*>,tr0
c: e8003600 pta/l 40 <.*>,tr0
10: e8003000 pta/u 40 <.*>,tr0
14: e8002c00 pta/u 40 <.*>,tr0
18: e8002a00 pta/l 40 <.*>,tr0
1c: e8002600 pta/l 40 <.*>,tr0
20: ec002000 ptb/u 40 <.*>,tr0
24: ec001c00 ptb/u 40 <.*>,tr0
28: ec001a00 ptb/l 40 <.*>,tr0
2c: ec001600 ptb/l 40 <.*>,tr0
30: e8001200 pta/l 40 <.*>,tr0
34: e8000e00 pta/l 40 <.*>,tr0
38: ec000a00 ptb/l 40 <.*>,tr0
3c: ec000600 ptb/l 40 <.*>,tr0
40: 040983f0 or r0,r32,r63
44: 240ffc00 getcon sr,r0
48: 27fffc00 getcon usr,r0
4c: 4405fc00 gettr tr0,r0
50: 4475fc00 gettr tr7,r0
54: 380003f0 fmov.s fr0,fr63
58: 380103e0 fmov.d dr0,dr62
5c: 140e0000 ftrv.s mtrx0,fv0,fv0
60: 170ef3c0 ftrv.s mtrx48,fv60,fv60
64: 240ffc00 getcon sr,r0
68: 241ffc00 getcon ssr,r0
6c: 242ffc00 getcon pssr,r0
70: 244ffc00 getcon intevt,r0
74: 245ffc00 getcon expevt,r0
78: 246ffc00 getcon pexpevt,r0
7c: 247ffc00 getcon tra,r0
80: 248ffc00 getcon spc,r0
84: 249ffc00 getcon pspc,r0
88: 24affc00 getcon resvec,r0
8c: 24bffc00 getcon vbr,r0
90: 24dffc00 getcon tea,r0
94: 250ffc00 getcon dcr,r0
98: 251ffc00 getcon kcr0,r0
9c: 252ffc00 getcon kcr1,r0
a0: 27effc00 getcon ctc,r0
a4: 27fffc00 getcon usr,r0
 
00000000000000a8 <.*>:
a8: e0 04 mov #4,r0
aa: 00 09 nop
 
00000000000000ac <.*>:
ac: cc001000 movi 4,r0
 
00000000000000b0 <.*>:
b0: 50 02 mov.l @\(8,r0\),r0
b2: 00 09 nop
 
00000000000000b4 <.*>:
b4: b0000400 ld.uw r0,2,r0
b8: 84000400 ld.w r0,2,r0
bc: a4000400 st.w r0,2,r0
c0: 88000400 ld.l r0,4,r0
c4: a8000400 st.l r0,4,r0
c8: 94000400 fld.s r0,4,fr0
cc: b4000400 fst.s r0,4,fr0
d0: e8000600 pta/l d4 <.*>,tr0
d4: ec000a00 ptb/l dc <.*>,tr0
d8: 8c000400 ld.q r0,8,r0
dc: ac000400 st.q r0,8,r0
e0: 9c000400 fld.d r0,8,dr0
e4: bc000400 fst.d r0,8,dr0
e8: 98000400 fld.p r0,8,fp0
ec: b8000400 fst.p r0,8,fp0
f0: e00407f0 alloco r0,32
f4: e00507f0 icbi r0,32
f8: e00907f0 ocbi r0,32
fc: e00807f0 ocbp r0,32
100: e00c07f0 ocbwb r0,32
104: e00107f0 prefi r0,32
 
0000000000000108 <.*>:
108: 90 01 mov.w 10e <.*>,r0 ! 8101
10a: 85 01 mov.w @\(2,r0\),r0
10c: c5 01 mov.w @\(2,gbr\),r0
10e: 81 01 mov.w r0,@\(2,r0\)
110: c1 01 mov.w r0,@\(2,gbr\)
112: 8b 01 bf 118 <.*>
114: 89 01 bt 11a <.*>
116: a0 01 bra 11c <.*>
118: b0 01 bsr 11e <.*>
11a: d0 00 mov.l 11c <.*>,r0 ! 5001c601
11c: 50 01 mov.l @\(4,r0\),r0
11e: c6 01 mov.l @\(4,gbr\),r0
120: c7 01 mova 128 <.*>,r0
122: 10 01 mov.l r0,@\(4,r0\)
124: c2 01 mov.l r0,@\(4,gbr\)
126: 00 09 nop
 
0000000000000128 <.*>:
128: 00000139 .long 0x00000139
12c: 0000013d .long 0x0000013d
130: 00000138 .long 0x00000138
134: 00000138 .long 0x00000138
 
0000000000000138 <.*>:
138: 00 00 .word 0x0000
13a: 01 40 .word 0x0140
13c: 00 00 .word 0x0000
13e: 01 61 .word 0x0161
 
0000000000000140 <.*>:
140: cc000000 movi 0,r0
144: c8000000 shori 0,r0
148: 6bf10200 ptabs/l r0,tr0
14c: 4401fd20 blink tr0,r18
150: cc000000 movi 0,r0
154: c8000000 shori 0,r0
158: 6bf10200 ptabs/l r0,tr0
15c: 4401fd20 blink tr0,r18
160: cfff7000 movi -36,r0
164: cfffe400 movi -7,r0
168: ebfffa00 pta/l 160 <.*>,tr0
 
000000000000016c <.*>:
16c: 0000016d .long 0x0000016d
 
0000000000000170 <.*>:
170: 00000171 .long 0x00000171
174: cfffd000 movi -12,r0
178: cfffc000 movi -16,r0
 
000000000000017c <.*>:
17c: c7 01 mova 184 <.*>,r0
17e: 60 12 mov.l @r1,r0
180: 30 1c add r1,r0
182: 00 03 bsrf r0
 
0000000000000184 <.*>:
184: 00 00 .word 0x0000
186: 00 05 mov.w r0,@\(r0,r0\)
 
0000000000000188 <.*>:
188: cc002400 movi 9,r0
18c: cc001c00 movi 7,r0
190: cc004000 movi 16,r0
194: cc001000 movi 4,r0
198: cffff800 movi -2,r0
19c: cc000400 movi 1,r0
1a0: cc002400 movi 9,r0
1a4: cc006000 movi 24,r0
1a8: cc002000 movi 8,r0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel32-1.d
0,0 → 1,86
#as: --abi=32
#objdump: -sr
#source: rel-1.s
#name: MOVI: PC-relative relocs, 32-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET *TYPE *VALUE
0+08 R_SH_IMM_LOW16_PCREL \.data\+0x0+8
0+0c R_SH_IMM_LOW16_PCREL \.data\+0x0+c
0+10 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+10
0+1c R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+20 R_SH_IMM_LOW16_PCREL \.data\+0x0+28
0+24 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+24
0+30 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+9
0+34 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+d
0+38 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+11
0+44 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+29
0+48 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+29
0+4c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+25
0+58 R_SH_IMM_LOW16_PCREL extern2
0+5c R_SH_IMM_LOW16_PCREL extern3
0+60 R_SH_IMM_MEDLOW16_PCREL extern4
0+6c R_SH_IMM_LOW16_PCREL extern6\+0x0+10
0+70 R_SH_IMM_LOW16_PCREL extern7\+0x0+c
0+74 R_SH_IMM_MEDLOW16_PCREL extern8\+0x0+4
0+80 R_SH_IMM_LOW16_PCREL gdata2
0+84 R_SH_IMM_LOW16_PCREL gdata3
0+88 R_SH_IMM_MEDLOW16_PCREL gdata4
0+94 R_SH_IMM_LOW16_PCREL gdata6\+0x0+10
0+98 R_SH_IMM_LOW16_PCREL gdata7\+0x0+c
0+9c R_SH_IMM_MEDLOW16_PCREL gdata8\+0x0+4
0+a8 R_SH_IMM_LOW16_PCREL gothertext2
0+ac R_SH_IMM_LOW16_PCREL gothertext3
0+b0 R_SH_IMM_MEDLOW16_PCREL gothertext4
0+bc R_SH_IMM_LOW16_PCREL gothertext6\+0x0+10
0+c0 R_SH_IMM_LOW16_PCREL gothertext7\+0x0+c
0+c4 R_SH_IMM_MEDLOW16_PCREL gothertext8\+0x0+4
0+00 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+4
0+04 R_SH_IMM_LOW16_PCREL \.data\+0x0+8
0+14 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+1c
0+18 R_SH_IMM_LOW16_PCREL \.data\+0x0+20
0+28 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+5
0+2c R_SH_IMM_LOW16_PCREL \.othertext\+0x0+9
0+3c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+1d
0+40 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+21
0+50 R_SH_IMM_MEDLOW16_PCREL extern1
0+54 R_SH_IMM_LOW16_PCREL extern1\+0x0+4
0+64 R_SH_IMM_MEDLOW16_PCREL extern5\+0x0+8
0+68 R_SH_IMM_LOW16_PCREL extern5\+0x0+c
0+78 R_SH_IMM_MEDLOW16_PCREL gdata1
0+7c R_SH_IMM_LOW16_PCREL gdata1\+0x0+4
0+8c R_SH_IMM_MEDLOW16_PCREL gdata5\+0x0+8
0+90 R_SH_IMM_LOW16_PCREL gdata5\+0x0+c
0+a0 R_SH_IMM_MEDLOW16_PCREL gothertext1
0+a4 R_SH_IMM_LOW16_PCREL gothertext1\+0x0+4
0+b4 R_SH_IMM_MEDLOW16_PCREL gothertext5\+0x0+8
0+b8 R_SH_IMM_LOW16_PCREL gothertext5\+0x0+c
 
Contents of section \.text:
0000 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
0010 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
0020 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0030 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0040 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
0050 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
0060 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
0070 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0080 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0090 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
00a0 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
00b0 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
00c0 cc0000a0 cc0000a0 .*
Contents of section \.data:
0000 00000000 00000000 00000000 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 00000000 00000000 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 .*
Contents of section \.othertext:
0000 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0040 6ff0fff0 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi-2.s
0,0 → 1,28
! Check MOVI expansion of local symbols that should get segment-relative
! relocations.
.text
start:
movi forw + 32,r33
movi forwdata + 40,r54
movi forwothertext + 44,r15
forw:
movi forwotherdata + 48,r25
 
.data
.long 0 ! To get a non-zero segment offset for "forwdata".
forwdata:
.long 0
 
.section .text.other,"ax"
forwdummylabel: ! Needed to hang a marker that this section is SHmedia.
nop
nop
forwothertext:
nop
 
.section .data.other,"aw"
.long 0
.long 0
forwotherdata:
.long 0
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/immexpr64-1.d
0,0 → 1,68
#as: --abi=64
#objdump: -dr
#source: immexpr1.s
#name: Immediate resolved operands, 64-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <start>:
[ ]+0:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+4:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+8:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+c:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+10:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+14:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+18:[ ]+d327d680[ ]+addi r50,501,r40
[ ]+1c:[ ]+d327da80[ ]+addi r50,502,r40
[ ]+20:[ ]+d3282e80[ ]+addi r50,-501,r40
[ ]+24:[ ]+d3282a80[ ]+addi r50,-502,r40
[ ]+28:[ ]+b1e7d280[ ]+ld\.uw r30,1000,r40
[ ]+2c:[ ]+b1e3e680[ ]+ld\.uw r30,498,r40
[ ]+30:[ ]+b1e3ee80[ ]+ld\.uw r30,502,r40
[ ]+34:[ ]+b327d140[ ]+ld\.uw r50,1000,r20
[ ]+38:[ ]+b1e83280[ ]+ld\.uw r30,-1000,r40
[ ]+3c:[ ]+b1ec1e80[ ]+ld\.uw r30,-498,r40
[ ]+40:[ ]+b1ec1680[ ]+ld\.uw r30,-502,r40
[ ]+44:[ ]+b3283140[ ]+ld\.uw r50,-1000,r20
[ ]+48:[ ]+8b27d140[ ]+ld\.l r50,2000,r20
[ ]+4c:[ ]+8b27d540[ ]+ld\.l r50,2004,r20
[ ]+50:[ ]+8b27cd40[ ]+ld\.l r50,1996,r20
[ ]+54:[ ]+8b27d140[ ]+ld\.l r50,2000,r20
[ ]+58:[ ]+8b27d540[ ]+ld\.l r50,2004,r20
[ ]+5c:[ ]+8b27cd40[ ]+ld\.l r50,1996,r20
[ ]+60:[ ]+8b283140[ ]+ld\.l r50,-2000,r20
[ ]+64:[ ]+8b282d40[ ]+ld\.l r50,-2004,r20
[ ]+68:[ ]+8b283540[ ]+ld\.l r50,-1996,r20
[ ]+6c:[ ]+8b283140[ ]+ld\.l r50,-2000,r20
[ ]+70:[ ]+8b283540[ ]+ld\.l r50,-1996,r20
[ ]+74:[ ]+8b282d40[ ]+ld\.l r50,-2004,r20
[ ]+78:[ ]+6ff0fff0[ ]+nop
[ ]+7c:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+80:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+84:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+88:[ ]+d327d680[ ]+addi r50,501,r40
[ ]+8c:[ ]+d327da80[ ]+addi r50,502,r40
[ ]+90:[ ]+b1e7d280[ ]+ld\.uw r30,1000,r40
[ ]+94:[ ]+b1e3e680[ ]+ld\.uw r30,498,r40
[ ]+98:[ ]+b1e3ee80[ ]+ld\.uw r30,502,r40
[ ]+9c:[ ]+b327d140[ ]+ld\.uw r50,1000,r20
[ ]+a0:[ ]+8b27d140[ ]+ld\.l r50,2000,r20
[ ]+a4:[ ]+8b27d540[ ]+ld\.l r50,2004,r20
[ ]+a8:[ ]+8b27cd40[ ]+ld\.l r50,1996,r20
[ ]+ac:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+b0:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+b4:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+b8:[ ]+d3282e80[ ]+addi r50,-501,r40
[ ]+bc:[ ]+d3282a80[ ]+addi r50,-502,r40
[ ]+c0:[ ]+b1e83280[ ]+ld\.uw r30,-1000,r40
[ ]+c4:[ ]+b1ec1e80[ ]+ld\.uw r30,-498,r40
[ ]+c8:[ ]+b1ec1680[ ]+ld\.uw r30,-502,r40
[ ]+cc:[ ]+b3283140[ ]+ld\.uw r50,-1000,r20
[ ]+d0:[ ]+8b283140[ ]+ld\.l r50,-2000,r20
[ ]+d4:[ ]+8b282d40[ ]+ld\.l r50,-2004,r20
[ ]+d8:[ ]+8b283540[ ]+ld\.l r50,-1996,r20
[ ]+dc:[ ]+6ff0fff0[ ]+nop
[ ]\.\.\.
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel32-5.d
0,0 → 1,30
#as: --abi=32
#objdump: -sr
#source: rel-5.s
#name: MOVI: PC-relative reloc within .text, 32-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET *TYPE *VALUE
0+3c R_SH_IMM_LOW16_PCREL gstart6\+0x0+18
0+40 R_SH_IMM_MEDLOW16_PCREL gstart7\+0x0+20
0+1c R_SH_IMM_MEDLOW16_PCREL gstart2\+0x0+8
0+20 R_SH_IMM_LOW16_PCREL gstart2\+0x0+c
0+24 R_SH_IMM_MEDLOW16_PCREL gstart3\+0x0+3
0+28 R_SH_IMM_LOW16_PCREL gstart3\+0x0+7
0+2c R_SH_IMM_MEDLOW16_PCREL gstart4\+0x0+8
0+30 R_SH_IMM_LOW16_PCREL gstart4\+0x0+c
0+34 R_SH_IMM_MEDLOW16_PCREL gstart5\+0x0+b
0+38 R_SH_IMM_LOW16_PCREL gstart5\+0x0+f
 
Contents of section \.text:
0000 6ff0fff0 cc0125e0 cc0111e0 cc0121e0 .*
0010 cc012de0 cc016280 cc000320 cc0001e0 .*
0020 c80001e0 cc0001e0 c80001e0 cc0001e0 .*
0030 c80001e0 cc0001e0 c80001e0 cc000280 .*
0040 cc000320 6ff0fff0 6ff0fff0 6ff0fff0 .*
0050 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0060 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0070 6ff0fff0 .*
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/eh-1.d
0,0 → 1,14
#as: --abi=32 --isa=shmedia
#objdump: -sr
#source: eh-1.s
#name: PR gas/6043
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.eh_frame\]:
OFFSET *TYPE *VALUE
00000000 R_SH_64_PCREL \.text\+0x00000005
 
 
Contents of section .eh_frame:
0000 00000000 00000000 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift-2.s
0,0 → 1,34
! Check that shift expressions translate to the proper reloc for MOVI and
! SHORI for local and external symbols. This is the 64-bit subset.
.text
.mode SHmedia
start:
movi (localsym >> 32) & 65535,r4
movi (localsym >> 48) & 65535,r4
 
movi ((localsym + 44) >> 32) & 65535,r4
movi ((localsym + 43) >> 48) & 65535,r4
 
movi (externsym >> 32) & 65535,r4
movi (externsym >> 48) & 65535,r4
 
movi ((externsym + 41) >> 32) & 65535,r4
movi ((externsym + 42) >> 48) & 65535,r4
 
shori (localsym >> 32) & 65535,r4
shori (localsym >> 48) & 65535,r4
 
shori ((localsym + 44) >> 32) & 65535,r4
shori ((localsym + 43) >> 48) & 65535,r4
 
shori (externsym >> 32) & 65535,r4
shori (externsym >> 48) & 65535,r4
 
shori ((externsym + 41) >> 32) & 65535,r4
shori ((externsym + 42) >> 48) & 65535,r4
 
.data
! Just make localsym have a non-zero offset into .data.
.long 0
localsym:
.long 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/endian-1.d
0,0 → 1,9
#as: --isa=shmedia --abi=64 --no-exp -little
#objdump: -s
#name: SH64 Little Endian
 
.*: file format elf64-sh64.*
 
Contents of section .text:
0000 00d048cc 78563412 34120000.*
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel-1.s
0,0 → 1,137
! Test pc-relative relocations in MOVI and MOVI expansion.
 
.mode SHmedia
.text
start:
movi data1 - datalabel $,r10
movi (data2 - datalabel $) & 65535,r10
movi ((data3 - datalabel $) >> 0) & 65535,r10
movi ((data4 - datalabel $) >> 16) & 65535,r10
movi data5 + 8 - datalabel $,r10
movi (data6 + 16 - datalabel $) & 65535,r10
movi ((data7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((data8 + 4 - datalabel $) >> 16) & 65535,r10
 
movi othertext1 - datalabel $,r10
movi (othertext2 - datalabel $) & 65535,r10
movi ((othertext3 - datalabel $) >> 0) & 65535,r10
movi ((othertext4 - datalabel $) >> 16) & 65535,r10
movi othertext5 + 8 - datalabel $,r10
movi (othertext6 + 16 - datalabel $) & 65535,r10
movi ((othertext7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((othertext8 + 4 - datalabel $) >> 16) & 65535,r10
 
movi extern1 - datalabel $,r10
movi (extern2 - datalabel $) & 65535,r10
movi ((extern3 - datalabel $) >> 0) & 65535,r10
movi ((extern4 - datalabel $) >> 16) & 65535,r10
movi extern5 + 8 - datalabel $,r10
movi (extern6 + 16 - datalabel $) & 65535,r10
movi ((extern7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((extern8 + 4 - datalabel $) >> 16) & 65535,r10
 
movi gdata1 - datalabel $,r10
movi (gdata2 - datalabel $) & 65535,r10
movi ((gdata3 - datalabel $) >> 0) & 65535,r10
movi ((gdata4 - datalabel $) >> 16) & 65535,r10
movi gdata5 + 8 - datalabel $,r10
movi (gdata6 + 16 - datalabel $) & 65535,r10
movi ((gdata7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((gdata8 + 4 - datalabel $) >> 16) & 65535,r10
 
movi gothertext1 - datalabel $,r10
movi (gothertext2 - datalabel $) & 65535,r10
movi ((gothertext3 - datalabel $) >> 0) & 65535,r10
movi ((gothertext4 - datalabel $) >> 16) & 65535,r10
movi gothertext5 + 8 - datalabel $,r10
movi (gothertext6 + 16 - datalabel $) & 65535,r10
movi ((gothertext7 + 12 - datalabel $) >> 0) & 65535,r10
movi ((gothertext8 + 4 - datalabel $) >> 16) & 65535,r10
 
.section .othertext,"ax"
x:
nop
othertext1:
nop
othertext2:
nop
othertext3:
nop
othertext4:
nop
othertext5:
nop
othertext6:
nop
othertext7:
nop
othertext8:
nop
.global gothertext1
gothertext1:
nop
.global gothertext2
gothertext2:
nop
.global gothertext3
gothertext3:
nop
.global gothertext4
gothertext4:
nop
.global gothertext5
gothertext5:
nop
.global gothertext6
gothertext6:
nop
.global gothertext7
gothertext7:
nop
.global gothertext8
gothertext8:
nop
 
.data
y:
.long 0
data1:
.long 0
data2:
.long 0
data3:
.long 0
data4:
.long 0
data5:
.long 0
data6:
.long 0
data7:
.long 0
data8:
.long 0
.global gdata1
gdata1:
.long 0
.global gdata2
gdata2:
.long 0
.global gdata3
gdata3:
.long 0
.global gdata4
gdata4:
.long 0
.global gdata5
gdata5:
.long 0
.global gdata6
gdata6:
.long 0
.global gdata7
gdata7:
.long 0
.global gdata8
gdata8:
.long 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt-1.s
0,0 → 1,17
! Check simple use of PT/PTA.
.text
start:
nop
start1:
nop
start4:
pt start1,tr5
nop
pt start2,tr7
nop
start2:
pta start3,tr4
nop
start3:
pta start4,tr3
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel-5.s
0,0 → 1,48
! Test MOVI pc-relative expansion within text section.
 
.text
.mode SHmedia
start:
nop
movi start2+8 - datalabel $,r30
movi start3+4 - $,r30
movi datalabel start4 + 8 - datalabel $,r30
movi datalabel start5 + 12 - $,r30
movi (datalabel start6 + 24 - datalabel $) & 65535,r40
movi ((datalabel start7 + 32 - datalabel $) >> 16) & 65535,r50
movi gstart2+8 - datalabel $,r30
movi gstart3+4 - $,r30
movi datalabel gstart4 + 8 - datalabel $,r30
movi datalabel gstart5 + 12 - $,r30
movi (datalabel gstart6 + 24 - datalabel $) & 65535,r40
movi ((datalabel gstart7 + 32 - datalabel $) >> 16) & 65535,r50
start2:
nop
start3:
nop
start4:
nop
start5:
nop
start6:
nop
start7:
nop
.global gstart2
gstart2:
nop
.global gstart3
gstart3:
nop
.global gstart4
gstart4:
nop
.global gstart5
gstart5:
nop
.global gstart6
gstart6:
nop
.global gstart7
gstart7:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptext64-noexp-1.d
0,0 → 1,22
#as: --isa=shmedia --abi=64 -no-expand
#source: ptext-1.s
#objdump: -dr
#name: PT, PTA, PTB non-expansion for external symbols, 64-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+e8000250[ ]+pta/l 0 <start>,tr5
[ ]+0:[ ]+R_SH_PT_16 externalsym1\+0x28
[ ]+4:[ ]+e8000640[ ]+pta/l 8 <start\+0x8>,tr4
[ ]+4:[ ]+R_SH_PT_16 externalsym2\+0x2c
[ ]+8:[ ]+ec000630[ ]+ptb/l c <start\+0xc>,tr3
[ ]+8:[ ]+R_SH_PT_16 externalsym3\+0x30
[ ]+c:[ ]+e8000050[ ]+pta/u c <start\+0xc>,tr5
[ ]+c:[ ]+R_SH_PT_16 externalsym4\+0x34
[ ]+10:[ ]+e8000440[ ]+pta/u 14 <start\+0x14>,tr4
[ ]+10:[ ]+R_SH_PT_16 externalsym5\+0x38
[ ]+14:[ ]+ec000430[ ]+ptb/u 18 <start\+0x18>,tr3
[ ]+14:[ ]+R_SH_PT_16 externalsym6\+0x3c
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/syntax-1.s
0,0 → 1,199
! Verify that minimum support is provided as per SH-5/ST50-047-02.
 
.text
.mode shmedia
start:
 
! Both all-upper and all-lower must be supported. PTA/PTB without /L
! or /U is equivalent to with /L
 
ld.l r1,4,r1
LD.L r1,4,r1
pta/l .L1,tr0
PTA/L .L1,tr0
pta/u .L1,tr0
PTA/U .L1,tr0
pta/l .L1,tr0
PTA/L .L1,tr0
ptb/u .L2,tr0
PTB/U .L2,tr0
ptb/l .L2,tr0
PTB/L .L2,tr0
pta .L1,tr0
PTA .L1,tr0
ptb .L2,tr0
PTB .L2,tr0
.L1:
.mode shcompact
.L2:
.align 2
.mode shmedia
 
! All register names accepted, either case.
 
or r0,r32,r63
GETCON CR0,R0
getcon cr63,r0
GETTR TR0,R0
gettr tr7,r0
FMOV.S FR0,FR63
fmov.d dr0,dr62
FTRV.S MTRX0,FV0,fv0
ftrv.s mtrx48,FV60,FV60
 
! All control register names
 
getcon sr,r0
getcon ssr,r0
getcon pssr,r0
getcon intevt,r0
getcon expevt,r0
getcon pexpevt,r0
getcon tra,r0
getcon spc,r0
getcon pspc,r0
getcon resvec,r0
getcon vbr,r0
getcon tea,r0
getcon dcr,r0
getcon kcr0,r0
getcon kcr1,r0
getcon ctc,r0
getcon usr,r0
 
! immediates
 
.mode shcompact
s1:
mov #4,r0
 
.align 2
.mode shmedia
s2:
movi 4,r0
 
! Scaled operands - user gives scaled value
 
.mode shcompact
s3:
mov.l @(8,r0),r0
 
.align 2
.mode shmedia
s4:
ld.uw r0,2,r0
ld.w r0,2,r0
st.w r0,2,r0
ld.l r0,4,r0
st.l r0,4,r0
fld.s r0,4,fr0
fst.s r0,4,fr0
pta .+4,tr0
ptb .+7,tr0
ld.q r0,8,r0
st.q r0,8,r0
fld.d r0,8,dr0
fst.d r0,8,dr0
fld.p r0,8,fp0
fst.p r0,8,fp0
alloco r0,32
icbi r0,32
ocbi r0,32
ocbp r0,32
ocbwb r0,32
prefi r0,32
 
.mode shcompact
s5:
mov.w @(6,pc),r0
mov.w @(2,r0),r0
mov.w @(2,gbr),r0
mov.w r0,@(2,r0)
mov.w r0,@(2,gbr)
bf .+6
bt .+6
bra .+6
bsr .+6
mov.l @(2,pc),r0
mov.l @(4,r0),r0
mov.l @(4,gbr),r0
mova @(8,pc),r0
mov.l r0,@(4,r0)
mov.l r0,@(4,gbr)
 
! branchlabel vs datalabel
 
.align 2
.mode shmedia
s6:
.long .L3
.long .L3 + 4
.long datalabel .L3
.long DATALABEL .L3
.L3:
.mode shcompact
 
s7:
.long .L4
.long .L5
.L4:
 
.align 2
.mode shmedia
s8:
 
movi (.L4 >> 16) & 65535,r0
shori .L4 & 65535, r0
ptabs r0,tr0
blink tr0,r18
 
movi (.L5 >> 16) & 65535,r0
shori .L5 & 65535, r0
ptabs r0,tr0
blink tr0,r18
.L5:
 
movi (.L4-DATALABEL .L6), r0
.L6:
movi (.L5-DATALABEL .L7), r0
.L7:
 
pt .L5,tr0
 
! Expressions
 
! Symbols
 
abcdefghijklmnopqrstuvwxyz0123456789_:
.long abcdefghijklmnopqrstuvwxyz0123456789_
_x:
.long _x
 
! program counter
 
movi .L7-$,r0
.L8: movi .L7-.L8,r0
 
.mode shcompact
s9:
mova @(litpool-$,pc), r0
mov.l @r1,r0
add r1,r0
bsrf r0
litpool:
.long s10 - DATALABEL $
 
! operators
 
.align 2
.mode shmedia
s10:
movi 8+1,r0
movi 8-1,r0
movi 8<<1,r0
movi 8>>1,r0
movi ~1,r0
movi 5&3,r0
movi 8|1,r0
movi 8*3,r0
movi 24/3,r0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptext32-1.d
0,0 → 1,40
#as: --isa=shmedia --abi=32
#source: ptext-1.s
#objdump: -dr
#name: PT, PTA, PTB expansion for external symbols, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000190[ ]+movi 0,r25
[ ]+0:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym1\+0x20
[ ]+4:[ ]+c8000190[ ]+shori 0,r25
[ ]+4:[ ]+R_SH_IMM_LOW16_PCREL externalsym1\+0x24
[ ]+8:[ ]+6bf56650[ ]+ptrel/l r25,tr5
[ ]+c:[ ]+cc000190[ ]+movi 0,r25
[ ]+c:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym2\+0x24
[ ]+10:[ ]+c8000190[ ]+shori 0,r25
[ ]+10:[ ]+R_SH_IMM_LOW16_PCREL externalsym2\+0x28
[ ]+14:[ ]+6bf56640[ ]+ptrel/l r25,tr4
[ ]+18:[ ]+cc000190[ ]+movi 0,r25
[ ]+18:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym3\+0x28
[ ]+1c:[ ]+c8000190[ ]+shori 0,r25
[ ]+1c:[ ]+R_SH_IMM_LOW16_PCREL externalsym3\+0x2c
[ ]+20:[ ]+6bf56630[ ]+ptrel/l r25,tr3
[ ]+24:[ ]+cc000190[ ]+movi 0,r25
[ ]+24:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym4\+0x2c
[ ]+28:[ ]+c8000190[ ]+shori 0,r25
[ ]+28:[ ]+R_SH_IMM_LOW16_PCREL externalsym4\+0x30
[ ]+2c:[ ]+6bf56450[ ]+ptrel/u r25,tr5
[ ]+30:[ ]+cc000190[ ]+movi 0,r25
[ ]+30:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym5\+0x30
[ ]+34:[ ]+c8000190[ ]+shori 0,r25
[ ]+34:[ ]+R_SH_IMM_LOW16_PCREL externalsym5\+0x34
[ ]+38:[ ]+6bf56440[ ]+ptrel/u r25,tr4
[ ]+3c:[ ]+cc000190[ ]+movi 0,r25
[ ]+3c:[ ]+R_SH_IMM_MEDLOW16_PCREL externalsym6\+0x34
[ ]+40:[ ]+c8000190[ ]+shori 0,r25
[ ]+40:[ ]+R_SH_IMM_LOW16_PCREL externalsym6\+0x38
[ ]+44:[ ]+6bf56430[ ]+ptrel/u r25,tr3
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift32-noexp-3.d
0,0 → 1,14
#as: --abi=32 -no-expand
#objdump: -dr
#source: shift-3.s
#name: Shift expression, local but undefined symbol, 32-bit ABI with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cc000010[ ]+movi 0,r1
[ ]+0:[ ]+R_SH_IMM_LOW16 \.LC0
[ ]+4:[ ]+cc000030[ ]+movi 0,r3
[ ]+4:[ ]+R_SH_IMM_MEDLOW16 \.LC0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/eh-1.s
0,0 → 1,7
! PR gas/6043
 
.text
.LFB1:
.section .eh_frame,"a",@progbits
.LASFDE1:
.uaquad .LFB1-.
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/endian-1.s
0,0 → 1,7
.text
.mode shmedia
start:
 
movi 0x1234,r0
.long 0x12345678
.word 0x1234, 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt32-noexp-2.d
0,0 → 1,34
#as: --isa=shmedia -abi=32 -no-expand
#objdump: -dr
#source: pt-2.s
#name: Inter-segment PT, 32-bit with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
0+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start1>:
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
0+8 <start4>:
[ ]+8:[ ]+ebfffe50[ ]+pta/l 4 <start1>,tr5
[ ]+c:[ ]+6ff0fff0[ ]+nop
[ ]+10:[ ]+e8000270[ ]+pta/l 10 <start4\+0x8>,tr7
[ ]+10:[ ]+R_SH_PT_16 \.text\.other\+0x5
[ ]+14:[ ]+6ff0fff0[ ]+nop
 
Disassembly of section \.text\.other:
 
0+ <dummylabel>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start2>:
[ ]+4:[ ]+e8000a40[ ]+pta/l c <start3>,tr4
[ ]+8:[ ]+6ff0fff0[ ]+nop
 
0+c <start3>:
[ ]+c:[ ]+e8000630[ ]+pta/l 10 <start3\+0x4>,tr3
[ ]+c:[ ]R_SH_PT_16 \.text\+0x9
[ ]+10:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange1-2.d
0,0 → 1,108
#as: --abi=32 --isa=SHcompact -shcompact-const-crange
#objdump: -sr
#source: crange1.s
#name: .cranges descriptors including SHcompact constant pool
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.cranges\]:
OFFSET *TYPE *VALUE
0+00 R_SH_DIR32 \.text\.shmediaanddata
0+0a R_SH_DIR32 \.text\.codemix
0+14 R_SH_DIR32 \.text\.codemixconst
0+1e R_SH_DIR32 \.text\.codemixconst
0+28 R_SH_DIR32 \.text\.codemixconst
0+32 R_SH_DIR32 \.text\.codemixconst2
0+3c R_SH_DIR32 \.text\.codemixconst2
0+46 R_SH_DIR32 \.text\.codemixconst2
0+50 R_SH_DIR32 \.text\.codemixconst2
0+5a R_SH_DIR32 \.text\.codemixconst2
0+64 R_SH_DIR32 \.text\.codemixconst2
0+6e R_SH_DIR32 \.text\.codemixconst2
0+78 R_SH_DIR32 \.text\.shmediaanddata
0+82 R_SH_DIR32 \.text\.codemix
0+8c R_SH_DIR32 \.text\.codemixconst
0+96 R_SH_DIR32 \.text\.codemixconst2
 
 
Contents of section \.text:
0000 6ff0fff0 cc00aad0 cc0022e0 6ff0fff0 .*
Contents of section \.text\.compact:
0000 0009e02a 89000009 0009 .*
Contents of section \.text\.shmediaanddata:
0000 cc00aad0 cc0022e0 6ff0fff0 00000014 .*
0010 00000032 .*
Contents of section \.cranges:
0000 00000000 00000008 00030000 00000000 .*
0010 00180003 00000000 0000001c 00030000 .*
0020 001c0000 00200001 0000003c 00000012 .*
0030 00020000 00000000 00240003 00000024 .*
0040 00000028 00010000 004c0000 00160002 .*
0050 00000062 000000d2 00010000 01340000 .*
0060 002c0003 00000160 0000001c 00010000 .*
0070 017c0000 00220002 00000008 0000000c .*
0080 00010000 00180000 000e0002 0000004e .*
0090 0000006e 00010000 019e0000 01320001 .*
Contents of section \.text\.codemix:
0000 cc00aad0 6ff0fff0 6ff0fff0 cc0062e0 .*
0010 6ff0fff0 6ff0fff0 0009e028 00090009 .*
0020 89000009 0009 .*
Contents of section \.text\.codemixconst:
0000 6ff0fff0 cc00aad0 6ff0fff0 6ff0fff0 .*
0010 cc00e2e0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff00000 0000fff0 6ff0fff0 .*
0030 6ff0fff0 00000000 000000b3 0009e02b .*
0040 00090009 89020009 00090009 00090000 .*
0050 00000000 00000000 00000000 00000000 .*
0060 00000000 00000000 00000000 00000000 .*
0070 00000000 00000000 00000000 00000000 .*
0080 00000000 00000000 00000000 00000000 .*
0090 00000000 00000000 00000000 00000000 .*
00a0 00000000 00000000 00000000 00000000 .*
00b0 00000000 00000000 0000007e .*
Contents of section \.text\.codemixconst2:
0000 6ff0fff0 cc00aad0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 cc0122e0 6ff0fff0 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 00000000 00000044 0009e02c .*
0050 00090009 89040009 00090009 00090009 .*
0060 00090009 09000000 00000000 00000000 .*
0070 00000000 00000000 00000000 00000000 .*
0080 00000000 00000000 00000000 00000000 .*
0090 00000000 00000000 00000000 00000000 .*
00a0 00000000 00000000 00000000 00000000 .*
00b0 00000000 00000000 00000000 00000000 .*
00c0 00000000 00000000 00000000 00000000 .*
00d0 00000000 00000000 00000000 00000000 .*
00e0 00000000 00000000 00000000 00000000 .*
00f0 00000000 00000000 00000000 00000000 .*
0100 00000000 00000000 00000000 00000000 .*
0110 00000000 00000000 00000000 00000000 .*
0120 00000000 00000000 00000000 00000000 .*
0130 000000e6 6ff0fff0 cc00aed0 6ff0fff0 .*
0140 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0150 6ff0fff0 6ff0fff0 6ff0fff0 cc0112e0 .*
0160 6ff0fff0 00000000 00000000 00000000 .*
0170 00000000 00000000 00000044 0009e00e .*
0180 00090009 890a0009 00090009 00090009 .*
0190 00090009 00090009 00090009 00090000 .*
01a0 00000000 00000000 00000000 00000000 .*
01b0 00000000 00000000 00000000 00000000 .*
01c0 00000000 00000000 00000000 00000000 .*
01d0 00000000 00000000 00000000 00000000 .*
01e0 00000000 00000000 00000000 00000000 .*
01f0 00000000 00000000 00000000 00000000 .*
0200 00000000 00000000 00000000 00000000 .*
0210 00000000 00000000 00000000 00000000 .*
0220 00000000 00000000 00000000 00000000 .*
0230 00000000 00000000 00000000 00000000 .*
0240 00000000 00000000 00000000 00000000 .*
0250 00000000 00000000 00000000 00000000 .*
0260 00000000 00000000 00000000 00000000 .*
0270 00000000 00000000 00000000 00000000 .*
0280 00000000 00000000 00000000 00000000 .*
0290 00000000 00000000 00000000 00000000 .*
02a0 00000000 00000000 00000000 00000000 .*
02b0 00000000 00000000 00000000 00000000 .*
02c0 00000000 00000000 00000000 00000152 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/immexpr1.s
0,0 → 1,85
! Check that immediate operands with expressions with differences between
! local symbols work for other than 16-bit operands.
 
.text
.mode SHmedia
start:
addi r50,.Lab500 - .Lab1,r40
addi r50,-(.Lab500 - .Lab1),r40
addi r50,(.Lab1000 - .Lab1)/2,r40
addi r50,(.Lab4000 - .Lab1)/8,r40
addi r50,-(.Lab1000 - .Lab1)/2,r40
addi r50,-(.Lab4000 - .Lab1)/8,r40
addi r50,.Lab500 - .Lab1 + 1,r40
addi r50,.Lab500 - .Lab1 + 2,r40
addi r50,-(.Lab500 - .Lab1 + 1),r40
addi r50,-(.Lab500 - .Lab1 + 2),r40
ld.uw r30,.Lab1000 - .Lab1,r40
ld.uw r30,.Lab500 - .Lab1 - 2,r40
ld.uw r30,.Lab500 - .Lab1 + 2,r40
ld.uw r50,(.Lab2000 - .Lab1)/2,r20
ld.uw r30,-(.Lab1000 - .Lab1),r40
ld.uw r30,-(.Lab500 - .Lab1 - 2),r40
ld.uw r30,-(.Lab500 - .Lab1 + 2),r40
ld.uw r50,-(.Lab2000 - .Lab1)/2,r20
ld.l r50,.Lab2000 - .Lab1,r20
ld.l r50,.Lab2000 - .Lab1 + 4,r20
ld.l r50,.Lab2000 - .Lab1 - 4,r20
ld.l r50,(.Lab4000 - .Lab1)/2,r20
ld.l r50,(.Lab4000 - .Lab1)/2 + 4,r20
ld.l r50,(.Lab4000 - .Lab1)/2 - 4,r20
ld.l r50,-(.Lab2000 - .Lab1),r20
ld.l r50,-(.Lab2000 - .Lab1 + 4),r20
ld.l r50,-(.Lab2000 - .Lab1 - 4),r20
ld.l r50,-(.Lab4000 - .Lab1)/2,r20
ld.l r50,-(.Lab4000 - .Lab1)/2 + 4,r20
ld.l r50,-(.Lab4000 - .Lab1)/2 - 4,r20
nop
addi r50,.Lab500t - .Lab1t,r40
addi r50,(.Lab1000t - .Lab1t)/2,r40
addi r50,(.Lab4000t - .Lab1t)/8,r40
addi r50,.Lab500t - .Lab1t + 1,r40
addi r50,.Lab500t - .Lab1t + 2,r40
ld.uw r30,.Lab1000t - .Lab1t,r40
ld.uw r30,.Lab500t - .Lab1t - 2,r40
ld.uw r30,.Lab500t - .Lab1t + 2,r40
ld.uw r50,(.Lab2000t - .Lab1t)/2,r20
ld.l r50,.Lab2000t - .Lab1t,r20
ld.l r50,.Lab2000t - .Lab1t + 4,r20
ld.l r50,.Lab2000t - .Lab1t - 4,r20
addi r50,.Lab500t - .Lab1t,r40
addi r50,-((.Lab1000t - .Lab1t)/2),r40
addi r50,-((.Lab4000t - .Lab1t)/8),r40
addi r50,-(.Lab500t - .Lab1t + 1),r40
addi r50,-(.Lab500t - .Lab1t + 2),r40
ld.uw r30,-(.Lab1000t - .Lab1t),r40
ld.uw r30,-(.Lab500t - .Lab1t - 2),r40
ld.uw r30,-(.Lab500t - .Lab1t + 2),r40
ld.uw r50,-((.Lab2000t - .Lab1t)/2),r20
ld.l r50,-(.Lab2000t - .Lab1t),r20
ld.l r50,-(.Lab2000t - .Lab1t + 4),r20
ld.l r50,-(.Lab2000t - .Lab1t - 4),r20
nop
.long 0
.Lab1t:
.zero 500,0
.Lab500t:
.zero 500,0
.Lab1000t:
.zero 1000,0
.Lab2000t:
.zero 2000,0
.Lab4000t:
 
.data
.long 0
.Lab1:
.zero 500,0
.Lab500:
.zero 500,0
.Lab1000:
.zero 1000,0
.Lab2000:
.zero 2000,0
.Lab4000:
.long 0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/mix-noexp-1.d
0,0 → 1,33
#as: --abi=32 -no-expand
#objdump: -dr
#source: mix-1.s
#name: Mixed-ISA objects with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <start>:
[ ]+0:[ ]+89 01 bt 6 <forw>
[ ]+2:[ ]+c7 00[ ]+mova 4 <start2>,r0
 
0+4 <start2>:
[ ]+4:[ ]+00[ ]+09 nop
 
0+6 <forw>:
[ ]+6:[ ]+00[ ]+09 nop
Disassembly of section \.text\.media:
 
0+ <mediacode>:
[ ]+0:[ ]+ec000640[ ]+ptb/l 4 <mediacode\+0x4>,tr4
[ ]+0:[ ]+R_SH_PT_16[ ]+\.text\+0x6
[ ]+4:[ ]+e8000250[ ]+pta/l 4 <mediacode\+0x4>,tr5
[ ]+4:[ ]+R_SH_PT_16[ ]+\.text\+0x4
 
0+8 <mediacode2>:
[ ]+8:[ ]+cc000360[ ]+movi 0,r54
[ ]+8:[ ]+R_SH_IMMS16[ ]+\.text\+0x4
[ ]+c:[ ]+cc0002d0[ ]+movi 0,r45
[ ]+c:[ ]+R_SH_IMMS16[ ]+\.text\.media\+0x9
[ ]+10:[ ]+ebfffa70[ ]+pta/l 8 <mediacode2>,tr7
[ ]+14:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/abi-64.d
0,0 → 1,9
#as: --abi=64
#objdump: -dr
#name: Assertion .abi 64.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/immexpr32-1.d
0,0 → 1,67
#as: --abi=32
#objdump: -dr
#source: immexpr1.s
#name: Immediate resolved operands, 32-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <start>:
[ ]+0:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+4:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+8:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+c:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+10:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+14:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+18:[ ]+d327d680[ ]+addi r50,501,r40
[ ]+1c:[ ]+d327da80[ ]+addi r50,502,r40
[ ]+20:[ ]+d3282e80[ ]+addi r50,-501,r40
[ ]+24:[ ]+d3282a80[ ]+addi r50,-502,r40
[ ]+28:[ ]+b1e7d280[ ]+ld\.uw r30,1000,r40
[ ]+2c:[ ]+b1e3e680[ ]+ld\.uw r30,498,r40
[ ]+30:[ ]+b1e3ee80[ ]+ld\.uw r30,502,r40
[ ]+34:[ ]+b327d140[ ]+ld\.uw r50,1000,r20
[ ]+38:[ ]+b1e83280[ ]+ld\.uw r30,-1000,r40
[ ]+3c:[ ]+b1ec1e80[ ]+ld\.uw r30,-498,r40
[ ]+40:[ ]+b1ec1680[ ]+ld\.uw r30,-502,r40
[ ]+44:[ ]+b3283140[ ]+ld\.uw r50,-1000,r20
[ ]+48:[ ]+8b27d140[ ]+ld\.l r50,2000,r20
[ ]+4c:[ ]+8b27d540[ ]+ld\.l r50,2004,r20
[ ]+50:[ ]+8b27cd40[ ]+ld\.l r50,1996,r20
[ ]+54:[ ]+8b27d140[ ]+ld\.l r50,2000,r20
[ ]+58:[ ]+8b27d540[ ]+ld\.l r50,2004,r20
[ ]+5c:[ ]+8b27cd40[ ]+ld\.l r50,1996,r20
[ ]+60:[ ]+8b283140[ ]+ld\.l r50,-2000,r20
[ ]+64:[ ]+8b282d40[ ]+ld\.l r50,-2004,r20
[ ]+68:[ ]+8b283540[ ]+ld\.l r50,-1996,r20
[ ]+6c:[ ]+8b283140[ ]+ld\.l r50,-2000,r20
[ ]+70:[ ]+8b283540[ ]+ld\.l r50,-1996,r20
[ ]+74:[ ]+8b282d40[ ]+ld\.l r50,-2004,r20
[ ]+78:[ ]+6ff0fff0[ ]+nop
[ ]+7c:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+80:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+84:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+88:[ ]+d327d680[ ]+addi r50,501,r40
[ ]+8c:[ ]+d327da80[ ]+addi r50,502,r40
[ ]+90:[ ]+b1e7d280[ ]+ld\.uw r30,1000,r40
[ ]+94:[ ]+b1e3e680[ ]+ld\.uw r30,498,r40
[ ]+98:[ ]+b1e3ee80[ ]+ld\.uw r30,502,r40
[ ]+9c:[ ]+b327d140[ ]+ld\.uw r50,1000,r20
[ ]+a0:[ ]+8b27d140[ ]+ld\.l r50,2000,r20
[ ]+a4:[ ]+8b27d540[ ]+ld\.l r50,2004,r20
[ ]+a8:[ ]+8b27cd40[ ]+ld\.l r50,1996,r20
[ ]+ac:[ ]+d327d280[ ]+addi r50,500,r40
[ ]+b0:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+b4:[ ]+d3283280[ ]+addi r50,-500,r40
[ ]+b8:[ ]+d3282e80[ ]+addi r50,-501,r40
[ ]+bc:[ ]+d3282a80[ ]+addi r50,-502,r40
[ ]+c0:[ ]+b1e83280[ ]+ld\.uw r30,-1000,r40
[ ]+c4:[ ]+b1ec1e80[ ]+ld\.uw r30,-498,r40
[ ]+c8:[ ]+b1ec1680[ ]+ld\.uw r30,-502,r40
[ ]+cc:[ ]+b3283140[ ]+ld\.uw r50,-1000,r20
[ ]+d0:[ ]+8b283140[ ]+ld\.l r50,-2000,r20
[ ]+d4:[ ]+8b282d40[ ]+ld\.l r50,-2004,r20
[ ]+d8:[ ]+8b283540[ ]+ld\.l r50,-1996,r20
[ ]+dc:[ ]+6ff0fff0[ ]+nop
[ ]\.\.\.
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi64-3.d
0,0 → 1,52
#as: --isa=shmedia --abi=64
#objdump: -dr
#source: movi-2.s
#name: MOVI expansion of local symbols with relocs, 64-bit ABI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
0+ <start>:
[ ]+0:[ ]+cc000210[ ]+movi 0,r33
[ ]+0:[ ]+R_SH_IMM_HI16 \.text\+0x51
[ ]+4:[ ]+c8000210[ ]+shori 0,r33
[ ]+4:[ ]+R_SH_IMM_MEDHI16 \.text\+0x51
[ ]+8:[ ]+c8000210[ ]+shori 0,r33
[ ]+8:[ ]+R_SH_IMM_MEDLOW16 \.text\+0x51
[ ]+c:[ ]+c8000210[ ]+shori 0,r33
[ ]+c:[ ]+R_SH_IMM_LOW16 \.text\+0x51
[ ]+10:[ ]+cc000360[ ]+movi 0,r54
[ ]+10:[ ]+R_SH_IMM_HI16 \.data\+0x2c
[ ]+14:[ ]+c8000360[ ]+shori 0,r54
[ ]+14:[ ]+R_SH_IMM_MEDHI16 \.data\+0x2c
[ ]+18:[ ]+c8000360[ ]+shori 0,r54
[ ]+18:[ ]+R_SH_IMM_MEDLOW16 \.data\+0x2c
[ ]+1c:[ ]+c8000360[ ]+shori 0,r54
[ ]+1c:[ ]+R_SH_IMM_LOW16 \.data\+0x2c
[ ]+20:[ ]+cc0000f0[ ]+movi 0,r15
[ ]+20:[ ]+R_SH_IMM_HI16 \.text\.other\+0x35
[ ]+24:[ ]+c80000f0[ ]+shori 0,r15
[ ]+24:[ ]+R_SH_IMM_MEDHI16 \.text\.other\+0x35
[ ]+28:[ ]+c80000f0[ ]+shori 0,r15
[ ]+28:[ ]+R_SH_IMM_MEDLOW16 \.text\.other\+0x35
[ ]+2c:[ ]+c80000f0[ ]+shori 0,r15
[ ]+2c:[ ]+R_SH_IMM_LOW16 \.text\.other\+0x35
 
0+30 <forw>:
[ ]+30:[ ]+cc000190[ ]+movi 0,r25
[ ]+30:[ ]+R_SH_IMM_HI16 \.data\.other\+0x38
[ ]+34:[ ]+c8000190[ ]+shori 0,r25
[ ]+34:[ ]+R_SH_IMM_MEDHI16 \.data\.other\+0x38
[ ]+38:[ ]+c8000190[ ]+shori 0,r25
[ ]+38:[ ]+R_SH_IMM_MEDLOW16 \.data\.other\+0x38
[ ]+3c:[ ]+c8000190[ ]+shori 0,r25
[ ]+3c:[ ]+R_SH_IMM_LOW16 \.data\.other\+0x38
Disassembly of section \.text\.other:
 
0+ <forwdummylabel>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
0+8 <forwothertext>:
[ ]+8:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel64-2.d
0,0 → 1,111
#as: --abi=64
#objdump: -sr
#source: rel-2.s
#name: MOVI: PC+1-relative relocs, 64-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET TYPE VALUE
0+10 R_SH_IMM_LOW16_PCREL \.data\+0x0+7
0+14 R_SH_IMM_LOW16_PCREL \.data\+0x0+b
0+18 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+f
0+2c R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+30 R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+34 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+23
0+48 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+8
0+4c R_SH_IMM_LOW16_PCREL \.othertext\+0x0+c
0+50 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+10
0+64 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+68 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+6c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+24
0+80 R_SH_IMM_LOW16_PCREL extern2\+0xffffffffffffffff
0+84 R_SH_IMM_LOW16_PCREL extern3\+0xffffffffffffffff
0+88 R_SH_IMM_MEDLOW16_PCREL extern4\+0xffffffffffffffff
0+9c R_SH_IMM_LOW16_PCREL extern6\+0x0+f
0+a0 R_SH_IMM_LOW16_PCREL extern7\+0x0+b
0+a4 R_SH_IMM_MEDLOW16_PCREL extern8\+0x0+3
0+b8 R_SH_IMM_LOW16_PCREL gdata2\+0xffffffffffffffff
0+bc R_SH_IMM_LOW16_PCREL gdata3\+0xffffffffffffffff
0+c0 R_SH_IMM_MEDLOW16_PCREL gdata4\+0xffffffffffffffff
0+d4 R_SH_IMM_LOW16_PCREL gdata6\+0x0+f
0+d8 R_SH_IMM_LOW16_PCREL gdata7\+0x0+b
0+dc R_SH_IMM_MEDLOW16_PCREL gdata8\+0x0+3
0+f0 R_SH_IMM_LOW16_PCREL gothertext2\+0xffffffffffffffff
0+f4 R_SH_IMM_LOW16_PCREL gothertext3\+0xffffffffffffffff
0+f8 R_SH_IMM_MEDLOW16_PCREL gothertext4\+0xffffffffffffffff
0+10c R_SH_IMM_LOW16_PCREL gothertext6\+0x0+f
0+110 R_SH_IMM_LOW16_PCREL gothertext7\+0x0+b
0+114 R_SH_IMM_MEDLOW16_PCREL gothertext8\+0x0+3
0+ R_SH_IMM_HI16_PCREL \.data\+0x0+3
0+4 R_SH_IMM_MEDHI16_PCREL \.data\+0x0+7
0+8 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+b
0+c R_SH_IMM_LOW16_PCREL \.data\+0x0+f
0+1c R_SH_IMM_HI16_PCREL \.data\+0x0+1b
0+20 R_SH_IMM_MEDHI16_PCREL \.data\+0x0+1f
0+24 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+23
0+28 R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+38 R_SH_IMM_HI16_PCREL \.othertext\+0x0+4
0+3c R_SH_IMM_MEDHI16_PCREL \.othertext\+0x0+8
0+40 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+c
0+44 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+10
0+54 R_SH_IMM_HI16_PCREL \.othertext\+0x0+1c
0+58 R_SH_IMM_MEDHI16_PCREL \.othertext\+0x0+20
0+5c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+24
0+60 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+70 R_SH_IMM_HI16_PCREL extern1\+0xffffffffffffffff
0+74 R_SH_IMM_MEDHI16_PCREL extern1\+0x0+3
0+78 R_SH_IMM_MEDLOW16_PCREL extern1\+0x0+7
0+7c R_SH_IMM_LOW16_PCREL extern1\+0x0+b
0+8c R_SH_IMM_HI16_PCREL extern5\+0x0+7
0+90 R_SH_IMM_MEDHI16_PCREL extern5\+0x0+b
0+94 R_SH_IMM_MEDLOW16_PCREL extern5\+0x0+f
0+98 R_SH_IMM_LOW16_PCREL extern5\+0x0+13
0+a8 R_SH_IMM_HI16_PCREL gdata1\+0xffffffffffffffff
0+ac R_SH_IMM_MEDHI16_PCREL gdata1\+0x0+3
0+b0 R_SH_IMM_MEDLOW16_PCREL gdata1\+0x0+7
0+b4 R_SH_IMM_LOW16_PCREL gdata1\+0x0+b
0+c4 R_SH_IMM_HI16_PCREL gdata5\+0x0+7
0+c8 R_SH_IMM_MEDHI16_PCREL gdata5\+0x0+b
0+cc R_SH_IMM_MEDLOW16_PCREL gdata5\+0x0+f
0+d0 R_SH_IMM_LOW16_PCREL gdata5\+0x0+13
0+e0 R_SH_IMM_HI16_PCREL gothertext1\+0xffffffffffffffff
0+e4 R_SH_IMM_MEDHI16_PCREL gothertext1\+0x0+3
0+e8 R_SH_IMM_MEDLOW16_PCREL gothertext1\+0x0+7
0+ec R_SH_IMM_LOW16_PCREL gothertext1\+0x0+b
0+fc R_SH_IMM_HI16_PCREL gothertext5\+0x0+7
0+100 R_SH_IMM_MEDHI16_PCREL gothertext5\+0x0+b
0+104 R_SH_IMM_MEDLOW16_PCREL gothertext5\+0x0+f
0+108 R_SH_IMM_LOW16_PCREL gothertext5\+0x0+13
 
Contents of section \.text:
0000 cc0000a0 c80000a0 c80000a0 c80000a0 .*
0010 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0020 c80000a0 c80000a0 c80000a0 cc0000a0 .*
0030 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0040 c80000a0 c80000a0 cc0000a0 cc0000a0 .*
0050 cc0000a0 cc0000a0 c80000a0 c80000a0 .*
0060 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
0070 cc0000a0 c80000a0 c80000a0 c80000a0 .*
0080 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0090 c80000a0 c80000a0 c80000a0 cc0000a0 .*
00a0 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
00b0 c80000a0 c80000a0 cc0000a0 cc0000a0 .*
00c0 cc0000a0 cc0000a0 c80000a0 c80000a0 .*
00d0 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
00e0 cc0000a0 c80000a0 c80000a0 c80000a0 .*
00f0 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0100 c80000a0 c80000a0 c80000a0 cc0000a0 .*
0110 cc0000a0 cc0000a0 .*
Contents of section \.data:
0000 00000000 00000000 00000000 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 00000000 00000000 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 .*
Contents of section \.othertext:
0000 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0040 6ff0fff0 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt64-1.d
0,0 → 1,47
#as: --isa=shmedia -abi=64
#objdump: -dr
#source: pt-2.s
#name: Inter-segment PT, 64-bit.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
0+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start1>:
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
0+8 <start4>:
[ ]+8:[ ]+ebfffe50[ ]+pta/l 4 <start1>,tr5
[ ]+c:[ ]+6ff0fff0[ ]+nop
[ ]+10:[ ]+cc000190[ ]+movi 0,r25
[ ]+10:[ ]+R_SH_IMM_HI16_PCREL \.text\.other\+0xfffffffffffffff5
[ ]+14:[ ]+c8000190[ ]+shori 0,r25
[ ]+14:[ ]+R_SH_IMM_MEDHI16_PCREL \.text\.other\+0xfffffffffffffff9
[ ]+18:[ ]+c8000190[ ]+shori 0,r25
[ ]+18:[ ]+R_SH_IMM_MEDLOW16_PCREL \.text\.other\+0xfffffffffffffffd
[ ]+1c:[ ]+c8000190[ ]+shori 0,r25
[ ]+1c:[ ]+R_SH_IMM_LOW16_PCREL \.text\.other\+0x1
[ ]+20:[ ]+6bf56670[ ]+ptrel/l r25,tr7
[ ]+24:[ ]+6ff0fff0[ ]+nop
Disassembly of section \.text\.other:
 
0+ <dummylabel>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start2>:
[ ]+4:[ ]+e8000a40[ ]+pta/l c <start3>,tr4
[ ]+8:[ ]+6ff0fff0[ ]+nop
 
0+c <start3>:
[ ]+c:[ ]+cc000190[ ]+movi 0,r25
[ ]+c:[ ]+R_SH_IMM_HI16_PCREL \.text\+0xfffffffffffffff9
[ ]+10:[ ]+c8000190[ ]+shori 0,r25
[ ]+10:[ ]+R_SH_IMM_MEDHI16_PCREL \.text\+0xfffffffffffffffd
[ ]+14:[ ]+c8000190[ ]+shori 0,r25
[ ]+14:[ ]+R_SH_IMM_MEDLOW16_PCREL \.text\+0x1
[ ]+18:[ ]+c8000190[ ]+shori 0,r25
[ ]+18:[ ]+R_SH_IMM_LOW16_PCREL \.text\+0x5
[ ]+1c:[ ]+6bf56630[ ]+ptrel/l r25,tr3
[ ]+20:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange1.s
0,0 → 1,210
! Test that .cranges are emitted:
! 1) Not for sections with single contents.
! 2) For data (through pseudo-ops) in SHmedia.
! 3) For mixed SHcompact and SHmedia sections.
! 4) For a mix of 2 and 3
! 5) For 4, repeated.
!
! Use section contents that need relaxing to strengthen the check that the
! .cranges implementation handles this correctly. Use different sizes for
! each contents part.
!
 
! The .text section has only SHmedia contents, and should not get a
! .cranges descriptor.
.mode SHmedia
.text
nop
shmedia:
movi 42,r45
movi shmediaend-shmedia,r46
shmediaend:
nop
 
! Likewise the SHcompact section.
.mode SHcompact
.section .text.compact,"ax"
nop
shcompact:
mov #42,r0
bt shcompactend
nop
shcompactend:
nop
 
! This section has SHmedia code followed by data. There should be two
! .cranges descriptors. Note that we put the .mode directive *after* the
! section change. It should not matter.
.section .text.shmediaanddata,"ax"
.mode SHmedia
shmedia_data_code:
movi 42,r45
movi shmedia_data_code_end-shmedia_data_code,r46
shmedia_data_code_end:
.long 0x6ff0fff0
.long shmedia_dataend-shmedia_data_code
.long 50
shmedia_dataend:
 
! This section mixes SHcompact and SHmedia code. There should be two
! .cranges descriptors.
.section .text.codemix,"ax"
shmedia_compact_code:
movi 42,r45
nop
nop
movi shmedia_compact_code_end-shmedia_compact_code,r46
nop
nop
shmedia_compact_code_end:
.mode SHcompact
compact_code:
nop
compact:
mov #40,r0
nop
nop
bt compactend
nop
compactend:
nop
 
! This section mixes SHcompact and SHmedia code, and has a constant
! section after the SHmedia code and one after the SHcompact code. There
! should be three or four .cranges descriptors, depending on whether one
! is emitted for the SHcompact constant pool: there's normally one such
! after each SHcompact function.
.mode SHmedia
.section .text.codemixconst,"ax"
nop
shmedia_compact_code2:
movi 42,r45
nop
nop
movi shmedia_compact_code_end2-shmedia_compact_code2,r46
nop
nop
.long 0x6ff0fff0
.long 0x6ff0fff0
.long 0x6ff00000
.long 0xfff0
.long 0x6ff0fff0
.long 0x6ff0fff0
.long 0
mediapoollabel:
.long mediapoollabel2-shmedia_compact_code2
mediapoolend:
shmedia_compact_code_end2:
.mode SHcompact
compact_code2:
nop
compact2:
mov #43,r0
nop
nop
bt compactend2
nop
nop
nop
compactend2:
nop
.space 102,0
.long 0
mediapoollabel2:
.long mediapoolend2-compact2
mediapoolend2:
 
! This section is like the previous, but repeated twice and adjusted to
! keep different sizes of each part.
.mode SHmedia
.section .text.codemixconst2,"ax"
nop
shmedia_compact_code3:
movi 42,r45
nop
nop
nop
nop
nop
nop
movi shmedia_compact_code_end3-shmedia_compact_code3,r46
.long 0x6ff0fff0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
mediapoollabel3a:
.long mediapoollabel3a-shmedia_compact_code3
mediapoolend3a:
shmedia_compact_code_end3:
.mode SHcompact
compact_code3:
nop
compact3:
mov #44,r0
nop
nop
bt compactend3
nop
nop
nop
nop
nop
compactend3:
nop
.word 9
.word 0x900
.space 198,0
.long 0
mediapoollabel3:
.long mediapoolend3-compact3
mediapoolend3:
.mode SHmedia
nop
shmedia_compact_code4:
movi 43,r45
nop
nop
nop
nop
nop
nop
nop
nop
movi shmedia_compact_code_end4-shmedia_compact_code4,r46
.long 0x6ff0fff0
.space 20,0
mediapoollabel4a:
.long mediapoolend4a-shmedia_compact_code4
mediapoolend4a:
shmedia_compact_code_end4:
.mode SHcompact
compact_code4:
nop
compact4:
mov #14,r0
nop
nop
bt compactend4
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
compactend4:
nop
.space 298,0
.long 0
mediapoollabel4:
.long mediapoolend4-compact4
mediapoolend4:
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/abi-64.s
0,0 → 1,7
! Check successful .abi assertion for 64-bit ABI.
 
.text
.abi 64
 
start:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/crange5.s
0,0 → 1,26
! Zero-sized range descriptors are handled well, but GAS should not emit
! them unnecessarily. This can happen if .align handling and insn
! assembling does not cater to this specifically and completely.
! Test-case shortened from gcc.c-torture/execute/20000205-1.c.
 
.text
_f:
pt .L2, tr0
addi.l r15, -32, r15
gettr tr5, r0
st.q r15, 0, r14
st.q r15, 24, r0
st.q r15, 16, r28
st.q r15, 8, r18
add.l r15, r63, r14
add r2, r63, r1
beqi r1, 0, tr0
pt _f, tr5
andi r1, 128, r28
.align 2
.L8:
pt .L2, tr0
movi 1, r2
.L2:
nop
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/datal-3.s
0,0 → 1,48
! Check "datalabel" qualifier.
! This is the next most simple use; references symbols defined in this file.
! Code tests are for SHmedia mode.
 
.mode SHmedia
.text
start:
movi datalabel foo,r3
movi DataLabel foo2 + 42,r3
movi ((datalabel foo3 + 46) >> 16) & 65535,r3
 
.section .rodata
.long datalabel foo4
myrodata1:
.long DATALABEL foo5 + 56
myrodata2:
.long datalabel $
.global myrodata3
myrodata3:
.long datalabel $+20
 
.text
movi datalabel foo7 + 42,r30
movi datalabel foo8,r30
movi ((datalabel foo9 + 64) >> 16) & 65535,r3
movi datalabel myrodata1,r56
foo:
movi DATALABEL myrodata2+30,r21
foo2:
movi DataLabel foo,r10
foo3:
movi datalabel $,r33
foo4:
movi datalabel $+40,r8
foo5:
movi datalabel myrodata3,r44
.global foo6
foo6:
movi datalabel foo6 + 42,r30
.global foo7
foo7:
nop
.global foo8
foo8:
nop
.global foo9
foo9:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-4.s
0,0 → 1,27
! { dg-do assemble }
! { dg-options "--abi=32 -no-mix" }
 
! Check that we can't have different ISA:s in the same section if disallowed.
 
.text
.mode SHmedia
start:
nop
 
.mode SHcompact
nop ! { dg-error "not allowed in same section" }
 
.section .text.other,"ax"
.mode SHmedia
nop
 
.mode SHcompact
nop ! { dg-error "not allowed in same section" }
 
.section .text.more,"ax"
.mode SHmedia
nop
 
.section .text.yetmore,"ax"
.mode SHcompact
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/relax-1.d
0,0 → 1,30
#as: --abi=64
#objdump: -dr
#source: relax-1.s
#name: Assembler PT relaxation limit, from first to second state.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start2>:
[ ]+4:[ ]+cc000990[ ]+movi 2,r25
[ ]+8:[ ]+c8000590[ ]+shori 1,r25
[ ]+c:[ ]+6bf56630[ ]+ptrel/l r25,tr3
 
0+10 <x1>:
[ ]+10:[ ]+e9fffe40[ ]+pta/l 2000c <x0>,tr4
[ ]+\.\.\.
 
0+2000c <x0>:
[ ]+2000c:[ ]+ea000650[ ]+pta/l 10 <x1>,tr5
[ ]+20010:[ ]+ea000260[ ]+pta/l 10 <x1>,tr6
[ ]+20014:[ ]+cffff590[ ]+movi -3,r25
[ ]+20018:[ ]+cbffd590[ ]+shori 65525,r25
[ ]+2001c:[ ]+6bf56660[ ]+ptrel/l r25,tr6
[ ]+20020:[ ]+cffff590[ ]+movi -3,r25
[ ]+20024:[ ]+cbffa590[ ]+shori 65513,r25
[ ]+20028:[ ]+6bf56670[ ]+ptrel/l r25,tr7
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi-3.d
0,0 → 1,18
#as: --abi=64
#objdump: -dr
#source: movi-3.s
#name: Assembler PC-rel resolved negative MOVI.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+cef68040[ ]+movi -16992,r4
[ ]+4:[ ]+cfffc050[ ]+movi -16,r5
[ ]+8:[ ]+cffffc60[ ]+movi -1,r6
[ ]+c:[ ]+cffffc70[ ]+movi -1,r7
[ ]+10:[ ]+cffffc80[ ]+movi -1,r8
[ ]+14:[ ]+cbfffc80[ ]+shori 65535,r8
[ ]+18:[ ]+cbffc080[ ]+shori 65520,r8
[ ]+1c:[ ]+caf68080[ ]+shori 48544,r8
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ua64-1.d
0,0 → 1,23
#as: --abi=64
#objdump: -sr
#name: Unaligned pseudos, 64-bit ABI.
#source: ua-1.s
 
# Note that the relocs for externsym0 + 3 and externsym2 + 42 are
# partial-in-place, i.e. REL-like, and are not displayed correctly.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.rodata\]:
OFFSET TYPE VALUE
0+0f R_SH_DIR32 externsym0
0+1b R_SH_64 externsym1\+0x0000000000000029
0+2c R_SH_DIR32 externsym2
0+30 R_SH_64 externsym3\+0x000000000000002b
 
 
Contents of section \.rodata:
0000 01234567 89abcdef 2a4a2143 b1abcd00 .*
0010 00000301 2c456d89 ab1d0f00 00000000 .*
0020 00000002 01a34b67 c9ab0d4f 0000002a .*
0030 00000000 00000000 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-pt32-cmd2.s
0,0 → 1,10
! Check command-line error checking. The option -expand-pt32 is invalid with
! -no-expand.
 
! { dg-do assemble }
! { dg-options "-abi=64 -expand-pt32 -no-expand" }
! { dg-error ".* invalid together with -no-expand" "" { target sh64-*-* } 0 }
 
.text
start:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/ptc32-noexp-1.d
0,0 → 1,12
#as: --abi=32 -no-expand
#objdump: -dr
#source: ptc-1.s
#name: PT constant, 32-bit ABI with -no-expand.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
 
[0]+ <start>:
[ ]+0:[ ]+e8000610[ ]+pta/l 4 <start\+0x4>,tr1
[ ]+0:[ ]+R_SH_PT_16 \*ABS\*\+0x100
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/syntax-2.d
0,0 → 1,11
#as: --isa=shmedia --abi=64
#objdump: -d
#name: Minimum SH64 Syntax Support - Pseudos.
 
dump.o: file format elf64-sh64.*
 
Disassembly of section .text:
 
0000000000000000 <.*>:
0: e8000a00 pta/l 8 <.*>,tr0
4: ec000600 ptb/l 8 <.*>,tr0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/rel32-2.d
0,0 → 1,86
#as: --abi=32
#objdump: -sr
#source: rel-2.s
#name: MOVI: PC+1-relative relocs, 32-bit ABI.
 
.*: file format .*-sh64.*
 
RELOCATION RECORDS FOR \[\.text\]:
OFFSET *TYPE *VALUE
0+8 R_SH_IMM_LOW16_PCREL \.data\+0x0+7
0+c R_SH_IMM_LOW16_PCREL \.data\+0x0+b
0+10 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+f
0+1c R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+20 R_SH_IMM_LOW16_PCREL \.data\+0x0+27
0+24 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+23
0+30 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+8
0+34 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+c
0+38 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+10
0+44 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+48 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+28
0+4c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+24
0+58 R_SH_IMM_LOW16_PCREL extern2\+0xf*ffffffff
0+5c R_SH_IMM_LOW16_PCREL extern3\+0xf*ffffffff
0+60 R_SH_IMM_MEDLOW16_PCREL extern4\+0xf*ffffffff
0+6c R_SH_IMM_LOW16_PCREL extern6\+0x0+f
0+70 R_SH_IMM_LOW16_PCREL extern7\+0x0+b
0+74 R_SH_IMM_MEDLOW16_PCREL extern8\+0x0+3
0+80 R_SH_IMM_LOW16_PCREL gdata2\+0xf*ffffffff
0+84 R_SH_IMM_LOW16_PCREL gdata3\+0xf*ffffffff
0+88 R_SH_IMM_MEDLOW16_PCREL gdata4\+0xf*ffffffff
0+94 R_SH_IMM_LOW16_PCREL gdata6\+0x0+f
0+98 R_SH_IMM_LOW16_PCREL gdata7\+0x0+b
0+9c R_SH_IMM_MEDLOW16_PCREL gdata8\+0x0+3
0+a8 R_SH_IMM_LOW16_PCREL gothertext2\+0xf*ffffffff
0+ac R_SH_IMM_LOW16_PCREL gothertext3\+0xf*ffffffff
0+b0 R_SH_IMM_MEDLOW16_PCREL gothertext4\+0xf*ffffffff
0+bc R_SH_IMM_LOW16_PCREL gothertext6\+0x0+f
0+c0 R_SH_IMM_LOW16_PCREL gothertext7\+0x0+b
0+c4 R_SH_IMM_MEDLOW16_PCREL gothertext8\+0x0+3
0+ R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+3
0+4 R_SH_IMM_LOW16_PCREL \.data\+0x0+7
0+14 R_SH_IMM_MEDLOW16_PCREL \.data\+0x0+1b
0+18 R_SH_IMM_LOW16_PCREL \.data\+0x0+1f
0+28 R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+4
0+2c R_SH_IMM_LOW16_PCREL \.othertext\+0x0+8
0+3c R_SH_IMM_MEDLOW16_PCREL \.othertext\+0x0+1c
0+40 R_SH_IMM_LOW16_PCREL \.othertext\+0x0+20
0+50 R_SH_IMM_MEDLOW16_PCREL extern1\+0xf*ffffffff
0+54 R_SH_IMM_LOW16_PCREL extern1\+0x0+3
0+64 R_SH_IMM_MEDLOW16_PCREL extern5\+0x0+7
0+68 R_SH_IMM_LOW16_PCREL extern5\+0x0+b
0+78 R_SH_IMM_MEDLOW16_PCREL gdata1\+0xf*ffffffff
0+7c R_SH_IMM_LOW16_PCREL gdata1\+0x0+3
0+8c R_SH_IMM_MEDLOW16_PCREL gdata5\+0x0+7
0+90 R_SH_IMM_LOW16_PCREL gdata5\+0x0+b
0+a0 R_SH_IMM_MEDLOW16_PCREL gothertext1\+0xf*ffffffff
0+a4 R_SH_IMM_LOW16_PCREL gothertext1\+0x0+3
0+b4 R_SH_IMM_MEDLOW16_PCREL gothertext5\+0x0+7
0+b8 R_SH_IMM_LOW16_PCREL gothertext5\+0x0+b
 
Contents of section \.text:
0000 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
0010 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
0020 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0030 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0040 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
0050 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
0060 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
0070 cc0000a0 cc0000a0 cc0000a0 c80000a0 .*
0080 cc0000a0 cc0000a0 cc0000a0 cc0000a0 .*
0090 c80000a0 cc0000a0 cc0000a0 cc0000a0 .*
00a0 cc0000a0 c80000a0 cc0000a0 cc0000a0 .*
00b0 cc0000a0 cc0000a0 c80000a0 cc0000a0 .*
00c0 cc0000a0 cc0000a0 .*
Contents of section \.data:
0000 00000000 00000000 00000000 00000000 .*
0010 00000000 00000000 00000000 00000000 .*
0020 00000000 00000000 00000000 00000000 .*
0030 00000000 00000000 00000000 00000000 .*
0040 00000000 .*
Contents of section \.othertext:
0000 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0010 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0020 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
0040 6ff0fff0 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/pt32-1.d
0,0 → 1,39
#as: --isa=shmedia -abi=32
#objdump: -dr
#source: pt-2.s
#name: Inter-segment PT, 32-bit.
 
.*: file format .*-sh64.*
 
Disassembly of section \.text:
0+ <start>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start1>:
[ ]+4:[ ]+6ff0fff0[ ]+nop
 
0+8 <start4>:
[ ]+8:[ ]+ebfffe50[ ]+pta/l 4 <start1>,tr5
[ ]+c:[ ]+6ff0fff0[ ]+nop
[ ]+10:[ ]+cc000190[ ]+movi 0,r25
[ ]+10:[ ]+R_SH_IMM_MEDLOW16_PCREL \.text\.other\+0xf*fffffffd
[ ]+14:[ ]+c8000190[ ]+shori 0,r25
[ ]+14:[ ]+R_SH_IMM_LOW16_PCREL \.text\.other\+0x1
[ ]+18:[ ]+6bf56670[ ]+ptrel/l r25,tr7
[ ]+1c:[ ]+6ff0fff0[ ]+nop
Disassembly of section \.text\.other:
 
0+ <dummylabel>:
[ ]+0:[ ]+6ff0fff0[ ]+nop
 
0+4 <start2>:
[ ]+4:[ ]+e8000a40[ ]+pta/l c <start3>,tr4
[ ]+8:[ ]+6ff0fff0[ ]+nop
 
0+c <start3>:
[ ]+c:[ ]+cc000190[ ]+movi 0,r25
[ ]+c:[ ]+R_SH_IMM_MEDLOW16_PCREL \.text\+0x1
[ ]+10:[ ]+c8000190[ ]+shori 0,r25
[ ]+10:[ ]+R_SH_IMM_LOW16_PCREL \.text\+0x5
[ ]+14:[ ]+6bf56630[ ]+ptrel/l r25,tr3
[ ]+18:[ ]+6ff0fff0[ ]+nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-abi-64.s
0,0 → 1,10
! Check .abi pseudo assertion.
 
! { dg-do assemble }
! { dg-options "-abi=32" }
 
.text
.abi 64 ! { dg-error "options do not specify 64-bit ABI" }
 
start:
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/err-ptb-1.s
0,0 → 1,34
! Check that PTB to a assembly-time-resolvable SHcompact operand
! gets an error. Likewise PTA.
 
! { dg-do assemble }
! { dg-options "--abi=32" }
 
.text
.mode SHmedia
start:
ptb shmediasymbol1,tr1 ! { dg-error "PTB operand is a SHmedia symbol" }
shmediasymbol3:
ptb shcompactsymbol1,tr1
pta shcompactsymbol2,tr3 ! { dg-error "PTA operand is a SHcompact symbol" }
shmediasymbol1:
ptb shmediasymbol2,tr2 ! { dg-error "PTB operand is a SHmedia symbol" }
 
.mode SHcompact
shcompact:
nop
nop
shcompactsymbol2:
nop
nop
shcompactsymbol1:
nop
nop
 
.mode SHmedia
shmedia:
nop
shmediasymbol2:
nop
ptb shmediasymbol3,tr3 ! { dg-error "PTB operand is a SHmedia symbol" }
nop
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/relax-1.s
0,0 → 1,18
! Check limits of PT assembler relaxation states. Unfortunately, we can't
! check the 32 and 48 bit limit on a host with 32-bit longs, so we just
! check the first state. This also checks that a PT expansion without a
! relocation to 32 bits works.
 
.mode SHmedia
start:
nop
start2:
pt x0,tr3
x1:
pt x0,tr4
.space 32767*4-4,0
x0:
pt x1,tr5
pt x1,tr6
pt x1,tr6
pt x1,tr7
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/movi-3.s
0,0 → 1,10
! There was a bug with negative pc-relative numbers.
.mode SHmedia
.text
start:
movi (start - 1000000 - end) & 65535,r4
movi ((start - 1000000 - end) >> 16) & 65535,r5
movi ((start - 1000000 - end) >> 32) & 65535,r6
movi ((start - 1000000 - end) >> 48) & 65535,r7
movi (start - 1000000 - end),r8
end:
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/immexpr64-2.d
0,0 → 1,11
#as: --abi=64
#objdump: -sr
#source: immexpr2.s
#name: Resolved 64-bit operand, 64-bit ABI.
 
.*: file format .*-sh64.*
 
Contents of section \.text:
0000 6ff0fff0 6ff0fff0 6ff0fff0 .*
Contents of section .data:
0000 00000000 00000004 00000000 00000008 .*
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh64/shift-3.s
0,0 → 1,7
! This should not get an internal error and it should emit the expected
! relocs, even though the symbol looks local and is undefined.
.text
.mode SHmedia
start:
movi .LC0 & 65535, r1
movi (.LC0 >> 16) & 65535, r3
/trunk/gnu/binutils/gas/testsuite/gas/sh/err-sh4al-dsp.s
0,0 → 1,20
! { dg-do assemble }
! { dg-options "-dsp" }
 
.text
.p2align 2
 
ldrc a0 ! { dg-error "invalid operand" }
movx.w @r3,x0 ! { dg-error "invalid operand" }
movx.w @r0,x0 movy.w a0,@r7+ ! { dg-error "requires nopy" }
movy.w a0,@r2+ movx.w @r4,x0 ! { dg-error "requires nopx" }
movx.w @r4,x0 movy.w a0,@r3+ ! { dg-error "combined with non-nopx" }
movy.w a0,@r6+ movx.w @r1,x0 ! { dg-error "combined with non-nopy" }
movx.l @r5,x1 movx.w @r0,x0 ! { dg-error "multiple movx" }
movx.l @r1+,y0 nopx ! { dg-error "multiple movx" }
movy.w @r7,y1 movy.l @r2,y0 ! { dg-error "multiple movy" }
movy.l @r3+,x0 nopy ! { dg-error "multiple movy" }
dct pclr x0 pmuls a1,x0,m0 ! { dg-error "combined with pmuls" }
pclr a0 pmuls x1,y1,a0 ! { dg-warning "register is same" }
/trunk/gnu/binutils/gas/testsuite/gas/sh/pcrel.d
0,0 → 1,24
#as: -big
#objdump: -d
#name: PC-relative loads
#stderr: pcrel.l
 
.*: file format .*sh.*
 
Disassembly of section .text:
 
00000000 <code>:
0: d0 04 mov\.l 14 <litpool>,r0 ! ffffffec
2: d1 05 mov\.l 18 <litpool\+0x4>,r1
4: d1 03 mov\.l 14 <litpool>,r1 ! ffffffec
6: d1 03 mov\.l 14 <litpool>,r1 ! ffffffec
8: c7 02 mova 14 <litpool>,r0
a: 61 02 mov\.l @r0,r1
c: d1 01 mov\.l 14 <litpool>,r1 ! ffffffec
e: 01 03 bsrf r1
10: 00 09 nop
12: 00 09 nop
 
00000014 <litpool>:
14: ff ff \.word 0xffff
16: ff ec \.word 0xffec
/trunk/gnu/binutils/gas/testsuite/gas/sh/err-1.s
0,0 → 1,11
! { dg-do assemble }
 
! Check that errors are emitted, with no crashes, when an external symbol
! is referenced in a conditional or unconditional branch.
start:
nop
bt externsym1 ! { dg-error "undefined symbol" }
nop
bra externsym2 ! { dg-error "undefined symbol" }
nop
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/pcrel2.s
0,0 → 1,17
.text
 
.p2align 2
code:
bf foo
mov.l bar, r0
mov.w bar, r0
.globl foo
foo:
bra foo
nop
.align 2
.globl bar
bar:
.long . - foo
.word . - foo
.byte . - foo
/trunk/gnu/binutils/gas/testsuite/gas/sh/tlsd.d
0,0 → 1,55
#objdump: -dr
#as: -big
#name: sh dynamic tls
 
.*: +file format .*
 
Disassembly of section .text:
 
0+000 <fn>:
0: 2f c6 [ ]*mov\.l r12,@-r15
2: 2f e6 [ ]*mov\.l r14,@-r15
4: 4f 22 [ ]*sts\.l pr,@-r15
6: c7 14 [ ]*mova 58 <fn\+0x58>,r0
8: dc 13 [ ]*mov\.l 58 <fn\+0x58>,r12[ ]+! 0 .*
a: 3c 0c [ ]*add r0,r12
c: 6e f3 [ ]*mov r15,r14
e: d4 04 [ ]*mov\.l 20 <fn\+0x20>,r4[ ]+! 0 .*
10: c7 04 [ ]*mova 24 <fn\+0x24>,r0
12: d1 04 [ ]*mov\.l 24 <fn\+0x24>,r1[ ]+! 0 .*
14: 31 0c [ ]*add r0,r1
16: 41 0b [ ]*jsr @r1
18: 34 cc [ ]*add r12,r4
1a: a0 05 [ ]*bra 28 <fn\+0x28>
1c: 00 09 [ ]*nop
1e: 00 09 [ ]*nop
\.\.\.
[ ]+20: R_SH_TLS_GD_32 foo
[ ]+24: R_SH_PLT32 __tls_get_addr
28: d4 03 [ ]*mov\.l 38 <fn\+0x38>,r4[ ]+! 0 .*
2a: c7 04 [ ]*mova 3c <fn\+0x3c>,r0
2c: d1 03 [ ]*mov\.l 3c <fn\+0x3c>,r1[ ]+! 0 .*
2e: 31 0c [ ]*add r0,r1
30: 41 0b [ ]*jsr @r1
32: 34 cc [ ]*add r12,r4
34: a0 04 [ ]*bra 40 <fn\+0x40>
36: 00 09 [ ]*nop
\.\.\.
[ ]+38: R_SH_TLS_LD_32 bar
[ ]+3c: R_SH_PLT32 __tls_get_addr
40: e2 01 [ ]*mov #1,r2
42: d1 06 [ ]*mov\.l 5c <fn\+0x5c>,r1[ ]+! 0 .*
44: 30 1c [ ]*add r1,r0
46: 20 22 [ ]*mov\.l r2,@r0
48: d1 05 [ ]*mov\.l 60 <fn\+0x60>,r1[ ]+! 0 .*
4a: 30 1c [ ]*add r1,r0
4c: 6f e3 [ ]*mov r14,r15
4e: 4f 26 [ ]*lds\.l @r15\+,pr
50: 6e f6 [ ]*mov\.l @r15\+,r14
52: 00 0b [ ]*rts
54: 6c f6 [ ]*mov\.l @r15\+,r12
56: 00 09 [ ]*nop
\.\.\.
[ ]+58: R_SH_GOTPC _GLOBAL_OFFSET_TABLE_
[ ]+5c: R_SH_TLS_LDO_32 bar
[ ]+60: R_SH_TLS_LDO_32 baz
/trunk/gnu/binutils/gas/testsuite/gas/sh/reg-prefix.d
0,0 → 1,11
#objdump: -dr --prefix-addresses --show-raw-insn
#as: --allow-reg-prefix -big
#name: SH --allow-reg-prefix option
#skip: sh*-*-symbian*
# Test SH register names prefixed with $:
 
.*: file format elf.*sh.*
 
Disassembly of section .text:
0x00000000 60 12 mov\.l @r1,r0
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/err-at.s
0,0 → 1,10
! { dg-do assemble }
 
! Make sure we reject the invalid uses below:
start:
mov.l r1,@r0 ! ok
mov.l r1,@(r0) ! { dg-error "syntax error" }
mov.l r1,@(r0,) ! { dg-error "syntax error" }
mov.l r1,@(r0,r0) ! ok
mov.l r1,@(r0,r1) ! ok
mov.l r1,@(r1,r0) ! { dg-error "must be" }
/trunk/gnu/binutils/gas/testsuite/gas/sh/tlsnopic.s
0,0 → 1,23
.section .tbss,"awT",@nobits
.align 2
.long foo
.text
.align 1
.global fn
.type fn, @function
fn:
! Main binary, no PIC
mov.l r14,@-r15
mov r15,r14
 
stc gbr,r1
mov.l .L2,r0
add r1,r0
! r0 now contains &foo
 
mov r14,r15
rts
mov.l @r15+,r14
.L3:
.align 2
.L2: .long foo@TPOFF
/trunk/gnu/binutils/gas/testsuite/gas/sh/pic.d
0,0 → 1,43
#objdump: -dr --prefix-addresses --show-raw-insn
#name: SH PIC constructs
# Test SH PIC constructs:
 
.*: file format elf.*sh.*
 
Disassembly of section \.text:
0x00000000 c7 0a mova 0x0000002c,r0
0x00000002 dc 0a mov\.l 0x0000002c,r12 ! 0
0x00000004 3c 0c add r0,r12
0x00000006 d0 0a mov\.l 0x00000030,r0 ! 0
0x00000008 00 ce mov\.l @\(r0,r12\),r0
0x0000000a 40 0b jsr @r0
0x0000000c 00 09 nop
0x0000000e d0 09 mov\.l 0x00000034,r0 ! 0
0x00000010 30 cc add r12,r0
0x00000012 40 0b jsr @r0
0x00000014 00 09 nop
0x00000016 d1 08 mov\.l 0x00000038,r1 ! 0
0x00000018 c7 07 mova 0x00000038,r0
0x0000001a 30 1c add r1,r0
0x0000001c 40 0b jsr @r0
0x0000001e 00 09 nop
0x00000020 d0 06 mov\.l 0x0000003c,r0 ! 16
0x00000022 40 0b jsr @r0
0x00000024 00 09 nop
0x00000026 d0 06 mov\.l 0x00000040,r0 ! 14
0x00000028 40 0b jsr @r0
0x0000002a 00 09 nop
\.\.\.
2c: R_SH_DIR32 GLOBAL_OFFSET_TABLE
30: R_SH_GOT32 foo
34: R_SH_GOTOFF foo
38: R_SH_PLT32 foo
0x0000003c 00 00 \.word 0x0000
3c: R_SH_PLT32 foo
0x0000003e 00 16 mov\.l r1,@\(r0,r0\)
0x00000040 00 00 \.word 0x0000
40: R_SH_PLT32 foo
0x00000042 00 14 mov\.b r1,@\(r0,r0\)
0x00000044 00 00 \.word 0x0000
44: R_SH_PLT32 foo
0x00000046 00 1e mov\.l @\(r0,r1\),r0
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh2a.s
0,0 → 1,96
.text
 
# New instructions
 
band.b #7,@(4095,r3)
 
bandnot.b #7,@(4095,r3)
 
bclr.b #7,@(4095,r3)
bclr #7,r3
 
bld.b #7,@(4095,r3)
bld #7,r3
 
bldnot.b #7,@(4095,r3)
 
bor.b #7,@(4095,r3)
 
bornot.b #7,@(4095,r3)
 
bset.b #7,@(4095,r3)
bset #7,r3
 
bst.b #7,@(4095,r3)
bst #7,r3
 
bxor.b #7,@(4095,r3)
 
clips.b r3
clips.w r3
clipu.b r3
clipu.w r3
 
divs r0,r3
divu r0,r3
 
fmov.s fr3,@(4095*4,r3)
fmov.d dr2,@(4095*8,r3)
fmov.s @(4095*4,r3),fr3
fmov.d @(4095*8,r3),dr2
 
jsr/n @r3
jsr/n @@(255*4,tbr)
 
ldbank @r3,r0
 
ldc r3,tbr
 
mov.b r3,@(4095,r4)
mov.w r3,@(4095*2,r4)
mov.l r3,@(4095*4,r4)
mov.b @(4095,r4),r5
mov.w @(4095*2,r4),r5
mov.l @(4095*4,r4),r5
 
mov.b r0,@r3+
mov.w r0,@r3+
mov.l r0,@r3+
mov.b @-r3,r0
mov.w @-r3,r0
mov.l @-r3,r0
 
movi20 #524287,r3
movi20 #-524288,r3
movi20s #524287*256,r3
movi20s #-524288*256,r3
 
movml.l r3,@-r15
movml.l @r15+,r3
 
movmu.l r3,@-r15
movmu.l @r15+,r3
 
movrt r3
 
movu.b @(4095,r3),r4
movu.w @(4095*2,r3),r4
 
mulr r0,r4
 
nott
 
pref @r5
 
resbank
 
rts/n
 
rtv/n r3
 
shad r3,r4
shld r3,r4
 
stbank r0,@r5
 
stc tbr,r4
/trunk/gnu/binutils/gas/testsuite/gas/sh/tlspic.s
0,0 → 1,30
.text
.align 1
.global fn
.type fn, @function
fn:
! Main binary, PIC
mov.l r12,@-r15
mov.l r14,@-r15
mov r15,r14
mova .L3,r0
mov.l .L3,r12
add r0,r12
 
mov.l 1f,r0
stc gbr,r1
mov.l @(r0,r12),r0
bra 2f
add r0,r1
.align 2
1: .long foo@GOTTPOFF
2: ! now r1 contains &foo
 
mov r1,r0
mov r14,r15
mov.l @r15+,r14
rts
mov.l @r15+,r12
 
.align 2
.L3: .long _GLOBAL_OFFSET_TABLE_
/trunk/gnu/binutils/gas/testsuite/gas/sh/pcrel.l
0,0 → 1,3
[^:]*pcrel.s: Assembler messages:
[^:]*pcrel(-coff)?\.s:5: Warning: Deprecated syntax.
[^:]*pcrel(-coff)?\.s:6: Warning: Deprecated syntax.
/trunk/gnu/binutils/gas/testsuite/gas/sh/renesas-1.s
0,0 → 1,3
.text
.long foo
foo:
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh4a.s
0,0 → 1,28
.text
.p2align 2
 
movli.l @r1,r0
movco.l r0,@r0
 
movli.l @r6,r0
movco.l r0,@r3
 
movli.l @r10,r0
movco.l r0,@r12
 
movua.l @r0,r0
movua.l @r13,r0
movua.l @r7,r0
 
movua.l @r5+,r0
movua.l @r2+,r0
movua.l @r11+,r0
 
icbi @r4
icbi @r15
icbi @r2
 
prefi @r5
prefi @r10
 
synco
/trunk/gnu/binutils/gas/testsuite/gas/sh/sh4a-fp.s
0,0 → 1,11
.text
.p2align 2
 
fpchg
 
fsrra fr1
fsrra fr9
fsrra fr6
 
fsca fpul, dr2
fsca fpul, dr12
/trunk/gnu/binutils/gas/testsuite/gas/sh/fp.s
0,0 → 1,44
.file "test.c"
.data
 
! Hitachi SH cc1 (cygnus-2.7.1-950728) arguments: -O -fpeephole
! -ffunction-cse -freg-struct-return -fdelayed-branch -fcommon -fgnu-linker
 
gcc2_compiled.:
___gnu_compiled_c:
.text
.align 2
.global _foo
_foo:
fmov.s @r0,fr0
fmov.s fr0,@r0
fmov.s @r0+,fr0
fmov.s fr0,@-r0
fmov.s @(r0,r0),fr0
fmov.s fr0,@(r0,r0)
fmov fr0,fr1
fldi0 fr0
fldi1 fr0
fadd fr0,fr1
fsub fr0,fr1
fmul fr0,fr1
fdiv fr0,fr1
fmac fr0,fr0,fr1
fcmp/eq fr0,fr1
fcmp/gt fr0,fr1
fneg fr0
fabs fr0
fsqrt fr0
float fpul,fr0
ftrc fr0,fpul
fsts fpul,fr0
flds fr0,fpul
lds r3,fpul
lds.l @r3+,fpul
lds r3,fpscr
lds.l @r3+,fpscr
sts fpul,r3
sts.l fpul,@-r3
sts fpscr,r3
sts.l fpscr,@-r3
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/pcrel.s
0,0 → 1,16
.text
 
.p2align 2
code:
mov.l @(litpool,pc), r0
mov.l @(litpool+4,pc), r1
mov.l litpool, r1
mov.l @(14,pc), r1
mova @(litpool-.,pc), r0
mov.l @r0,r1
mov.l @(litpool-.,pc), r1
bsrf r1
nop
nop
litpool:
.long code - .
/trunk/gnu/binutils/gas/testsuite/gas/sh/fdpic.d
0,0 → 1,13
#objdump: -dr --prefix-addresses --show-raw-insn
#name: FDPIC relocations
 
dump.o: file format elf32-sh.*
 
Disassembly of section .text:
\.\.\.
0: R_SH_REL32 foo
4: R_SH_FUNCDESC foo
8: R_SH_GOT32 foo
c: R_SH_GOTOFF foo
10: R_SH_GOTFUNCDESC foo
14: R_SH_GOTOFFFUNCDESC foo
/trunk/gnu/binutils/gas/testsuite/gas/sh/tlsd.s
0,0 → 1,71
.section .tbss,"awT",@nobits
.align 2
.global foo, bar
.hidden bar
foo: .long 25
bar: .long 27
baz: .long 29
.text
.align 1
.global fn
.type fn, @function
fn:
mov.l r12,@-r15
mov.l r14,@-r15
sts.l pr,@-r15
mova .L3,r0
mov.l .L3,r12
add r0,r12
mov r15,r14
 
! Dynamic TLS model, foo not known to be in the current object
mov.l 1f,r4
mova 2f,r0
mov.l 2f,r1
add r0,r1
jsr @r1
add r12,r4
bra 3f
nop
.align 2
1: .long foo@TLSGD
2: .long __tls_get_addr@PLT
3:
 
! Dynamic TLS model, bar and baz known to be in the current object
mov.l 1f,r4
mova 2f,r0
mov.l 2f,r1
add r0,r1
jsr @r1
add r12,r4
bra 3f
nop
.align 2
1: .long bar@TLSLDM
2: .long __tls_get_addr@PLT
3:
! Just show that there can be arbitrary instructions here
mov #1,r2
 
mov.l .L4,r1
add r1,r0
! r0 now contains &bar
 
! Again, arbitrary instructions
mov.l r2,@r0
 
mov.l .L5,r1
add r1,r0
! r0 now contains &baz
 
mov r14,r15
lds.l @r15+,pr
mov.l @r15+,r14
rts
mov.l @r15+,r12
 
.align 2
.L3: .long _GLOBAL_OFFSET_TABLE_
.L4: .long bar@DTPOFF
.L5: .long baz@DTPOFF
/trunk/gnu/binutils/gas/testsuite/gas/sh/dsp.d
0,0 → 1,27
#objdump: -dr --prefix-addresses --show-raw-insn
#name: SH DSP basic instructions
#as: -dsp
# Test the SH DSP instructions:
 
.*: +file format .*sh.*
 
Disassembly of section .text:
0+000 <[^>]*> f6 80 [ ]*movs.w @-r2,x0
0+002 <[^>]*> f7 94 [ ]*movs.w @r3,x1
0+004 <[^>]*> f4 a8 [ ]*movs.w @r4\+,y0
0+006 <[^>]*> f5 bc [ ]*movs.w @r5\+r8,y1
0+008 <[^>]*> f5 c1 [ ]*movs.w m0,@-r5
0+00a <[^>]*> f4 e5 [ ]*movs.w m1,@r4
0+00c <[^>]*> f7 79 [ ]*movs.w a0,@r3\+
0+00e <[^>]*> f6 5d [ ]*movs.w a1,@r2\+r8
0+010 <[^>]*> f6 f2 [ ]*movs.l @-r2,a0g
0+012 <[^>]*> f7 d6 [ ]*movs.l @r3,a1g
0+014 <[^>]*> f4 8a [ ]*movs.l @r4\+,x0
0+016 <[^>]*> f5 9e [ ]*movs.l @r5\+r8,x1
0+018 <[^>]*> f5 a3 [ ]*movs.l y0,@-r5
0+01a <[^>]*> f4 b7 [ ]*movs.l y1,@r4
0+01c <[^>]*> f7 cb [ ]*movs.l m0,@r3\+
0+01e <[^>]*> f6 ef [ ]*movs.l m1,@r2\+r8
0+020 <[^>]*> f8 00 b1 07 [ ]padd x0,y0,a0
0+024 <[^>]*> f8 00 ed 07 [ ]plds a0,mach
0+028 <[^>]*> f8 00 b1 07 [ ]padd x0,y0,a0
/trunk/gnu/binutils/gas/testsuite/gas/sh/reg-prefix.s
0,0 → 1,3
.text
mov.l @r1,$r0
 
/trunk/gnu/binutils/gas/testsuite/gas/sh/basic.exp
0,0 → 1,182
# Copyright (C) 1995, 1996, 1997, 2002, 2003, 2004, 2005, 2006, 2007, 2009
# Free Software Foundation, Inc.
 
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
# Please email any bugs, comments, and/or additions to this file to:
# dejagnu@gnu.org
 
# Written by Cygnus Support.
 
if {[istarget "sh*-*-linux-*"] || [istarget "sh*l*-*-netbsdelf*"]} then {
global ASFLAGS
set ASFLAGS "$ASFLAGS -big"
}
if {[istarget "sh64*-*-*"] || [istarget "sh5*-*-*"]} then {
global ASFLAGS
 
set old_ASFLAGS $ASFLAGS
set ASFLAGS "$ASFLAGS --abi=32 --isa=SHcompact"
}
 
proc do_fp {} {
set testname "fp.s: floating point tests (sh3e)"
set x 0
 
gas_start "fp.s" "-al"
 
# Check the assembled instruction against a table built by the HP assembler
# Any differences should be checked by hand -- with the number of problems
# I've seen in the HP assembler I don't completely trust it.
#
# Instead of having a variable for each match string just increment the
# total number of matches seen. That's simpler when testing large numbers
# of instructions (as these tests to).
while 1 {
expect {
-re "^ +\[0-9\]+ 0000 F008\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0002 F00A\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0004 F009\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0006 F00B\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0008 F006\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 000a F007\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 000c F10C\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 000e F08D\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0010 F09D\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0012 F100\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0014 F101\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0016 F102\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0018 F103\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 001a F10E\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 001c F104\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 001e F105\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0020 F04D\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0022 F05D\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0024 F06D\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0026 F02D\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0028 F03D\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 002a F00D\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 002c F01D\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 002e 435A\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0030 4356\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0032 436A\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0034 4366\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0036 035A\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0038 4352\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 003a 036A\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 003c 4362\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0000 08F0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0002 0AF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0004 09F0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0006 0BF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0008 06F0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 000a 07F0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 000c 0CF1\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 000e 8DF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0010 9DF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0012 00F1\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0014 01F1\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0016 02F1\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0018 03F1\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 001a 0EF1\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 001c 04F1\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 001e 05F1\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0020 4DF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0022 5DF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0024 6DF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0026 2DF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0028 3DF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 002a 0DF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 002c 1DF0\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 002e 5A43\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0030 5643\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0032 6A43\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0034 6643\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0036 5A03\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 0038 5243\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 003a 6A03\[^\n\]*\n" { set x [expr $x+1] }
-re "^ +\[0-9\]+ 003c 6243\[^\n\]*\n" { set x [expr $x+1] }
-re "\[^\n\]*\n" { }
timeout { perror "timeout\n"; break }
eof { break }
}
}
 
# This was intended to do any cleanup necessary. It kinda looks like it
# isn't needed, but just in case, please keep it in for now.
gas_finish
 
# Did we find what we were looking for? If not, flunk it.
if [expr $x==31] then { pass $testname } else { fail $testname }
}
 
 
if [istarget sh*-*-*] then {
# Test the basic instruction parser.
do_fp
 
# coff is missing information about the machine type, so everything is
# dumped as sh4.
if {[istarget sh*-*coff] || [istarget sh*-pe*] || [istarget sh*-rtems]} then {
run_dump_test "pcrel-coff"
} elseif {[istarget sh*-hms] } {
run_dump_test "pcrel-hms"
} elseif {![istarget sh64*-*-*] && ![istarget sh5*-*-*] } {
# Test DSP instructions
run_dump_test "dsp"
 
run_dump_test "pcrel"
 
run_dump_test "pcrel2"
}
 
if {[istarget sh*-*elf] || [istarget sh*-*linux*]} then {
if {![istarget "sh64*-*-*"] && ![istarget "sh5*-*-*"]} then {
run_dump_test "sh4a"
run_dump_test "sh4a-fp"
 
run_dump_test "sh4a-dsp"
run_dump_test "sh4al-dsp"
 
run_dump_test "sh2a"
run_dump_test "sh2a-pic"
}
 
run_dump_test "pic"
run_dump_test "fdpic"
 
# Test TLS.
run_dump_test "tlsd"
 
run_dump_test "tlspic"
 
run_dump_test "tlsnopic"
 
# Test --renesas.
run_dump_test "renesas-1"
 
# Test --allow-reg-prefix.
run_dump_test "reg-prefix"
 
run_dump_test "too_large"
 
run_dump_test "sign-extension"
}
}
 
if {[info exists old_ASFLAGS]} {
global ASFLAGS
set ASFLAGS $old_ASFLAGS
}
/trunk/gnu/binutils/gas/testsuite/gas/sh/pic.s
0,0 → 1,43
.text
.align
 
mova .Lgot, r0
mov.l .Lgot, r12
add r0, r12
mov.l .Lfoogot, r0
mov.l @(r0,r12), r0
jsr @r0
nop
mov.l .Lfoogotoff, r0
add r12, r0
jsr @r0
nop
mov.l .Lfooplt, r1
mova .Lfooplt, r0
add r1, r0
jsr @r0
nop
mov.l .Lfooplt_old, r0
jsr @r0
.LPLTcall_old:
nop
mov.l .Lfooplt_new, r0
jsr @r0
.LPLTcall_new:
nop
.p2align 2
.Lgot:
.long GLOBAL_OFFSET_TABLE
.Lfoogot:
.long foo@GOT
.Lfoogotoff:
.long foo@GOTOFF
.Lfooplt:
.long foo@PLT
.Lfooplt_old:
.long foo@PLT + . - (.LPLTcall_old + 2)
.Lfooplt_new:
.long foo@PLT - (.LPLTcall_new + 2 - .)
.Lfooplt_old2:
.long foo@PLT + . - 2 - .LPLTcall_old
/trunk/gnu/binutils/gas/testsuite/gas/sh/err-be.s
0,0 → 1,10
! { dg-do assemble { target sh*-*-elf} }
! { dg-options "-little" }
! { dg-error "-big required" "" { target sh*-*-elf } 0 }
 
! Check that a mismatch between command-line options and the .big
! directive is identified.
 
.big
start:
nop

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