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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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  • This comparison shows the changes necessary to convert path 
    /open8_urisc
    from Rev 187 to Rev 188
    ↔ Reverse comparison
  •

Rev 187 → Rev 188

/trunk/VHDL/Open8_pkg.vhd
33,6 → 33,8
-- Seth Henry 03/12/20 Rationalized the naming of the CPU flags to match
-- the assembler names. Also removed superfluous
-- signals in the ALU and PC records.
-- Seth Henry 03/17/20 Added new subtype and constants for external
-- GP flags.
 
library ieee;
use ieee.std_logic_1164.all;
59,6 → 61,13
-- Note: INTERRUPT_BUNDLE must be exactly the same width as DATA_TYPE
subtype INTERRUPT_BUNDLE is DATA_TYPE;
 
subtype EXT_GP_FLAGS is std_logic_vector(3 downto 0);
 
constant EXT_GP4 : integer := 0;
constant EXT_GP5 : integer := 1;
constant EXT_GP6 : integer := 2;
constant EXT_GP7 : integer := 3;
 
-- Component declaration
-- (assumes a 1K RAM at 0x0000 and ROM at the top of the memory map)
component o8_cpu is
71,6 → 80,7
Enable_Auto_Increment : boolean := false;
BRK_Implements_WAI : boolean := false;
Enable_NMI : boolean := true;
RTI_Ignores_GP_Flags : boolean := false;
Default_Interrupt_Mask : DATA_TYPE := x"FF";
Reset_Level : std_logic := '0' );
port(
78,6 → 88,7
Reset : in std_logic;
CPU_Halt : in std_logic;
Interrupts : in INTERRUPT_BUNDLE;
GP_Flags : out EXT_GP_FLAGS;
Address : out ADDRESS_TYPE;
Rd_Data : in DATA_TYPE;
Rd_Enable : out std_logic;
/trunk/VHDL/o8_cpu.vhd
70,6 → 70,12
-- : non-maskable interrupt at the highest priority. To remain
-- : true to the original core, this should be set false.
-- :
-- : RTI_Ignores_GP_Flags alters the set of flag bits restored
-- : after an interrupt. By default, all of the flag bits are put
-- : back to their original state. If this flag is set true, only
-- : the lower four bits are restored, allowing ISR code to alter
-- : the GP flags persistently.
-- :
-- : Default_Interrupt_Mask sets the intial/reset value of the
-- : interrupt mask. To remain true to the original core, which
-- : had no interrupt mask, this should be set to x"FF". Otherwise
183,6 → 189,11
-- much smaller impact on Fmax/complexity than the
-- original clock enable, but imposes a mild impact
-- due to the need to reset the instruction pipeline
-- Seth Henry 03/17/20 Added generic to control whether RTI full restores
-- the flags, including the general purpose ones, or
-- only the core ALU flags (Z, N, and C). Also
-- brought out copies of the GP flags for external
-- connection.
 
library ieee;
use ieee.std_logic_1164.all;
199,10 → 210,11
ISR_Start_Addr : ADDRESS_TYPE := x"FFF0"; -- Bottom of ISR vec's
Stack_Start_Addr : ADDRESS_TYPE := x"03FF"; -- Top of Stack
Allow_Stack_Address_Move : boolean := false; -- Use Normal v8 RSP
Stack_Xfer_Flag : integer := PSR_GP4; -- If enabled, use GP4 to control RSP
Stack_Xfer_Flag : integer := PSR_GP4; -- GP4 modifies RSP
Enable_Auto_Increment : boolean := false; -- Modify indexed instr
BRK_Implements_WAI : boolean := false; -- BRK -> Wait for Int
Enable_NMI : boolean := true; -- Force INTR0 enabled
RTI_Ignores_GP_Flags : boolean := false; -- RTI restores all flags
Default_Interrupt_Mask : DATA_TYPE := x"FF"; -- Enable all Ints
Reset_Level : std_logic := '0' ); -- Active reset level
port(
210,6 → 222,7
Reset : in std_logic;
CPU_Halt : in std_logic := '0';
Interrupts : in INTERRUPT_BUNDLE := x"00";
GP_Flags : out EXT_GP_FLAGS;
--
Address : out ADDRESS_TYPE;
Rd_Data : in DATA_TYPE;
850,7 → 863,7
 
CPU_Regs: process( Reset, Clock )
variable Offset_SX : ADDRESS_TYPE;
variable i_Ints : INTERRUPT_BUNDLE := (others => '0');
variable i_Ints : INTERRUPT_BUNDLE := x"00";
variable Index : integer range 0 to 7 := 0;
variable Sum : std_logic_vector(8 downto 0) := "000000000";
variable Temp : std_logic_vector(8 downto 0) := "000000000";
867,7 → 880,7
 
CPU_Halt_Req <= '0';
 
Wr_Data <= (others => '0');
Wr_Data <= x"00";
Wr_Enable <= '0';
Rd_Enable <= '1';
 
889,10 → 902,12
ISR_Addr <= INT_VECTOR_0;
 
for i in 0 to 7 loop
Regfile(i) <= (others => '0');
Regfile(i) <= x"00";
end loop;
Flags <= x"00";
 
GP_Flags <= x"0";
 
elsif( rising_edge(Clock) )then
 
CPU_Halt_Req <= CPU_Halt;
1205,7 → 1220,10
Regfile(Index) <= Operand1;
 
when ALU_RFLG =>
Flags <= Operand1;
Flags(3 downto 0) <= Operand1(3 downto 0);
if( not RTI_Ignores_GP_Flags )then
Flags(7 downto 4)<= Operand1(7 downto 4);
end if;
 
when ALU_RSP =>
Regfile(0) <= Stack_Ptr(7 downto 0);
1219,6 → 1237,8
null;
end case;
 
GP_Flags <= Flags(7 downto 4);
 
end if;
end process;
 

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