URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc
- from Rev 207 to Rev 208
- ↔ Reverse comparison
Rev 207 → Rev 208
/trunk/VHDL/async_ser_rx.vhd
31,9 → 31,6
use ieee.std_logic_arith.all; |
use ieee.std_logic_misc.all; |
|
library work; |
use work.open8_pkg.all; |
|
entity async_ser_rx is |
generic( |
Reset_Level : std_logic; |
77,16 → 74,17
constant FULL_PERIOD : std_logic_vector(Baud_Bits - 1 downto 0) := |
conv_std_logic_vector(Full_Per_i, Baud_Bits); |
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signal Rx_Baud_Cntr : std_logic_vector(Baud_Bits - 1 downto 0); |
signal Rx_Baud_Cntr : std_logic_vector(Baud_Bits - 1 downto 0) := |
(others => '0'); |
|
signal Rx_In_SR : std_logic_vector(3 downto 0); |
signal Rx_In_SR : std_logic_vector(3 downto 0) := x"0"; |
alias Rx_In_Q is Rx_In_SR(3); |
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signal Rx_Buffer : std_logic_vector(7 downto 0); |
signal Rx_Parity : std_logic; |
signal Rx_PErr_int : std_logic; |
signal Rx_Buffer : std_logic_vector(7 downto 0) := x"00"; |
signal Rx_Parity : std_logic := '0'; |
signal Rx_PErr_int : std_logic := '0'; |
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signal Rx_State : std_logic_vector(3 downto 0); |
signal Rx_State : std_logic_vector(3 downto 0) := x"0"; |
alias Rx_Bit_Sel is Rx_State(2 downto 0); |
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-- State machine definitions |
/trunk/VHDL/async_ser_tx.vhd
31,9 → 31,6
use ieee.std_logic_arith.all; |
use ieee.std_logic_misc.all; |
|
library work; |
use work.open8_pkg.all; |
|
entity async_ser_tx is |
generic( |
Reset_Level : std_logic; |
55,19 → 52,31
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architecture behave of async_ser_tx is |
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-- The ceil_log2 function returns the minimum register width required to |
-- hold the supplied integer. |
function ceil_log2 (x : in natural) return natural is |
variable retval : natural; |
begin |
retval := 1; |
while ((2**retval) - 1) < x loop |
retval := retval + 1; |
end loop; |
return retval; |
end ceil_log2; |
|
constant Tick_Base : integer := Clock_Divider - 1; |
constant Tick_Bits : integer := ceil_log2(Tick_Base); |
constant TICK_DIV : std_logic_vector(Tick_Bits - 1 downto 0) := |
conv_std_logic_vector(Tick_Base, Tick_Bits); |
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signal Tick_Cntr : std_logic_vector(Tick_Bits - 1 downto 0); |
signal Tick_Trig : std_logic; |
signal Tick_Cntr : std_logic_vector(Tick_Bits - 1 downto 0) := |
(others => '0'); |
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signal Tx_Enable : std_logic; |
signal Tx_Buffer : std_logic_vector(7 downto 0); |
signal Tx_Parity : std_logic; |
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signal Tx_State : std_logic_vector(3 downto 0); |
signal Tick_Trig : std_logic := '0'; |
signal Tx_Enable : std_logic := '0'; |
signal Tx_Buffer : std_logic_vector(7 downto 0) := x"00"; |
signal Tx_Parity : std_logic := '0'; |
signal Tx_State : std_logic_vector(3 downto 0) := x"0"; |
alias Tx_Bit_Sel is Tx_State(2 downto 0); |
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-- State machine definitions |