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URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

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    /open8_urisc
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Rev 239 → Rev 240

/trunk/Sample Projects.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/VHDL/Open8_cfg.vhd
23,8 → 23,7
 
-- VHDL Units : open8_cfg
-- Description: Contains project specific constants to configure an Open8
-- system. This file contains an example from a working
-- configuration to demonstrate how it was used.
-- system
--
-- Revision History
-- Author Date Change
42,88 → 41,104
package open8_cfg is
 
-- Internal signals & constants
constant Clock_Frequency : real := 100000000.0;
constant Clock_Frequency : real := 100000000.0;
 
-- Peripheral Options
 
-- SDLC Configuration
constant Master_Mode : boolean := true;
constant BitClock_Freq : real := 20000000.0;
constant Clock_Offset : integer := 3;
constant Master_Mode : boolean := true;
constant BitClock_Freq : real := 20000000.0;
constant Clock_Offset : integer := 3;
 
-- FM Serial Configuration
constant SERIAL_58_125K : real := 58125.0;
constant PARITY_ENABLE : boolean := true;
constant PARITY_ODD_EVENn : std_logic := '1';
 
-- MAX7221 Driver Configuration
constant MAX7221_BITRATE : real := 5000000.0;
constant MAX7221_BITRATE : real := 5000000.0;
 
-- Test Vector Receiver Configuration
constant VECTOR_BITRATE : real := 10000000.0;
constant VECTOR_PARITY : boolean := TRUE;
constant VECTOR_ODD_EVENn : std_logic := '0';
 
-- Open8 CPU Options
constant Allow_Stack_Address_Move : boolean := true;
constant Stack_Xfer_Flag : integer := PSR_GP4;
constant Enable_Auto_Increment : boolean := true;
constant BRK_Implements_WAI : boolean := true;
constant Enable_NMI : boolean := true;
constant Sequential_Interrupts : boolean := true;
constant RTI_Ignores_GP_Flags : boolean := true;
constant Allow_Stack_Address_Move : boolean := true;
constant Stack_Xfer_Flag : integer := PSR_GP4;
constant Enable_Auto_Increment : boolean := true;
constant BRK_Implements_WAI : boolean := true;
constant Enable_NMI : boolean := true;
constant Sequential_Interrupts : boolean := true;
constant RTI_Ignores_GP_Flags : boolean := true;
constant Default_Int_Mask : DATA_TYPE := x"00";
 
-- Location and size of variable memory (BSS_START)
constant LRAM_Size : integer := 4096; -- Should match the LRAM model
constant LRAM_Address : ADDRESS_TYPE := x"0000";
-- System Memory Map
constant RAM_Address : ADDRESS_TYPE := x"0000"; -- System RAM
constant ALU_Address : ADDRESS_TYPE := x"1000"; -- ALU16 coprocessor
constant RTC_Address : ADDRESS_TYPE := x"1100"; -- System Timer / RT Clock
constant ETC_Address : ADDRESS_TYPE := x"1200"; -- Epoch Timer/Alarm Clock
constant TMR_Address : ADDRESS_TYPE := x"1400"; -- PIT timer
constant SDLC_Address : ADDRESS_TYPE := x"1800"; -- LCD serial interface
constant LED_Address : ADDRESS_TYPE := x"2000"; -- LED Display
constant DSW_Address : ADDRESS_TYPE := x"2100"; -- Dip Switches
constant BTN_Address : ADDRESS_TYPE := x"2200"; -- Push Buttons
constant SER_Address : ADDRESS_TYPE := x"2400"; -- UART interface
constant MAX_Address : ADDRESS_TYPE := x"2800"; -- Max 7221 base address
constant VEC_Address : ADDRESS_TYPE := x"3000"; -- Vector RX base address
constant CHR_Address : ADDRESS_TYPE := x"3100"; -- Elapsed Time / Chronometer
constant ROM_Address : ADDRESS_TYPE := x"8000"; -- Application ROM
constant ISR_Start_Addr : ADDRESS_TYPE := x"FFF0"; -- ISR Vector Table
 
-- Store interrupt vectors at the top of ROM (INTR_VEC_TABLE)
constant ISR_Start_Addr : ADDRESS_TYPE := x"FFF0";
-- RAM size is used to calculate the initial stack pointer, which is set at
-- the top of the RAM region.
constant RAM_Size : integer := 4096;
 
-- Interrupt assignments
-- These are assigned in order priority from 0 (highest) to 7 (lowest)
constant INT_PIT : integer range 0 to OPEN8_DATA_WIDTH - 1 := 0;
constant INT_ETC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 1;
constant INT_ALU : integer range 0 to OPEN8_DATA_WIDTH - 1 := 2;
constant INT_RTC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 3;
constant INT_SDLC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 4;
constant INT_BTN : integer range 0 to OPEN8_DATA_WIDTH - 1 := 5;
constant INT_VEC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 6;
constant INT_PIT : integer range 0 to OPEN8_DATA_WIDTH - 1 := 0;
constant INT_ETC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 1;
constant INT_TMR : integer range 0 to OPEN8_DATA_WIDTH - 1 := 2;
constant INT_ALU : integer range 0 to OPEN8_DATA_WIDTH - 1 := 3;
constant INT_RTC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 4;
constant INT_SDLC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 5;
constant INT_BTN : integer range 0 to OPEN8_DATA_WIDTH - 1 := 6;
constant INT_VEC : integer range 0 to OPEN8_DATA_WIDTH - 1 := 7;
 
-- Peripheral I/O map
constant ALU_Address : ADDRESS_TYPE := x"1000"; -- ALU16 coprocessor
constant TMR_Address : ADDRESS_TYPE := x"1100"; -- System Timer / RT Clock
constant ETC_Address : ADDRESS_TYPE := x"1200"; -- Epoch Timer/Alarm Clock
constant LED_Address : ADDRESS_TYPE := x"1400"; -- LED Display
constant DSW_Address : ADDRESS_TYPE := x"1800"; -- Dip Switches
constant BTN_Address : ADDRESS_TYPE := x"2000"; -- Push Buttons
constant SDLC_Address : ADDRESS_TYPE := x"2200"; -- LCD serial interface
constant SER_Address : ADDRESS_TYPE := x"2400"; -- UART interface
constant MAX_Address : ADDRESS_TYPE := x"2800"; -- Max 7221 base address
constant ROM_Address : ADDRESS_TYPE := x"8000"; -- Application ROM
-- Set this to the number of readable modules (entities wth a Rd_Data port) in the design,
-- as it sets the number of ports on the read aggregator function.
constant NUM_READ_BUSES : integer := 13;
 
-- Set this to the number of readable modules in the design, as it sets the
-- number of ports on the read aggregator function.
constant OPEN8_READ_BUSES : integer := 10;
 
-- Read Data Bus aggregator and bus assignments.
-- Note that the ordering isn't important, only that each device has a
-- unique number less than READ_BUS_COUNT.
constant RDB_RAM : integer range 0 to OPEN8_READ_BUSES - 1 := 0;
constant RDB_ALU : integer range 0 to OPEN8_READ_BUSES - 1 := 1;
constant RDB_TMR : integer range 0 to OPEN8_READ_BUSES - 1 := 2;
constant RDB_ETC : integer range 0 to OPEN8_READ_BUSES - 1 := 3;
constant RDB_LED : integer range 0 to OPEN8_READ_BUSES - 1 := 4;
constant RDB_DSW : integer range 0 to OPEN8_READ_BUSES - 1 := 5;
constant RDB_BTN : integer range 0 to OPEN8_READ_BUSES - 1 := 6;
constant RDB_SDLC : integer range 0 to OPEN8_READ_BUSES - 1 := 7;
constant RDB_SER : integer range 0 to OPEN8_READ_BUSES - 1 := 8;
constant RDB_ROM : integer range 0 to OPEN8_READ_BUSES - 1 := 9;
constant RDB_RAM : integer range 0 to NUM_READ_BUSES - 1 := 0;
constant RDB_ALU : integer range 0 to NUM_READ_BUSES - 1 := 1;
constant RDB_RTC : integer range 0 to NUM_READ_BUSES - 1 := 2;
constant RDB_TMR : integer range 0 to NUM_READ_BUSES - 1 := 3;
constant RDB_ETC : integer range 0 to NUM_READ_BUSES - 1 := 4;
constant RDB_LED : integer range 0 to NUM_READ_BUSES - 1 := 5;
constant RDB_DSW : integer range 0 to NUM_READ_BUSES - 1 := 6;
constant RDB_BTN : integer range 0 to NUM_READ_BUSES - 1 := 7;
constant RDB_SDLC : integer range 0 to NUM_READ_BUSES - 1 := 8;
constant RDB_SER : integer range 0 to NUM_READ_BUSES - 1 := 9;
constant RDB_VEC : integer range 0 to NUM_READ_BUSES - 1 := 10;
constant RDB_CHR : integer range 0 to NUM_READ_BUSES - 1 := 11;
constant RDB_ROM : integer range 0 to NUM_READ_BUSES - 1 := 12;
 
-- System configuration calculations - no adjustable parameters below this point
type OPEN8_BUS_ARRAY is array(0 to OPEN8_READ_BUSES - 1) of DATA_TYPE;
type OPEN8_BUS_ARRAY is array(0 to NUM_READ_BUSES - 1) of DATA_TYPE;
 
constant INIT_READ_BUS : OPEN8_BUS_ARRAY := (others => OPEN8_NULLBUS);
constant INIT_READ_BUS : OPEN8_BUS_ARRAY := (others => OPEN8_NULLBUS);
 
function merge_buses (x : in OPEN8_BUS_ARRAY) return DATA_TYPE;
 
-- Compute the stack start address based on the RAM size
constant RAM_Vector_Size : integer := ceil_log2(LRAM_Size - 1);
constant RAM_END_vector : std_logic_vector(RAM_Vector_Size - 1 downto 0)
:= (others => '1');
constant RAM_Vector_Size : integer := ceil_log2(RAM_Size - 1);
constant RAM_End_Addr : std_logic_vector(RAM_Vector_Size - 1 downto 0)
:= (others => '1');
 
constant Stack_Start_Addr : ADDRESS_TYPE := LRAM_Address + RAM_END_vector;
constant Stack_Start_Addr : ADDRESS_TYPE := RAM_Address + RAM_End_Addr;
 
end package;
 
134,7 → 149,7
variable retval : DATA_TYPE := x"00";
begin
retval := x"00";
for i in 0 to OPEN8_READ_BUSES - 1 loop
for i in 0 to NUM_READ_BUSES - 1 loop
retval := retval or x(i);
end loop;
return retval;
/trunk/VHDL/o8_sys_timer_ii.vhd
31,7 → 31,7
-- 0x01 AAAAAAAA Req Interval Byte 1 (RW)
-- 0x02 AAAAAAAA Req Interval Byte 2 (RW)
-- 0x03 BA------ Control/Status Register (RW)
-- A: Update timer (WR) or Update pending (RD)
-- A: Update timer (WR) or pending (RD) (RW)
-- B: Output Enable
--
-- Notes : Setting the output to 0x000000 will disable the timer
/trunk/VHDL/o8_vector_rx.vhd
0,0 → 1,230
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Entity: o8_vector_rx
-- Description: Receives a 6-bit vector command and 16-bit argument from the
-- vector_tx entity. Issues interrupt to the CPU on receipt of
-- three bytes.
--
-- Register Map:
-- Offset Bitfield Description Read/Write
-- 0x0 --AAAAAA Vector Select
-- 0x1 AAAAAAAA Vector Argument LB
-- 0x2 AAAAAAAA Vector Argument UB
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 04/15/20 Created from o8_epoch_timer due to requirement
-- change.
-- Seth Henry 04/16/20 Modified to make use of Open8 bus record
-- Seth Henry 05/06/20 Modified to eliminate request line and detect idle
-- conditions instead
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
library work;
use work.Open8_pkg.all;
 
entity o8_vector_rx is
generic(
Bit_Rate : real;
Enable_Parity : boolean;
Parity_Odd_Even_n : std_logic;
Clock_Frequency : real;
Address : ADDRESS_TYPE
);
port(
Open8_Bus : in OPEN8_BUS_TYPE;
Rd_Data : out DATA_TYPE;
Interrupt : out std_logic;
--
Rx_In : in std_logic
);
end entity;
 
architecture behave of o8_vector_rx is
 
alias Clock is Open8_Bus.Clock;
alias Reset is Open8_Bus.Reset;
 
constant User_Addr : std_logic_vector(15 downto 2) :=
Address(15 downto 2);
alias Comp_Addr is Open8_Bus.Address(15 downto 2);
signal Addr_Match : std_logic := '0';
 
alias Reg_Addr is Open8_Bus.Address(1 downto 0);
signal Reg_Sel : std_logic_vector(1 downto 0) := "00";
signal Rd_En : std_logic := '0';
 
constant BAUD_RATE_DIV : integer := integer(Clock_Frequency / Bit_Rate);
 
-- Period of each bit in sub-clocks (subtract one to account for zero)
constant Full_Per_i : integer := BAUD_RATE_DIV - 1;
constant Baud_Bits : integer := ceil_log2(Full_Per_i);
 
constant FULL_PERIOD : std_logic_vector(Baud_Bits - 1 downto 0) :=
conv_std_logic_vector(Full_Per_i, Baud_Bits);
 
signal Rx_Baud_Cntr : std_logic_vector(Baud_Bits - 1 downto 0) :=
(others => '0');
signal Rx_Baud_Tick : std_logic;
 
signal Rx_In_SR : std_logic_vector(2 downto 0);
alias Rx_In_MS is Rx_In_SR(2);
signal Rx_Idle_Cntr : std_logic_vector(3 downto 0);
signal RX_Idle : std_logic;
 
type VECTOR_RX_STATES is ( GET_VECTOR_CMD, GET_VECTOR_ARG_LB, GET_VECTOR_ARG_UB,
SEND_INTERRUPT );
signal Vector_State : VECTOR_RX_STATES := GET_VECTOR_CMD;
 
signal Vector_Cmd : DATA_TYPE := x"00";
signal Vector_Arg_LB : DATA_TYPE := x"00";
signal Vector_Arg_UB : DATA_TYPE := x"00";
 
signal Rx_Data : DATA_TYPE := x"00";
signal Rx_Valid : std_logic;
 
begin
 
Addr_Match <= '1' when Comp_Addr = User_Addr else '0';
 
io_reg: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rd_En <= '0';
Reg_Sel <= (others => '0');
Rd_Data <= OPEN8_NULLBUS;
elsif( rising_edge( Clock ) )then
Rd_Data <= OPEN8_NULLBUS;
Rd_En <= Addr_Match and Open8_Bus.Rd_En;
Reg_Sel <= Reg_Addr;
if( Rd_En = '1' )then
case( Reg_Sel )is
when "00" =>
Rd_Data <= Vector_Cmd;
when "01" =>
Rd_Data <= Vector_Arg_LB;
when "10" =>
Rd_Data <= Vector_Arg_UB;
when others =>
null;
end case;
end if;
end if;
end process;
 
RX_Idle_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Rx_Baud_Cntr <= (others => '0');
Rx_Baud_Tick <= '0';
Rx_In_SR <= (others => '1');
Rx_Idle_Cntr <= (others => '0');
Rx_Idle <= '0';
elsif( rising_edge(Clock) )then
Rx_Baud_Cntr <= Rx_Baud_Cntr - 1;
Rx_Baud_Tick <= '0';
if( Rx_Baud_Cntr = 0 )then
Rx_Baud_Cntr <= FULL_PERIOD;
Rx_Baud_Tick <= '1';
end if;
 
Rx_In_SR <= Rx_In_SR(1 downto 0) & Rx_In;
Rx_Idle_Cntr <= Rx_Idle_Cntr - Rx_Baud_Tick;
if( Rx_In_MS = '0' )then
Rx_Idle_Cntr <= (others => '1');
elsif( Rx_Idle_Cntr = 0 )then
Rx_Idle_Cntr <= (others => '0');
end if;
Rx_Idle <= nor_reduce(Rx_Idle_Cntr);
end if;
end process;
 
U_RX : entity work.async_ser_rx
generic map(
Reset_Level => Reset_Level,
Enable_Parity => Enable_Parity,
Parity_Odd_Even_n => Parity_Odd_Even_n,
Clock_Divider => BAUD_RATE_DIV
)
port map(
Clock => Clock,
Reset => Reset,
--
Rx_In => RX_In,
--
Rx_Data => RX_Data,
Rx_Valid => RX_Valid,
Rx_PErr => open
);
 
Vector_RX_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Vector_State <= GET_VECTOR_CMD;
Vector_Cmd <= x"00";
Vector_Arg_LB <= x"00";
Vector_Arg_UB <= x"00";
Interrupt <= '0';
elsif( rising_edge(Clock) )then
Interrupt <= '0';
case( Vector_State )is
when GET_VECTOR_CMD =>
if( Rx_Valid = '1' )then
Vector_Cmd <= Rx_Data;
Vector_State <= GET_VECTOR_ARG_LB;
end if;
 
when GET_VECTOR_ARG_LB =>
if( Rx_Valid = '1' )then
Vector_Arg_LB <= Rx_Data;
Vector_State <= GET_VECTOR_ARG_UB;
end if;
 
when GET_VECTOR_ARG_UB =>
if( Rx_Valid = '1' )then
Vector_Arg_UB <= Rx_Data;
Vector_State <= SEND_INTERRUPT;
end if;
 
when SEND_INTERRUPT =>
Interrupt <= '1';
Vector_State <= GET_VECTOR_CMD;
when others => null;
end case;
 
if( Rx_Idle = '1' )then
Vector_State <= GET_VECTOR_CMD;
end if;
 
end if;
end process;
 
end architecture;
/trunk/VHDL/vector_tx.vhd
0,0 → 1,214
-- Copyright (c)2020 Jeremy Seth Henry
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution,
-- where applicable (as part of a user interface, debugging port, etc.)
--
-- THIS SOFTWARE IS PROVIDED BY JEREMY SETH HENRY ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL JEREMY SETH HENRY BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- VHDL Entity: vector_tx
-- Description: Reads the pushbuttons and switches on the DE1-SOC board and
-- sends a vector command and argument to a vector_rx receiver
-- which executes them in lieu of a parallel controller.
--
-- Revision History
-- Author Date Change
------------------ -------- ---------------------------------------------------
-- Seth Henry 05/06/20 Added version block
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
 
entity vector_tx is
generic(
Button_Level : std_logic;
Bit_Rate : real;
Enable_Parity : boolean;
Parity_Odd_Even_n : std_logic;
Sys_Freq : real;
Reset_Level : std_logic
);
port(
Clock : in std_logic;
Reset : in std_logic;
--
Switches : in std_logic_vector(9 downto 0);
Pushbutton : in std_logic;
--
Tx_Out : out std_logic
);
end entity;
 
architecture behave of vector_tx is
 
signal uSec_Tick : std_logic;
signal mSec_Tick : std_logic;
 
signal Button_Pressed : std_logic := '0';
signal Button_CoS : std_logic := '0';
 
type VEC_ARG_TYPE is array(0 to 15) of std_logic_vector(15 downto 0);
constant VEC_ARGS : VEC_ARG_TYPE := (
x"0000",
x"1111",
x"2222",
x"3333",
x"4444",
x"5555",
x"6666",
x"7777",
x"8888",
x"9999",
x"AAAA",
x"BBBB",
x"CCCC",
x"DDDD",
x"EEEE",
x"FFFF"
);
 
alias Vector_Arg_Sel is Switches(9 downto 6);
alias Vector_Cmd_Sel is Switches(5 downto 0);
 
signal Vector_Cmd : std_logic_vector(7 downto 0);
 
signal Vector_Arg : std_logic_vector(15 downto 0);
alias Vector_Arg_LB is Vector_Arg(7 downto 0);
alias Vector_Arg_UB is Vector_Arg(15 downto 8);
 
type VECTOR_TX_STATES is (IDLE, SEND_CMD, WAIT_CMD, SEND_ARG_LB, WAIT_ARG_LB, SEND_ARG_UB, WAIT_ARG_UB );
signal Vector_State : VECTOR_TX_STATES := IDLE;
 
constant BAUD_RATE_DIV : integer := integer(Sys_Freq / Bit_Rate);
 
signal Tx_Data : std_logic_vector(7 downto 0) := x"00";
signal Tx_Valid : std_logic := '0';
signal Tx_Done : std_logic := '0';
 
begin
 
U_USEC : entity work.sys_tick
generic map(
Reset_Level => Reset_Level,
Sys_Freq => Sys_Freq
)
port map(
Clock => Clock,
Reset => Reset,
uSec_Tick => uSec_Tick,
mSec_Tick => mSec_Tick
);
 
U_BTN : entity work.button_db
generic map(
Button_Level => Button_Level,
Reset_Level => Reset_Level
)
port map(
Clock => Clock,
Reset => Reset,
mSec_Tick => mSec_Tick,
--
Button_In => Pushbutton,
--
Button_Pressed => Button_Pressed,
Button_CoS => Button_CoS
);
 
Input_reg_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Vector_Cmd <= x"00";
Vector_Arg <= x"0000";
elsif( rising_edge(Clock) )then
Vector_Cmd <= "00" & Vector_Cmd_Sel;
Vector_Arg <= VEC_ARGS(conv_integer(Vector_Arg_Sel));
end if;
end process;
 
TX_FSM_proc: process( Clock, Reset )
begin
if( Reset = Reset_Level )then
Vector_State <= IDLE;
Tx_Data <= x"00";
Tx_Valid <= '0';
elsif( rising_edge(Clock) )then
Tx_Data <= x"00";
Tx_Valid <= '0';
case( Vector_State )is
when IDLE =>
if( Button_CoS = '1' and Button_Pressed = '1' )then
Vector_State <= SEND_CMD;
end if;
 
when SEND_CMD =>
Tx_Data <= Vector_Cmd;
Tx_Valid <= '1';
Vector_State <= WAIT_CMD;
 
when WAIT_CMD =>
if( Tx_Done = '1' )then
Vector_State <= SEND_ARG_LB;
end if;
 
when SEND_ARG_LB =>
Tx_Data <= Vector_Arg_LB;
Tx_Valid <= '1';
Vector_State <= WAIT_ARG_LB;
 
when WAIT_ARG_LB =>
if( Tx_Done = '1' )then
Vector_State <= SEND_ARG_UB;
end if;
 
when SEND_ARG_UB =>
Tx_Data <= Vector_Arg_UB;
Tx_Valid <= '1';
Vector_State <= WAIT_ARG_UB;
 
when WAIT_ARG_UB =>
if( Tx_Done = '1' )then
Vector_State <= IDLE;
end if;
 
end case;
end if;
end process;
 
U_TX : entity work.async_ser_tx
generic map(
Reset_Level => Reset_Level,
Enable_Parity => Enable_Parity,
Parity_Odd_Even_n => Parity_Odd_Even_n,
Clock_Divider => BAUD_RATE_DIV
)
port map(
Clock => Clock,
Reset => Reset,
--
Tx_Data => Tx_Data,
Tx_Valid => Tx_Valid,
--
Tx_Out => Tx_Out,
Tx_Done => Tx_Done
);
 
end architecture;

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