URL
https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
Subversion Repositories open8_urisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/open8_urisc
- from Rev 282 to Rev 283
- ↔ Reverse comparison
Rev 282 → Rev 283
/trunk/VHDL/o8_sdlc_if.vhd
212,9 → 212,7
signal BClk_Okay : std_logic := '0'; |
|
-- Packet Transmit state logic |
type TX_FSM_STATES is ( INIT_FLAG, |
WR_CLOCK_STATE, WAIT_FOR_CLOCK, |
WAIT_FOR_UPDATE, |
type TX_FSM_STATES is ( INIT_FLAG, WR_CLOCK_STATE, WAIT_FOR_UPDATE, |
RD_TX_REGISTER, TX_INIT, |
TX_START_FLAG, TX_WAIT_START_FLAG, |
TX_MESG_DATA, TX_ADV_ADDR, TX_WAIT_MESG_DATA, |
616,14 → 614,6
TX_FSM_State <= WR_CLOCK_STATE; |
end if; |
|
when WAIT_FOR_UPDATE => |
if( TX_Ctl_Clk = '1' )then |
TX_FSM_State <= WR_CLOCK_STATE; |
end if; |
if( TX_Ctl_Len = '1' )then |
TX_FSM_State <= RD_TX_REGISTER; |
end if; |
|
when WR_CLOCK_STATE => |
DP_Port0_Addr <= CK_REGISTER; |
DP_Port0_Req <= '1'; |
633,13 → 623,16
TX_Interrupt <= TX_Int_pend; |
TX_Int_pend <= '0'; |
DP_Port0_Req <= '0'; |
TX_FSM_State <= WAIT_FOR_CLOCK; |
TX_FSM_State <= WAIT_FOR_UPDATE; |
end if; |
|
when WAIT_FOR_CLOCK => |
if( BClk_Okay = '1' )then |
TX_FSM_State <= WAIT_FOR_UPDATE; |
when WAIT_FOR_UPDATE => |
if( TX_Ctl_Clk = '1' )then |
TX_FSM_State <= WR_CLOCK_STATE; |
end if; |
if( TX_Ctl_Len = '1' and BClk_Okay = '1' )then |
TX_FSM_State <= RD_TX_REGISTER; |
end if; |
|
when RD_TX_REGISTER => |
DP_Port0_Addr <= TX_REGISTER; |