URL
https://opencores.org/ocsvn/open_hitter/open_hitter/trunk
Subversion Repositories open_hitter
Compare Revisions
- This comparison shows the changes necessary to convert path
/open_hitter/trunk/bench/vhdl
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/hitter_wrapper.vhd
1,32 → 1,120
-- hitter_wrapper.vhd |
-- Synthesizable wrapper, exercise wrapper with NSEW buttons and LEDs to report on fpga dev board |
-- target env: Xilinx Virtex 6 / ML605 |
-- |
-- <LGPL Required> |
-- <History from svn, link required> |
|
--//////////////////////////////////////////////////////////////////// |
--// //// |
--// hitter_wrapper.vhd //// |
--// //// |
--// This file is part of the open_hitter opencores effort. //// |
--// <http://www.opencores.org/cores/open_hitter/> //// |
--// //// |
--// Module Description: //// |
--// Simulation program (non-synthesizable) //// |
--// Drives auto regression tests via NSEW button actions and //// |
--// NSEW LED reporting //// |
--// target env: ghdl <attrib required> //// |
--// //// |
--// To Do: //// |
--// #LOTS //// |
--// //// |
--// Author(s): //// |
--// - Stephen Hawes //// |
--// //// |
--//////////////////////////////////////////////////////////////////// |
--// //// |
--// Copyright (C) 2015 Stephen Hawes and OPENCORES.ORG //// |
--// //// |
--// This source file may be used and distributed without //// |
--// restriction provided that this copyright statement is not //// |
--// removed from the file and that any derivative work contains //// |
--// the original copyright notice and the associated disclaimer. //// |
--// //// |
--// This source file is free software; you can redistribute it //// |
--// and/or modify it under the terms of the GNU Lesser General //// |
--// Public License as published by the Free Software Foundation; //// |
--// either version 2.1 of the License, or (at your option) any //// |
--// later version. //// |
--// //// |
--// This source is distributed in the hope that it will be //// |
--// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
--// PURPOSE. See the GNU Lesser General Public License for more //// |
--// details. //// |
--// //// |
--// You should have received a copy of the GNU Lesser General //// |
--// Public License along with this source; if not, download it //// |
--// from <http://www.opencores.org/lgpl.shtml> //// |
--// //// |
--//////////////////////////////////////////////////////////////////// |
--// |
--// \$Id\$ TAKE OUT THE \'s and this comment in order to get this to work |
--// |
--// CVS Revision History |
--// |
--// \$Log\$ TAKE OUT THE \'s and this comment in order to get this to work |
--// |
library ieee; |
use ieee.std_logic_1164.all; |
--use ieee.std_logic_arith.all; |
--library unisim; |
--use unisim.vcomponents.all; |
use ieee.std_logic_1164.all; |
use std.textio.all; -- Imports the standard textio package. |
|
entity hitter_wrapper is |
end hitter_wrapper; |
|
architecture behaviour of hitter_wrapper is |
component hitter_sim |
port( RX_CLK: in std_logic; |
PUSH_BUTTONS_5BITS_TRI_I: in std_logic_vector(4 downto 0); |
LEDS_POSITIONS_TRI_O: out std_logic_vector(4 downto 0) |
); |
end component; |
for hitter_sim_0: hitter_sim use entity work.hitter_sim; |
signal RX_CLK: std_logic; |
signal PUSH_BUTTONS_5BITS_TRI_I: std_logic_vector(4 downto 0); |
signal LEDS_POSITIONS_TRI_O: std_logic_vector(4 downto 0); |
begin |
hitter_sim_0: hitter_sim port map ( |
RX_CLK => RX_CLK, |
PUSH_BUTTONS_5BITS_TRI_I => PUSH_BUTTONS_5BITS_TRI_I, |
LEDS_POSITIONS_TRI_O => LEDS_POSITIONS_TRI_O ); |
process |
variable l : line; |
variable counted : integer; |
begin |
write (l, String'("Exercising hitter_sim")); |
writeline (output, l); |
|
entity hitter_wrapper is |
port ( |
PUSH_BUTTONS_5BITS_TRI_I: in std_logic_vector(4 downto 0); |
LEDS_POSITIONS_TRI_O: out std_logic_vector(4 downto 0) |
); |
end hitter_wrapper; |
RX_CLK <= '0'; |
wait for 1 ns; |
|
architecture implementation of hitter_wrapper is |
begin |
LEDS_POSITIONS_TRI_O(0) <= PUSH_BUTTONS_5BITS_TRI_I(1); |
LEDS_POSITIONS_TRI_O(1) <= PUSH_BUTTONS_5BITS_TRI_I(2); |
LEDS_POSITIONS_TRI_O(2) <= PUSH_BUTTONS_5BITS_TRI_I(3); |
LEDS_POSITIONS_TRI_O(3) <= PUSH_BUTTONS_5BITS_TRI_I(4); |
LEDS_POSITIONS_TRI_O(4) <= PUSH_BUTTONS_5BITS_TRI_I(0); |
for counted in 0 to 30 loop |
-- Instruct: |
|
end implementation; |
if (counted = 2) then |
PUSH_BUTTONS_5BITS_TRI_I <= std_logic_vector'("11111"); |
else |
PUSH_BUTTONS_5BITS_TRI_I <= std_logic_vector'("00000"); |
end if; |
|
RX_CLK <= '1'; |
wait for 1 ns; |
|
-- Report: |
write (l, String'("Count:")); |
write(l, counted); |
write (l, String'(" LEDs: ")); |
for i in LEDS_POSITIONS_TRI_O'range loop |
case LEDS_POSITIONS_TRI_O(i) is |
when '1' => write(l, character'('1')); |
when others => write(l, character'('0')); |
end case; |
end loop; |
writeline(output, l); |
|
-- Reset: |
RX_CLK <= '0'; |
wait for 1 ns; |
end loop; |
|
write (l, String'("Done hitter_sim")); |
writeline (output, l); |
wait; |
end process; |
end behaviour; |
|
/parse_price_sim.vhd
0,0 → 1,148
--//////////////////////////////////////////////////////////////////// |
--// //// |
--// parse_price_sim.vhd //// |
--// //// |
--// This file is part of the open_hitter opencores effort. //// |
--// <http://www.opencores.org/cores/open_hitter/> //// |
--// //// |
--// Module Description: //// |
--// Simulation program (synthesizable) //// |
--// Unit test for parse_price.vhd //// |
--// //// |
--// To Do: //// |
--// #LOTS //// |
--// //// |
--// Author(s): //// |
--// - Stephen Hawes //// |
--// //// |
--//////////////////////////////////////////////////////////////////// |
--// //// |
--// Copyright (C) 2015 Stephen Hawes and OPENCORES.ORG //// |
--// //// |
--// This source file may be used and distributed without //// |
--// restriction provided that this copyright statement is not //// |
--// removed from the file and that any derivative work contains //// |
--// the original copyright notice and the associated disclaimer. //// |
--// //// |
--// This source file is free software; you can redistribute it //// |
--// and/or modify it under the terms of the GNU Lesser General //// |
--// Public License as published by the Free Software Foundation; //// |
--// either version 2.1 of the License, or (at your option) any //// |
--// later version. //// |
--// //// |
--// This source is distributed in the hope that it will be //// |
--// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
--// PURPOSE. See the GNU Lesser General Public License for more //// |
--// details. //// |
--// //// |
--// You should have received a copy of the GNU Lesser General //// |
--// Public License along with this source; if not, download it //// |
--// from <http://www.opencores.org/lgpl.shtml> //// |
--// //// |
--//////////////////////////////////////////////////////////////////// |
--// |
--// \$Id\$ TAKE OUT THE \'s and this comment in order to get this to work |
--// |
--// CVS Revision History |
--// |
--// \$Log\$ TAKE OUT THE \'s and this comment in order to get this to work |
--// |
library ieee; |
use ieee.std_logic_1164.all; |
|
entity parse_price_sim is |
port ( |
RX_CLK: in std_logic; |
restart: in std_logic; |
processing: out std_logic; |
result_is_ok: out std_logic |
); |
end parse_price_sim; |
|
architecture behav of parse_price_sim is |
component parse_price |
port ( |
in_byte: in std_logic_vector(7 downto 0); |
byte_reset: in std_logic; |
byte_ready: in std_logic; |
price_ready: out std_logic; |
-- pxdata: out price_packet |
px_type: out std_logic_vector(4 downto 0); |
buy_sell: out std_logic_vector(2 downto 0); -- 111 buy, 000 sell |
px: out std_logic_vector(15 downto 0); -- price |
qty: out std_logic_vector(15 downto 0); -- quantity |
sec: out std_logic_vector(55 downto 0); -- 7x 8bits securities identifier |
id: out std_logic_vector(15 downto 0) -- unique/identifier/counter |
); |
end component; |
-- Specifies which entity is bound with the component. |
for parse_price_0: parse_price use entity work.parse_price; |
signal in_byte: std_logic_vector(7 downto 0); |
signal byte_reset: std_logic; |
signal byte_ready: std_logic; |
signal price_ready: std_logic; |
-- pxdata: price_packet |
signal px_type: std_logic_vector(4 downto 0); |
signal buy_sell: std_logic_vector(2 downto 0); -- 111 buy, 000 sell |
signal px: std_logic_vector(15 downto 0); -- price |
signal qty: std_logic_vector(15 downto 0); -- quantity |
signal sec: std_logic_vector(55 downto 0); -- 7x 8bits securities identifier |
signal id: std_logic_vector(15 downto 0); -- unique/identifier/counter |
signal pos: integer; |
begin |
-- Component instantiation. |
parse_price_0: parse_price port map ( |
in_byte => in_byte, |
byte_reset => byte_reset, |
byte_ready => byte_ready, |
price_ready => price_ready, |
-- price_packet |
px_type => px_type, |
buy_sell => buy_sell, |
px => px, |
qty => qty, |
sec => sec, |
id => id |
); |
process (RX_CLK) is |
constant pkt : std_logic_vector(103 downto 0) := X"081234567857484154534543C0"; |
begin |
if (px_type = B"01000") and (buy_sell = B"000") and (px = B"00000000_00001000") |
and (qty = B"00110100_00110100") |
and (sec = B"01001000_01000001_01000001_01010100_01010100_01010011_01010011") |
and (id = B"01000011_01000011") |
then |
result_is_ok <= '1'; |
processing <= '0'; |
else |
result_is_ok <= '0'; |
end if; |
|
if rising_edge(RX_CLK) then |
if (pos < 0) then |
byte_ready <= '0'; |
elsif (pos < 13) then |
in_byte <= pkt(8*pos+7 downto 8*pos); |
byte_ready <= '1'; |
byte_reset <= '0'; |
else |
byte_ready <= '0'; |
end if; |
|
if (restart = '1') then |
byte_reset <= '1'; |
processing <= '1'; |
pos <= 15; |
end if; |
|
if (pos > -10) then |
pos <= pos -1; |
end if; |
|
else -- falling edge RX_CLK |
byte_ready <= '0'; |
end if; |
|
end process; |
end behav; |
/hitter_sim.vhd
1,51 → 1,108
-- hitter_sim.vhd |
-- simulation program (non-synthesizable) to drive auto regression tests |
-- target env: vhdl <attrib required> |
-- |
-- <LGPL reqd> |
-- <svn link for change history reqd> |
--//////////////////////////////////////////////////////////////////// |
--// //// |
--// hitter_sim.vhd //// |
--// //// |
--// This file is part of the open_hitter opencores effort. //// |
--// <http://www.opencores.org/cores/open_hitter/> //// |
--// //// |
--// Module Description: //// |
--// Synthesizable simulation class for the class 'hitter' //// |
--// * translates button actions/results onto NSEW buttons //// |
--// and NSEW LEDs //// |
--// * target env: Xilinx Virtex 6 / ML605 //// |
--// //// |
--// To Do: //// |
--// #LOTS //// |
--// //// |
--// Author(s): //// |
--// - Stephen Hawes //// |
--// //// |
--//////////////////////////////////////////////////////////////////// |
--// //// |
--// Copyright (C) 2015 Stephen Hawes and OPENCORES.ORG //// |
--// //// |
--// This source file may be used and distributed without //// |
--// restriction provided that this copyright statement is not //// |
--// removed from the file and that any derivative work contains //// |
--// the original copyright notice and the associated disclaimer. //// |
--// //// |
--// This source file is free software; you can redistribute it //// |
--// and/or modify it under the terms of the GNU Lesser General //// |
--// Public License as published by the Free Software Foundation; //// |
--// either version 2.1 of the License, or (at your option) any //// |
--// later version. //// |
--// //// |
--// This source is distributed in the hope that it will be //// |
--// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
--// PURPOSE. See the GNU Lesser General Public License for more //// |
--// details. //// |
--// //// |
--// You should have received a copy of the GNU Lesser General //// |
--// Public License along with this source; if not, download it //// |
--// from <http://www.opencores.org/lgpl.shtml> //// |
--// //// |
--//////////////////////////////////////////////////////////////////// |
--// |
--// \$Id\$ TAKE OUT THE \'s and this comment in order to get this to work |
--// |
--// CVS Revision History |
--// |
--// \$Log\$ TAKE OUT THE \'s and this comment in order to get this to work |
--// |
library ieee; |
use ieee.std_logic_1164.all; |
use std.textio.all; -- Imports the standard textio package. |
use ieee.std_logic_1164.all; |
|
-- Seed buttons wrapper program |
entity hitter_sim is |
end hitter_sim; |
|
architecture behaviour of hitter_sim is |
component hitter_wrapper |
port( PUSH_BUTTONS_5BITS_TRI_I: in std_logic_vector(4 downto 0); |
LEDS_POSITIONS_TRI_O: out std_logic_vector(4 downto 0) |
); |
end component; |
-- Specifies which entity is bound with the component. |
for hitter_wrapper_0: hitter_wrapper use entity work.hitter_wrapper; |
signal PUSH_BUTTONS_5BITS_TRI_I: std_logic_vector(4 downto 0); |
signal LEDS_POSITIONS_TRI_O: std_logic_vector(4 downto 0); |
begin |
-- Component instantiation. |
hitter_wrapper_0: hitter_wrapper port map ( |
PUSH_BUTTONS_5BITS_TRI_I => PUSH_BUTTONS_5BITS_TRI_I, |
LEDS_POSITIONS_TRI_O => LEDS_POSITIONS_TRI_O ); |
process |
variable l : line; |
begin |
write (l, String'("Exercising hitter_wrapper")); |
writeline (output, l); |
entity hitter_sim is |
port ( |
RX_CLK: in std_logic; |
PUSH_BUTTONS_5BITS_TRI_I: in std_logic_vector(4 downto 0); |
LEDS_POSITIONS_TRI_O: out std_logic_vector(4 downto 0) |
); |
end hitter_sim; |
|
PUSH_BUTTONS_5BITS_TRI_I <= std_logic_vector'("00100"); |
wait for 1 ns; |
for i in LEDS_POSITIONS_TRI_O'range loop |
case LEDS_POSITIONS_TRI_O(i) is |
when '1' => write(l, character'('1')); |
when others => write(l, character'('0')); |
end case; |
end loop; |
writeline(output, l); |
architecture implementation of hitter_sim is |
component parse_price_sim |
port ( |
RX_CLK: in std_logic; |
restart: in std_logic; |
processing: out std_logic; |
result_is_ok: out std_logic |
); |
end component; |
for parse_price_sim_0: parse_price_sim use entity work.parse_price_sim; |
--signal RX_CLK: std_logic; |
signal restart: std_logic; |
signal processing: std_logic; |
signal result_is_ok: std_logic; |
-- |
signal alight: std_logic := '0'; |
signal pos: integer := 0; |
begin |
parse_price_sim_0: parse_price_sim port map ( |
RX_CLK => RX_CLK, |
restart => restart, |
processing => processing, |
result_is_ok => result_is_ok |
); |
-- |
flasher: process (RX_CLK) is |
begin |
if rising_edge(RX_CLK) then |
if (pos < 4) then -- ghdl flash |
-- if (pos < 62500000) then -- 125Mhz timing / 0.5s |
pos <= pos + 1; |
else |
alight <= not alight; |
pos <= 0; |
end if; |
end if; |
end process flasher; |
|
write (l, String'("Done hitter_wrapper")); |
writeline (output, l); |
wait; |
end process; |
end behaviour; |
LEDS_POSITIONS_TRI_O(0) <= alight; |
LEDS_POSITIONS_TRI_O(1) <= result_is_ok; |
LEDS_POSITIONS_TRI_O(2) <= result_is_ok; |
LEDS_POSITIONS_TRI_O(3) <= processing; |
restart <= PUSH_BUTTONS_5BITS_TRI_I(0); |
end implementation; |
|
/build.sh
0,0 → 1,20
#!/bin/bash |
|
# analysis |
ghdl -a parse_price.vhd |
ghdl -a parse_price_sim.vhd |
ghdl -a parse_price_wrapper.vhd |
ghdl -a hitter_sim.vhd |
ghdl -a hitter_wrapper.vhd |
|
# elaboration & run |
ghdl -e parse_price |
|
ghdl -e hitter_sim |
ghdl -e parse_price_sim |
|
ghdl -e parse_price_wrapper |
ghdl -r parse_price_wrapper |
|
ghdl -e hitter_wrapper |
ghdl -r hitter_wrapper |
build.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: parse_price.vhd
===================================================================
--- parse_price.vhd (nonexistent)
+++ parse_price.vhd (revision 3)
@@ -0,0 +1,119 @@
+--////////////////////////////////////////////////////////////////////
+--// ////
+--// parse_price.vhd ////
+--// ////
+--// This file is part of the open_hitter opencores effort. ////
+--// ////
+--// ////
+--// Module Description: ////
+--// Byte stream input, open hitter price output ////
+--// ////
+--// To Do: ////
+--// #LOTS ////
+--// ////
+--// Author(s): ////
+--// - Stephen Hawes ////
+--// ////
+--////////////////////////////////////////////////////////////////////
+--// ////
+--// Copyright (C) 2015 Stephen Hawes and OPENCORES.ORG ////
+--// ////
+--// This source file may be used and distributed without ////
+--// restriction provided that this copyright statement is not ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer. ////
+--// ////
+--// This source file is free software; you can redistribute it ////
+--// and/or modify it under the terms of the GNU Lesser General ////
+--// Public License as published by the Free Software Foundation; ////
+--// either version 2.1 of the License, or (at your option) any ////
+--// later version. ////
+--// ////
+--// This source is distributed in the hope that it will be ////
+--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+--// PURPOSE. See the GNU Lesser General Public License for more ////
+--// details. ////
+--// ////
+--// You should have received a copy of the GNU Lesser General ////
+--// Public License along with this source; if not, download it ////
+--// from ////
+--// ////
+--////////////////////////////////////////////////////////////////////
+--//
+--// \$Id\$ TAKE OUT THE \'s and this comment in order to get this to work
+--//
+--// CVS Revision History
+--//
+--// \$Log\$ TAKE OUT THE \'s and this comment in order to get this to work
+--//
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity parse_price is
+ port (
+ in_byte: in std_logic_vector(7 downto 0);
+ byte_reset: in std_logic;
+ byte_ready: in std_logic;
+ price_ready: out std_logic;
+ -- pxdata: out price_packet
+ px_type: out std_logic_vector(4 downto 0);
+ buy_sell: out std_logic_vector(2 downto 0); -- 111 buy, 000 sell
+ px: out std_logic_vector(15 downto 0); -- price
+ qty: out std_logic_vector(15 downto 0); -- quantity
+ sec: out std_logic_vector(55 downto 0); -- 7x 8bits securities identifier
+ id: out std_logic_vector(15 downto 0) -- unique/identifier/counter
+ );
+end parse_price;
+
+architecture parse_price_implementation of parse_price is
+ signal infield: std_logic_vector(55 downto 0);
+ signal pos: integer range 0 to 13;
+begin
+ parse: process (byte_ready) is
+ begin
+ infield(55 downto 8) <= infield(47 downto 0);
+ infield(7 downto 0) <= in_byte;
+ if rising_edge(byte_ready) then
+ case pos is
+ when 0 =>
+ px_type <= in_byte(4 downto 0);
+ buy_sell <= in_byte(7 downto 5);
+ infield <= (others=>'0');
+ when 1 =>
+ px <= infield(15 downto 0);
+ infield <= (others=>'0');
+ when 3 =>
+ qty <= infield(15 downto 0);
+ infield <= (others=>'0');
+ when 10 =>
+ sec <= infield(55 downto 0);
+ infield <= (others=>'0');
+ when 12 =>
+ id <= infield(15 downto 0);
+ infield <= (others=>'0');
+ price_ready <= std_logic'('1');
+ when others => null;
+ end case;
+
+ if byte_reset = '1' then
+ pos <= 0;
+ else
+ pos <= pos+1;
+ end if;
+ end if;
+ end process parse;
+
+end parse_price_implementation;
+
+-- 2008: can make price packet generic, eg;
+-- generic ( type price_packet );
+-- type price_packet is record
+-- px_type: std_logic_vector(4 downto 0);
+-- buy_sell: std_logic_vector(2 downto 0); -- 111 buy, 000 sell
+-- px: std_logic_vector(15 downto 0); -- price
+-- qty: std_logic_vector(15 downto 0); -- quantity
+-- sec: std_logic_vector(55 downto 0); -- 7x 8bits securities identifier
+-- id: std_logic_vector(15 downto 0); -- unique/identifier/counter
+-- end record price_packet;
+
Index: parse_price_wrapper.vhd
===================================================================
--- parse_price_wrapper.vhd (nonexistent)
+++ parse_price_wrapper.vhd (revision 3)
@@ -0,0 +1,182 @@
+--////////////////////////////////////////////////////////////////////
+--// ////
+--// parse_price_wrapper.vhd ////
+--// ////
+--// This file is part of the open_hitter opencores effort. ////
+--// ////
+--// ////
+--// Module Description: ////
+--// Simulation program (non-synthesizable) ////
+--// Single module development: parse_price.vhd ////
+--// target env: ghdl ////
+--// ////
+--// To Do: ////
+--// #LOTS ////
+--// ////
+--// Author(s): ////
+--// - Stephen Hawes ////
+--// ////
+--////////////////////////////////////////////////////////////////////
+--// ////
+--// Copyright (C) 2015 Stephen Hawes and OPENCORES.ORG ////
+--// ////
+--// This source file may be used and distributed without ////
+--// restriction provided that this copyright statement is not ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer. ////
+--// ////
+--// This source file is free software; you can redistribute it ////
+--// and/or modify it under the terms of the GNU Lesser General ////
+--// Public License as published by the Free Software Foundation; ////
+--// either version 2.1 of the License, or (at your option) any ////
+--// later version. ////
+--// ////
+--// This source is distributed in the hope that it will be ////
+--// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+--// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+--// PURPOSE. See the GNU Lesser General Public License for more ////
+--// details. ////
+--// ////
+--// You should have received a copy of the GNU Lesser General ////
+--// Public License along with this source; if not, download it ////
+--// from ////
+--// ////
+--////////////////////////////////////////////////////////////////////
+--//
+--// \$Id\$ TAKE OUT THE \'s and this comment in order to get this to work
+--//
+--// CVS Revision History
+--//
+--// \$Log\$ TAKE OUT THE \'s and this comment in order to get this to work
+--//
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all; -- Imports the standard textio package.
+-- use ieee.std_logic_textio.all;
+
+ entity parse_price_wrapper is
+ end parse_price_wrapper;
+
+ architecture behaviour of parse_price_wrapper is
+ component parse_price
+ port (
+ in_byte: in std_logic_vector(7 downto 0);
+ byte_reset: in std_logic;
+ byte_ready: in std_logic;
+ price_ready: out std_logic;
+ -- pxdata: out price_packet
+ px_type: out std_logic_vector(4 downto 0);
+ buy_sell: out std_logic_vector(2 downto 0); -- 111 buy, 000 sell
+ px: out std_logic_vector(15 downto 0); -- price
+ qty: out std_logic_vector(15 downto 0); -- quantity
+ sec: out std_logic_vector(55 downto 0); -- 7x 8bits securities identifier
+ id: out std_logic_vector(15 downto 0) -- unique/identifier/counter
+ );
+ end component;
+ for parse_price_0: parse_price use entity work.parse_price;
+ signal in_byte: std_logic_vector(7 downto 0);
+ signal byte_reset: std_logic;
+ signal byte_ready: std_logic;
+ signal price_ready: std_logic;
+ -- pxdata: price_packet
+ signal px_type: std_logic_vector(4 downto 0);
+ signal buy_sell: std_logic_vector(2 downto 0); -- 111 buy, 000 sell
+ signal px: std_logic_vector(15 downto 0); -- price
+ signal qty: std_logic_vector(15 downto 0); -- quantity
+ signal sec: std_logic_vector(55 downto 0); -- 7x 8bits securities identifier
+ signal id: std_logic_vector(15 downto 0); -- unique/identifier/counter
+ begin
+ parse_price_0: parse_price port map (
+ in_byte => in_byte,
+ byte_reset => byte_reset,
+ byte_ready => byte_ready,
+ price_ready => price_ready,
+ -- price_packet
+ px_type => px_type,
+ buy_sell => buy_sell,
+ px => px,
+ qty => qty,
+ sec => sec,
+ id => id
+ );
+ process
+ variable l : line;
+ -- WWHHAATTSSEECC
+ constant pkt : std_logic_vector(103 downto 0) := X"081234567857484154534543C0";
+ variable pos : integer;
+ variable offset : integer;
+ variable eoffset : integer;
+ begin
+ write (l, String'("Exercising parse_price"));
+ writeline (output, l);
+
+ byte_ready <= '0';
+ wait for 1 ns;
+ byte_reset <= '1';
+ byte_ready <= '1';
+ wait for 1 ns;
+ byte_ready <= '0';
+ wait for 1 ns;
+ byte_reset <= '0';
+
+ for pos in 12 downto 0 loop
+ in_byte <= pkt(8*pos+7 downto 8*pos);
+ byte_ready <= '1';
+ wait for 1 ns;
+
+ for i in in_byte'range loop
+ write(l, std_logic'image(in_byte(i)) );
+ end loop;
+
+ write(l, String'(" px_type:"));
+ for i in px_type'range loop
+ write(l, std_logic'image(px_type(i)) );
+ end loop;
+
+ write(l, String'(" buy_sell:"));
+ for i in buy_sell'range loop
+ write(l, std_logic'image(buy_sell(i)) );
+ end loop;
+
+ write(l, String'(" px:"));
+ for i in px'range loop
+ write(l, std_logic'image(px(i)) );
+ end loop;
+
+ write(l, String'(" qty:"));
+ for i in qty'range loop
+ write(l, std_logic'image(qty(i)) );
+ end loop;
+
+ write(l, String'(" sec:"));
+ for i in sec'range loop
+ write(l, std_logic'image(sec(i)) );
+ end loop;
+
+ write(l, String'(" id:"));
+ for i in id'range loop
+ write(l, std_logic'image(id(i)) );
+ end loop;
+
+ writeline(output, l);
+
+ byte_ready <= '0';
+ wait for 1 ns;
+ end loop;
+
+
+ write (l, String'("Done parse_price"));
+ writeline (output, l);
+
+ if (px_type = B"01000") and (buy_sell = B"000") and (px = B"00000000_00001000")
+ and (qty = B"00110100_00110100")
+ and (sec = B"01001000_01000001_01000001_01010100_01010100_01010011_01010011")
+ and (id = B"01000011_01000011")
+ then
+ write (l, String'("... and Price is OK."));
+ writeline (output, l);
+ end if;
+
+ wait;
+ end process;
+ end behaviour;