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URL https://opencores.org/ocsvn/openarty/openarty/trunk

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  • This comparison shows the changes necessary to convert path 
    /openarty/trunk/bench/cpp
    from Rev 9 to Rev 10
    ↔ Reverse comparison
  •

Rev 9 → Rev 10

/eqspiflash_tb.cpp
1,3 → 1,43
////////////////////////////////////////////////////////////////////////////////
//
// Filename: eqspiflash_tb.cpp
//
// Project: OpenArty, an entirely open SoC based upon the Arty platform
//
// Purpose: To determine whether or not the eqspiflash module works. Run
// this with no arguments, and check whether or not the last line
// contains "SUCCESS" or not. If it does contain "SUCCESS", then the
// module passes all tests found within here.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#include "verilated.h"
#include "Veqspiflash.h"
#include "eqspiflashsim.h"
89,7 → 129,7
 
printf(" LL:[%s%s%d(%08x)->%08x]",
(m_core->v__DOT__spi_busy)?"BSY":" ",
(m_core->v__DOT__lowlvl__DOT__rd_valid)?"VAL":" ",
(m_core->v__DOT__lowlvl__DOT__rd_valid_2)?"VAL":" ",
(m_core->v__DOT__lowlvl__DOT__state),
(m_core->v__DOT__lowlvl__DOT__r_input),
(m_core->v__DOT__spi_out));
155,7 → 195,14
(m_core->v__DOT__id_bus_ack)?" BUSAK":"",
(m_core->v__DOT__idotp__DOT__id_read_request)?" IDRD":"");
 
if (m_core->v__DOT__rdproc__DOT__r_requested)
fputs(" RD:R_REQUESTED", stdout);
if (m_core->v__DOT__rdproc__DOT__r_leave_xip)
fputs(" RD:R_LVXIP", stdout);
if (m_core->v__DOT__rdproc__DOT__ack_valid)
fputs(" RD:R_ACKV", stdout);
 
 
printf("\n");
 
m_core->eval();
/eqspiflashsim.cpp
280,19 → 280,21
 
m_oreg = 0x0fe;
m_count= 0;
int out = m_nxtout;
m_nxtout = dat;
int out = m_nxtout[1];
m_nxtout[1] = m_nxtout[0];
m_nxtout[0] = dat;
return out;
} else if ((!m_last_sck)||(sck == m_last_sck)) {
// Only change on the falling clock edge
// printf("SFLASH-SKIP, CLK=%d -> %d\n", m_last_sck, sck);
m_last_sck = sck;
int out = m_nxtout;
int out = m_nxtout[1];
m_nxtout[1] = m_nxtout[0];
if (m_quad_mode)
m_nxtout = (m_oreg>>8)&0x0f;
m_nxtout[0] = (m_oreg>>8)&0x0f;
else
// return ((m_oreg & 0x0100)?2:0) | (dat & 0x0d);
m_nxtout = (m_oreg & 0x0100)?2:0;
m_nxtout[0] = (m_oreg & 0x0100)?2:0;
return out;
}
 
310,6 → 312,8
}
 
 
printf("QSPI: STATE = %d, COUNT = %d\n", m_state, m_count);
 
// printf("PROCESS, COUNT = %d, IREG = %02x\n", m_count, m_ireg);
if (m_state == EQSPIF_XIP) {
assert(m_quad_mode);
544,7 → 548,11
assert(m_addr < 65);
m_otp[64] = (m_otp_wp)?0:1;
if (m_debug) printf("READOTP, SETTING ADDR = %08x\n", m_addr);
if (m_debug) printf("READOTP, SETTING ADDR = %08x (%02x:%02x:%02x:%02x)\n", m_addr,
(m_addr<65)?m_otp[m_addr]:0,
(m_addr<64)?m_otp[m_addr+1]:0,
(m_addr<63)?m_otp[m_addr+2]:0,
(m_addr<62)?m_otp[m_addr+3]:0);
if (m_debug) printf("READOTP, Array is %s, m_otp[64] = %d\n",
(m_otp_wp)?"Locked":"Unlocked",
m_otp[64]);
611,28 → 619,38
if (m_count == 32) {
m_addr = m_ireg & 0x0ffffff;
// printf("FAST READ, ADDR = %08x\n", m_addr);
printf("EQSPI: QUAD READ, ADDR = %06x\n", m_addr);
assert((m_addr & 0xfc00000)==0);
printf("EQSPI: QUAD READ, ADDR = %06x (%02x:%02x:%02x:%02x)\n", m_addr,
(m_addr<0x1000000)?(m_mem[m_addr]&0x0ff):0,
(m_addr<0x0ffffff)?(m_mem[m_addr+1]&0x0ff):0,
(m_addr<0x0fffffe)?(m_mem[m_addr+2]&0x0ff):0,
(m_addr<0x0fffffd)?(m_mem[m_addr+3]&0x0ff):0);
assert((m_addr & (~(MEMBYTES-1)))==0);
} else if (m_count == 32+8) {
QOREG(m_mem[m_addr++]);
m_quad_mode = true;
m_mode_byte = (m_ireg & 0x080);
// printf("EQSPI: MODE BYTE = %02x\n", m_mode_byte);
printf("EQSPI: (QUAD) MODE BYTE = %02x\n", m_mode_byte);
} else if ((m_count > 32+8)&&(0 == (m_sreg&0x01))) {
QOREG(m_mem[m_addr++]);
// printf("EQSPIF[%08x]/QR = %02x\n",
// m_addr-1, m_oreg);
} else m_oreg = 0;
} else {
printf("ERR: EQSPIF--TRYING TO READ WHILE BUSY!\n");
m_oreg = 0;
}
break;
case EQSPIF_QUAD_READ:
if (m_count == 24+8*4) {// Requires 8 QUAD clocks
m_mode_byte = (m_ireg>>24) & 0x10;
// printf("EQSPI/QR: MODE BYTE = %02x\n", m_mode_byte);
printf("EQSPI/QR: MODE BYTE = %02x\n", m_mode_byte);
QOREG(m_mem[m_addr++]);
} else if ((m_count >= 64)&&(0 == (m_sreg&0x01))) {
QOREG(m_mem[m_addr++]);
// printf("EQSPIF[%08x]/QR = %02x\n", m_addr-1, m_oreg & 0x0ff);
} else m_oreg = 0;
printf("EQSPIF[%08x]/QR = %02x\n", m_addr-1, m_oreg & 0x0ff);
} else {
m_oreg = 0;
printf("EQSPI/QR ... m_count = %d\n", m_count);
}
break;
case EQSPIF_PP:
if (m_count == 32) {
688,6 → 706,7
} break;
*/
default:
printf("EQSPI ... DEFAULT OP???\n");
QOREG(0xff);
break;
}
694,11 → 713,12
} // else printf("SFLASH->count = %d\n", m_count);
 
m_last_sck = sck;
int out = m_nxtout;
int out = m_nxtout[1];
m_nxtout[1] = m_nxtout[0];
if (m_quad_mode)
m_nxtout = (m_oreg>>8)&0x0f;
m_nxtout[0] = (m_oreg>>8)&0x0f;
else
m_nxtout = (m_oreg & 0x0100)?2:0;
m_nxtout[0] = (m_oreg & 0x0100)?2:0;
return out;
}
 
/eqspiflashsim.h
83,7 → 83,7
int m_last_sck;
unsigned m_write_count, m_ireg, m_oreg, m_sreg, m_addr,
m_count, m_config, m_mode_byte, m_creg,
m_nvconfig, m_evconfig, m_flagreg, m_nxtout;
m_nvconfig, m_evconfig, m_flagreg, m_nxtout[2];
bool m_quad_mode, m_debug, m_otp_wp;
 
public:

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