URL
https://opencores.org/ocsvn/openarty/openarty/trunk
Subversion Repositories openarty
Compare Revisions
- This comparison shows the changes necessary to convert path
/openarty/trunk/bench
- from Rev 30 to Rev 32
- ↔ Reverse comparison
Rev 30 → Rev 32
/cpp/fastmaster_tb.cpp
155,7 → 155,7
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PIPECMDR::tick(); |
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#define DEBUGGING_OUTPUT |
// #define DEBUGGING_OUTPUT |
#ifdef DEBUGGING_OUTPUT |
bool writeout = false; |
|
215,8 → 215,6
(m_core->v__DOT__wb_err)?'E':'.'); |
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/* |
*/ |
|
// CPU Pipeline debugging |
printf("%s%s%s%s%s%s%s%s%s%s%s", |
// (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-", |
338,7 → 336,9
m_core->v__DOT__zip_dbg_data); |
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printf(" %s,0x%08x", (m_core->i_ram_ack)?"RCK":" ", m_core->i_ram_rdata); |
*/ |
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|
/* |
printf(" SDSPI[%d,%d(%d),(%d)]", |
m_core->v__DOT__sdcard_controller__DOT__r_cmd_busy, |
/cpp/memsim.cpp
113,16 → 113,22
m_mem[wb_addr & m_mask] = wb_data; |
m_fifo_ack[m_head] = 1; |
m_fifo_data[m_head] = m_mem[wb_addr & m_mask]; |
#ifdef DEBUG |
printf("MEMBUS %s[%08x] = %08x\n", |
(wb_we)?"W":"R", |
wb_addr&m_mask, |
m_mem[wb_addr&m_mask]); |
#endif |
// o_ack = 1; |
} if (o_ack) { |
} |
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#ifdef DEBUG |
if (o_ack) { |
printf("MEMBUS -- ACK %s 0x%08x - 0x%08x\n", |
(wb_we)?"WRITE":"READ ", |
wb_addr, o_data); |
} |
#endif |
} |
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cpp
Property changes :
Added: svn:ignore
## -0,0 +1,8 ##
+busmaster_tb
+enetctrl_tb
+enetctrlsim.o
+eqspiflash_tb
+obj-pc
+.gitignore
+.*.swp
+debug.txt