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    /openarty/trunk/rtl/cpu
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Rev 3 → Rev 25

/div.v
34,8 → 34,8
//
module div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator,
o_busy, o_valid, o_err, o_quotient, o_flags);
parameter BW=32, LGBW = 5;
input i_clk, i_rst;
parameter BW=32, LGBW = 5;
input i_clk, i_rst;
// Input parameters
input i_wr, i_signed;
input [(BW-1):0] i_numerator, i_denominator;
/zipbones.v
186,7 → 186,7
`endif
);
end else begin
zipcpuhs #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE)
thecpu(i_clk, cpu_reset, i_ext_int,
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
i_dbg_data, cpu_dbg_stall, cpu_dbg_data,
/zipcpuhs.v
1,6 → 1,6
///////////////////////////////////////////////////////////////////////////////
//
// Filename: zipcpu.v
// Filename: zipcpuhs.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
7,63 → 7,85
// Purpose: This is the top level module holding the core of the Zip CPU
// together. The Zip CPU is designed to be as simple as possible.
// (actual implementation aside ...) The instruction set is about as
// RISC as you can get, there are only 16 instruction types supported.
// Please see the accompanying spec.pdf file for a description of these
// instructions.
// RISC as you can get, there are only 26 instruction types supported, not
// including the floating point instruction set. Please see the
// accompanying spec.pdf file for a description of these instructions.
//
// All instructions are 32-bits wide. All bus accesses, both address and
// data, are 32-bits over a wishbone bus.
//
// The Zip CPU is fully pipelined with the following pipeline stages:
//
// This version of the ZipCPU has been modified for "high speed" operation.
// By that I mean, it has been modified so that it can handle a high speed
// system clock. The nominal five stage pipeline has therefore been
// broken into nine pieces, as outlined below:
//
// 1. Prefetch, returns the instruction from memory.
//
// 2. Instruction Decode
// 2. Instruction Decode: triplet instructions, VLIW upper half,
// VLIW lower half, and normal instructions
//
// 3. Read Operands
// 3. Instruction Decode: Select among the four types of
// instructions
//
// 4. Apply Instruction
// 4. Read Operand B
//
// 4. Write-back Results
// 5. Read Operand A, add the immediate offset to Operand B
//
// Further information about the inner workings of this CPU may be
// found in the spec.pdf file. (The documentation within this file
// had become out of date and out of sync with the spec.pdf, so look
// to the spec.pdf for accurate and up to date information.)
// 6. 16 ALU operations
//
// 7. Select among ALU results
//
// In general, the pipelining is controlled by three pieces of logic
// per stage: _ce, _stall, and _valid. _valid means that the stage
// holds a valid instruction. _ce means that the instruction from the
// previous stage is to move into this one, and _stall means that the
// instruction from the previous stage may not move into this one.
// The difference between these control signals allows individual stages
// to propagate instructions independently. In general, the logic works
// as:
// 8. Select from ALU, Memory, Divide, FPU results
//
// 9. Write-back Results
//
// assign (n)_ce = (n-1)_valid && (~(n)_stall)
// Further information about the ZipCPU may be found in the spec.pdf file.
// (The documentation within this file is likely to become out of date
// and out of sync with the spec.pdf, so look to the spec.pdf for
// accurate and up to date information.)
//
//
// always @(posedge i_clk)
// if ((i_rst)||(clear_pipeline))
// (n)_valid = 0
// else if (n)_ce
// (n)_valid = 1
// else if (n+1)_ce
// (n)_valid = 0
// A note about pipelining. The approach used to accommodate pipelining
// in this implementation assumes that if will be impossible to tell if
// a particular stage will stall until the logic for that stage completes.
// There is no time, therefore, for the stall logic to ripple from the
// end of the pipeline to the beginning. At best, it can ripple from
// one stage to the next. Stall logic, therefore, is latched in a
// FLIP-FLOP, rather than done in a combinatorial fashion. Hopefully,
// you'll have a copy of the stall logic slides. If not, here's the
// outline of how stalls will be done:
//
// assign (n)_stall = ( (n-1)_valid && ( pipeline hazard detection ) )
// || ( (n)_valid && (n+1)_stall );
// assign (n)_slp = // stall logic for location n, based upon the prior
// // stages info
// assign (n)_slc = // stall logic for location n, based upon a copy of
// // what was in the prior stage
//
// and ...
//
// // We'll shorten _valid to _v, _stall to _s, _copy to _c
// always @(posedge i_clk)
// if (n)_ce
// (n)_variable = ... whatever logic for this stage
// if ((i_rst)||(clear_pipeline)
// (n)_v = 0;
// else if (!(n)_stall)
// (n)_v = ( (n-1)_v && (!(n)_slp) );
// else
// (n)_v = ( !(n)_slc );
//
// Note that a stage can stall even if no instruction is loaded into
// it.
// always @(posedge i_clk)
// if ((i_rst)||(clear_pipeline)
// (n)_s = 1'b0;
// else if (!(n)_s)
// (n)_s = ((n-1)_v) && ( (n)_slp || (n+1)_s );
// else
// (n)_s = ( (n)_slc || (n+1)_s );
//
// always @(posedge i_clk)
// if ((n)_s)
// (n)_data = PROCESS[(n)_c];
// // Can't chnge copy if not stalled
// else
// (n)_data = PROCESS[(n-1)_data];
// (n)_c <= (n-1)_data;
//
//
// Creator: Dan Gisselquist, Ph.D.
239,7 → 261,7
wire [31:0] pf_data;
wire [31:0] instruction;
wire [(AW-1):0] instruction_pc;
wire pf_valid, instruction_gie, pf_illegal;
wire pf_v, instruction_gie, pf_illegal;
 
//
//
257,7 → 279,7
dcdF_wr, dcd_gie, dcd_break, dcd_lock,
dcd_pipe, dcd_ljmp;
reg [1:0] r_dcdvalid;
wire dcd_valid;
wire dcd_v;
wire [(AW-1):0] dcd_pc;
wire [31:0] dcd_I;
wire dcd_zI; // true if dcdI == 0
276,7 → 298,7
//
//
// Now, let's read our operands
reg opa_valid, opa_DV, opa_FP, opa_ALU, opa_M,
reg opa_v, opa_DV, opa_FP, opa_ALU, opa_M,
opa_rA, opa_rB;
reg [4:0] alu_reg;
reg [3:0] opa_opn;
292,12 → 314,7
// Some pipeline control wires
reg opa_A_alu, opa_A_mem;
reg opa_B_alu, opa_B_mem;
`ifdef OPT_ILLEGAL_INSTRUCTION
reg opa_illegal;
`else
wire opa_illegal;
assign opa_illegal = 1'b0;
`endif
reg opa_break;
reg opa_lock;
 
310,8 → 327,8
//
// Now, let's read our operands
reg [3:0] opb_opn;
reg opb_valid, opb_valid_mem, opb_valid_alu;
reg opb_valid_div, opb_valid_fpu;
reg opb_v, opb_v_mem, opb_v_alu;
reg opb_v_div, opb_v_fpu;
reg [4:0] opb_R;
reg [31:0] r_opb_A, r_opb_B;
reg [(AW-1):0] opb_pc;
324,12 → 341,7
// Some pipeline control wires
reg opb_A_alu, opb_A_mem;
reg opb_B_alu, opb_B_mem;
`ifdef OPT_ILLEGAL_INSTRUCTION
reg opb_illegal;
`else
wire opb_illegal;
assign opb_illegal = 1'b0;
`endif
reg opb_break;
reg opb_lock;
 
340,14 → 352,15
// Variable declarations
//
//
reg stage_busy;
reg [(AW-1):0] alu_pc;
reg r_alu_pc_valid, mem_pc_valid;
wire alu_pc_valid;
reg r_alu_pc_v, mem_pc_v;
wire alu_pc_v;
wire alu_phase;
wire alu_ce, alu_stall;
wire [31:0] alu_result;
wire [3:0] alu_flags;
wire alu_valid, alu_busy;
wire alu_v, alu_busy;
wire set_cond;
reg alu_wr, alF_wr, alu_gie;
wire alu_illegal_op;
357,7 → 370,7
 
wire mem_ce, mem_stalled;
wire mem_pipe_stalled;
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err,
wire mem_v, mem_ack, mem_stall, mem_err, bus_err,
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
wire [4:0] mem_wreg;
 
365,18 → 378,18
wire [(AW-1):0] mem_addr;
wire [31:0] mem_data, mem_result;
 
wire div_ce, div_error, div_busy, div_valid;
wire div_ce, div_error, div_busy, div_v;
wire [31:0] div_result;
wire [3:0] div_flags;
 
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opb_valid_div)
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opb_v_div)
&&(~stage_busy)&&(set_cond);
 
wire fpu_ce, fpu_error, fpu_busy, fpu_valid;
wire fpu_ce, fpu_error, fpu_busy, fpu_v;
wire [31:0] fpu_result;
wire [3:0] fpu_flags;
 
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opb_valid_fpu)
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opb_v_fpu)
&&(~stage_busy)&&(set_cond);
 
//
408,46 → 421,42
//
// PIPELINE STAGE #2 :: Instruction Decode
// Calculate stall conditions
assign dcd_ce = ((~dcd_valid)||(~dcd_stalled))&&(~clear_pipeline);
assign dcd_ce = ((~dcd_v)||(~dcd_stalled))&&(~clear_pipeline);
 
assign dcd_stalled = (dcd_valid)&&(op_stall);
assign dcd_stalled = (dcd_v)&&(opa_stall);
//
// PIPELINE STAGE #3 :: Read Operands
// Calculate stall conditions
wire op_lock_stall;
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
// Stall if we're stopped, and not allowed to execute
// an instruction
// (~master_ce) // Already captured in alu_stall
//
// Stall if going into the ALU and the ALU is stalled
// i.e. if the memory is busy, or we are single
// stepping. This also includes our stalls for
// op_break and op_lock, so we don't need to
// include those as well here.
// This also includes whether or not the divide or
// floating point units are busy.
(alu_stall)
//
// Stall if we are going into memory with an operation
// that cannot be pipelined, and the memory is
// already busy
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
)
||(dcd_valid)&&(
// Stall if we need to wait for an operand A
// to be ready to read
(dcdA_stall)
assign opa_stall_slp = (
// Likewise for B, also includes logic
// regarding immediate offset (register must
// be in register file if we need to add to
// an immediate)
||(dcdB_stall)
(((dcdB_rd)&&(~dcd_zI))
&&((opa_v)&&(opb_R == dcdB)
||(mem_rdbusy)
||((div_busy)&&(div_R == dcdB))
||((fpu_busy)&&(fpu_R == dcdB))
||((alua_v)&&(alua_R==dcdB))
||((alub_v)&&(alub_R==dcdB))
||((alu_busy))
&&(
// 1.
((~dcd_zI)&&(
((opb_R == dcdB)&&(opb_wR))
||((mem_rdbusy)&&(~dcd_pipe))
))
// 2.
||((opF_wr)&&(dcdB_cc))
)))
// Or if we need to wait on flags to work on the
// CC register
||(dcdF_stall)
||(((~dcdF[3])
||((dcd_rA)&&(dcdA_cc))
||((dcd_rB)&&(dcdB_cc)))
&&(opb_v)&&(opb_ccR))
);
assign opa_ce = ((dcd_valid)||(dcd_illegal))&&(~opa_stall);
 
//
// PIPELINE STAGE #4 :: ALU / Memory
462,34 → 471,30
// 4. Last case: Stall if we would otherwise move a break instruction
// through the ALU. Break instructions are not allowed through
// the ALU.
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
// Old case #3--this isn't an ALU stall though ...
||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
&&(wr_write_cc)) // Case 3
||((opvalid)&&(op_lock)&&(op_lock_stall))
||((opvalid)&&(op_break))
||(div_busy)||(fpu_busy);
assign alu_ce = (master_ce)&&(stage_ce)&&(opvalid_alu)&&(~clear_pipeline);
assign alu_stall_clp = (~master_ce);
assign alu_stall_cls = (~master_ce);
always @(posedge i_clk)
stage_busy <= (alu_ce)||(mem_ce)||(fpu_ce)||(div_ce)
||(alu_busy)||(mem_rdbusy)||(fpu_busy)||(div_busy);
assign stage_ce = (~div_busy)&&(~alu_busy)&&(~mem_rdbusy)&&(~fpu_busy);
//
 
//
// Note: if you change the conditions for mem_ce, you must also change
// alu_pc_valid.
// alu_pc_v.
//
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
assign mem_ce = (master_ce)&&(opb_v_mem)&&(~mem_stalled)
&&(~clear_pipeline);
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
(mem_pipe_stalled)
||((~op_pipe)&&(mem_busy))
||(div_busy)
||(fpu_busy)
// Stall waiting for flags to be valid
// Or waiting for a write to the PC register
// Or CC register, since that can change the
// PC as well
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
&&((wr_write_pc)||(wr_write_cc)))));
assign mem_stall_clp = (~master_ce)||(alu_busy)||(div_busy)||(fpu_busy)
||(wr_write_pc)||(wr_write_cc)
||((opb_v_mem)&&(
(mem_pipe_stalled)
||((~opb_pipe)&&(mem_busy))));
assign mem_stall_cls = (~master_ce)||(alu_busy)||(div_busy)||(fpu_busy)
||(wr_write_pc)||(wr_write_cc)
||((cp_opb_v_mem)&&(
(mem_pipe_stalled)
||((~cp_opb_pipe)&&(mem_busy))));
 
 
//
504,7 → 509,7
~dcd_stalled,
((dcd_early_branch)&&(~clear_pipeline))
? dcd_branch_pc:pf_pc,
instruction, instruction_pc, pf_valid,
instruction, instruction_pc, pf_v,
pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
pf_ack, pf_stall, pf_err, i_wb_data,
pf_illegal);
513,7 → 518,7
//
// The ifastdec decoder takes two clocks to decode an instruction.
// Therefore, to determine if a decoded instruction is valid, we
// need to wait two clocks from pf_valid. Hence, we dump this into
// need to wait two clocks from pf_v. Hence, we dump this into
// a pipeline below.
//
initial r_dcdvalid = 2'b00;
521,21 → 526,21
if ((i_rst)||(clear_pipeline)||(w_clear_icache))
r_dcdvalid <= 2'b00;
else if (dcd_ce)
r_dcdvalid <= { r_dcdvalid[0], pf_valid };
r_dcdvalid <= { r_dcdvalid[0], pf_v };
else if (opa_ce)
r_dcdvalid <= 1'b0;
assign dcd_valid = r_dcdvalid[1];
assign dcd_v = r_dcdvalid[1];
 
ifastdec #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
IMPLEMENT_FPU)
instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
dcd_ce, dcd_stalled, instruction, instruction_gie,
instruction_pc, pf_valid, pf_illegal, dcd_phase,
instruction_pc, pf_v, pf_illegal, dcd_phase,
dcd_illegal, dcd_pc, dcd_gie,
{ dcdR_cc, dcdR_pc, dcd_iR },
{ dcdA_cc, dcdA_pc, dcd_iA },
{ dcdB_cc, dcdB_pc, dcd_iB },
dcd_I, dcd_zI, dcdF, dcdF_wr, dcdOp,
{ dcd_Rcc, dcd_Rpc, dcd_iR },
{ dcd_Acc, dcd_Apc, dcd_iA },
{ dcd_Bcc, dcd_Bpc, dcd_iB },
dcd_I, dcd_zI, dcd_F, dcd_wF, dcdOp,
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
dcd_wR,dcd_rA, dcd_rB,
dcd_early_branch,
542,9 → 547,14
dcd_branch_pc, dcd_ljmp,
dcd_pipe);
 
reg r_op_pipe;
//
//
// PIPELINE STAGE #3 :: Read Operands (Registers)
//
//
 
initial r_op_pipe = 1'b0;
reg opa_pipe;
initial opa_pipe = 1'b0;
// To be a pipeable operation, there must be
// two valid adjacent instructions
// Both must be memory instructions
555,20 → 565,78
// However ... we need to know this before this clock, hence this is
// calculated in the instruction decoder.
always @(posedge i_clk)
if (op_ce)
r_op_pipe <= dcd_pipe;
else if (mem_ce) // Clear us any time an op_ is clocked in
r_op_pipe <= 1'b0;
assign op_pipe = r_op_pipe;
if (!opa_stall)
begin
opa_v <= dcdvalid&&(~opa_stall_slp);
opa_stall <= (dcdvalid)&&(opa_stall_slp);
opa_pipe <= dcd_pipe;
 
//
//
// PIPELINE STAGE #3 :: Read Operands (Registers)
//
//
assign w_opA = regset[dcd_iA];
assign w_opB = regset[dcd_iB];
opa_wR <= dcd_wR;
{ opa_Acc, opa_Apc, opa_iA, opa_rA }
<= { dcd_Acc, dcd_Apc, dcd_iA, dcd_rA };
{ opa_Bcc, opa_Bpc, opa_iB, opa_rB }
<= { dcd_Bcc, dcd_Bpc, dcd_iB, dcd_rB };
 
// Register A
if (dcd_Apc)
opa_vA <= (dcd_iA[4]==dcd_gie) ? dcd_pc
: (dcd_iA)?upc : ipc;
else if (dcd_Acc)
opa_vA <= (dcd_iA[4])?user_flags_reg
: supervisor_flags_reg;
else
opa_vA <= regset[dcd_iA];
 
// Register B
if (!dcd_rB)
opa_vB <= 32'h00;
else if (dcd_Bpc)
opa_vB <= (dcd_iB[4]==dcd_gie) ? dcd_pc
: (dcd_iB)?upc : ipc;
else if (dcd_Bcc)
opa_vB <= (dcd_iB[4])?user_flags_reg
: supervisor_flags_reg;
else
opa_vB <= regset[dcd_iB];
 
// Copy
cp_opa_pc <= dcd_pc;
cp_opa_gie <= dcd_gie;
cp_opa_pipe <= dcd_pipe;
{ cp_opa_Rcc, cp_opa_Rpc, cp_opa_iR }
<= { dcd_Rcc, dcd_Rpc, dcd_iR };
{ cp_opa_Acc, cp_opa_Apc, cp_opa_iA }
<= { dcd_Acc, dcd_Apc, dcd_iA };
{ cp_opa_Bcc, cp_opa_Bpc, cp_opa_iB }
<= { dcd_Bcc, dcd_Bpc, dcd_iB };
end else begin
opa_v <= (~opa_stall_slc);
opa_stall <= (opa_stall_slc);
opa_pipe <= cp_opa_pipe;
 
// Register A
if (cp_opa_Apc)
opa_vA <= (cp_opa_iA[4]==cp_opa_gie) ? cp_opa_pc
: (cp_opa_iA)?upc : ipc;
else if (dcd_Acc)
opa_vA <= (cp_opa_iA[4])?user_flags_reg
: supervisor_flags_reg;
else
opa_vA <= regset[cp_opa_iA];
 
// Register B
if (!cp_opa_rB)
opa_vB <= 32'h00;
else if (cp_opa_Bpc)
opa_vB <= (cp_opa_iB[4]==cp_opa_gie) ? cp_opa_pc
: (cp_opa_iB)?upc : ipc;
else if (cp_opa_Bcc)
opa_vB <= (cp_opa_iB[4])?user_flags_reg
: supervisor_flags_reg;
else
opa_vB <= regset[cp_opa_iB];
end
 
wire [8:0] w_cpu_info;
assign w_cpu_info = {
`ifdef OPT_ILLEGAL_INSTRUCTION
601,28 → 669,9
`endif
};
 
wire [31:0] w_pcA_v;
generate
if (AW < 32)
assign w_pcA_v = {{(32-AW){1'b0}}, (dcd_iA[4] == dcd_gie)?dcd_pc:upc };
else
assign w_pcA_v = (dcd_iA[4] == dcd_gie)?dcd_pc:upc;
endgenerate
 
reg [4:0] opa_Aid, opa_Bid;
reg opa_Ard, opa_Brd;
always @(posedge i_clk)
if (opa_ce)
begin
opa_iA <= dcd_iA;
opa_iB <= dcd_iB;
opa_rA <= dcd_rA;
opa_rB <= dcd_rB;
end
 
always @(posedge i_clk)
if (opa_ce)
begin
if ((wr_reg_ce)&&(wr_reg_id == dcd_iA))
r_opA <= wr_gpreg_vl;
else if (dcdA_pc)
707,39 → 756,39
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
assign opb_F = { r_opb_F[3], r_opb_F[5], r_opb_F[1], r_opb_F[4:0] };
 
wire w_opa_valid;
wire w_opa_v;
always @(posedge i_clk)
if (i_rst)
opa_valid <= 1'b0;
opa_v <= 1'b0;
else if (opa_ce)
opa_valid <= ((dcd_valid)||(dcd_illegal))&&(~clear_pipeline);
opa_v <= ((dcd_v)||(dcd_illegal))&&(~clear_pipeline);
 
always @(posedge i_clk)
if ((i_rst)||(clear_pipeline))
begin
opa_valid <= 1'b0;
opa_v <= 1'b0;
end else if (opa_ce)
begin
opa_valid <=(dcd_valid);
opa_M <= (dcd_valid)&&(opa_M )&&(~opa_illegal);
opa_DV <= (dcd_valid)&&(opa_DV )&&(~opa_illegal);
opa_FP <= (dcd_valid)&&(opa_FP )&&(~opa_illegal);
opa_v <=(dcd_v);
opa_M <= (dcd_v)&&(opa_M )&&(~opa_illegal);
opa_DV <= (dcd_v)&&(opa_DV )&&(~opa_illegal);
opa_FP <= (dcd_v)&&(opa_FP )&&(~opa_illegal);
end else if (opb_ce)
opa_valid <= 1'b0;
opa_v <= 1'b0;
 
initial opb_valid = 1'b0;
initial opb_valid_alu = 1'b0;
initial opb_valid_mem = 1'b0;
initial opb_valid_div = 1'b0;
initial opb_valid_fpu = 1'b0;
initial opb_v = 1'b0;
initial opb_v_alu = 1'b0;
initial opb_v_mem = 1'b0;
initial opb_v_div = 1'b0;
initial opb_v_fpu = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(clear_pipeline))
begin
opb_valid <= 1'b0;
opb_valid_alu <= 1'b0;
opb_valid_mem <= 1'b0;
opb_valid_div <= 1'b0;
opb_valid_fpu <= 1'b0;
opb_v <= 1'b0;
opb_v_alu <= 1'b0;
opb_v_mem <= 1'b0;
opb_v_div <= 1'b0;
opb_v_fpu <= 1'b0;
end else if (opb_ce)
begin
// Do we have a valid instruction?
750,18 → 799,18
// Hence, the test on dcd_stalled here. If we must
// wait until our operands are valid, then we aren't
// valid yet until then.
opb_valid <= (opa_valid);
opb_valid_alu <=(opa_valid)&&((opa_ALU)||(opa_illegal));
opb_valid_mem <= (opa_valid)&&(opa_M )&&(~opa_illegal);
opb_valid_div <= (opa_valid)&&(opa_DV )&&(~opa_illegal);
opb_valid_fpu <= (opa_valid)&&(opa_FP )&&(~opa_illegal);
opb_v <= (opa_v);
opb_v_alu <=(opa_v)&&((opa_ALU)||(opa_illegal));
opb_v_mem <= (opa_v)&&(opa_M )&&(~opa_illegal);
opb_v_div <= (opa_v)&&(opa_DV )&&(~opa_illegal);
opb_v_fpu <= (opa_v)&&(opa_FP )&&(~opa_illegal);
end else if ((clear_pipeline)||(stage_ce))
begin
opb_valid <= 1'b0;
opb_valid_alu <= 1'b0;
opb_valid_mem <= 1'b0;
opb_valid_div <= 1'b0;
opb_valid_fpu <= 1'b0;
opb_v <= 1'b0;
opb_v_alu <= 1'b0;
opb_v_mem <= 1'b0;
opb_v_div <= 1'b0;
opb_v_fpu <= 1'b0;
end
 
initial op_break = 1'b0;
769,7 → 818,7
if (i_rst) opb_break <= 1'b0;
else if (opb_ce)
opb_break <= (opa_break)&&((break_en)||(~opa_gie));
else if ((clear_pipeline)||(~opb_valid))
else if ((clear_pipeline)||(~opb_v))
opb_break <= 1'b0;
 
reg r_op_lock, r_op_lock_stall;
779,8 → 828,8
if (i_rst)
r_op_lock_stall <= 1'b0;
else
r_op_lock_stall <= (~opvalid)||(~op_lock)
||(~dcd_valid)||(~pf_valid);
r_op_lock_stall <= (~opb_v)||(~opb_lock)
||(~opa_v)||(~dcd_v)||(~pf_v);
 
assign op_lock_stall = r_op_lock_stall;
 
832,7 → 881,7
opa_ccR <= (dcdR_cc)&&(dcd_wR)&&(dcd_iR[4]==dcd_gie);
opa_gie <= dcd_gie;
//
opa_pc <= dcd_valid;
opa_pc <= dcd_v;
opa_rA <= dcd_;
opa_rB <= dcd_;
end
863,12 → 912,12
assign opA = r_opA;
 
assign dcdA_stall = (dcd_rA) // &&(dcdvalid) is checked for elsewhere
&&((opa_valid)||(mem_rdbusy)
&&((opa_v)||(mem_rdbusy)
||(div_busy)||(fpu_busy))
&&((opF_wr)&&(dcdA_cc));
 
assign dcdB_stall = (dcdB_rd)
&&((opa_valid)||(mem_rdbusy)
&&((opa_v)||(mem_rdbusy)
||(div_busy)||(fpu_busy)||(alu_busy))
&&(
// 1.
882,7 → 931,7
assign dcdF_stall = ((~dcdF[3])
||((dcd_rA)&&(dcdA_cc))
||((dcd_rB)&&(dcdB_cc)))
&&(opvalid)&&(opb_ccR);
&&(opb_v)&&(opb_ccR);
//
//
// PIPELINE STAGE #4 :: Apply Instruction
889,12 → 938,12
//
//
fastops fastalu(i_clk, i_rst, alu_ce,
(opb_valid_alu), opb_opn, opb_A, opb_B,
alu_result, alu_flags, alu_valid, alu_illegal_op,
(opb_v_alu), opb_opn, opb_A, opb_B,
alu_result, alu_flags, alu_v, alu_illegal_op,
alu_busy);
 
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opb_opn[0],
opb_A, opb_B, div_busy, div_valid, div_error, div_result,
opb_A, opb_B, div_busy, div_v, div_error, div_result,
div_flags);
 
generate
902,18 → 951,18
begin
//
// sfpu thefpu(i_clk, i_rst, fpu_ce,
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
// opA, opB, fpu_busy, fpu_v, fpu_err, fpu_result,
// fpu_flags);
//
assign fpu_error = 1'b0; // Must only be true if fpu_valid
assign fpu_error = 1'b0; // Must only be true if fpu_v
assign fpu_busy = 1'b0;
assign fpu_valid = 1'b0;
assign fpu_v = 1'b0;
assign fpu_result= 32'h00;
assign fpu_flags = 4'h0;
end else begin
assign fpu_error = 1'b0;
assign fpu_busy = 1'b0;
assign fpu_valid = 1'b0;
assign fpu_v = 1'b0;
assign fpu_result= 32'h00;
assign fpu_flags = 4'h0;
end endgenerate
976,21 → 1025,21
else if (stage_ce)
alu_illegal <= opb_illegal;
 
initial r_alu_pc_valid = 1'b0;
initial mem_pc_valid = 1'b0;
initial r_alu_pc_v = 1'b0;
initial mem_pc_v = 1'b0;
always @(posedge i_clk)
if (i_rst)
r_alu_pc_valid <= 1'b0;
r_alu_pc_v <= 1'b0;
else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline)
r_alu_pc_valid <= 1'b1;
r_alu_pc_v <= 1'b1;
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
r_alu_pc_valid <= 1'b0;
assign alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
r_alu_pc_v <= 1'b0;
assign alu_pc_v = (r_alu_pc_v)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
always @(posedge i_clk)
if (i_rst)
mem_pc_valid <= 1'b0;
mem_pc_v <= 1'b0;
else
mem_pc_valid <= (mem_ce);
mem_pc_v <= (mem_ce);
 
wire bus_lock;
 
1001,7 → 1050,7
r_bus_lock <= 2'b00;
else if ((opb_ce)&&(opb_lock))
r_bus_lock <= 2'b11;
else if ((|r_bus_lock)&&((~opb_valid_mem)||(~opb_ce)))
else if ((|r_bus_lock)&&((~opb_v_mem)||(~opb_ce)))
r_bus_lock <= r_bus_lock + 2'b11; // r_bus_lock -= 1
assign bus_lock = |r_bus_lock;
 
1008,7 → 1057,7
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
(opb_opn[0]), opb_B, opb_A, opb_R,
mem_busy, mem_pipe_stalled,
mem_valid, bus_err, mem_wreg, mem_result,
mem_v, bus_err, mem_wreg, mem_result,
mem_cyc_gbl, mem_cyc_lcl,
mem_stb_gbl, mem_stb_lcl,
mem_we, mem_addr, mem_data,
1053,10 → 1102,10
 
// 1. Will we need to write a register?
always @(posedge i_clk)
r_wr_ce <= (dbgv)||(mem_valid)
r_wr_ce <= (dbgv)||(mem_v)
||((~clear_pipeline)&&(~alu_illegal)
&&(((alu_wr)&&(alu_valid))
||(div_valid)||(fpu_valid)));
&&(((alu_wr)&&(alu_v))
||(div_v)||(fpu_v)));
assign wr_reg_ce = r_wr_ce;
 
// 2. Did the ALU/MEM/DIV/FPU stage produce an error of any type?
1067,19 → 1116,19
// these will be causes for an interrupt on the next clock after this
// one.
always @(posedge i_clk)
r_wr_err <= ((div_valid)&&(div_error))
||((fpu_valid)&&(fpu_error))
||((alu_pc_valid)&&(alu_illegal))
r_wr_err <= ((div_v)&&(div_error))
||((fpu_v)&&(fpu_error))
||((alu_pc_v)&&(alu_illegal))
||(bus_err);
reg r_wr_illegal;
always @(posedge i_clk)
r_wr_illegal <= (alu_pc_valid)&&(alu_illegal);
r_wr_illegal <= (alu_pc_v)&&(alu_illegal);
 
// Which register shall be written?
// Note that the alu_reg is the register to write on a divide or
// FPU operation.
always @(posedge i_clk)
r_wr_reg <= (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
r_wr_reg <= (alu_wr|div_v|fpu_v)?alu_reg:mem_wreg;
assign wr_reg_id = r_wr_reg;
 
// Are we writing to the CC register?
1091,9 → 1140,9
 
// What value to write?
always @(posedge i_clk)
r_wr_val <= ((mem_valid) ? mem_result
:((div_valid|fpu_valid))
? ((div_valid) ? div_result:fpu_result)
r_wr_val <= ((mem_v) ? mem_result
:((div_v|fpu_v))
? ((div_v) ? div_result:fpu_result)
:((dbgv) ? dbg_val : alu_result));
assign wr_gpreg_vl = r_wr_val;
assign wr_spreg_vl = r_wr_val;
1102,17 → 1151,17
reg r_wr_flags_ce;
initial r_wr_flags_ce = 1'b0;
always @(posedge i_clk)
r_wr_flags_ce <= ((alF_wr)||(div_valid)||(fpu_valid))
r_wr_flags_ce <= ((alF_wr)||(div_v)||(fpu_v))
&&(~clear_pipeline)&&(~alu_illegal);
assign wr_flags_ce = r_wr_flags_ce;
 
reg [3:0] r_wr_newflags;
always @(posedge i_clk)
if (div_valid)
if (div_v)
r_wr_newflags <= div_flags;
else if (fpu_valid)
else if (fpu_v)
r_wr_newflags <= fpu_flags;
else // if (alu_valid)
else // if (alu_v)
r_wr_newflags <= alu_flags;
 
reg r_wr_gie;
1119,14 → 1168,14
always @(posedge i_clk)
r_wr_gie <= (~dbgv)&&(alu_gie);
 
reg r_wr_pc_valid;
initial r_wr_pc_valid = 1'b0;
reg r_wr_pc_v;
initial r_wr_pc_v = 1'b0;
always @(posedge i_clk)
r_wr_pc_valid <= ((alu_pc_valid)&&(~clear_pipeline))
||(mem_pc_valid);
r_wr_pc_v <= ((alu_pc_v)&&(~clear_pipeline))
||(mem_pc_v);
reg [(AW-1):0] r_wr_pc;
always @(posedge i_clk)
r_wr_pc <= alu_pc; // (alu_pc_valid)?alu_pc : mem_pc;
r_wr_pc <= alu_pc; // (alu_pc_v)?alu_pc : mem_pc;
 
////
//
1214,7 → 1263,7
initial fast_interrupt = 1'b0;
always @(posedge i_clk) // 12 inputs
fast_interrupt <= ((gie)||(alu_gie))&&(
((r_wr_pc_valid)&&(step)&&(~alu_phase)&&(~bus_lock))
((r_wr_pc_v)&&(step)&&(~alu_phase)&&(~bus_lock))
// Or ... if we encountered some form of error in our
// instruction ...
||(r_wr_err)
1282,7 → 1331,7
step <= 1'b0;
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
step <= wr_spreg_vl[`CPU_STEP_BIT];
else if (((alu_pc_valid)||(mem_pc_valid))&&(step)&&(gie))
else if (((alu_pc_v)||(mem_pc_v))&&(step)&&(gie))
step <= 1'b0;
 
 
1348,7 → 1397,7
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
&&(~wr_spreg_vl[`CPU_DIVERR_BIT]))
r_idiv_err_flag <= 1'b0;
else if ((div_error)&&(div_valid)&&(~r_wr_gie))
else if ((div_error)&&(div_v)&&(~r_wr_gie))
r_idiv_err_flag <= 1'b1;
// User divide (by zero) error flag -- if ever set, it will
// cause a sudden switch interrupt to supervisor mode.
1362,7 → 1411,7
&&(~wr_spreg_vl[`CPU_DIVERR_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
r_udiv_err_flag <= 1'b0;
else if ((div_error)&&(r_wr_gie)&&(div_valid))
else if ((div_error)&&(r_wr_gie)&&(div_v))
r_udiv_err_flag <= 1'b1;
 
assign idiv_err_flag = r_idiv_err_flag;
1381,7 → 1430,7
else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
&&(~wr_spreg_vl[`CPU_FPUERR_BIT]))
r_ifpu_err_flag <= 1'b0;
else if ((fpu_error)&&(fpu_valid)&&(~r_wr_gie))
else if ((fpu_error)&&(fpu_v)&&(~r_wr_gie))
r_ifpu_err_flag <= 1'b1;
// User floating point error flag -- if ever set, it will cause
// a sudden switch interrupt to supervisor mode.
1395,7 → 1444,7
&&(~wr_spreg_vl[`CPU_FPUERR_BIT])
&&(wr_reg_id[4])&&(wr_write_cc))
r_ufpu_err_flag <= 1'b0;
else if ((fpu_error)&&(r_wr_gie)&&(fpu_valid))
else if ((fpu_error)&&(r_wr_gie)&&(fpu_v))
r_ufpu_err_flag <= 1'b1;
 
assign ifpu_err_flag = r_ifpu_err_flag;
1413,7 → 1462,7
always @(posedge i_clk)
if (i_rst)
r_ihalt_phase <= 1'b0;
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
else if ((~alu_gie)&&(alu_pc_v)&&(~clear_pipeline))
r_ihalt_phase <= alu_phase;
always @(posedge i_clk)
if (r_wr_gie)
1442,8 → 1491,8
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
upc <= wr_spreg_vl[(AW-1):0];
else if ((r_wr_gie)&&
(((alu_pc_valid)&&(~clear_pipeline))
||(mem_pc_valid)))
(((alu_pc_v)&&(~clear_pipeline))
||(mem_pc_v)))
upc <= alu_pc;
 
always @(posedge i_clk)
1452,8 → 1501,8
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
ipc <= wr_spreg_vl[(AW-1):0];
else if ((~r_wr_gie)&&
(((alu_pc_valid)&&(~clear_pipeline))
||(mem_pc_valid)))
(((alu_pc_v)&&(~clear_pipeline))
||(mem_pc_v)))
ipc <= alu_pc;
 
always @(posedge i_clk)
1468,12 → 1517,12
`ifdef OPT_PIPELINED
else if ((dcd_early_branch)&&(~clear_pipeline))
pf_pc <= dcd_branch_pc + 1;
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
else if ((new_pc)||((~dcd_stalled)&&(pf_v)))
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
`else
else if ((alu_gie==gie)&&(
((alu_pc_valid)&&(~clear_pipeline))
||(mem_pc_valid)))
((alu_pc_v)&&(~clear_pipeline))
||(mem_pc_v)))
pf_pc <= alu_pc;
`endif
 
1547,7 → 1596,7
(~pf_cyc)&&(~mem_busy)&&(~alu_busy)
&&(~div_busy)&&(~fpu_busy)
// Operations must either be valid, or illegal
&&((opvalid)||(i_rst)||(dcd_illegal))
&&((opb_v)||(i_rst)||(dcd_illegal))
// Decode stage must be either valid, in reset, or ill
&&((dcdvalid)||(i_rst)||(pf_illegal)));
assign o_dbg_stall = ~r_halted;
1559,8 → 1608,8
//
//
assign o_op_stall = (master_ce)&&(op_stall);
assign o_pf_stall = (master_ce)&&(~pf_valid);
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline);
assign o_pf_stall = (master_ce)&&(~pf_v);
assign o_i_count = (alu_pc_v)&&(~clear_pipeline);
 
`ifdef DEBUG_SCOPE
always @(posedge i_clk)
1568,7 → 1617,7
/*
o_break, i_wb_err, pf_pc[1:0],
flags,
pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
pf_v, dcdvalid, opvalid, alu_v, mem_v,
op_ce, alu_ce, mem_ce,
//
master_ce, opvalid_alu, opvalid_mem,
1584,7 → 1633,7
/*
i_rst, master_ce, (new_pc),
((dcd_early_branch)&&(dcdvalid)),
pf_valid, pf_illegal,
pf_v, pf_illegal,
op_ce, dcd_ce, dcdvalid, dcd_stalled,
pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
pf_pc[7:0], pf_addr[7:0]
1596,12 → 1645,12
(mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
o_wb_addr[8:0] }
: { instruction[31:21] },
pf_valid, (pf_valid) ? alu_pc[14:0]
pf_v, (pf_v) ? alu_pc[14:0]
:{ pf_cyc, pf_stb, pf_pc[12:0] }
 
/*
i_wb_err, gie, new_pc, dcd_early_branch, // 4
pf_valid, pf_cyc, pf_stb, instruction_pc[0], // 4
pf_v, pf_cyc, pf_stb, instruction_pc[0], // 4
instruction[30:27], // 4
dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb, // 4
dcdvalid,

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