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  • This comparison shows the changes necessary to convert path 
    /openarty/trunk/rtl/cpu
    from Rev 30 to Rev 32
    ↔ Reverse comparison
  •

Rev 30 → Rev 32

/cpudefs.v
69,8 → 69,8
// illegal instructions are quietly ignored and their behaviour is ...
// undefined. (Many get treated like NOOPs ...)
//
// I recommend setting this flag, although it can be taken out if area is
// critical ...
// I recommend setting this flag so highly, that I'm likely going to remove
// the option to turn this off in future versions of this CPU.
//
`define OPT_ILLEGAL_INSTRUCTION
//
/pipemem.v
52,7 → 52,7
input [4:0] i_oreg;
// CPU outputs
output wire o_busy;
output reg o_pipe_stalled;
output wire o_pipe_stalled;
output reg o_valid;
output reg o_err;
output reg [4:0] o_wreg;
164,13 → 164,8
// then either.
o_result <= i_wb_data;
 
/*
assign o_pipe_stalled = (cyc)
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
*/
always @(posedge i_clk)
o_pipe_stalled <= (i_pipe_stb)&&(cyc)&&(i_wb_stall);
 
generate
if (IMPLEMENT_LOCK != 0)
/wbdmac.v
189,7 → 189,7
// When the slave wishbone writes, and we are in this
// (ready) configuration, then allow the DMA to be controlled
// and thus to start.
if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we))
if ((i_swb_stb)&&(i_swb_we))
begin
case(i_swb_addr)
2'b00: begin
340,8 → 340,7
always @(posedge i_clk)
if (dma_state == `DMA_IDLE)
begin
if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)
&&(i_swb_addr==2'b00))
if ((i_swb_stb)&&(i_swb_we)&&(i_swb_addr==2'b00))
cfg_err <= 1'b0;
end else if (((i_mwb_err)&&(o_mwb_cyc))||(abort))
cfg_err <= 1'b1;
366,7 → 365,7
always @(posedge i_clk)
if ((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
begin
if (i_mwb_ack)
if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall)))
last_read_ack <= (nread+2 == nracks);
else
last_read_ack <= (nread+1 == nracks);
390,7 → 389,7
always @(posedge i_clk)
if((dma_state == `DMA_WRITE_REQ)||(dma_state == `DMA_WRITE_ACK))
begin
if (i_mwb_ack)
if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall)))
last_write_ack <= (nwacks+2 == nwritten);
else
last_write_ack <= (nwacks+1 == nwritten);
457,13 → 456,13
// but ack it anyway. In other words, before writing to the device,
// double check that it isn't busy, and then write.
always @(posedge i_clk)
o_swb_ack <= (i_swb_cyc)&&(i_swb_stb);
o_swb_ack <= (i_swb_stb);
 
assign o_swb_stall = 1'b0;
 
initial abort = 1'b0;
always @(posedge i_clk)
abort <= (i_rst)||((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)
abort <= (i_rst)||((i_swb_stb)&&(i_swb_we)
&&(i_swb_addr == 2'b00)
&&(i_swb_data == 32'hffed0000));
 
/zipbones.v
179,7 → 179,7
cpu_lcl_cyc, cpu_lcl_stb,
o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_data,
(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)),
(i_wb_err)||(cpu_lcl_cyc),
cpu_op_stall, cpu_pf_stall, cpu_i_count
`ifdef DEBUG_SCOPE
, o_zip_debug
208,7 → 208,7
initial o_dbg_ack = 1'b0;
always @(posedge i_clk)
o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall));
assign o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
assign o_dbg_stall= 1'b0; //(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr);
 
assign o_ext_int = (cmd_halt) && (~i_wb_stall);
 
/zipcounter.v
64,7 → 64,7
initial o_int = 0;
initial o_wb_data = 32'h00;
always @(posedge i_clk)
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
if ((i_wb_stb)&&(i_wb_we))
{ o_int, o_wb_data } <= { 1'b0, i_wb_data };
else if (i_ce)
{ o_int, o_wb_data } <= o_wb_data+{{(BW-1){1'b0}},1'b1};
73,6 → 73,6
 
initial o_wb_ack = 1'b0;
always @(posedge i_clk)
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
o_wb_ack <= (i_wb_stb);
assign o_wb_stall = 1'b0;
endmodule
/zipcpu.v
1866,10 → 1866,53
// DATWR: If write value, produce 4-bits of register ID, 27 bits of value
// STALL: If neither, produce pipeline stall information
// ADDR: If bus is valid, no ack, return the bus address
wire this_write;
assign this_write = ((mem_valid)||((~clear_pipeline)&&(~alu_illegal)
&&(((alu_wr)&&(alu_valid))
||(div_valid)||(fpu_valid))));
reg last_write;
always @(posedge i_clk)
last_write <= this_write;
 
reg [4:0] last_wreg;
always @(posedge i_clk)
last_wreg <= wr_reg_id;
 
reg halt_primed;
initial halt_primed = 0;
always @(posedge i_clk)
if (master_ce)
halt_primed <= 1'b1;
else if (debug_trigger)
halt_primed <= 1'b0;
reg [6:0] halt_count;
initial halt_count = 0;
always @(posedge i_clk)
if ((i_rst)||(!i_halt)||(r_halted)||(!halt_primed))
halt_count <= 0;
else if (!(&halt_count))
halt_count <= halt_count + 1'b1;
 
reg [9:0] mem_counter;
initial mem_counter = 0;
always @(posedge i_clk)
if ((i_rst)||(!halt_primed)||(!mem_busy))
mem_counter <= 0;
else if (!(&mem_counter))
mem_counter <= mem_counter + 1'b1;
 
reg [15:0] long_trigger;
always @(posedge i_clk)
long_trigger[15:1] <= long_trigger[14:0];
always @(posedge i_clk)
long_trigger[0] <= ((last_write)&&(last_wreg == wr_reg_id))
||(&halt_count)||(&mem_counter);
 
reg debug_trigger;
initial debug_trigger = 1'b0;
always @(posedge i_clk)
debug_trigger <= (!i_halt)&&(o_break);
debug_trigger <= (!i_halt)&&(o_break)||(long_trigger == 16'hffff);
 
wire [31:0] debug_flags;
assign debug_flags = { debug_trigger, 3'b101,
1880,7 → 1923,18
op_pipe, alu_ce, alu_busy, alu_wr,
alu_illegal, alF_wr, mem_ce, mem_we,
mem_busy, mem_pipe_stalled, (new_pc), (dcd_early_branch) };
 
wire [25:0] bus_debug;
assign bus_debug = { debug_trigger,
mem_ce, mem_we, mem_busy, mem_pipe_stalled,
o_wb_gbl_cyc, o_wb_gbl_stb, o_wb_lcl_cyc, o_wb_lcl_stb,
o_wb_we, i_wb_ack, i_wb_stall, i_wb_err,
pf_cyc, pf_stb, pf_ack, pf_stall,
pf_err,
mem_cyc_gbl, mem_stb_gbl, mem_cyc_lcl, mem_stb_lcl,
mem_we, mem_ack, mem_stall, mem_err
};
always @(posedge i_clk)
begin
if ((i_halt)||(!master_ce)||(debug_trigger)||(o_break))
1896,6 → 1950,7
(o_wb_we)?o_wb_data[26:0] : o_wb_addr[26:0] };
else
o_debug <= debug_flags;
// o_debug[25:0] <= bus_debug;
end
`endif
 
/zipsystem.v
558,7 → 558,7
wire ctri_sel, ctri_stall;
reg ctri_ack;
wire [31:0] ctri_data;
assign ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
assign ctri_sel = (sys_stb)&&(sys_addr == `CTRINT);
always @(posedge i_clk)
ctri_ack <= ctri_sel;
assign ctri_stall = 1'b0;
662,7 → 662,7
assign pic_stall = 1'b0;
reg pic_ack;
always @(posedge i_clk)
pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
pic_ack <= (sys_stb)&&(sys_addr == `INTCTRL);
 
//
// The CPU itself
812,7 → 812,7
 
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
| wdt_stall | ctri_stall | actr_stall
| pic_stall | dmac_stall);
| pic_stall | dmac_stall); // Always 1'b0!
assign cpu_stall = (sys_stall)|(cpu_ext_stall);
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
assign cpu_ack = (sys_ack)||(cpu_ext_ack);
/.
. Property changes : Added: svn:ignore ## -0,0 +1,3 ## +pipefetch.m +.gitignore +.*.swp

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