OpenCores
URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openarty/trunk/rtl
    from Rev 3 to Rev 12
    ↔ Reverse comparison
  •

Rev 3 → Rev 12

/sdspi.v
96,14 → 96,51
// Some WB simplifications:
//
reg r_cmd_busy;
 
wire wb_stb, write_stb, cmd_stb, new_data, new_cmd;
wire [1:0] wb_addr;
wire [31:0] wb_data;
`ifdef WB_CLOCK
wire wb_stb, write_stb, cmd_stb; // read_stb
assign wb_stb = ((i_wb_cyc)&&(i_wb_stb)&&(~o_wb_stall));
assign wb_stb = ((i_wb_stb)&&(~o_wb_stall));
assign write_stb = ((wb_stb)&&( i_wb_we));
// assign read_stb = ((wb_stb)&&(~i_wb_we));
assign cmd_stb = (~r_cmd_busy)&&(write_stb)
&&(i_wb_addr==`SDSPI_CMD_ADDRESS);
assign wb_addr = i_wb_addr;
assign wb_data = i_wb_data;
assign new_cmd = cmd_stb;
assign new_data = (i_wb_stb)&&(~o_wb_stall)&&(i_wb_we)
&&(i_wb_addr == `SDSPI_DAT_ADDRESS);
`else
reg r_wb_stb, r_write_stb, r_cmd_stb, r_new_data;
reg [1:0] r_wb_addr;
reg [31:0] r_wb_data;
always @(posedge i_clk)
r_wb_stb <= ((i_wb_stb)&&(~o_wb_stall));
always @(posedge i_clk)
r_write_stb <= ((i_wb_stb)&&(~o_wb_stall)&&(i_wb_we));
always @(posedge i_clk)
r_cmd_stb <= (~r_cmd_busy)&&(i_wb_stb)&&(~o_wb_stall)&&(i_wb_we)
&&(i_wb_addr == `SDSPI_CMD_ADDRESS);
always @(posedge i_clk)
r_new_data <= (i_wb_stb)&&(~o_wb_stall)&&(i_wb_we)
&&(i_wb_addr == `SDSPI_DAT_ADDRESS);
always @(posedge i_clk)
r_wb_addr <= i_wb_addr;
always @(posedge i_clk)
r_wb_data <= i_wb_data;
 
assign wb_stb = r_wb_stb;
assign write_stb= r_write_stb;
assign cmd_stb = r_cmd_stb;
assign new_cmd = r_cmd_stb;
assign new_data = r_new_data;
assign wb_addr = r_wb_addr;
assign wb_data = r_wb_data;
`endif
 
 
//
// Access to our lower-level SDSPI driver, the one that actually
// uses/sets the SPI ports
183,16 → 220,6
reg pre_cmd_state;
 
// Relieve some stress from the WB bus timing
reg new_data, new_cmd;
reg [31:0] r_wb_data;
always @(posedge i_clk)
new_data <= (write_stb)&&(i_wb_addr == `SDSPI_DAT_ADDRESS);
always @(posedge i_clk)
new_cmd <= (~r_cmd_busy)&&(write_stb)
&&(i_wb_addr==`SDSPI_CMD_ADDRESS);
always @(posedge i_clk)
r_wb_data <= i_wb_data;
 
initial r_cmd_busy = 1'b0;
initial r_data_reg = 32'h00;
359,33 → 386,33
// Clear the error on any write, whether a commanding
// one or not. -- provided the user requests clearing
// it (by setting the bit high)
r_cmd_err <= (r_cmd_err)&&(~r_wb_data[15]);
r_cmd_err <= (r_cmd_err)&&(~wb_data[15]);
// In a similar fashion, we can switch fifos even if
// not in the middle of a command
r_fifo_id <= r_wb_data[12];
r_fifo_id <= wb_data[12];
//
// Doesn't matter what this is set to as long as we
// aren't busy, so we can set it irrelevantly here.
ll_cmd_dat <= r_wb_data[7:0];
ll_cmd_dat <= wb_data[7:0];
//
// Note that we only issue a write upon receiving a
// valid command. Such a command is 8 bits, and must
// start with its high order bits set to zero and one.
// Hence ... we test for that here.
if (r_wb_data[7:6] == 2'b01)
if (wb_data[7:6] == 2'b01)
begin // Issue a command
//
r_cmd_busy <= 1'b1;
//
ll_cmd_stb <= 1'b1;
r_cmd_resp <= r_wb_data[9:8];
r_cmd_resp <= wb_data[9:8];
//
r_cmd_crc_stb <= 1'b1;
//
r_fifo_wr <= r_wb_data[10];
r_use_fifo <= r_wb_data[11];
r_fifo_wr <= wb_data[10];
r_use_fifo <= wb_data[11];
//
end else if (r_wb_data[7])
end else if (wb_data[7])
// If, on the other hand, the command was invalid,
// then it must have been an attempt to read our
// internal configuration. So we'll place that on
394,7 → 421,7
4'h0, max_lgblklen,
4'h0, r_lgblklen, 1'b0, r_sdspi_clk };
end else if (new_data) // Data write
r_data_reg <= r_wb_data;
r_data_reg <= wb_data;
end
 
 
479,7 → 506,7
// with the card. These include the speed of the interface,
// and the size of the block length to expect as part of a FIFO
// command.
if ((new_cmd)&&(r_wb_data[7:6]==2'b11)&&(~r_data_reg[7])
if ((new_cmd)&&(wb_data[7:6]==2'b11)&&(~r_data_reg[7])
&&(r_data_reg[15:12]==4'h00))
begin
if (|r_data_reg[6:0])
492,7 → 519,7
 
assign need_reset = 1'b0;
always @(posedge i_clk)
case(i_wb_addr)
case(wb_addr)
`SDSPI_CMD_ADDRESS:
o_wb_data <= { need_reset, 11'h00,
3'h0, fifo_crc_err,
524,11 → 551,11
//
always @(posedge i_clk)
begin
if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS))
if ((write_stb)&&(wb_addr == `SDSPI_CMD_ADDRESS))
begin // Command write
// Clear the read/write address
fifo_wb_addr <= {(LGFIFOLN){1'b0}};
end else if ((wb_stb)&&(i_wb_addr[1]))
end else if ((wb_stb)&&(wb_addr[1]))
begin // On read or write, of either FIFO,
// we increase our pointer
fifo_wb_addr <= fifo_wb_addr + 1;
564,8 → 591,6
pre_fifo_addr_inc_rd <= ((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle));//&&(ll_fifo_pkt_state[2:0]!=3'b000));
always @(posedge i_clk)
begin
// if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS)&&(i_wb_data[11]))
// ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
if (~r_cmd_busy)
ll_fifo_addr <= {(LGFIFOLN+2){1'b0}};
else if ((pre_fifo_addr_inc_wr)||(pre_fifo_addr_inc_rd))
604,7 → 629,7
fifo_wr_crc_stb <= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b00)&&(r_have_start_token);
pre_fifo_crc_a<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b01);
pre_fifo_crc_b<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b10);
clear_fifo_crc <= (new_cmd)&&(r_wb_data[15]);
clear_fifo_crc <= (new_cmd)&&(wb_data[15]);
end
 
reg fifo_a_wr, fifo_b_wr;
617,12 → 642,12
begin // One and only memory write allowed
fifo_a_wr <= 1'b0;
fifo_a_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
if ((write_stb)&&(i_wb_addr[1:0]==2'b10))
if ((write_stb)&&(wb_addr[1:0]==2'b10))
begin
fifo_a_wr <= 1'b1;
fifo_a_wr_mask <= 4'b1111;
fifo_a_wr_addr <= fifo_wb_addr;
fifo_a_wr_data <= i_wb_data;
fifo_a_wr_data <= wb_data;
end else if (pre_fifo_a_wr)
begin
fifo_a_wr <= 1'b1;
646,12 → 671,12
 
fifo_b_wr <= 1'b0;
fifo_b_wr_data <= { ll_out_dat, ll_out_dat, ll_out_dat, ll_out_dat };
if ((write_stb)&&(i_wb_addr[1:0]==2'b11))
if ((write_stb)&&(wb_addr[1:0]==2'b11))
begin
fifo_b_wr <= 1'b1;
fifo_b_wr_mask <= 4'b1111;
fifo_b_wr_addr <= fifo_wb_addr;
fifo_b_wr_data <= i_wb_data;
fifo_b_wr_data <= wb_data;
end else if (pre_fifo_b_wr)
begin
fifo_b_wr <= 1'b1;
773,11 → 798,11
ll_fifo_rd_complete <= 1'b1;
fifo_byte <= 8'hff;
end
end else if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS))
end else if ((write_stb)&&(wb_addr == `SDSPI_CMD_ADDRESS))
begin
ll_fifo_pkt_state <= 3'h0;
ll_fifo_rd_complete <= 1'b0;
fifo_byte <= (i_wb_data[12]) ? fifo_b_byte : fifo_a_byte;
fifo_byte <= (wb_data[12]) ? fifo_b_byte : fifo_a_byte;
fifo_rd_crc_stb <= 1'b1;
end else begin // Packet state is IDLE (clear the CRC registers)
ll_fifo_pkt_state <= 3'b111;
/eqspiflash.v
724,7 → 724,7
accepted <= (~i_spi_busy)&&(i_grant)&&(o_spi_wr)&&(~accepted);
 
reg [3:0] rd_state;
reg r_leave_xip, r_xip, r_quad, r_requested;
reg r_leave_xip, r_xip, r_quad, r_requested, ack_valid;
initial rd_state = `RD_IDLE;
initial o_data_ack = 1'b0;
initial o_bus_ack = 1'b0;
738,6 → 738,7
o_data <= i_spi_data;
case(rd_state)
`RD_IDLE: begin
ack_valid <= 1'b0;
r_requested <= 1'b0;
o_qspi_req <= 1'b0;
o_spi_word <= { ((i_quad)? 8'h6B: 8'h0b), i_addr, 2'b00 };
756,6 → 757,7
`RD_IDLE_GET_PORT: begin
o_spi_wr <= 1'b1; // Write the address
o_qspi_req <= 1'b1;
ack_valid <= 1'b0;
if (accepted)
rd_state <= `RD_SLOW_DUMMY;
end
766,6 → 768,7
o_spi_spd <= 1'b0;
o_spi_word[31:24] <= (r_xip) ? 8'h00 : 8'hff;
o_spi_len <= 2'b00; // 8 clocks = 8-bits
ack_valid <= 1'b0;
if (accepted)
rd_state <= (r_quad)?`RD_QUAD_READ_DATA
: `RD_SLOW_READ_DATA;
778,9 → 781,10
o_spi_wr <= (~r_requested)||(i_piperd);
// if (accepted)
// o_spi_wr <= (i_piperd);
o_data_ack <= (r_requested)&&(i_spi_valid);
o_data_ack <= (ack_valid)&&(i_spi_valid);
o_bus_ack <= (r_requested)&&(accepted)&&(i_piperd);
r_requested <= (r_requested)||(accepted);
ack_valid <= (accepted)?(r_requested):ack_valid;
if ((i_spi_valid)&&(~o_spi_wr))
rd_state <= `RD_GO_TO_IDLE;
end
791,12 → 795,13
o_spi_len <= 2'b11;
o_spi_recycle <= (r_leave_xip)? 1'b1: 1'b0;
r_requested <= (r_requested)||(accepted);
o_data_ack <= (r_requested)&&(i_spi_valid)&&(~r_leave_xip);
ack_valid <= (r_requested);
o_data_ack <= (ack_valid)&&(i_spi_valid)&&(~r_leave_xip);
o_bus_ack <= (r_requested)&&(accepted)&&(i_piperd)&&(~r_leave_xip);
o_spi_wr <= (~r_requested)||(i_piperd);
// if (accepted)
// o_spi_wr <= (i_piperd);
if (accepted)
if (accepted) // only happens if (o_spi_wr)
o_data <= i_spi_data;
if ((i_spi_valid)&&(~o_spi_wr))
rd_state <= ((r_leave_xip)||(~r_xip))?`RD_GO_TO_IDLE:`RD_GO_TO_XIP;
839,12 → 844,16
o_bus_ack <= i_readreq;
end end
`RD_GO_TO_IDLE: begin
r_requested <= 1'b0;
ack_valid <= 1'b0;
o_spi_wr <= 1'b0;
o_qspi_req <= 1'b0;
o_spi_wr <= 1'b0;
if ((i_spi_stopped)&&(~i_grant))
rd_state <= `RD_IDLE;
end
`RD_GO_TO_XIP: begin
r_requested <= 1'b0;
ack_valid <= 1'b0;
o_qspi_req <= 1'b1;
o_spi_wr <= 1'b0;
if (i_spi_stopped)
925,7 → 934,7
accepted <= (~i_spi_busy)&&(i_qspi_grant)&&(o_spi_wr)&&(~accepted);
 
 
reg cyc, chk_wip;
reg cyc, chk_wip, valid_status;
reg [3:0] wr_state;
initial wr_state = `WR_IDLE;
initial cyc = 1'b0;
937,6 → 946,7
cyc <= (cyc)&&(~i_endpipe);
case(wr_state)
`WR_IDLE: begin
valid_status <= 1'b0;
o_qspi_req <= 1'b0;
cyc <= 1'b0;
if (i_ereq)
1061,6 → 1071,7
o_spi_word <= 32'h00;
if (accepted)
wr_state <= `WR_READ_STATUS;
valid_status <= 1'b0;
end
`WR_READ_STATUS: begin
o_wip <= 1'b1;
1072,6 → 1083,8
o_spi_dir <= 1'b1; // Read
o_spi_word <= 32'h00;
if (i_spi_valid)
valid_status <= 1'b1;
if ((i_spi_valid)&&(valid_status))
chk_wip <= 1'b1;
if ((chk_wip)&&(~i_spi_data[0]))
wr_state <= `WR_WAIT_ON_FINAL_STOP;
1153,7 → 1166,7
always @(posedge i_clk)
accepted <= (~i_spi_busy)&&(i_grant)&&(o_spi_wr)&&(~accepted);
 
reg r_ctdat_len, ctbus_ack;
reg r_ctdat_len, ctbus_ack, first_valid;
assign ctdat_len = { 1'b0, r_ctdat_len };
 
// First step, calculate the values for our state machine
1304,11 → 1317,14
ctstate <= (ctdat_wr)?`CT_WAIT_FOR_IDLE:`CT_READ_DATA;
if ((accepted)&&(ctdat_wr))
o_data_ack <= 1'b1;
first_valid <= 1'b0;
end
`CT_READ_DATA: begin
o_spi_wr <= 1'b0; // No more words to go, just to wait
o_spi_req <= 1'b1;
if (i_spi_valid) // for a value to read
if (i_spi_valid)
first_valid <= 1'b1;
if ((i_spi_valid)&&(first_valid)) // for a value to read
begin
o_data_ack <= 1'b1;
o_data <= i_spi_data;
1426,7 → 1442,7
reg nxt_data_ack, nxt_data_spi;
reg [31:0] nxt_data;
 
reg set_val, chk_wip;
reg set_val, chk_wip, first_valid, valid_status;
reg [2:0] set_addr;
 
always @(posedge i_clk)
1454,6 → 1470,7
o_spi_word[6:0] <= { req_addr[4:0], 2'b00 };
r_data <= i_data;
o_wip <= 1'b0;
first_valid <= 1'b0;
if (otp_read_request)
begin
// o_spi_word <= { 8'h48, 8'h00, 8'h00, 8'h00 };
1498,11 → 1515,12
end
`ID_READ_DATA_COMMAND: begin
o_spi_len <= 2'b11; // 32-bits
o_spi_wr <= (~last_addr); // Still transmitting
o_spi_wr <= 1'b1; // Still transmitting
o_spi_dir <= 1'b1; // Read from SPI
o_qspi_req <= 1'b1;
if (accepted)
id_state <= `ID_GET_DATA;
first_valid <= 1'b0;
end
`ID_GET_DATA: begin
o_spi_len <= 2'b11; // 32-bits
1509,7 → 1527,9
o_spi_wr <= (~last_addr); // Still transmitting
o_spi_dir <= 1'b1; // Read from SPI
o_qspi_req <= 1'b1;
if (i_spi_valid) // same as accepted
if (i_spi_valid) // two clocks after accepted
first_valid <= 1'b1;
if((i_spi_valid)&&(first_valid))
begin
set_val <= 1'b1;
set_addr <= lcl_id_addr[2:0];
1542,12 → 1562,14
`ID_OTP_CLEAR: begin
o_spi_wr <= 1'b1; // Still writing
o_spi_dir <= 1'b1; // Read from SPI
o_spi_len <= 2'b11; // Read from SPI
o_spi_len <= 2'b11; // Read 32 bits
if (accepted)
id_state <= `ID_OTP_GET_DATA;
end
`ID_OTP_GET_DATA: begin
if (i_spi_valid)
first_valid <= 1'b1;
if ((i_spi_valid)&&(first_valid))
begin
id_state <= `ID_FINAL_STOP;
nxt_data_ack <= 1'b1;
1587,6 → 1609,7
o_spi_dir <= 1'b1; // Read
o_spi_len <= 2'b00; // 8 bits
// o_spi_word <= dont care
valid_status <= 1'b0;
if (accepted)
id_state <= `ID_READ_STATUS;
end
1597,6 → 1620,8
o_spi_len <= 2'b00; // 8 bits
// o_spi_word <= dont care
if (i_spi_valid)
valid_status <= 1'b1;
if ((i_spi_valid)&&(valid_status))
chk_wip <= 1'b1;
if ((chk_wip)&&(~i_spi_data[0]))
begin
/gpsclock.v
183,16 → 183,31
pre_step <= { 16'h00,
(({ r_def_step[27:0], 20'h00 })>>r_def_step[31:28])};
 
// Delay writes by one clock
wire [1:0] wb_addr;
wire [31:0] wb_data;
reg wb_write;
reg [1:0] r_wb_addr;
reg [31:0] r_wb_data;
always @(posedge i_clk)
wb_write <= (i_wb_cyc_stb)&&(i_wb_we);
always @(posedge i_clk)
r_wb_data <= i_wb_data;
always @(posedge i_clk)
r_wb_addr <= i_wb_addr;
assign wb_data = r_wb_data;
assign wb_addr = r_wb_addr;
 
initial new_config = 1'b0;
always @(posedge i_clk)
if ((i_wb_cyc_stb)&&(i_wb_we))
if (wb_write)
begin
new_config = 1'b1;
case(i_wb_addr)
2'b00: r_alpha <= i_wb_data[5:0];
2'b01: r_beta <= i_wb_data;
2'b10: r_gamma <= i_wb_data;
2'b11: r_def_step <= i_wb_data;
case(wb_addr)
2'b00: r_alpha <= wb_data[5:0];
2'b01: r_beta <= wb_data;
2'b10: r_gamma <= wb_data;
2'b11: r_def_step <= wb_data;
default: begin end
// r_defstep <= i_wb_data;
endcase
/fastmaster.v
41,7 → 41,7
`define NO_ZIP_WBU_DELAY
// `define ZIPCPU
`ifdef ZIPCPU
//`define ZIP_SYSTEM
`define ZIP_SYSTEM
`ifndef ZIP_SYSTEM
`define ZIP_BONES
`endif // ZIP_SYSTEM
54,7 → 54,7
`define ICAPE_ACCESS
`endif
`define FLASH_ACCESS
//`define SDRAM_ACCESS
// `define SDRAM_ACCESS
`define GPS_CLOCK
// UART_ACCESS and GPS_UART have both been placed within fastio
// `define UART_ACCESS
62,10 → 62,10
`define RTC_ACCESS
`define OLEDRGB_ACCESS
//
// `define CPU_SCOPE
// `define GPS_SCOPE
`define FLASH_SCOPE
// `define SDRAM_SCOPE
`define FLASH_SCOPE // Position zero
// `define CPU_SCOPE // Position zero
// `define GPS_SCOPE // Position one
// `define SDRAM_SCOPE // Position two
// `define ENET_SCOPE
//
//
82,7 → 82,8
// The DDR3 SDRAM
o_ddr_reset_n, o_ddr_cke,
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
o_ddr_dqs, o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data,
// The SD Card
o_sd_sck, o_sd_cmd, o_sd_data, i_sd_cmd, i_sd_data, i_sd_detect,
// Ethernet control (MDIO) lines
119,7 → 120,8
// DDR3 RAM controller
output wire o_ddr_reset_n, o_ddr_cke,
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
output wire [2:0] o_ddr_dqs;
output wire o_ddr_dqs;
output wire o_ddr_dm, o_ddr_odt, o_ddr_bus_oe;
output wire [13:0] o_ddr_addr;
output wire [2:0] o_ddr_ba;
output wire [31:0] o_ddr_data;
621,9 → 623,18
(!dbg_counter_cyc[25])|w_led[1],
(!dbg_counter_err[25])|w_led[0] };
*/
assign o_led = w_led;
 
reg [25:0] dbg_counter_sdram;
always @(posedge i_clk)
if ((ram_sel)&&(wb_stb))
dbg_counter_sdram <= 0;
else if (wb_stb)
dbg_counter_sdram[25] <= 1'b1;
else if (!dbg_counter_sdram[25])
dbg_counter_sdram <= dbg_counter_sdram+26'h1;
assign o_led = { w_led[3:1], w_led[0] | (!dbg_counter_sdram[25]) };
 
 
//
//
// Real Time Clock (RTC) device level access
897,12 → 908,12
//
//
`ifdef SDRAM_ACCESS
wbddrsdram rami(i_clk,
wbddrsdram #(13,13'd1520) rami(i_clk, i_rst,
wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data,
ram_ack, ram_stall, ram_data,
o_ddr_reset_n, o_ddr_cke,
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
o_ddr_dqs,
o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_oe,
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
`else
assign ram_data = 32'h00;
916,9 → 927,9
assign o_ddr_reset_n = 1'b0; // Leave the SDRAM in reset
assign o_ddr_cke = 1'b0; // Disable the SDRAM clock
// DQS
assign o_ddr_dqs = 3'b100; // Leave DQS pins in high impedence
assign o_ddr_dqs = 1'b0; // Leave DQS pins in high impedence
// DDR3 control wires (not enabled if CKE=0)
assign o_ddr_cs_n = 1'b0; // NOOP command
assign o_ddr_cs_n = 1'b1; // Deselect command
assign o_ddr_ras_n = 1'b1;
assign o_ddr_cas_n = 1'b1;
assign o_ddr_we_n = 1'b1;
1024,7 → 1035,32
wire [31:0] scop_c_data;
wire scop_c_ack, scop_c_stall, scop_c_interrupt;
//
//`else
`ifdef SDRAM_SCOPE
wire [31:0] scop_sdram_data;
wire scop_sdram_ack, scop_sdram_stall, scop_sdram_interrupt;
wire sdram_trigger;
wire [31:0] sdram_debug;
assign sdram_trigger = (ram_sel)&&(wb_stb);
assign sdram_debug= {
o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
(wb_stb)&&(ram_sel), wb_we, ram_stall, ram_ack,
o_ddr_dqs, o_ddr_dm, o_ddr_bus_oe,
o_ddr_addr[10], o_ddr_addr[3],
o_ddr_data[5:0], i_ddr_data[5:0], 8'h00
};
 
wbscope #(5'd12,32,1) ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
wb_we, wb_addr[0], wb_data,
scop_sdram_ack, scop_sdram_stall, scop_sdram_data,
scop_sdram_interrupt);
 
assign scop_c_ack = scop_sdram_ack;
assign scop_c_stall = scop_sdram_stall;
assign scop_c_data = scop_sdram_data;
assign scop_c_interrupt = scop_sdram_interrupt;
`else
assign scop_c_data = 32'h00;
assign scop_c_stall = 1'b0;
assign scop_c_interrupt = 1'b0;
1033,7 → 1069,7
always @(posedge i_clk)
r_scop_c_ack <= (wb_stb)&&(scop_sel)&&(wb_addr[2:1] == 2'b10);
assign scop_c_ack = r_scop_c_ack;
//`endif
`endif
 
//
// SCOPE D
/Makefile
57,7 → 57,7
wbuidleint.v wbuinput.v wbuoutput.v wbureadcw.v wbusixchar.v \
wbutohex.v
PERIPHERALS:= enetctrl.v fastio.v icontrol.v rtcdate.v rtcgps.v \
rxuart.v txuart.v eqspiflash.v llqspi.v flash_config.v \
rxuart.v txuart.v eqspiflash.v lleqspi.v flash_config.v \
wbicapetwo.v sdspi.v gpsclock_tb.v gpsclock.v wboled.v lloled.v \
wbscopc.v wbscope.v memdev.v wbddrsdram.v
BIGMATH:= bigadd.v bigsmpy.v bigsub.v
75,7 → 75,7
$(VDIRFB)/Vbusmaster.h $(VDIRFB)/Vbusmaster.cpp $(VDIRFB)/Vbusmaster.mk: $(SLOWSRC)
 
$(VDIRFB)/Venetctrl.h $(VDIRFB)/Venetctrl.cpp $(VDIRFB)/Venetctrl.mk: enetctrl.v
$(VDIRFB)/Veqspiflash.h $(VDIRFB)/Veqspiflash.cpp $(VDIRFB)/Veqspiflash.mk: eqspiflash.v llqspi.v
$(VDIRFB)/Veqspiflash.h $(VDIRFB)/Veqspiflash.cpp $(VDIRFB)/Veqspiflash.mk: eqspiflash.v lleqspi.v
$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
verilator -cc -y $(CPUDR) $*.v
 
/fasttop.v
108,10 → 108,10
input i_aux_rx, i_aux_rts;
output wire o_aux_tx, o_aux_cts;
 
// `define FULLCLOCK
`define FULLCLOCK
// Build our master clock
wire i_clk, clk_for_ddr, clk2_unused, enet_clk, clk5_unused,
clk_feedback, clk_locked;
wire i_clk, clk_for_ddr, clk2_unused, enet_clk, clk_analyzer,
clk_feedback, clk_locked, clk_analyzer_b;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
120,11 → 120,11
// CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: divide amount for each CLKOUT(1-128)
.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
.CLKOUT0_DIVIDE(4), // 200 MHz
.CLKOUT1_DIVIDE(4), // 200 MHz
.CLKOUT1_DIVIDE(4), // 200 MHz clock for DDR memory
.CLKOUT2_DIVIDE(8), // 100 MHz
.CLKOUT3_DIVIDE(32), // 25 MHz
.CLKOUT4_DIVIDE(16), // 50 MHz
.CLKOUT5_DIVIDE(24),
.CLKOUT4_DIVIDE(1), // 800 MHz
.CLKOUT5_DIVIDE(1),
`else
// 100*64/40 = 160 -- the fastest speed where the UART will
// still work at 4MBaud. Others will still support 115200
134,11 → 134,11
// 100*64/33 = 193.94
.CLKFBOUT_MULT(8), // Multiply value for all CLKOUT (2-64)
.CLKOUT0_DIVIDE(5), // 160 MHz
.CLKOUT1_DIVIDE(5), // 160 MHz
.CLKOUT1_DIVIDE(5), // 160 MHz //Clock too slow for DDR mem
.CLKOUT2_DIVIDE(10), // 80 MHz
.CLKOUT3_DIVIDE(40), // 20 MHz
.CLKOUT4_DIVIDE(20), // 40 MHz
.CLKOUT5_DIVIDE(30),
.CLKOUT4_DIVIDE(1), // 40 MHz
.CLKOUT5_DIVIDE(1),
`endif
// CLKOUT0_DUTY_CYCLE -- Duty cycle for each CLKOUT
.CLKOUT0_DUTY_CYCLE(0.5),
149,11 → 149,11
.CLKOUT5_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE -- phase offset for each CLKOUT
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(90.0),
.CLKOUT1_PHASE(270.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT5_PHASE(180.0),
.DIVCLK_DIVIDE(1), // Master division value , (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999)
.STARTUP_WAIT("FALSE") // Delayu DONE until PLL Locks, ("TRUE"/"FALSE")
163,8 → 163,8
.CLKOUT1(clk_for_ddr),
.CLKOUT2(clk2_unused), // Reserved for flash, should we need it
.CLKOUT3(enet_clk),
.CLKOUT4(clk4_unused),
.CLKOUT5(clk5_unused),
.CLKOUT4(clk_analyzer),
.CLKOUT5(clk_analyzer_b),
.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
.LOCKED(clk_locked),
.CLKIN1(i_clk_100mhz),
220,8 → 220,13
wire [3:0] i_qspi_dat;
 
//
wire [2:0] w_ddr_dqs;
wire [31:0] wo_ddr_data, wi_ddr_data;
wire w_ddr_dqs, w_ddr_dm, w_ddr_bus_oe, w_ddr_odt;
wire [2:0] w_ddr_ba;
wire w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n;
wire [13:0] w_ddr_addr;
reg [31:0] r_ddr_data;
 
//
wire w_mdio, w_mdwe;
//
239,8 → 244,9
o_qspi_cs_n, w_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
// DDR3 SDRAM
o_ddr_reset_n, o_ddr_cke,
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
w_ddr_dqs, o_ddr_addr, o_ddr_ba, wo_ddr_data, wi_ddr_data,
w_ddr_cs_n, w_ddr_ras_n, w_ddr_cas_n, w_ddr_we_n,
w_ddr_dqs, w_ddr_dm, w_ddr_odt, w_ddr_bus_oe,
w_ddr_addr, w_ddr_ba, wo_ddr_data, r_ddr_data,
// SD Card
o_sd_sck, w_sd_cmd, w_sd_data, io_sd_cmd, io_sd, i_sd_cs,
// Ethernet control (MDIO) lines
272,33 → 278,30
// ?? Dual mode out (not yet)
//
//
`define QSPI_OUT_VERSION_ONE
`ifdef QSPI_OUT_VERSION_ONE
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
assign i_qspi_dat = io_qspi_dat;
assign o_qspi_sck = w_qspi_sck;
/*
wire [3:0] i_qspi_dat_ign;
ODDR #(.DDR_CLK_EDGE("OPPOSITE_EDGE"), .INIT(1'b1), .SRTYPE("SYNC"))
qsck(
.Q(o_qspi_sck),
.C(i_clk),
.CE(1'b1),
.D1(w_qspi_sck),
.D2(w_qspi_sck),
.R(1'b0), .S(1'b0));
xioddr qd0(i_clk, (~qspi_bmod[1])|(~qspi_bmod[0]),
`else
wire [3:0] i_qspi_ignore;
 
xoddr xqspi_sck( i_clk, { w_qspi_sck, w_qspi_sck }, o_qspi_sck);
//
xioddr xqspi_d0( i_clk, (~qspi_bmod[0])||(~qspi_bmod[1]),
{ qspi_dat[0], qspi_dat[0] },
{ i_qspi_dat[0], i_qspi_dat_ign[0] }, io_qspi_dat[0]);
xioddr qd1(i_clk, (qspi_bmod == 2'b10),
{ i_qspi_ignore[0], i_qspi_dat[0] }, io_qspi_dat[0]);
xioddr xqspi_d1( i_clk, (qspi_bmod==2'b10),
{ qspi_dat[1], qspi_dat[1] },
{ i_qspi_dat[1], i_qspi_dat_ign[1] }, io_qspi_dat[1]);
xioddr qd2(i_clk, (~qspi_bmod[1])||(~qspi_bmod[0]),
{ qspi_dat[2], qspi_dat[2] },
{ i_qspi_dat[2], i_qspi_dat_ign[2] }, io_qspi_dat[2]);
xioddr qd3(i_clk, (~qspi_bmod[1])||(~qspi_bmod[0]),
{ qspi_dat[3], qspi_dat[3] },
{ i_qspi_dat[3], i_qspi_dat_ign[3] }, io_qspi_dat[3]);
*/
{ i_qspi_ignore[1], i_qspi_dat[1] }, io_qspi_dat[1]);
xioddr xqspi_d2( i_clk, (qspi_bmod!=2'b11),
(qspi_bmod[1])?{ qspi_dat[2], qspi_dat[2] }:2'b11,
{ i_qspi_ignore[2], i_qspi_dat[2] }, io_qspi_dat[2]);
xioddr xqspi_d3( i_clk, (qspi_bmod!=2'b11),
(qspi_bmod[1])?{ qspi_dat[3], qspi_dat[3] }:2'b11,
{ i_qspi_ignore[3], i_qspi_dat[3] }, io_qspi_dat[3]);
`endif
 
//
// Proposed QSPI mode select, to allow dual I/O mode
316,8 → 319,9
 
//
//
// The following primitive is necessary in order to gain access
// to the o_qspi_sck pin.
// The following primitive is necessary on other boards in order to
// gain access to the o_qspi_sck pin. On the Arty, however, there is
// a clock PIN, so we don't need this primitive.
//
//
/*
387,7 → 391,6
assign io_sd[1] = w_sd_data[1]? 1'bz:1'b0;
assign io_sd[2] = w_sd_data[2]? 1'bz:1'b0;
assign io_sd[3] = w_sd_data[3]? 1'bz:1'b0;
assign o_sd_wp = 1'b0;
 
 
//
402,68 → 405,142
// Wires for setting up the DDR3 memory
//
//
wire [31:0] r_ddr_data;
 
xioddr p0(i_clk, ~o_ddr_we_n, { wo_ddr_data[16], wo_ddr_data[0] },
`ifdef SDRAM_ACCESS
reg [15:0] bottom_half_data;
always @(posedge i_clk)
bottom_half_data <= wo_ddr_data[15:0];
xioddr p0(i_clk, w_ddr_bus_oe, { wo_ddr_data[16], wo_ddr_data[0] },
{ wi_ddr_data[16], wi_ddr_data[0] }, io_ddr_data[0]);
 
xioddr p1(i_clk, ~o_ddr_we_n, { wo_ddr_data[17], wo_ddr_data[1] },
xioddr p1(i_clk, w_ddr_bus_oe, { wo_ddr_data[17], wo_ddr_data[1] },
{ wi_ddr_data[17], wi_ddr_data[1] }, io_ddr_data[1]);
 
xioddr p2(i_clk, ~o_ddr_we_n, { wo_ddr_data[18], wo_ddr_data[2] },
xioddr p2(i_clk, w_ddr_bus_oe, { wo_ddr_data[18], wo_ddr_data[2] },
{ wi_ddr_data[18], wi_ddr_data[2] }, io_ddr_data[2]);
 
xioddr p3(i_clk, ~o_ddr_we_n, { wo_ddr_data[19], wo_ddr_data[3] },
xioddr p3(i_clk, w_ddr_bus_oe, { wo_ddr_data[19], wo_ddr_data[3] },
{ wi_ddr_data[19], wi_ddr_data[3] }, io_ddr_data[3]);
 
xioddr p4(i_clk, ~o_ddr_we_n, { wo_ddr_data[20], wo_ddr_data[4] },
xioddr p4(i_clk, w_ddr_bus_oe, { wo_ddr_data[20], wo_ddr_data[4] },
{ wi_ddr_data[20], wi_ddr_data[4] }, io_ddr_data[4]);
 
xioddr p5(i_clk, ~o_ddr_we_n, { wo_ddr_data[21], wo_ddr_data[5] },
xioddr p5(i_clk, w_ddr_bus_oe, { wo_ddr_data[21], wo_ddr_data[5] },
{ wi_ddr_data[21], wi_ddr_data[5] }, io_ddr_data[5]);
 
xioddr p6(i_clk, ~o_ddr_we_n, { wo_ddr_data[22], wo_ddr_data[6] },
xioddr p6(i_clk, w_ddr_bus_oe, { wo_ddr_data[22], wo_ddr_data[6] },
{ wi_ddr_data[22], wi_ddr_data[6] }, io_ddr_data[6]);
 
xioddr p7(i_clk, ~o_ddr_we_n, { wo_ddr_data[23], wo_ddr_data[7] },
xioddr p7(i_clk, w_ddr_bus_oe, { wo_ddr_data[23], wo_ddr_data[7] },
{ wi_ddr_data[23], wi_ddr_data[7] }, io_ddr_data[7]);
 
xioddr p8(i_clk, ~o_ddr_we_n, { wo_ddr_data[24], wo_ddr_data[8] },
xioddr p8(i_clk, w_ddr_bus_oe, { wo_ddr_data[24], wo_ddr_data[8] },
{ wi_ddr_data[24], wi_ddr_data[8] }, io_ddr_data[8]);
 
xioddr p9(i_clk, ~o_ddr_we_n, { wo_ddr_data[25], wo_ddr_data[9] },
xioddr p9(i_clk, w_ddr_bus_oe, { wo_ddr_data[25], wo_ddr_data[9] },
{ wi_ddr_data[25], wi_ddr_data[9] }, io_ddr_data[9]);
 
xioddr pa(i_clk, ~o_ddr_we_n, { wo_ddr_data[26], wo_ddr_data[10] },
xioddr pa(i_clk, w_ddr_bus_oe, { wo_ddr_data[26], wo_ddr_data[10] },
{ wi_ddr_data[26], wi_ddr_data[10] }, io_ddr_data[10]);
 
xioddr pb(i_clk, ~o_ddr_we_n, { wo_ddr_data[27], wo_ddr_data[11] },
xioddr pb(i_clk, w_ddr_bus_oe, { wo_ddr_data[27], wo_ddr_data[11] },
{ wi_ddr_data[27], wi_ddr_data[11] }, io_ddr_data[11]);
 
xioddr pc(i_clk, ~o_ddr_we_n, { wo_ddr_data[28], wo_ddr_data[12] },
xioddr pc(i_clk, w_ddr_bus_oe, { wo_ddr_data[28], wo_ddr_data[12] },
{ wi_ddr_data[28], wi_ddr_data[12] }, io_ddr_data[12]);
 
xioddr pd(i_clk, ~o_ddr_we_n, { wo_ddr_data[29], wo_ddr_data[13] },
xioddr pd(i_clk, w_ddr_bus_oe, { wo_ddr_data[29], wo_ddr_data[13] },
{ wi_ddr_data[29], wi_ddr_data[13] }, io_ddr_data[13]);
 
xioddr pe(i_clk, ~o_ddr_we_n, { wo_ddr_data[30], wo_ddr_data[14] },
xioddr pe(i_clk, w_ddr_bus_oe, { wo_ddr_data[30], wo_ddr_data[14] },
{ wi_ddr_data[30], wi_ddr_data[14] }, io_ddr_data[14]);
 
xioddr pf(i_clk, ~o_ddr_we_n, { wo_ddr_data[31], wo_ddr_data[15] },
xioddr pf(i_clk, w_ddr_bus_oe, { wo_ddr_data[31], wo_ddr_data[15] },
{ wi_ddr_data[31], wi_ddr_data[15] }, io_ddr_data[15]);
always @(posedge i_clk)
r_ddr_data <= wi_ddr_data;
 
OBUFTDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
dqsbuf0(.O(io_ddr_dqs_p[0]), .OB(io_ddr_dqs_n[0]),
.I(w_ddr_dqs[1]), .T(w_ddr_dqs[2]));
OBUFTDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
dqsbuf1(.O(io_ddr_dqs_p[1]), .OB(io_ddr_dqs_n[1]),
.I(w_ddr_dqs[0]), .T(w_ddr_dqs[2]));
wire [7:0] w_dqs_ignore;
xioddrds dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
{ w_dqs_ignore[0], w_dqs_ignore[1] },
io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
xioddrds dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
{ w_dqs_ignore[2], w_dqs_ignore[3] },
io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
 
xoddr xcs_n( i_clk, { w_ddr_cs_n, w_ddr_cs_n }, o_ddr_cs_n);
xoddr xras_n(i_clk, { w_ddr_ras_n, w_ddr_ras_n }, o_ddr_ras_n);
xoddr xcas_n(i_clk, { w_ddr_cas_n, w_ddr_cas_n }, o_ddr_cas_n);
xoddr xwe_n( i_clk, { w_ddr_we_n, w_ddr_we_n }, o_ddr_we_n);
xoddr xba0( i_clk, { w_ddr_ba[0], w_ddr_ba[0] }, o_ddr_ba[0]);
xoddr xba1( i_clk, { w_ddr_ba[1], w_ddr_ba[1] }, o_ddr_ba[1]);
xoddr xba2( i_clk, { w_ddr_ba[2], w_ddr_ba[2] }, o_ddr_ba[2]);
xoddr xaddr0(i_clk, { w_ddr_addr[0], w_ddr_addr[0] }, o_ddr_addr[0]);
xoddr xaddr1(i_clk, { w_ddr_addr[1], w_ddr_addr[1] }, o_ddr_addr[1]);
xoddr xaddr2(i_clk, { w_ddr_addr[2], w_ddr_addr[2] }, o_ddr_addr[2]);
xoddr xaddr3(i_clk, { w_ddr_addr[3], w_ddr_addr[3] }, o_ddr_addr[3]);
xoddr xaddr4(i_clk, { w_ddr_addr[4], w_ddr_addr[4] }, o_ddr_addr[4]);
xoddr xaddr5(i_clk, { w_ddr_addr[5], w_ddr_addr[5] }, o_ddr_addr[5]);
xoddr xaddr6(i_clk, { w_ddr_addr[6], w_ddr_addr[6] }, o_ddr_addr[6]);
xoddr xaddr7(i_clk, { w_ddr_addr[7], w_ddr_addr[7] }, o_ddr_addr[7]);
xoddr xaddr8(i_clk, { w_ddr_addr[8], w_ddr_addr[8] }, o_ddr_addr[8]);
xoddr xaddr9(i_clk, { w_ddr_addr[9], w_ddr_addr[9] }, o_ddr_addr[9]);
xoddr xaddr10(i_clk,{ w_ddr_addr[10],w_ddr_addr[10]}, o_ddr_addr[10]);
xoddr xaddr11(i_clk,{ w_ddr_addr[11],w_ddr_addr[11]}, o_ddr_addr[11]);
xoddr xaddr12(i_clk,{ w_ddr_addr[12],w_ddr_addr[12]}, o_ddr_addr[12]);
xoddr xaddr13(i_clk,{ w_ddr_addr[13],w_ddr_addr[13]}, o_ddr_addr[13]);
 
wire w_clk_for_ddr;
ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(clk_for_ddr));
clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(w_clk_for_ddr));
 
assign o_ddr_dm = 2'b00;
assign o_ddr_odt = 1'b0;
// assign o_ddr_dm[0] = w_ddr_dm;
// assign o_ddr_dm[1] = w_ddr_dm;
xoddr xdm0(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[0]);
xoddr xdm1(i_clk,{ w_ddr_dm, w_ddr_dm }, o_ddr_dm[1]);
 
assign o_ddr_odt = (~o_ddr_reset_n)? 1'bz : w_ddr_odt;
 
// xlogicanalyzer ladata(i_clk, io_ddr_data[0], w_ddr_debug[3:0]);
// xlogicanalyzer ladclk(clk_analyzer, clk_analyzer_b,
// i_clk, o_ddr_ck_p, w_ddr_debug[7:4]);
assign w_ddr_debug[7:4] = 4'h0;
assign w_ddr_debug[3:0] = 4'h0;
`else
assign o_ddr_cs_n = w_ddr_cs_n;
assign o_ddr_ras_n = w_ddr_ras_n;
assign o_ddr_cas_n = w_ddr_cas_n;
assign o_ddr_we_n = w_ddr_we_n;
//
assign o_ddr_ba = w_ddr_ba;
assign o_ddr_addr = w_ddr_addr;
//
assign o_ddr_dm[1:0] = 2'b00;
assign o_ddr_odt = 1'b0;
//
assign io_ddr_data = 16'bzzzz_zzzz_zzzz_zzzz;
always @(posedge i_clk)
r_ddr_data = 16'h0000;
 
//wire w_clk_for_ddr;
//ODDR #(.DDR_CLK_EDGE("SAME_EDGE"))
//memclkddr(.Q(w_clk_for_ddr), .C(clk_for_ddr), .CE(1'b1),
//.D1(1'b0), .D2(1'b1), .R(1'b0), .S(1'b0));
OBUFDS #(.IOSTANDARD("DIFF_SSTL135"), .SLEW("FAST"))
clkbuf(.O(o_ddr_ck_p), .OB(o_ddr_ck_n), .I(1'b1));
 
wire [7:0] w_dqs_ignore;
xioddrds dqs0(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
{ w_dqs_ignore[0], w_dqs_ignore[1] },
io_ddr_dqs_p[0], io_ddr_dqs_n[0]);
xioddrds dqs1(clk_for_ddr, w_ddr_dqs, { 1'b0, 1'b1 },
{ w_dqs_ignore[2], w_dqs_ignore[3] },
io_ddr_dqs_p[1], io_ddr_dqs_n[1]);
 
 
`endif
 
endmodule
 
/builddate.v
38,4 → 38,4
////////////////////////////////////////////////////////////////////////////////
//
//
`define DATESTAMP 32'h20160725
`define DATESTAMP 32'h20160810
/lleqspi.v
297,22 → 297,39
*/
end
 
`define EXTRA_DELAY
`ifdef EXTRA_DELAY
reg rd_input_2, rd_valid_2, r_spd_2;
always @(posedge i_clk)
rd_input_2 <= rd_input;
always @(posedge i_clk)
rd_valid_2 <= rd_valid;
always @(posedge i_clk)
r_spd_2 <= r_spd;
`else
wire rd_input_2, rd_valid_2, r_spd_2;
assign rd_input_2 = rd_input;
assign rd_valid_2 = rd_valid;
assign r_spd_2 = rd_spd;
`endif
 
 
always @(posedge i_clk)
begin
if ((state == `EQSPI_IDLE)||(rd_valid))
if ((state == `EQSPI_IDLE)||(rd_valid_2))
r_input <= 31'h00;
else if ((rd_input)&&(r_spd))
else if ((rd_input_2)&&(r_spd_2))
r_input <= { r_input[26:0], i_dat };
else if (rd_input)
else if (rd_input_2)
r_input <= { r_input[29:0], i_miso };
 
if ((rd_valid)&&(r_spd))
if ((rd_valid)&&(rd_spd))
o_word <= { r_input[27:0], i_dat };
else if (rd_valid)
o_word <= { r_input[30:0], i_miso };
end
 
assign o_valid = rd_valid;
assign o_valid = rd_valid_2;
 
endmodule
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.