URL
https://opencores.org/ocsvn/openarty/openarty/trunk
Subversion Repositories openarty
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- This comparison shows the changes necessary to convert path
/openarty/trunk/rtl
- from Rev 44 to Rev 49
- ↔ Reverse comparison
Rev 44 → Rev 49
/builddate.v
38,4 → 38,4
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define DATESTAMP 32'h20161102 |
`define DATESTAMP 32'h20161123 |
/busmaster.v
671,7 → 671,8
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0], |
wb_data, io_ack, io_stall, io_data, |
rtc_ppd, |
bus_err_addr, gps_now[63:32], gps_step[47:16], master_ints, w_interrupt, |
bus_err_addr, gps_now[63:32], gps_step[47:16], |
master_ints, w_interrupt, |
board_ints); |
assign { gpio_int, auxrx_int, auxtx_int, gpsrx_int, gpstx_int, sw_int, btn_int } = board_ints; |
|
/cpu/cpudefs.v
281,4 → 281,7
// |
`define DEBUG_SCOPE |
// |
// The following is experimental: |
// `define OPT_NO_USERMODE // Savings: about 143 LUTs or so |
// |
`endif // CPUDEFS_H |
/cpu/idecode.v
96,13 → 96,14
|
|
wire [4:0] w_op; |
wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop; |
wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop, |
w_mpy; |
wire [4:0] w_dcdR, w_dcdB, w_dcdA; |
wire w_dcdR_pc, w_dcdR_cc; |
wire w_dcdA_pc, w_dcdA_cc; |
wire w_dcdB_pc, w_dcdB_cc; |
wire [3:0] w_cond; |
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP; |
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP, w_sto; |
wire w_wR, w_rA, w_rB, w_wR_n; |
wire w_ljmp, w_ljmp_dly; |
wire [31:0] iword; |
133,16 → 134,21
assign w_brev = (w_op == 5'hc); |
assign w_cmptst = (w_op[4:1] == 4'h8); |
assign w_ldilo = (w_op[4:0] == 5'h9); |
assign w_mpy = ((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08)); |
assign w_ALU = (~w_op[4]); |
|
// 4 LUTs |
// |
// Two parts to the result register: the register set, given for |
// moves in i_word[18] but only for the supervisor, and the other |
// moves in iword[18] but only for the supervisor, and the other |
// four bits encoded in the instruction. |
// |
`ifdef OPT_NO_USERMODE |
assign w_dcdR = { 1'b0, iword[30:27] }; |
`else |
assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
iword[30:27] }; |
`endif |
// 2 LUTs |
// |
// If the result register is either CC or PC, and this would otherwise |
152,9 → 158,13
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7)) |
||(IMPLEMENT_FPU==0)); |
|
`ifdef OPT_NO_USERMODE |
assign w_dcdB = { 1'b0, iword[17:14] }; |
`else |
// 4 LUTs |
assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie, |
iword[17:14] }; |
`endif |
|
// 0 LUTs |
assign w_dcdA = w_dcdR; |
180,6 → 190,7
|
// 1 LUT |
assign w_dcdM = (w_op[4:1] == 4'h9); |
assign w_sto = (w_dcdM)&&(w_op[0]); |
// 1 LUT |
assign w_dcdDV = (w_op[4:1] == 4'ha); |
// 1 LUT |
191,18 → 202,17
||(w_dcdDV) |
// ALU read's A, unless it's a MOV to A |
// This includes LDIHI/LDILO |
||((~w_op[4])&&(w_op[3:0]!=4'hf)) |
||((~w_op[4])&&(w_op[3:0]!=4'hf)&&(!w_brev)) |
// STO's read A |
||((w_dcdM)&&(w_op[0])) |
// Test/compares |
||(w_op[4:1]== 4'h8); |
||(w_cmptst); |
// 1 LUTs -- do we read a register for operand B? Specifically, do |
// we need to stall if the register is not (yet) ready? |
assign w_rB = (w_mov)||((iword[18])&&(~w_ldi)); |
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR |
assign w_wR_n = ((w_dcdM)&&(w_op[0])) |
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)) |
||(w_cmptst); |
assign w_wR_n = (w_sto)||(w_cmptst) |
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)); |
assign w_wR = ~w_wR_n; |
// |
// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits) |
279,7 → 289,7
`else |
o_illegal <= ((i_illegal) || (i_instruction[31])); |
`endif |
if ((IMPLEMENT_MPY==0)&&((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08))) |
if ((IMPLEMENT_MPY==0)&&(w_mpy)) |
o_illegal <= 1'b1; |
|
if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV)) |
425,7 → 435,7
begin |
if (r_ljmp) |
r_branch_pc <= iword[(AW-1):0]; |
else if (w_op[4:1] == 4'hb) // LDI |
else if (w_ldi) // LDI |
r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]}; |
else // Add x,PC |
r_branch_pc <= i_pc |
/cpu/memops.v
44,7 → 44,8
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_stb, i_lock; |
// CPU interface |
72,8 → 73,8
|
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
assign lcl_stb = (i_stb)&&(i_addr[31:24]==8'hff); |
assign gbl_stb = (i_stb)&&(i_addr[31:24]!=8'hff); |
|
initial r_wb_cyc_gbl = 1'b0; |
initial r_wb_cyc_lcl = 1'b0; |
/cpu/pipemem.v
42,7 → 42,8
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH; |
parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_pipe_stb, i_lock; |
// CPU interface |
90,7 → 91,7
assign nxt_rdaddr = rdaddr + 4'h1; |
|
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0); |
assign lcl_stb = (i_addr[31:24]==8'hff); |
assign gbl_stb = (~lcl_stb); |
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); |
|
/cpu/zipcpu.v
203,22 → 203,26
// that logic. |
// |
(* ram_style = "distributed" *) |
`ifdef OPT_NO_USERMODE |
reg [31:0] regset [0:15]; |
`else |
reg [31:0] regset [0:31]; |
`endif |
|
// Condition codes |
// (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z |
reg [3:0] flags, iflags; |
wire [14:0] w_uflags, w_iflags; |
reg trap, break_en, step, gie, sleep, r_halted; |
wire break_pending; |
wire w_clear_icache; |
reg break_en, step, sleep, r_halted; |
wire break_pending, trap, gie, ubreak; |
wire w_clear_icache, ill_err_u; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg ill_err_u, ill_err_i; |
reg ill_err_i; |
`else |
wire ill_err_u, ill_err_i; |
wire ill_err_i; |
`endif |
reg ubreak; |
reg ibus_err_flag, ubus_err_flag; |
reg ibus_err_flag; |
wire ubus_err_flag; |
wire idiv_err_flag, udiv_err_flag; |
wire ifpu_err_flag, ufpu_err_flag; |
wire ihalt_phase, uhalt_phase; |
330,9 → 334,7
|
|
wire mem_ce, mem_stalled; |
`ifdef OPT_PIPELINED_BUS_ACCESS |
wire mem_pipe_stalled; |
`endif |
wire mem_valid, mem_ack, mem_stall, mem_err, bus_err, |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we; |
wire [4:0] mem_wreg; |
369,7 → 371,8
wire [4:0] wr_reg_id; |
wire [31:0] wr_gpreg_vl, wr_spreg_vl; |
wire w_switch_to_interrupt, w_release_from_interrupt; |
reg [(AW-1):0] upc, ipc; |
reg [(AW-1):0] ipc; |
wire [(AW-1):0] upc; |
|
|
|
445,7 → 448,7
// CC register |
||(dcdF_stall) |
); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline); |
assign op_ce = ((dcdvalid)||(dcd_illegal)||(dcd_early_branch))&&(~op_stall)&&(~clear_pipeline); |
|
|
// BUT ... op_ce is too complex for many of the data operations. So |
456,7 → 459,7
assign op_change_data_ce = (~op_stall); |
`else |
assign op_stall = (opvalid)&&(~master_ce); |
assign op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline); |
assign op_ce = ((dcdvalid)||(dcd_illegal)||(dcd_early_branch))&&(~clear_pipeline); |
assign op_change_data_ce = 1'b1; |
`endif |
|
476,7 → 479,7
`ifdef OPT_PIPELINED |
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2 |
||((opvalid)&&(op_lock)&&(op_lock_stall)) |
||((opvalid)&&(op_break)) // || op_illegal |
||((opvalid)&&(op_break)) |
||(wr_reg_ce)&&(wr_write_cc) |
||(div_busy)||(fpu_busy); |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall) |
594,7 → 597,11
(mem_cyc_lcl)||(mem_cyc_gbl), |
pf_illegal); |
`endif |
`ifdef OPT_NO_USERMODE |
assign instruction_gie = 1'b0; |
`else |
assign instruction_gie = gie; |
`endif |
|
initial r_dcdvalid = 1'b0; |
always @(posedge i_clk) |
673,8 → 680,13
// PIPELINE STAGE #3 :: Read Operands (Registers) |
// |
// |
`ifdef OPT_NO_USERMODE |
assign w_opA = regset[dcdA[3:0]]; |
assign w_opB = regset[dcdB[3:0]]; |
`else |
assign w_opA = regset[dcdA]; |
assign w_opB = regset[dcdB]; |
`endif |
|
wire [8:0] w_cpu_info; |
assign w_cpu_info = { |
843,7 → 855,7
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] }; |
|
wire w_opvalid; |
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp); |
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp)&&(!dcd_early_branch); |
initial opvalid = 1'b0; |
initial opvalid_alu = 1'b0; |
initial opvalid_mem = 1'b0; |
867,14 → 879,15
// Hence, the test on dcd_stalled here. If we must |
// wait until our operands are valid, then we aren't |
// valid yet until then. |
opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid); |
opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid)||(dcd_early_branch); |
`ifdef OPT_ILLEGAL_INSTRUCTION |
opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal)); |
opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal) |
||(dcd_early_branch)); |
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid); |
`else |
opvalid_alu <= (dcdALU)&&(w_opvalid); |
opvalid_alu <= (dcdALU)&&(w_opvalid)||(dcd_early_branch); |
opvalid_mem <= (dcdM)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(w_opvalid); |
903,7 → 916,7
initial r_op_break = 1'b0; |
always @(posedge i_clk) |
if (i_rst) r_op_break <= 1'b0; |
else if (op_ce) r_op_break <= (dcd_break); //||dcd_illegal &&(dcdvalid) |
else if (op_ce) r_op_break <= (dcd_break); |
else if ((clear_pipeline)||(~opvalid)) |
r_op_break <= 1'b0; |
assign op_break = r_op_break; |
988,7 → 1001,9
always @(posedge i_clk) |
if (op_change_data_ce) |
begin |
r_opn <= dcdOp; // Which ALU operation? |
// Which ALU operation? Early branches are |
// unimplemented moves |
r_opn <= (dcd_early_branch) ? 4'hf : dcdOp; |
// opM <= dcdM; // Is this a memory operation? |
// What register will these results be written into? |
r_opR <= dcdR; |
996,18 → 1011,25
// User level (1), vs supervisor (0)/interrupts disabled |
r_op_gie <= dcd_gie; |
|
|
// |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
end |
assign opn = r_opn; |
assign opR = r_opR; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign op_gie = r_op_gie; |
`endif |
assign opR_cc = r_opR_cc; |
`else |
assign opn = dcdOp; |
assign opR = dcdR; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign op_gie = dcd_gie; |
`endif |
// With no pipelining, there is no early branching. We keep it |
always @(posedge i_clk) |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
1229,6 → 1251,9
reg [31:0] dbg_val; |
always @(posedge i_clk) |
dbg_val <= i_dbg_data; |
`ifdef OPT_NO_USERMODE |
assign alu_gie = 1'b0; |
`else |
`ifdef OPT_PIPELINED |
reg r_alu_gie; |
|
1236,7 → 1261,12
if ((adf_ce_unconditional)||(mem_ce)) |
r_alu_gie <= op_gie; |
assign alu_gie = r_alu_gie; |
`else |
assign alu_gie = op_gie; |
`endif |
`endif |
|
`ifdef OPT_PIPELINED |
reg [(AW-1):0] r_alu_pc; |
always @(posedge i_clk) |
if ((adf_ce_unconditional) |
1245,7 → 1275,6
r_alu_pc <= op_pc; |
assign alu_pc = r_alu_pc; |
`else |
assign alu_gie = op_gie; |
assign alu_pc = op_pc; |
`endif |
|
1321,6 → 1350,7
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_ack, mem_stall, mem_err, i_wb_data); |
assign mem_pipe_stalled = 1'b0; |
`endif // PIPELINED_BUS_ACCESS |
assign mem_rdbusy = ((mem_busy)&&(~mem_we)); |
|
1380,7 → 1410,14
// One or PC, one for CC, and one for GIE match |
// Note that the alu_reg is the register to write on a divide or |
// FPU operation. |
`ifdef OPT_NO_USERMODE |
assign wr_reg_id[3:0] = (alu_wr|div_valid|fpu_valid) |
? alu_reg[3:0]:mem_wreg[3:0]; |
assign wr_reg_id[4] = 1'b0; |
`else |
assign wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg; |
`endif |
|
// Are we writing to the CC register? |
assign wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG); |
assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG}); |
1397,7 → 1434,11
:((dbgv) ? dbg_val : alu_result)); |
always @(posedge i_clk) |
if (wr_reg_ce) |
regset[wr_reg_id] <= wr_gpreg_vl; |
`ifdef OPT_NO_USERMODE |
regset[wr_reg_id[3:0]] <= wr_gpreg_vl; |
`else |
regset[wr_reg_id] <= wr_gpreg_vl; |
`endif |
|
// |
// Write back to the condition codes/flags register ... |
1483,7 → 1524,29
// a panic/fault halt. The trick is that you cannot be allowed to |
// set the sleep bit and switch to supervisor mode in the same |
// instruction: users are not allowed to halt the CPU. |
initial sleep = 1'b0; |
`ifdef OPT_NO_USERMODE |
reg r_sleep_is_halt; |
initial r_sleep_is_halt = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_sleep_is_halt <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc) |
&&(wr_spreg_vl[`CPU_SLEEP_BIT]) |
&&(~wr_spreg_vl[`CPU_GIE_BIT])) |
r_sleep_is_halt <= 1'b1; |
|
// Trying to switch to user mode, either via a WAIT or an RTU |
// instruction will cause the CPU to sleep until an interrupt, in |
// the NO-USERMODE build. |
always @(posedge i_clk) |
if ((i_rst)||((i_interrupt)&&(!r_sleep_is_halt))) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc) |
&&(wr_spreg_vl[`CPU_GIE_BIT])) |
sleep <= 1'b1; |
`else |
always @(posedge i_clk) |
if ((i_rst)||(w_switch_to_interrupt)) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie)) |
1503,6 → 1566,7
// to sleep mode *and* supervisor mode at the same |
// time, lest you halt the CPU. |
sleep <= wr_spreg_vl[`CPU_SLEEP_BIT]; |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
1511,6 → 1575,10
step <= wr_spreg_vl[`CPU_STEP_BIT]; |
|
// The GIE register. Only interrupts can disable the interrupt register |
`ifdef OPT_NO_USERMODE |
assign w_switch_to_interrupt = 1'b0; |
assign w_release_from_interrupt = 1'b0; |
`else |
assign w_switch_to_interrupt = (gie)&&( |
// On interrupt (obviously) |
((i_interrupt)&&(~alu_phase)&&(~bus_lock)) |
1542,34 → 1610,56
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_scc)) |
); |
`endif |
|
`ifdef OPT_NO_USERMODE |
assign gie = 1'b0; |
`else |
reg r_gie; |
|
initial r_gie = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
gie <= 1'b0; |
r_gie <= 1'b0; |
else if (w_switch_to_interrupt) |
gie <= 1'b0; |
r_gie <= 1'b0; |
else if (w_release_from_interrupt) |
gie <= 1'b1; |
r_gie <= 1'b1; |
assign gie = r_gie; |
`endif |
|
initial trap = 1'b0; |
`ifdef OPT_NO_USERMODE |
assign trap = 1'b0; |
assign ubreak = 1'b0; |
`else |
reg r_trap; |
|
initial r_trap = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
trap <= 1'b0; |
r_trap <= 1'b0; |
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied |
trap <= 1'b1; |
r_trap <= 1'b1; |
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie)) |
trap <= (trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]); |
r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]); |
|
initial ubreak = 1'b0; |
reg r_ubreak; |
|
initial r_ubreak = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
ubreak <= 1'b0; |
r_ubreak <= 1'b0; |
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt)) |
ubreak <= 1'b1; |
r_ubreak <= 1'b1; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]); |
r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]); |
|
assign trap = r_trap; |
assign ubreak = r_ubreak; |
`endif |
|
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial ill_err_i = 1'b0; |
always @(posedge i_clk) |
1580,18 → 1670,25
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]); |
else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline)) |
ill_err_i <= 1'b1; |
initial ill_err_u = 1'b0; |
|
`ifdef OPT_NO_USERMODE |
assign ill_err_u = 1'b0; |
`else |
reg r_ill_err_u; |
|
initial r_ill_err_u = 1'b0; |
always @(posedge i_clk) |
// The bit is automatically cleared on release from interrupt |
// or reset |
if ((i_rst)||(w_release_from_interrupt)) |
ill_err_u <= 1'b0; |
r_ill_err_u <= 1'b0; |
// If the supervisor (or debugger) writes to this register, |
// clearing the bit, then clear it |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT])); |
r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT])); |
else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline)) |
ill_err_u <= 1'b1; |
r_ill_err_u <= 1'b1; |
`endif |
`else |
assign ill_err_u = 1'b0; |
assign ill_err_i = 1'b0; |
1607,16 → 1704,24
else if ((bus_err)&&(~alu_gie)) |
ibus_err_flag <= 1'b1; |
// User bus error flag -- if ever set, it will cause an interrupt to |
// supervisor mode. |
initial ubus_err_flag = 1'b0; |
// supervisor mode. |
`ifdef OPT_NO_USERMODE |
assign ubus_err_flag = 1'b0; |
`else |
reg r_ubus_err_flag; |
|
initial r_ubus_err_flag = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
ubus_err_flag <= 1'b0; |
r_ubus_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
else if ((bus_err)&&(alu_gie)) |
ubus_err_flag <= 1'b1; |
r_ubus_err_flag <= 1'b1; |
|
assign ubus_err_flag = r_ubus_err_flag; |
`endif |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
1633,6 → 1738,11
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]); |
else if ((div_error)&&(~alu_gie)) |
r_idiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
`ifdef OPT_NO_USERMODE |
assign udiv_err_flag = 1'b0; |
`else |
// User divide (by zero) error flag -- if ever set, it will |
// cause a sudden switch interrupt to supervisor mode. |
initial r_udiv_err_flag = 1'b0; |
1645,8 → 1755,8
else if ((div_error)&&(alu_gie)) |
r_udiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
assign udiv_err_flag = r_udiv_err_flag; |
`endif |
end else begin |
assign idiv_err_flag = 1'b0; |
assign udiv_err_flag = 1'b0; |
1686,15 → 1796,23
end endgenerate |
|
`ifdef OPT_VLIW |
reg r_ihalt_phase, r_uhalt_phase; |
reg r_ihalt_phase; |
|
initial r_ihalt_phase = 0; |
initial r_uhalt_phase = 0; |
always @(posedge i_clk) |
if (i_rst) |
r_ihalt_phase <= 1'b0; |
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline)) |
r_ihalt_phase <= alu_phase; |
|
assign ihalt_phase = r_ihalt_phase; |
|
`ifdef OPT_NO_USERMODE |
assign uhalt_phase = 1'b0; |
`else |
reg r_uhalt_phase; |
|
initial r_uhalt_phase = 0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_uhalt_phase <= 1'b0; |
1703,8 → 1821,8
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc)) |
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT]; |
|
assign ihalt_phase = r_ihalt_phase; |
assign uhalt_phase = r_uhalt_phase; |
`endif |
`else |
assign ihalt_phase = 1'b0; |
assign uhalt_phase = 1'b0; |
1720,13 → 1838,20
// What happens when the pipeline has gie and ~gie instructions within |
// it? Do we clear both? What if a gie instruction tries to clear |
// a non-gie instruction? |
`ifdef OPT_NO_USERMODE |
assign upc = {(AW){1'b0}}; |
`else |
reg [(AW-1):0] r_upc; |
|
always @(posedge i_clk) |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc)) |
upc <= wr_spreg_vl[(AW-1):0]; |
r_upc <= wr_spreg_vl[(AW-1):0]; |
else if ((alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
||(mem_pc_valid))) |
upc <= alu_pc; |
r_upc <= alu_pc; |
assign upc = r_upc; |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
1734,7 → 1859,7
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc)) |
ipc <= wr_spreg_vl[(AW-1):0]; |
else if ((~alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)) |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
||(mem_pc_valid))) |
ipc <= alu_pc; |
|
1759,19 → 1884,6
pf_pc <= alu_pc; |
`endif |
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(i_clear_pf_cache)) |
new_pc <= 1'b1; |
else if (w_switch_to_interrupt) |
new_pc <= 1'b1; |
else if (w_release_from_interrupt) |
new_pc <= 1'b1; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
new_pc <= 1'b1; |
else |
new_pc <= 1'b0; |
|
`ifdef OPT_PIPELINED |
reg r_clear_icache; |
initial r_clear_icache = 1'b1; |
1784,42 → 1896,65
r_clear_icache <= 1'b0; |
assign w_clear_icache = r_clear_icache; |
`else |
assign w_clear_icache = 1'b0; |
assign w_clear_icache = i_clear_pf_cache; |
`endif |
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(w_clear_icache)) |
new_pc <= 1'b1; |
else if (w_switch_to_interrupt) |
new_pc <= 1'b1; |
else if (w_release_from_interrupt) |
new_pc <= 1'b1; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
new_pc <= 1'b1; |
else |
new_pc <= 1'b0; |
|
// |
// The debug interface |
wire [31:0] w_debug_pc; |
generate |
`ifdef OPT_NO_USERMODE |
if (AW<32) |
assign w_debug_pc = {{(32-AW){1'b0}},ipc}; |
else |
assign w_debug_pc = ipc; |
`else |
if (AW<32) |
assign w_debug_pc = {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc}; |
else |
assign w_debug_pc = (i_dbg_reg[4])?upc:ipc; |
`endif |
endgenerate |
|
always @(posedge i_clk) |
begin |
always @(posedge i_clk) |
`ifdef OPT_NO_USERMODE |
o_dbg_reg <= regset[i_dbg_reg[3:0]]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= w_debug_pc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc}; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
o_dbg_reg[14:0] <= w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end else begin |
always @(posedge i_clk) |
`else |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= w_debug_pc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg <= regset[i_dbg_reg]; |
if (i_dbg_reg[3:0] == `CPU_PC_REG) |
o_dbg_reg <= (i_dbg_reg[4])?upc:ipc; |
else if (i_dbg_reg[3:0] == `CPU_CC_REG) |
begin |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags; |
o_dbg_reg[15] <= 1'b0; |
o_dbg_reg[31:23] <= w_cpu_info; |
o_dbg_reg[`CPU_GIE_BIT] <= gie; |
end |
end endgenerate |
`endif |
end |
|
always @(posedge i_clk) |
o_dbg_cc <= { o_break, bus_err, gie, sleep }; |
1908,7 → 2043,7
assign debug_flags = { debug_trigger, 3'b101, |
master_ce, i_halt, o_break, sleep, |
gie, ibus_err_flag, trap, ill_err_i, |
r_clear_icache, pf_valid, pf_illegal, dcd_ce, |
w_clear_icache, pf_valid, pf_illegal, dcd_ce, |
dcdvalid, dcd_stalled, op_ce, opvalid, |
op_pipe, alu_ce, alu_busy, alu_wr, |
alu_illegal, alF_wr, mem_ce, mem_we, |
/enetpackets.v
200,8 → 200,10
reg [(MAW+1):0] tx_len; |
|
`ifdef RX_SYNCHRONOUS_WITH_WB_CLK |
wire rx_broadcast; |
wire [(MAW+1):0] rx_len; |
`else |
(* ASYNC_REG = "TRUE" *) reg rx_broadcast; |
(* ASYNC_REG = "TRUE" *) reg [(MAW+1):0] rx_len; |
`endif |
|
303,7 → 305,9
wire [3:0] w_maw; |
|
assign w_maw = MAW+2; // Number of bits in the packet length field |
assign w_rx_ctrl = { 4'h0, w_maw, {(24-19){1'b0}}, rx_crcerr, rx_err, |
assign w_rx_ctrl = { 4'h0, w_maw, {(24-20){1'b0}}, |
(rx_valid)&&(rx_broadcast)&&(!rx_clear), |
rx_crcerr, rx_err, |
rx_miss, rx_busy, (rx_valid)&&(!rx_clear), |
{(14-MAW-2){1'b0}}, rx_len }; |
|
683,6 → 687,7
assign rx_busy = n_rx_busy; |
assign rx_valid = n_rx_valid; |
assign rx_len = n_rx_len; |
assign rx_broadcast = n_rx_broadcast; |
`else |
reg r_rx_busy, r_rx_valid; |
always @(posedge i_wb_clk) |
694,6 → 699,7
rx_busy <= r_rx_busy; |
|
rx_len <= n_rx_len; |
rx_broadcast <= n_rx_broadcast; |
end |
|
`endif |
/fastio.v
4,7 → 4,12
// |
// Project: OpenArty, an entirely open SoC based upon the Arty platform |
// |
// Purpose: |
// Purpose: This file is used to group all of the simple I/O registers |
// together. These are the I/O registers whose values can be |
// read without requesting it of any submodules, and that are guaranteed |
// not to stall the bus. In general, these are items that can be read |
// or written in one clock (two, if an extra delay is needed to match |
// timing requirements). |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
159,11 → 164,28
initial pwr_counter = 32'h00; |
always @(posedge i_clk) |
if (pwr_counter[31]) |
pwr_counter[30:0] <= pwr_counter[30:0] + 31'h001; |
pwr_counter[30:0] <= pwr_counter[30:0] + 1'b1; |
else |
pwr_counter[31:0] <= pwr_counter[31:0] + 31'h001; |
pwr_counter[31:0] <= pwr_counter[31:0] + 1'b1; |
|
// |
// These pwr_counter bits are used for generating a PWM modulated |
// color LED output--allowing us to create multiple different, varied, |
// color LED "colors". Here, we reverse the bits, to make their |
// transitions and PWM that much *less* noticable. (a 50% |
// value, thus, is now an on-off-on-off-etc sequence, vice a |
// sequence of 256 ons followed by a sequence of 256 offs --- it |
// places the transitions into a higher frequency bracket, and costs |
// us no logic to do--only a touch more pain to understand on behalf |
// of the programmer.) |
wire [8:0] rev_pwr_counter; |
assign rev_pwr_counter[8:0] = { pwr_counter[0], |
pwr_counter[1], pwr_counter[2], |
pwr_counter[3], pwr_counter[4], |
pwr_counter[5], pwr_counter[6], |
pwr_counter[7], pwr_counter[8] }; |
|
// |
// BTNSW |
// |
// The button and switch control register |
269,9 → 291,9
r_clr_led0_r[7:0], r_clr_led0_g[7:0], r_clr_led0_b[7:0] |
}; |
always @(posedge i_clk) |
o_clr_led0 <= { (pwr_counter[8:0] < r_clr_led0_r), |
(pwr_counter[8:0] < r_clr_led0_g), |
(pwr_counter[8:0] < r_clr_led0_b) }; |
o_clr_led0 <= { (rev_pwr_counter[8:0] < r_clr_led0_r), |
(rev_pwr_counter[8:0] < r_clr_led0_g), |
(rev_pwr_counter[8:0] < r_clr_led0_b) }; |
|
// CLR LED 1 |
wire [31:0] w_clr_led1; |
291,9 → 313,9
r_clr_led1_r[7:0], r_clr_led1_g[7:0], r_clr_led1_b[7:0] |
}; |
always @(posedge i_clk) |
o_clr_led1 <= { (pwr_counter[8:0] < r_clr_led1_r), |
(pwr_counter[8:0] < r_clr_led1_g), |
(pwr_counter[8:0] < r_clr_led1_b) }; |
o_clr_led1 <= { (rev_pwr_counter[8:0] < r_clr_led1_r), |
(rev_pwr_counter[8:0] < r_clr_led1_g), |
(rev_pwr_counter[8:0] < r_clr_led1_b) }; |
// CLR LED 0 |
wire [31:0] w_clr_led2; |
reg [8:0] r_clr_led2_r, r_clr_led2_g, r_clr_led2_b; |
312,9 → 334,9
r_clr_led2_r[7:0], r_clr_led2_g[7:0], r_clr_led2_b[7:0] |
}; |
always @(posedge i_clk) |
o_clr_led2 <= { (pwr_counter[8:0] < r_clr_led2_r), |
(pwr_counter[8:0] < r_clr_led2_g), |
(pwr_counter[8:0] < r_clr_led2_b) }; |
o_clr_led2 <= { (rev_pwr_counter[8:0] < r_clr_led2_r), |
(rev_pwr_counter[8:0] < r_clr_led2_g), |
(rev_pwr_counter[8:0] < r_clr_led2_b) }; |
// CLR LED 3 |
wire [31:0] w_clr_led3; |
reg [8:0] r_clr_led3_r, r_clr_led3_g, r_clr_led3_b; |
333,9 → 355,9
r_clr_led3_r[7:0], r_clr_led3_g[7:0], r_clr_led3_b[7:0] |
}; |
always @(posedge i_clk) |
o_clr_led3 <= { (pwr_counter[8:0] < r_clr_led3_r), |
(pwr_counter[8:0] < r_clr_led3_g), |
(pwr_counter[8:0] < r_clr_led3_b) }; |
o_clr_led3 <= { (rev_pwr_counter[8:0] < r_clr_led3_r), |
(rev_pwr_counter[8:0] < r_clr_led3_g), |
(rev_pwr_counter[8:0] < r_clr_led3_b) }; |
|
// |
// The Calendar DATE |
463,7 → 485,23
r_gpstx_data }; |
assign gpstx_int = !gpstx_busy; |
|
reg [32:0] sec_step; |
initial sec_step = 33'h1; |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'h12)) |
sec_step <= { 1'b1, w_wb_data }; |
else if (!pps_int) |
sec_step <= 33'h1; |
|
reg [31:0] time_now_secs; |
initial time_now_secs = 32'h00; |
always @(posedge i_clk) |
if (pps_int) |
time_now_secs <= time_now_secs + sec_step[31:0]; |
else if (sec_step[32]) |
time_now_secs <= time_now_secs + sec_step[31:0]; |
|
always @(posedge i_clk) |
case(i_wb_addr) |
5'h00: o_wb_data <= `DATESTAMP; |
5'h01: o_wb_data <= pic_data; |
483,13 → 521,9
5'h0f: o_wb_data <= auxtx_data; |
5'h10: o_wb_data <= gpsrx_data; |
5'h11: o_wb_data <= gpstx_data; |
// 5'h12: o_wb_data <= i_gps_secs; |
5'h12: o_wb_data <= time_now_secs; |
5'h13: o_wb_data <= i_gps_sub; |
5'h14: o_wb_data <= i_gps_step; |
// 5'hf: UART_SETUP |
// 4'h6: GPIO |
// ?? : GPS-UARTRX |
// ?? : GPS-UARTTX |
default: o_wb_data <= 32'h00; |
endcase |
|