URL
https://opencores.org/ocsvn/openarty/openarty/trunk
Subversion Repositories openarty
Compare Revisions
- This comparison shows the changes necessary to convert path
/openarty/trunk
- from Rev 31 to Rev 32
- ↔ Reverse comparison
Rev 31 → Rev 32
/README.md
28,6 → 28,11
|
So ... it's a work in progress. |
|
# Repository |
|
Due to the ongoing issues with OpenCores, the official OpenArty repository |
is being kept on GitHub, under the ZipCPU username. |
|
# License |
|
Gisselquist Technology, LLC, is pleased to provide you with this entire |
/bench/cpp/fastmaster_tb.cpp
155,7 → 155,7
|
PIPECMDR::tick(); |
|
#define DEBUGGING_OUTPUT |
// #define DEBUGGING_OUTPUT |
#ifdef DEBUGGING_OUTPUT |
bool writeout = false; |
|
215,8 → 215,6
(m_core->v__DOT__wb_err)?'E':'.'); |
|
/* |
*/ |
|
// CPU Pipeline debugging |
printf("%s%s%s%s%s%s%s%s%s%s%s", |
// (m_core->v__DOT__zippy__DOT__dbg_ack)?"A":"-", |
338,7 → 336,9
m_core->v__DOT__zip_dbg_data); |
|
printf(" %s,0x%08x", (m_core->i_ram_ack)?"RCK":" ", m_core->i_ram_rdata); |
*/ |
|
|
/* |
printf(" SDSPI[%d,%d(%d),(%d)]", |
m_core->v__DOT__sdcard_controller__DOT__r_cmd_busy, |
/bench/cpp/memsim.cpp
113,16 → 113,22
m_mem[wb_addr & m_mask] = wb_data; |
m_fifo_ack[m_head] = 1; |
m_fifo_data[m_head] = m_mem[wb_addr & m_mask]; |
#ifdef DEBUG |
printf("MEMBUS %s[%08x] = %08x\n", |
(wb_we)?"W":"R", |
wb_addr&m_mask, |
m_mem[wb_addr&m_mask]); |
#endif |
// o_ack = 1; |
} if (o_ack) { |
} |
|
#ifdef DEBUG |
if (o_ack) { |
printf("MEMBUS -- ACK %s 0x%08x - 0x%08x\n", |
(wb_we)?"WRITE":"READ ", |
wb_addr, o_data); |
} |
#endif |
} |
|
|
bench/cpp
Property changes :
Added: svn:ignore
## -0,0 +1,8 ##
+busmaster_tb
+enetctrl_tb
+enetctrlsim.o
+eqspiflash_tb
+obj-pc
+.gitignore
+.*.swp
+debug.txt
Index: rtl/busmaster.v
===================================================================
--- rtl/busmaster.v (revision 31)
+++ rtl/busmaster.v (revision 32)
@@ -1191,12 +1191,14 @@
assign sdram_trigger = (ram_sel)&&(wb_stb);
assign sdram_debug= i_ram_dbg;
- wbscope #(5'd9,32,1) ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
- // Wishbone interface
- i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
- wb_we, wb_addr[0], wb_data,
+ wbscope #(5'd9,32,1)
+ ramscope(i_clk, 1'b1, sdram_trigger, sdram_debug,
+ // Wishbone interface
+ i_clk, wb_cyc,
+ ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b10)),
+ wb_we, wb_addr[0], wb_data,
scop_sdram_ack, scop_sdram_stall, scop_sdram_data,
- scop_sdram_interrupt);
+ scop_sdram_interrupt);
assign scop_c_ack = scop_sdram_ack;
assign scop_c_stall = scop_sdram_stall;
/rtl/cpu/cpudefs.v
69,8 → 69,8
// illegal instructions are quietly ignored and their behaviour is ... |
// undefined. (Many get treated like NOOPs ...) |
// |
// I recommend setting this flag, although it can be taken out if area is |
// critical ... |
// I recommend setting this flag so highly, that I'm likely going to remove |
// the option to turn this off in future versions of this CPU. |
// |
`define OPT_ILLEGAL_INSTRUCTION |
// |
/rtl/cpu/pipemem.v
52,7 → 52,7
input [4:0] i_oreg; |
// CPU outputs |
output wire o_busy; |
output reg o_pipe_stalled; |
output wire o_pipe_stalled; |
output reg o_valid; |
output reg o_err; |
output reg [4:0] o_wreg; |
164,13 → 164,8
// then either. |
o_result <= i_wb_data; |
|
/* |
assign o_pipe_stalled = (cyc) |
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl))); |
*/ |
always @(posedge i_clk) |
o_pipe_stalled <= (i_pipe_stb)&&(cyc)&&(i_wb_stall); |
|
|
generate |
if (IMPLEMENT_LOCK != 0) |
/rtl/cpu/wbdmac.v
189,7 → 189,7
// When the slave wishbone writes, and we are in this |
// (ready) configuration, then allow the DMA to be controlled |
// and thus to start. |
if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)) |
if ((i_swb_stb)&&(i_swb_we)) |
begin |
case(i_swb_addr) |
2'b00: begin |
340,8 → 340,7
always @(posedge i_clk) |
if (dma_state == `DMA_IDLE) |
begin |
if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we) |
&&(i_swb_addr==2'b00)) |
if ((i_swb_stb)&&(i_swb_we)&&(i_swb_addr==2'b00)) |
cfg_err <= 1'b0; |
end else if (((i_mwb_err)&&(o_mwb_cyc))||(abort)) |
cfg_err <= 1'b1; |
366,7 → 365,7
always @(posedge i_clk) |
if ((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK)) |
begin |
if (i_mwb_ack) |
if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall))) |
last_read_ack <= (nread+2 == nracks); |
else |
last_read_ack <= (nread+1 == nracks); |
390,7 → 389,7
always @(posedge i_clk) |
if((dma_state == `DMA_WRITE_REQ)||(dma_state == `DMA_WRITE_ACK)) |
begin |
if (i_mwb_ack) |
if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall))) |
last_write_ack <= (nwacks+2 == nwritten); |
else |
last_write_ack <= (nwacks+1 == nwritten); |
457,13 → 456,13
// but ack it anyway. In other words, before writing to the device, |
// double check that it isn't busy, and then write. |
always @(posedge i_clk) |
o_swb_ack <= (i_swb_cyc)&&(i_swb_stb); |
o_swb_ack <= (i_swb_stb); |
|
assign o_swb_stall = 1'b0; |
|
initial abort = 1'b0; |
always @(posedge i_clk) |
abort <= (i_rst)||((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we) |
abort <= (i_rst)||((i_swb_stb)&&(i_swb_we) |
&&(i_swb_addr == 2'b00) |
&&(i_swb_data == 32'hffed0000)); |
|
/rtl/cpu/zipbones.v
179,7 → 179,7
cpu_lcl_cyc, cpu_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_data, |
(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)), |
(i_wb_err)||(cpu_lcl_cyc), |
cpu_op_stall, cpu_pf_stall, cpu_i_count |
`ifdef DEBUG_SCOPE |
, o_zip_debug |
208,7 → 208,7
initial o_dbg_ack = 1'b0; |
always @(posedge i_clk) |
o_dbg_ack <= (i_dbg_cyc)&&((~i_dbg_addr)||(~o_dbg_stall)); |
assign o_dbg_stall=(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr); |
assign o_dbg_stall= 1'b0; //(i_dbg_cyc)&&(cpu_dbg_stall)&&(i_dbg_addr); |
|
assign o_ext_int = (cmd_halt) && (~i_wb_stall); |
|
/rtl/cpu/zipcounter.v
64,7 → 64,7
initial o_int = 0; |
initial o_wb_data = 32'h00; |
always @(posedge i_clk) |
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)) |
if ((i_wb_stb)&&(i_wb_we)) |
{ o_int, o_wb_data } <= { 1'b0, i_wb_data }; |
else if (i_ce) |
{ o_int, o_wb_data } <= o_wb_data+{{(BW-1){1'b0}},1'b1}; |
73,6 → 73,6
|
initial o_wb_ack = 1'b0; |
always @(posedge i_clk) |
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); |
o_wb_ack <= (i_wb_stb); |
assign o_wb_stall = 1'b0; |
endmodule |
/rtl/cpu/zipcpu.v
1866,10 → 1866,53
// DATWR: If write value, produce 4-bits of register ID, 27 bits of value |
// STALL: If neither, produce pipeline stall information |
// ADDR: If bus is valid, no ack, return the bus address |
wire this_write; |
assign this_write = ((mem_valid)||((~clear_pipeline)&&(~alu_illegal) |
&&(((alu_wr)&&(alu_valid)) |
||(div_valid)||(fpu_valid)))); |
reg last_write; |
always @(posedge i_clk) |
last_write <= this_write; |
|
reg [4:0] last_wreg; |
always @(posedge i_clk) |
last_wreg <= wr_reg_id; |
|
reg halt_primed; |
initial halt_primed = 0; |
always @(posedge i_clk) |
if (master_ce) |
halt_primed <= 1'b1; |
else if (debug_trigger) |
halt_primed <= 1'b0; |
|
reg [6:0] halt_count; |
initial halt_count = 0; |
always @(posedge i_clk) |
if ((i_rst)||(!i_halt)||(r_halted)||(!halt_primed)) |
halt_count <= 0; |
else if (!(&halt_count)) |
halt_count <= halt_count + 1'b1; |
|
reg [9:0] mem_counter; |
initial mem_counter = 0; |
always @(posedge i_clk) |
if ((i_rst)||(!halt_primed)||(!mem_busy)) |
mem_counter <= 0; |
else if (!(&mem_counter)) |
mem_counter <= mem_counter + 1'b1; |
|
reg [15:0] long_trigger; |
always @(posedge i_clk) |
long_trigger[15:1] <= long_trigger[14:0]; |
always @(posedge i_clk) |
long_trigger[0] <= ((last_write)&&(last_wreg == wr_reg_id)) |
||(&halt_count)||(&mem_counter); |
|
reg debug_trigger; |
initial debug_trigger = 1'b0; |
always @(posedge i_clk) |
debug_trigger <= (!i_halt)&&(o_break); |
debug_trigger <= (!i_halt)&&(o_break)||(long_trigger == 16'hffff); |
|
wire [31:0] debug_flags; |
assign debug_flags = { debug_trigger, 3'b101, |
1880,7 → 1923,18
op_pipe, alu_ce, alu_busy, alu_wr, |
alu_illegal, alF_wr, mem_ce, mem_we, |
mem_busy, mem_pipe_stalled, (new_pc), (dcd_early_branch) }; |
|
|
wire [25:0] bus_debug; |
assign bus_debug = { debug_trigger, |
mem_ce, mem_we, mem_busy, mem_pipe_stalled, |
o_wb_gbl_cyc, o_wb_gbl_stb, o_wb_lcl_cyc, o_wb_lcl_stb, |
o_wb_we, i_wb_ack, i_wb_stall, i_wb_err, |
pf_cyc, pf_stb, pf_ack, pf_stall, |
pf_err, |
mem_cyc_gbl, mem_stb_gbl, mem_cyc_lcl, mem_stb_lcl, |
mem_we, mem_ack, mem_stall, mem_err |
}; |
|
always @(posedge i_clk) |
begin |
if ((i_halt)||(!master_ce)||(debug_trigger)||(o_break)) |
1896,6 → 1950,7
(o_wb_we)?o_wb_data[26:0] : o_wb_addr[26:0] }; |
else |
o_debug <= debug_flags; |
// o_debug[25:0] <= bus_debug; |
end |
`endif |
|
/rtl/cpu/zipsystem.v
558,7 → 558,7
wire ctri_sel, ctri_stall; |
reg ctri_ack; |
wire [31:0] ctri_data; |
assign ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT); |
assign ctri_sel = (sys_stb)&&(sys_addr == `CTRINT); |
always @(posedge i_clk) |
ctri_ack <= ctri_sel; |
assign ctri_stall = 1'b0; |
662,7 → 662,7
assign pic_stall = 1'b0; |
reg pic_ack; |
always @(posedge i_clk) |
pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL); |
pic_ack <= (sys_stb)&&(sys_addr == `INTCTRL); |
|
// |
// The CPU itself |
812,7 → 812,7
|
assign sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall |
| wdt_stall | ctri_stall | actr_stall |
| pic_stall | dmac_stall); |
| pic_stall | dmac_stall); // Always 1'b0! |
assign cpu_stall = (sys_stall)|(cpu_ext_stall); |
assign sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack); |
assign cpu_ack = (sys_ack)||(cpu_ext_ack); |
rtl/cpu
Property changes :
Added: svn:ignore
## -0,0 +1,3 ##
+pipefetch.m
+.gitignore
+.*.swp
Index: rtl/wbm2axisp.v
===================================================================
--- rtl/wbm2axisp.v (revision 31)
+++ rtl/wbm2axisp.v (revision 32)
@@ -319,11 +319,23 @@
end
end
+ //
+ // The debug wires are set up for a 6-bit ID. In hind sight,
+ // I only ever needed 5-bit ID's. Hence, let's expand those
+ // five bit ID's for 6-bits so we can still fit nicely into
+ // our 32-bit words.
+ //
+ wire [5:0] six_head, six_tail, six_rid, six_bid;
+ assign six_head = {{(6-LGFIFOLN){1'b0}}, fifo_head };
+ assign six_tail = {{(6-LGFIFOLN){1'b0}}, fifo_tail };
+ assign six_rid = {{(6-LGFIFOLN){1'b0}}, i_axi_rid };
+ assign six_bid = {{(6-LGFIFOLN){1'b0}}, i_axi_bid };
+
assign o_dbg = {
i_wb_stb, o_wb_stall, o_wb_ack, o_wb_err,
- fifo_head, fifo_tail, // 12 bits
- { ((i_axi_rvalid)&&(o_axi_rready)) ? i_axi_rid
- : ((i_axi_bvalid)&&(o_axi_bready)) ? i_axi_bid
+ six_head, six_tail, // 12 bits
+ { ((i_axi_rvalid)&&(o_axi_rready)) ? six_rid
+ : ((i_axi_bvalid)&&(o_axi_bready)) ? six_bid
: 6'hf }, // 6 bits
o_axi_arvalid, i_axi_arready,
o_axi_awvalid, i_axi_awready,
rtl
Property changes :
Added: svn:ignore
## -0,0 +1,11 ##
+.gitignore
+builddate.v
+cpu/fastcache.v
+cpu/fastops.v
+cpu/ifastdec.v
+cpu/zipcpuhs.v
+qspi-notes.txt
+fastscope-broken.v
+debug.txt
+obj_dir
+.*.swp
Index: sw/board/artyboard.h
===================================================================
--- sw/board/artyboard.h (revision 31)
+++ sw/board/artyboard.h (revision 32)
@@ -134,12 +134,12 @@
volatile unsigned io_btnsw;
volatile unsigned io_ledctrl;
volatile unsigned io_auxsetup, io_gpssetup;
- unsigned io_reserved[32-18];
volatile unsigned io_clrled[4];
volatile unsigned io_rtcdate;
volatile unsigned io_gpio;
volatile unsigned io_uart_rx, io_uart_tx;
volatile unsigned io_gps_rx, io_gps_tx;
+ unsigned io_reserved[32-18];
SCOPE io_scope[4];
RTC io_rtc;
SDCARD io_sd;
Index: sw/board/exstartup.c
===================================================================
--- sw/board/exstartup.c (revision 31)
+++ sw/board/exstartup.c (revision 32)
@@ -124,50 +124,45 @@
;
// Repeating timer, every 250ms
- // zip->tma = (second/4) | 0x80000000;
- zip->tma = 1024 | 0x80000000;
+ zip->tma = (second/4) | 0x80000000;
+ // zip->tma = 1024 | 0x80000000;
// Restart the PIC -- listening for SYSINT_TMA only
- zip->pic = SYSINT_TMA;
zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
zip_rtu();
+ zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
sys->io_clrled[0] = green;
sys->io_ledctrl = 0x010;
- zip->pic = SYSINT_TMA;
+ zip_rtu();
zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
- zip_rtu();
sys->io_clrled[0] = dimgreen;
sys->io_clrled[1] = green;
- sys->io_scope[0].s_ctrl = 32 | SCOPE_TRIGGER;
+ sys->io_scope[0].s_ctrl = 32 | 0x80000000; // SCOPE_TRIGGER;
sys->io_ledctrl = 0x020;
- zip->pic = SYSINT_TMA;
+ zip_rtu();
zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
- zip_rtu();
sys->io_clrled[1] = dimgreen;
sys->io_clrled[2] = green;
sys->io_ledctrl = 0x040;
- zip->pic = SYSINT_TMA;
- zip->pic = EINT(SYSINT_TMA);
zip_rtu();
+ zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
sys->io_clrled[2] = dimgreen;
sys->io_clrled[3] = green;
sys->io_ledctrl = 0x080;
- zip->pic = SYSINT_TMA;
- zip->pic = EINT(SYSINT_TMA);
zip_rtu();
+ zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
sys->io_clrled[3] = dimgreen;
- zip->pic = SYSINT_TMA;
- zip->pic = EINT(SYSINT_TMA);
zip_rtu();
+ zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
for(i=0; i<4; i++)
sys->io_clrled[i] = black;
@@ -174,9 +169,8 @@
// Wait one second ...
for(i=0; i<4; i++) {
- zip->pic = SYSINT_TMA;
- zip->pic = EINT(SYSINT_TMA);
zip_rtu();
+ zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
}
sw = sys->io_btnsw & 0x0f;
@@ -186,9 +180,8 @@
// Wait another two second ...
for(i=0; i<8; i++) {
- zip->pic = SYSINT_TMA;
- zip->pic = EINT(SYSINT_TMA);
zip_rtu();
+ zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
}
// Blink all the LEDs
@@ -195,15 +188,13 @@
// First turn them on
sys->io_ledctrl = 0x0ff;
// Then wait a quarter second
- zip->pic = SYSINT_TMA;
+ zip_rtu();
zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
- zip_rtu();
// Then turn the back off
sys->io_ledctrl = 0x0f0;
// and wait another quarter second
- zip->pic = SYSINT_TMA;
+ zip_rtu();
zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
- zip_rtu();
// Now, read buttons, and flash an LED on any button being held
// down ... ? neat?
@@ -212,18 +203,19 @@
while(1) {
unsigned btn, ledc;
- zip->pic = SYSINT_TMA;
- zip->pic = EINT(SYSINT_TMA);
zip_rtu();
+ zip->pic = EINT(SYSINT_TMA)|SYSINT_TMA;
// If the button is pressed, toggle the LED
// Otherwise, turn the LED off.
//
// First, get all the pressed buttons
btn = (sys->io_btnsw >> 4) & 0x0f;
- sys->io_btnsw = 0x0f0;
+ // Now, acknowledge the button presses that we just read
+ sys->io_btnsw = (btn<<4);
// Of any LEDs that are on, or buttons on, toggle their values
- ledc = (sys->io_ledctrl | btn)&0x0f;
+ ledc = (sys->io_ledctrl)&0x0f;
+ ledc = (ledc | btn)&0x0f ^ ledc;
// Make sure we set everything
ledc |= 0x0f0;
// Now issue the command
sw/board
Property changes :
Added: svn:ignore
## -0,0 +1,6 ##
+dump.txt
+exstartup
+exstartup.map
+exstartup.txt
+.gitignore
+.*.swp
Index: sw/host/portbus.cpp
===================================================================
--- sw/host/portbus.cpp (revision 31)
+++ sw/host/portbus.cpp (nonexistent)
@@ -1,665 +0,0 @@
-//
-//
-// Filename: portbus.cpp
-//
-// Project: UART to WISHBONE FPGA library
-//
-// Purpose: This is the C++ program on the command side that will interact
-// with a UART on an FPGA, to command the WISHBONE on that same
-// FPGA to ... whatever we wish to command it to do.
-//
-// This code does not run on an FPGA, is not a test bench, neither
-// is it a simulator. It is a portion of a command program
-// for commanding an FPGA.
-//
-// Creator: Dan Gisselquist
-// Gisselquist Tecnology, LLC
-//
-// Copyright: 2015
-//
-//
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "portbus.h"
-
-char PORTBUS::charenc(const int sixbitval) {
- if (sixbitval < 10)
- return '0' + sixbitval;
- else if (sixbitval < 10+26)
- return 'A' - 10 + sixbitval;
- else if (sixbitval < 10+26+26)
- return 'a' - 10 - 26 + sixbitval;
- else if (sixbitval == 0x3e)
- return '@';
- else if (sixbitval == 0x3f)
- return '%';
-
- fprintf(stderr, "SIXBITVAL isn\'t!!!! sixbitval = %08x\n", sixbitval);
- assert((sixbitval & (~0x03f))==0);
- return 0;
-}
-
-unsigned PORTBUS::chardec(const char b) {
- if ((b >= '0')&&(b <= '9'))
- return b-'0';
- else if ((b >= 'A')&&(b <= 'Z'))
- return b-'A'+10;
- else if ((b >= 'a')&&(b <= 'z'))
- return b-'a'+36;
- else if (b == '@')
- return 0x03e;
- else if (b == '%')
- return 0x03f;
- else
- return 0x0100; // ERR -- invalid code
-}
-
-int PORTBUS::lclread(char *buf, int len) {
- int nr;
- nr = m_dev->read(buf, len);
-
- if (false) {
- // if (nr > 0)
- // printf("READ %d bytes (%5x:%5x), req %d, raw %d\n", nr, m_rdfirst, m_rdlast, rq, rnr);
- for(int i=0; i= len))
- return;
- if (m_buf)
- delete[] m_buf;
- m_buflen = (len&(-0x3f))+0x40;
- m_buf = new char[m_buflen];
-}
-
-void PORTBUS::encode(const int hb, const BUSW val, char *buf) {
- buf[0] = charenc( (hb<<2)|((val>>30)&0x03) );
- buf[1] = charenc( (val>>24)&0x3f);
- buf[2] = charenc( (val>>18)&0x3f);
- buf[3] = charenc( (val>>12)&0x3f);
- buf[4] = charenc( (val>> 6)&0x3f);
- buf[5] = charenc( (val )&0x3f);
-}
-
-unsigned PORTBUS::decodestr(const char *buf) {
- unsigned r;
-
- r = chardec(buf[0]) & 0x03;
- r = (r<<6) | (chardec(buf[1]) & 0x03f);
- r = (r<<6) | (chardec(buf[2]) & 0x03f);
- r = (r<<6) | (chardec(buf[3]) & 0x03f);
- r = (r<<6) | (chardec(buf[4]) & 0x03f);
- r = (r<<6) | (chardec(buf[5]) & 0x03f);
-
- return r;
-}
-
-int PORTBUS::decodehex(const char hx) {
- if ((hx >= '0')&&(hx <= '9'))
- return hx-'0';
- else if ((hx >= 'A')&&(hx <= 'Z'))
- return hx-'A'+10;
- else if ((hx >= 'a')&&(hx <= 'z'))
- return hx-'a'+10;
- else
- return 0;
-}
-
-void PORTBUS::writeio(const BUSW a, const BUSW v) {
- if (a == m_lastaddr) {
- encode(1, v, &m_buf[0]);
- m_buf[6] = '\n';
- m_buf[7] = '\0';
- m_dev->write(m_buf, 7);
- } else if (a == (m_lastaddr + 1)) {
- if ((v >= 0)&&(v <= 255)) {
- encode(3, v<<24, &m_buf[0]);
- m_buf[2] = '\n';
- m_buf[3] = '\0';
- m_dev->write(m_buf, 3);
- } else {
- encode(2, v, &m_buf[0]);
- m_buf[6] = '\n';
- m_buf[7] = '\0';
- m_dev->write(m_buf, 7);
- }
- } else { // Gotta do this the hard way
- // printf("WRITEIO--HARD(%08x, %08x)\n", a, v);
- encode(0, a, &m_buf[0]);
- encode(0, v, &m_buf[6]);
- m_buf[12] = '\n';
- m_buf[13] = '\0';
- m_dev->write(m_buf, 12);
- }
-
- m_lastaddr = a; m_addr_set = true;
-}
-
-void PORTBUS::writev(const BUSW a, const int p, const int len, const BUSW *buf) {
- int ci;
-
- // Allocate a buffer of six bytes per word, one for addr, plus six more
- bufalloc((len+2)*6);
-
- // Encode the address
- encode(0, a, &m_buf[0]); ci = 6; m_lastaddr = a; m_addr_set = true;
- // Now all but the last of the data
- for(int i=0; iwrite(m_buf, ci-1);
-}
-
-void PORTBUS::writez(const BUSW a, const int len, const BUSW *buf) {
- writev(a, 1, len, buf);
-}
-
-void PORTBUS::writei(const BUSW a, const int len, const BUSW *buf) {
- writev(a, 2, len, buf);
-}
-
-PORTBUS::BUSW PORTBUS::readio(const PORTBUS::BUSW a) {
- m_bus_err = false;
- // printf("READIO(0x%08x, last = %08x)\n", a, m_lastaddr);
- if ((m_lastaddr == a)&&(m_addr_set)) {
- m_buf[0] = charenc(0x05<<2);
- m_buf[1] = '\n';
- m_buf[2] = '\0';
- m_dev->write(m_buf, 2);
- } else if (((m_lastaddr+1) == a)&&(m_addr_set)) {
- m_buf[0] = charenc((0x05<<2)+1);
- m_buf[1] = '\n';
- m_buf[2] = '\0';
- m_dev->write(m_buf, 2);
- } else if ((m_lastaddr+255 >= a)&&(m_lastaddr-256 <= a)&&(m_addr_set)) {
- int offset;
-
- // m_lastaddr + offset = a
- // offset = a - m_lastaddr
- offset = (a - m_lastaddr) & 0x1ff;
- m_buf[0] = charenc((3<<3)|((offset>>6)&0x07));
- m_buf[1] = charenc(offset & 0x03f);
- m_buf[2] = '\n';
- m_buf[3] = '\0';
- m_dev->write(m_buf, 3);
- } else { // Do this the hard way
- encode(4, a, m_buf);
- m_buf[ 6] = '\n';
- m_buf[ 7] = '\0';
- m_dev->write(m_buf, 7);
- }
-
- // Read I/O is never a vector read, so we skip that here
- BUSW v;
-
- try {
- v = readword();
- } catch(BUSERR b) {
- throw BUSERR(a);
- }
-
- if ((m_lastaddr != a)&&(m_addr_set)) {
- printf("LAST-ADDR MIS-MATCH: (RCVD) %08x != %08x (XPECTED)\n", m_lastaddr, a);
- m_addr_set = false;
-
- exit(-3);
- } else {
- m_lastaddr = a; m_addr_set = true;
- }
-
- return v;
-}
-
-void PORTBUS::readv(const PORTBUS::BUSW a, const int inc, const int len, PORTBUS::BUSW *buf) {
- int nxtln = len;
- PORTBUS::BUSW addr = a;
- char *ptr;
-
- if (len <= 0)
- return;
-
- // printf("READV(%08x,+%d,%d,&buf)\n", a, inc, len);
-
- // bufalloc(6+10);
-
- // printf("READV[0x%08x]->0x%08x\n", a, a+inc*len);
- if (true) { // ((m_lastaddr != addr)||(!m_addr_set)) {
- encode(4, addr, m_buf);
- ptr = &m_buf[6];
- nxtln = len - 1;
- if (nxtln <= 0) {
- *ptr++ = '\n';
- *ptr++ = '\0';
- m_dev->write(m_buf, 7);
- buf[0] = readword();
- return;
- }
-
- addr += inc;
- } else {
- // We still need to issue a read command, but this time from
- // this address. Otherwise we'll bomb the vector read by
- // incrementing before reading.
- m_buf[0] = charenc(0x05<<2);
- ptr = &m_buf[1];
- if (nxtln <= 0) {
- *ptr++ = '\n';
- *ptr++ = '\0';
- m_dev->write(m_buf, 7);
- buf[0] = readword();
- return;
- }
- }
-
- // printf(" ... READV(%08x,+%d,%d,&buf)\n", addr, inc, nxtln);
-
- nxtln &= 0x03ff;
- *ptr++ = charenc(0x20+((inc)?0x10:0)+((nxtln>>6)&0x0f));
- *ptr++ = charenc(nxtln & 0x03f);
- *ptr++ = '\n'; *ptr = '\0';
- m_dev->write(m_buf, (ptr-m_buf));
-
- for(int i=0; i MAXLN) {
- readv(addr, 1, MAXLN, bptr); printf("#"); fflush(stdout);
- bptr += MAXLN;
- ln -= MAXLN;
- addr += MAXLN;
- } if (ln > 0)
- readv(addr, 1, ln, bptr);
-}
-
-void PORTBUS::readz(const PORTBUS::BUSW a, const int len, PORTBUS::BUSW *buf) {
- int MAXLN = 1023;
- int ln = len;
- PORTBUS::BUSW *bptr = buf;
-
- while(ln > MAXLN) {
- readv(a, 0, MAXLN, bptr);
- bptr += MAXLN;
- ln -= MAXLN;
- } if (ln > 0)
- readv(a, 0, ln, bptr);
-}
-
-PORTBUS::BUSW PORTBUS::readword(void) {
- PORTBUS::BUSW val = 0;
- int nr;
- unsigned sixbits;
-
-
- // printf("READ-WORD()\n");
-
- bool found_start = false;
- do {
- // Blocking read (for now)
- do {
- nr = lclreadcode(&m_buf[0], 1);
- } while (nr < 1);
-
- sixbits = chardec(m_buf[0]);
-
- if (m_buf[0] == 'I')
- m_interrupt_flag = true;
- else if (m_buf[0] == 'E') {
- m_bus_err = true;
- throw BUSERR(0);
- } else if (m_buf[0] == 'R') {
- m_bus_err = true;
- throw BUSERR(0);
- } else if (m_buf[0] == 'B') { // Bus is still busy
- ; // printf("BUSY\n");
- } else if (m_buf[0] == 'Q') { // Transaction abandoned
- ; // printf("BUSY\n");
- //
- // We could fail our transaction here, but ...
- // what if the 'Q' was in the 'Q' from before our
- // read command? Reading it doesn't mean there's
- // anything wrong, just that time has passed.
- //
- // m_bus_err = true;
- // printf("\nTRANSACTION FAILURE!\n");
- // exit(-3);
- // return 0;
- } else if (sixbits&(~0x03f))
- // Ignore new lines, unprintables, and characters
- // not a part of our code
- ;
- else if (0 == (sixbits & 0x38)) {
- // A 'W' ... adjust our known address ... NOT
- // We adjust our address automatically at the end
- // of the write command, not based upon what write
- // response gets read from the port--those are just
- // bonus.
- //
- // if (sixbits == 0x04)
- // m_addr_set = false;
- // else if (sixbits & 0x04)
- // m_lastaddr += (-1<<2)|(sixbits&0x03);
- // else m_lastaddr += (sixbits & 0x03);
- } else if (0x20 == sixbits) { // Legacy 'W')
- ; // m_addr_set = false;
- } else if (0x0c == (sixbits & 0x03e)) {
- found_start = true;
- } else if (0x01c == (sixbits & 0x03e)) {
- found_start = true;
- } else if (0x20 & sixbits) {
- found_start = true;
- } else if (0x1f == sixbits) { // Legacy 'V')
- printf("Found a legacy read word\n");
- exit(-1);
- } else if (0x14 == (sixbits & 0x3c)) {
- found_start = true;
- }
- } while(!found_start);
-
- if (m_buf[0] == 'V') {
- //
- // LEGACY READ
- //
- // Read the flag and the data word, but not the newline
- nr = 0;
- do {
- nr += lclread(&m_buf[1+nr], 10-nr);
- } while(nr < 10);
- m_buf[1+10] = '\0';
- if (m_buf[6] != ':')
- m_decode_err = true;
- val = 0;
- for(int i=0; i<4; i++)
- val = (val << 4) | decodehex(m_buf[2+i]);
- for(int i=0; i<4; i++)
- val = (val << 4) | decodehex(m_buf[7+i]);
- m_buf[11] = '\0';
- // printf("DEC: %11s --> %08x\n", m_buf, val);
-
- if (m_buf[1] == 'x') {
- // The address of this read follows, suck in the newline as well
- nr = 0;
- do {
- nr += lclread(&m_buf[11+nr], 4+8+2-nr);
- } while(nr < 4+8+1);
-
- m_buf[11+4+8+1] = '\0';
-
- if (m_buf[17] != ':')
- m_decode_err = true;
- m_lastaddr = 0;
- for(int i=0; i<4; i++)
- m_lastaddr = (m_lastaddr << 4) | decodehex(m_buf[13+i]);
- for(int i=0; i<4; i++)
- m_lastaddr = (m_lastaddr << 4) | decodehex(m_buf[18+i]);
- m_addr_set = true;
- // printf("READ-ADDR = %08x\n", m_lastaddr);
- } else {
- // Read the end of line, so thus ready for another
- lclread(&m_buf[11], 1);
- m_buf[12] = '\n'; m_buf[13] = '\0';
-
- if (m_buf[1] == '+')
- m_lastaddr += 1;
- }
- } else if (0x14 == (sixbits & 0x3c)) { // 'N'
- // Passes, for a read of zero
- m_lastaddr = 0; m_addr_set = true;
- do {
- nr += lclreadcode(&m_buf[nr], 6-nr);
- } while (nr < 6);
- val = decodestr(m_buf);
- } else if (0x0c == (sixbits & 0x3e)) { // Vx {1,Addr}, Data
- do {
- nr += lclreadcode(&m_buf[nr], 12-nr);
- } while (nr < 12);
- m_lastaddr = decodestr(m_buf);
- m_lastaddr |= 0x80000000;
- val = decodestr(&m_buf[6]);
- printf("Vx: Read a %08x from %08x\n", val, m_lastaddr);
- // Can't test--don't have negative addresses in my design
- } else if (0x1c == (sixbits & 0x3e)) { // Vx {0,Addr}, Data
- do {
- nr += lclreadcode(&m_buf[nr], 12-nr);
- } while (nr < 12);
- m_lastaddr = decodestr(m_buf);
- val = decodestr(&m_buf[6]);
- // S0006000D%
- // Vx Addr = 6, Data = Da(a) = 6'hD,6'h24
- // Data = 001101 100100
- // Data = 011 0110 0100
- // Data = 0x364 = 878
- // = DFFF = 57343
- // printf("Vx(%c%c%c%c%c%c,%c%c%c%c%c%c): Read a %08x from %08x\n",
- // m_buf[0], m_buf[1], m_buf[2], m_buf[3], m_buf[4], m_buf[5],
- // m_buf[6], m_buf[7], m_buf[8], m_buf[9], m_buf[10], m_buf[11],
- // val, m_lastaddr);
- // PASSES!
- } else if (0x20 == (sixbits & 0x30)) { // V+ {2-bit offset}, Data
- do {
- nr += lclreadcode(&m_buf[nr], 6-nr);
- } while (nr < 6);
- if (0x04 == (sixbits & 0x0c)) {
- m_lastaddr--;
- } else if (0x08 == (sixbits & 0x0c)) {
- ; // m_lastaddr = m_lastaddr
- } else if (0x0c == (sixbits & 0x0c)) {
- m_lastaddr++;
- }
- val = decodestr(&m_buf[0]);
- // printf("V++(%c%c%c%c%c%c,%02x): Read a %08x from %08x\n",
- // m_buf[0], m_buf[1], m_buf[2], m_buf[3], m_buf[4], m_buf[5],
- // sixbits,
- // val, m_lastaddr);
- // Passes!
- } else if (0x30 == (sixbits & 0x30)) { // V+ {6-bit offset}, Data
- do {
- nr += lclreadcode(&m_buf[nr], 7-nr);
- } while(nr < 7);
- if (sixbits&0x08) { // Sign extension necessary
- m_lastaddr += (-1<<8)+((sixbits<<4)&0xf0)
- +((chardec(m_buf[1])&0x3c)>>2);
- } else {
- m_lastaddr += ((sixbits<<4)&0x0f0)
- +((chardec(m_buf[1])&0x3c)>>2);
- }
- val = decodestr(&m_buf[1]);
- // printf("V+8(%c%c%c%c%c%c%c,%02x): Read a %08x from %08x\n",
- // m_buf[0], m_buf[1], m_buf[2], m_buf[3], m_buf[4], m_buf[5], m_buf[6],
- // sixbits,
- // val, m_lastaddr);
- // PASSES!
- } else {
- fprintf(stderr, "CANT DECODE %c, SIXBITS = %02x!!!!\n",
- m_buf[0], sixbits);
- exit(-1);
- }
-
-
- // printf("RDWORD %s\n", m_buf);
- return val;
-}
-
-#ifdef LEGACY_READWORD
-PORTBUS::BUSW PORTBUS::legacy_readword(void) {
- PORTBUS::BUSW val = 0;
- int nr;
-
- // printf("READ-WORD()\n");
-
- do {
- // Blocking read (for now)
- do {
- nr = lclread(&m_buf[0], 1);
- } while (nr < 1);
-
- if (m_buf[0] == 'I')
- m_interrupt_flag = true;
- else if (m_buf[0] == 'E') {
- m_bus_err = true;
- throw BUSERR(0);
- return 0;
- } else if (m_buf[0] == 'Q') // Bus is still busy
- ; // printf("BUSY\n");
- else if (m_buf[0] == '\n') // Ignore new lines
- ;
- else if (m_buf[0] == '\r') // Ignore carriage returns
- ;
- } while(m_buf[0] != 'V');
-
- // Read the flag and the data word, but not the newline
- nr = 0;
- do {
- nr += lclread(&m_buf[1+nr], 10-nr);
- } while(nr < 10);
- m_buf[1+10] = '\0';
- if (m_buf[6] != ':')
- m_decode_err = true;
- val = 0;
- for(int i=0; i<4; i++)
- val = (val << 4) | decodehex(m_buf[2+i]);
- for(int i=0; i<4; i++)
- val = (val << 4) | decodehex(m_buf[7+i]);
- m_buf[11] = '\0';
- // printf("DEC: %11s --> %08x\n", m_buf, val);
-
- if (m_buf[1] == 'x') {
- // The address of this read follows, suck in the newline as well
- nr = 0;
- do {
- nr += lclread(&m_buf[11+nr], 4+8+2-nr);
- } while(nr < 4+8+1);
-
- m_buf[11+4+8+1] = '\0';
-
- if (m_buf[17] != ':')
- m_decode_err = true;
- m_lastaddr = 0;
- for(int i=0; i<4; i++)
- m_lastaddr = (m_lastaddr << 4) | decodehex(m_buf[13+i]);
- for(int i=0; i<4; i++)
- m_lastaddr = (m_lastaddr << 4) | decodehex(m_buf[18+i]);
- m_addr_set = true;
- // printf("READ-ADDR = %08x\n", m_lastaddr);
- } else {
- // Read the end of line, so thus ready for another
- lclread(&m_buf[11], 1);
- m_buf[12] = '\n'; m_buf[13] = '\0';
-
- if (m_buf[1] == '+')
- m_lastaddr += 1;
- }
-
- // printf("RDWORD %s\n", m_buf);
- return val;
-}
-#endif
-
-void PORTBUS::usleep(unsigned ms) {
- if (m_dev->poll(ms)) {
- int nr;
- nr = lclread(m_buf, 16);
- if (nr == 0) {
- // Connection closed, let it drop
- printf("Connection closed!!\n");
- m_dev->close();
- exit(-1);
- } for(int i=0; i 0)&&(isprint(m_buf[0]))&&(!isspace(m_buf[0])))
- // printf("RCVD: \'%c\'\n", m_buf[0]);
- usleep(200);
- } while(!m_interrupt_flag);
- // m_interrupt_flag = true;
-}
-
Index: sw/host/portbus.h
===================================================================
--- sw/host/portbus.h (revision 31)
+++ sw/host/portbus.h (nonexistent)
@@ -1,92 +0,0 @@
-//
-//
-// Filename: portbus.h
-//
-// Project: UART to WISHBONE FPGA library
-//
-// Purpose: This is the C++ program on the command side that will interact
-// with a UART on an FPGA, to command the WISHBONE on that same
-// FPGA to ... whatever we wish to command it to do.
-//
-// This code does not run on an FPGA, is not a test bench, neither
-// is it a simulator. It is a portion of a command program
-// for commanding an FPGA.
-//
-// Creator: Dan Gisselquist
-// Gisselquist Tecnology, LLC
-//
-// Copyright: 2015
-//
-//
-#ifndef PORTBUS_H
-#define PORTBUS_H
-
-#include
-#include "llcomms.h"
-#include "devbus.h"
-
-typedef unsigned int uint32;
-
-#define RDBUFLN 2048
-
-class PORTBUS : public DEVBUS {
-public:
- unsigned long m_total_nread;
-private:
- LLCOMMSI *m_dev;
- bool m_interrupt_flag, m_decode_err, m_addr_set, m_bus_err;
- unsigned int m_lastaddr;
-
- int m_buflen, m_rdfirst, m_rdlast;
- char *m_buf, *m_rdbuf;
-
- void init(void) {
- m_interrupt_flag = false;
- m_buflen = 0; m_buf = NULL;
- m_addr_set = false;
- bufalloc(64);
- m_bus_err = false;
- m_decode_err = false;
-
- m_rdfirst = m_rdlast = 0;
- m_rdbuf = new char[RDBUFLN];
- m_total_nread = 0l;
- }
-
- char charenc(const int sixbitval);
- unsigned chardec(const char b);
- void encode(const int fbits, const BUSW v, char *buf);
- unsigned decodestr(const char *buf);
- int decodehex(const char hx);
- void bufalloc(int len);
- BUSW readword(void); // Reads a word value from the bus
- void readv(const BUSW a, const int inc, const int len, BUSW *buf);
- void writev(const BUSW a, const int p, const int len, const BUSW *buf);
-
- int lclread(char *buf, int len);
- int lclreadcode(char *buf, int len);
-public:
- PORTBUS(void) { init(); }
- PORTBUS(LLCOMMSI *comms) : m_dev(comms) { init(); }
- ~PORTBUS(void) { m_dev->close();
- if (m_buf) delete[] m_buf; m_buf = NULL; }
-
- void kill(void) { m_dev->close(); }
- void open(const char *dev);
- void open(const char *host, const int port);
- void close(void) { m_dev->close(); }
- void writeio(const BUSW a, const BUSW v);
- BUSW readio(const BUSW a);
- void readi(const BUSW a, const int len, BUSW *buf);
- void readz(const BUSW a, const int len, BUSW *buf);
- void writei(const BUSW a, const int len, const BUSW *buf);
- void writez(const BUSW a, const int len, const BUSW *buf);
- bool poll(void) { return m_interrupt_flag; };
- void usleep(unsigned msec); // Sleep until interrupt
- void wait(void); // Sleep until interrupt
- bool bus_err(void) const { return m_bus_err; };
- void reset_err(void) { m_bus_err = false; }
- void clear(void) { m_interrupt_flag = false; }
-};
-
-#endif
Index: sw/host/cpuscope.cpp
===================================================================
--- sw/host/cpuscope.cpp (revision 31)
+++ sw/host/cpuscope.cpp (revision 32)
@@ -74,6 +74,7 @@
printf("TRIG ");
else
printf(" ");
+ if (true) {
if ((val & 0x40000000)==0) {
printf("%s <- 0x.%08x", regstr[(val>>32-6)&0xf], val&0x03ffffff);
} else if ((val & 0x60000000)==0x60000000) {
@@ -144,6 +145,65 @@
if (memwe) printf(" MEM-WE");
if (membsy) printf(" MEM-BUSY");
//
+ }}
+
+ if (false) {
+ // CPU internal bus_debug
+ int mce, mwe, mbsy, mpip,
+ gcyc, gstb, lcyc, lstb, we, ack, stall, err,
+ pcyc, pstb, pack, pstall, perr,
+ mcycg, mstbg, mcycl, mstbl, mack, mstall, merr;
+
+ mce = (val>>24)&1;
+ //
+ mbsy = (val>>22)&1;
+ mpip = (val>>21)&1;
+ gcyc = (val>>20)&1;
+ gstb = (val>>19)&1;
+ lcyc = (val>>18)&1;
+ lstb = (val>>17)&1;
+ we = (val>>16)&1;
+ ack = (val>>15)&1;
+ stall = (val>>14)&1;
+ err = (val>>13)&1;
+ pcyc = (val>>12)&1;
+ pstb = (val>>11)&1;
+ pack = (val>>10)&1;
+ pstall = (val>> 9)&1;
+ perr = (val>> 8)&1;
+ mcycg = (val>> 7)&1;
+ mstbg = (val>> 6)&1;
+ mcycl = (val>> 5)&1;
+ mstbl = (val>> 4)&1;
+ mwe = (val>> 3)&1;
+ mack = (val>> 2)&1;
+ mstall = (val>> 1)&1;
+ merr = (val&1);
+
+ printf("P[%s%s%s%s%s]",
+ (pcyc)?"C":" ",
+ (pstb)?"S":" ",
+ (pack)?"A":" ",
+ (pstall)?"S":" ",
+ (perr)?"E":" ");
+
+ printf("M[(%s%s)(%s%s)%s%s%s%s]",
+ (mcycg)?"C":" ", (mstbg)?"S":" ",
+ (mcycl)?"C":" ", (mstbl)?"S":" ",
+ (mwe)?"W":"R", (mack)?"A":" ",
+ (mstall)?"S":" ",
+ (merr)?"E":" ");
+
+ printf("O[(%s%s)(%s%s)%s%s%s%s]",
+ (gcyc)?"C":" ", (gstb)?"S":" ",
+ (lcyc)?"C":" ", (lstb)?"S":" ",
+ (we)?"W":"R", (ack)?"A":" ",
+ (stall)?"S":" ",
+ (err)?"E":" ");
+
+ if (mbsy) printf("M-BUSY ");
+ if (mpip) printf("M-PIPE ");
+ if (mce) printf("M-CE ");
}
}
};
Index: sw/host/flashdrvr.cpp
===================================================================
--- sw/host/flashdrvr.cpp (revision 31)
+++ sw/host/flashdrvr.cpp (revision 32)
@@ -167,7 +167,7 @@
bool FLASHDRVR::verify_config(void) {
unsigned cfg = m_fpga->readio(R_QSPI_VCONF);
- printf("CFG = %02x\n", cfg);
+ // printf("CFG = %02x\n", cfg);
return (cfg == VCONF_VALUE);
}
/sw/host/ttybus.cpp
49,7 → 49,7
const unsigned TTYBUS::MAXWRLEN = 32; |
|
// #define DBGPRINTF printf |
#define DBGPRINTF filedump |
// #define DBGPRINTF filedump |
#ifndef DBGPRINTF |
#define DBGPRINTF null |
#else |
sw/host
Property changes :
Added: svn:ignore
## -0,0 +1,35 ##
+cfgscope
+cpuscope
+crctest
+dbg.txt
+dbg2.txt
+debug.txt
+dumpflash
+eqspiscope
+eqspidump-original.bin
+eqspidump.bin
+erxscope
+etxscope
+genoimage
+genoimage.cpp
+manping
+mdioscope
+mtee.txt
+mtest
+netsetup
+netuart
+obj-pc
+scopout
+scopout.txt
+scopout2.txt
+sdramscope
+tags
+wbprogram
+wbregs
+wbsettime
+wbuscope
+zipdbg
+zipload
+zipstate
+.gitignore
+.*.swp
Index: sw
===================================================================
--- sw (revision 31)
+++ sw (revision 32)
sw
Property changes :
Added: svn:ignore
## -0,0 +1,4 ##
+debug.txt
+eqspidump.bin
+.gitignore
+.*.swp
Index: .
===================================================================
--- . (revision 31)
+++ . (revision 32)
.
Property changes :
Added: svn:ignore
## -0,0 +1 ##
+2*-arty.tjz