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+\documentclass[11pt]{article}
+
+\title{GNU GENERAL PUBLIC LICENSE}
+\date{Version 3, 29 June 2007}
+
+\begin{document}
+\maketitle
+
+\begin{center}
+{\parindent 0in
+
+Copyright \copyright\ 2007 Free Software Foundation, Inc. \texttt{http://fsf.org/}
+
+\bigskip
+Everyone is permitted to copy and distribute verbatim copies of this
+
+license document, but changing it is not allowed.}
+
+\end{center}
+
+\renewcommand{\abstractname}{Preamble}
+\begin{abstract}
+The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works. By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users. We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors. You can apply it to
+your programs, too.
+
+When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
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+free programs, and that you know you can do these things.
+
+To protect your rights, we need to prevent others from denying you
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+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+For example, if you distribute copies of such a program, whether
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+or can get the source code. And you must show them these terms so they
+know their rights.
+
+Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+For the developers' and authors' protection, the GPL clearly explains
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+authors' sake, the GPL requires that modified versions be marked as
+changed, so that their problems will not be attributed erroneously to
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+
+Some devices are designed to deny users access to install or run
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+
+Finally, every program is threatened constantly by software patents.
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+patents cannot be used to render the program non-free.
+
+The precise terms and conditions for copying, distribution and
+modification follow.
+\end{abstract}
+
+\begin{center}
+{\Large \sc Terms and Conditions}
+\end{center}
+
+
+\begin{enumerate}
+
+\addtocounter{enumi}{-1}
+
+\item Definitions.
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+``This License'' refers to version 3 of the GNU General Public License.
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+ COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM ``AS IS''
+ WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED,
+ INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE
+ RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.
+ SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL
+ NECESSARY SERVICING, REPAIR OR CORRECTION.
+\end{sloppypar}
+
+\item Limitation of Liability.
+
+ IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
+ WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES
+ AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR
+ DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
+ DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM
+ (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED
+ INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE
+ OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH
+ HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ DAMAGES.
+
+\item Interpretation of Sections 15 and 16.
+
+If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+\begin{center}
+{\Large\sc End of Terms and Conditions}
+
+\bigskip
+How to Apply These Terms to Your New Programs
+\end{center}
+
+If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the ``copyright'' line and a pointer to where the full notice is found.
+
+{\footnotesize
+\begin{verbatim}
+
+
+Copyright (C)
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see Copyright (C)
+
+This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+\end{verbatim}
+}
+
+The hypothetical commands {\tt show w} and {\tt show c} should show
+the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an ``about box''.
+
+You should also get your employer (if you work as a programmer) or
+school, if any, to sign a ``copyright disclaimer'' for the program, if
+necessary. For more information on this, and how to apply and follow
+the GNU GPL, see \texttt{http://www.gnu.org/licenses/}.
+
+The GNU General Public License does not permit incorporating your
+program into proprietary programs. If your program is a subroutine
+library, you may consider it more useful to permit linking proprietary
+applications with the library. If this is what you want to do, use
+the GNU Lesser General Public License instead of this License. But
+first, please read \texttt{http://www.gnu.org/philosophy/why-not-lgpl.html}.
+
+\end{enumerate}
+
+\end{document}
Index: trunk/doc/src/GT.eps
===================================================================
--- trunk/doc/src/GT.eps (nonexistent)
+++ trunk/doc/src/GT.eps (revision 2)
@@ -0,0 +1,94 @@
+%!PS-Adobe-3.0 EPSF-3.0
+%%BoundingBox: 0 0 504 288
+%%Creator: Gisselquist Technology LLC
+%%Title: Gisselquist Technology Logo
+%%CreationDate: 11 Mar 2014
+%%EndComments
+%%BeginProlog
+/black { 0 setgray } def
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+ newpath
+ % (height + lw)/2 + lw
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+%%EOF
Index: trunk/doc/src/gqtekspec.cls
===================================================================
--- trunk/doc/src/gqtekspec.cls (nonexistent)
+++ trunk/doc/src/gqtekspec.cls (revision 2)
@@ -0,0 +1,298 @@
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%/
+%
+% Copyright (C) 2015, Gisselquist Technology, LLC
+%
+% This template is free software: you can redistribute it and/or modify it
+% under the terms of the GNU General Public License as published by the
+% Free Software Foundation, either version 3 of the License, or (at your
+% option) any later version.
+%
+% This template is distributed in the hope that it will be useful, but WITHOUT
+% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+% for more details.
+%
+% You should have received a copy of the GNU General Public License along
+% with this program. If not, see } will write the given value into the
+ given address. While both address and value have the semantics of
+ numbers acceptable to {\tt strtoul()}, the address can also be a named
+ address. Supported names can be found in {\tt regdefs.cpp}, and their
+ register mapping in {\tt regdefs.h}.
+\item {\tt ziprun}:
+\item {\tt zipload}:
+\end{itemize}
+
+\section{Zip CPU Programs}
+\begin{itemize}
+\item {\tt ntpserver}:
+\item {\tt goldenstart}:
+\end{itemize}
+\section{ZipOS}
+\subsection{System Calls}
+\begin{itemize}
+\item {\tt int wait(unsigned event\_mask, int timeout)}
+\item {\tt int clear(unsigned event\_mask, int timeout)}
+\item {\tt void post(unsigned event\_mask)}
+\item {\tt void yield(void) }
+\item {\tt int read(int fid, void *buf, int len)}
+\item {\tt int write(int fid, void *buf, int len)}
+\item {\tt unsigned time(void) }
+% \item SEMGET
+% \item SEMPUT
+\item {\tt void *malloc(void)}
+\item {\tt void free(void *buf)}
+% \item FORK
+% \item opendir
+% \item EXEC
+% \item OPEN
+\end{itemize}
+\subsection{Scheduler}
+
+\chapter{Operation}
+
+\chapter{Registers}
+There are several address regions on the S6~SoC, as shown in
+Tbl.~\ref{tbl:memregions}.
+\begin{table}[htbp]
+\begin{center}\begin{tabular}{|p{2.25in}|p{0.6in}|p{0.45in}|p{2.0in}|}\hline
+\rowcolor[gray]{0.85} Binary Address & Base & Size(W) & Purpose \\\hline\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 000x xxxx} & \scalebox{0.9}{\tt 0x00000100} & \hfill 32 & Peripheral I/O Control \\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0010 0yyx} & \scalebox{0.9}{\tt 0x00000120} & \hfill 8 & Debug scope control\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0010 10xx} & \scalebox{0.9}{\tt 0x00000128} & \hfill 4 & RTC control\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0010 11xx} & \scalebox{0.9}{\tt 0x0000012c} & \hfill 4 & SDCard controller\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 00xx} & \scalebox{0.9}{\tt 0x00000130} & \hfill 4 & GPS Clock loop control\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 01xx} & \scalebox{0.9}{\tt 0x00000134} & \hfill 4 & Network packet interface\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 10xx} & \scalebox{0.9}{\tt 0x00000138} & \hfill 4 & OLEDrgb control\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0011 11xx} & \scalebox{0.9}{\tt 0x0000013c} & \hfill 4 & {\em Unused}\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0100 0xxx} & \scalebox{0.9}{\tt 0x00000140} & \hfill 8 & GPS Testbench\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0100 1xxx} & \scalebox{0.9}{\tt 0x00000148} & \hfill 8 & {\em Unused}\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 0101 xxxx} & \scalebox{0.9}{\tt 0x00000150} & \hfill 16 & {\em Unused}\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 011x xxxx} & \scalebox{0.9}{\tt 0x00000160} & \hfill 32 & {\em Unused}\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 100x xxxx} & \scalebox{0.9}{\tt 0x00000180} & \hfill 32 & {\em Unused}\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 101x xxxx} & \scalebox{0.9}{\tt 0x000001a0} & \hfill 32 & Ethernet configuration registers\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 110x xxxx} & \scalebox{0.9}{\tt 0x000001c0} & \hfill 32 & Extended Flash Control Port\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 0001 111x xxxx} & \scalebox{0.9}{\tt 0x000001e0} & \hfill 32 & ICAPE2 Configuration Port\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 10xx xxxx xxxx} & \scalebox{0.9}{\tt 0x00000800} & \hfill 1k & Ethernet TX Buffer\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 0000 11xx xxxx xxxx} & \scalebox{0.9}{\tt 0x00000c00} & \hfill 1k & Ethernet RX Buffer\\\hline
+\scalebox{0.9}{\tt 0000 0000 0000 1xxx xxxx xxxx xxxx} & \scalebox{0.9}{\tt 0x00008000} & \hfill 32k & On-chip Block RAM\\\hline
+\scalebox{0.9}{\tt 0000 01xx xxxx xxxx xxxx xxxx xxxx} & \scalebox{0.9}{\tt 0x00400000} & \hfill 4M & QuadSPI Flash\\\hline
+\scalebox{0.9}{\tt 01xx xxxx xxxx xxxx xxxx xxxx xxxx} & \scalebox{0.9}{\tt 0x04000000} & \hfill 64M & DDR3 SDRAM\\\hline
+\scalebox{0.9}{\tt 1000 0000 0000 0000 0000 0000 000x} & \scalebox{0.9}{\tt 0x08000000} & \hfill 2 & ZipCPU debug control port---only visible to debug WB master\\\hline
+\end{tabular}
+\caption{Address Regions}\label{tbl:memregions}
+\end{center}\end{table}
+
+\begin{table}[htbp]
+\begin{center}\begin{tabular}{|p{0.9in}|p{0.45in}|p{3.5in}|}\hline
+\rowcolor[gray]{0.85} Base & Size(W) & Purpose \\\hline\hline
+\scalebox{0.9}{\tt 0x0c0000000} & 1 & Primary Zip PIC\\\hline
+\scalebox{0.9}{\tt 0x0c0000001} & 1 & Watchdog Timer\\\hline
+\scalebox{0.9}{\tt 0x0c0000002} & 1 & Bus Watchdog Timer\\\hline
+\scalebox{0.9}{\tt 0x0c0000003} & 1 & Alternate Zip PIC\\\hline
+\scalebox{0.9}{\tt 0x0c0000004} & 1 & ZipTimer-A\\\hline
+\scalebox{0.9}{\tt 0x0c0000005} & 1 & ZipTimer-B\\\hline
+\scalebox{0.9}{\tt 0x0c0000006} & 1 & ZipTimer-C\\\hline
+\scalebox{0.9}{\tt 0x0c0000007} & 1 & ZipJiffies\\\hline
+\scalebox{0.9}{\tt 0x0c0000008} & 1 & Master task counter\\\hline
+\scalebox{0.9}{\tt 0x0c0000009} & 1 & Master prefetch stall counter\\\hline
+\scalebox{0.9}{\tt 0x0c000000a} & 1 & Master memory stall counter\\\hline
+\scalebox{0.9}{\tt 0x0c000000b} & 1 & Master instruction counter\\\hline
+\scalebox{0.9}{\tt 0x0c000000c} & 1 & User task counter\\\hline
+\scalebox{0.9}{\tt 0x0c000000d} & 1 & User prefetch stall counter\\\hline
+\scalebox{0.9}{\tt 0x0c000000e} & 1 & User memory stall counter\\\hline
+\scalebox{0.9}{\tt 0x0c000000f} & 1 & User instruction counter\\\hline
+\scalebox{0.9}{\tt 0x0c0000010} & 1 & DMA command register\\\hline
+\scalebox{0.9}{\tt 0x0c0000011} & 1 & DMA length\\\hline
+\scalebox{0.9}{\tt 0x0c0000012} & 1 & DMA source address\\\hline
+\scalebox{0.9}{\tt 0x0c0000013} & 1 & DMA destination address\\\hline
+\scalebox{0.9}{\tt 0x0c0000040} & 1 & {\em Reserved for MMU context register}\\\hline
+\scalebox{0.9}{\tt 0x0c0000080} & 32 & {\em Reserved for MMU TLB}\\\hline
+\end{tabular}
+\caption{ZipSystem Addresses}\label{tbl:zipio}
+\end{center}\end{table}
+
+\section{Peripheral I/O Control}
+Tbl.~\ref{tbl:ioregs}
+\begin{table}[htbp]
+\begin{center}\begin{reglist}
+VERSION &\scalebox{0.8}{\tt 0x0100} & 32 & R & Build date\\\hline
+PIC &\scalebox{0.8}{\tt 0x0101} & 32 & R/W & Bus Interrupt Controller \\\hline
+BUSERR &\scalebox{0.8}{\tt 0x0102} & 32 & R & Last Bus Error Address\\\hline
+PWRCOUNT &\scalebox{0.8}{\tt 0x0103} & 32 & R & Ticks since startup\\\hline
+BTNSW &\scalebox{0.8}{\tt 0x0104} & 32 & R/W & Button/Switch controller\\\hline
+LEDCTRL &\scalebox{0.8}{\tt 0x0105} & 32 & R/W & LED Controller \\\hline
+AUXSETUP &\scalebox{0.8}{\tt 0x0106} & 29 & R/W & Auxilliary UART config\\\hline
+GPSSETUP &\scalebox{0.8}{\tt 0x0107} & 29 & R/W & GPS UART config\\\hline
+CLR-LEDx &\scalebox{0.8}{\tt 0x0108-b} & 32 & R/W & Color LED controller\\\hline
+RTCDATE &\scalebox{0.8}{\tt 0x010c} & 32 & R/W & BCD Calendar Date\\\hline
+GPIO &\scalebox{0.8}{\tt 0x010d} & 32 & R/W & GPIO controller\\\hline
+UARTRX &\scalebox{0.8}{\tt 0x010e} & 32 & R/W & Aux UART receive byte\\\hline
+UARTTX &\scalebox{0.8}{\tt 0x010f} & 32 & R/W & Aux UART transmit byte\\\hline
+GPSRX &\scalebox{0.8}{\tt 0x0110} & 32 & R/W & GPS UART receive byte\\\hline
+GPSTX &\scalebox{0.8}{\tt 0x0111} & 32 & R/W & GPS UART transmit byte\\\hline
+% 0x010c-0x010f
+\end{reglist}
+\caption{I/O Peripheral Registers}\label{tbl:ioregs}
+\end{center}\end{table}
+shows the addresses of various I/O peripherals included as part of the SoC.
+We'll walk through each of these peripherals in turn, describing how they work.
+
+\subsection{Interrupt Controller}
+The OpenArty design maintains three interrupt controllers. Two of them
+are found within the ZipSystem, and the third is located on the bus
+itself. Of these, the primary interrupt controller is located in the ZipSystem.
+This interrupt controller accepts, as interrupt inputs, the outputs of both
+the auxilliary interrupt controller as well as the bus interrupt controller.
+Hence, even though the CPU only supports a single interrupt line, by using
+these three interrupt controllers many more interrupts can be supported.
+
+The primary interrupt controller handles interrupts from the sources listed
+in Tbl.~\ref{tbl:sys-ints}. These interrupts are listed together with the
+mask that would need to be used when referencing them to the interrupt
+controller. In a similar fashion, the auxilliary interrupt controller accepts
+inputs from the sources listed in Tbl.~\ref{tbl:aux-ints}. Finally, the
+bus interrupt controller handles the interrupts from the sources listed in
+Tbl.~\ref{tbl:bus-ints}.
+
+\begin{table}[htbp]
+\begin{center}\begin{tabular}{|p{0.9in}|p{0.75in}|p{0.75in}|p{3.00in}|}\hline
+\rowcolor[gray]{0.85} Name & Bit Mask & DMAC ID &Description \\\hline\hline
+SYS\_DMAC & 0x0001 && The DMA controller is idle.\\\hline
+SYS\_JIF & 0x0002 & 1 & A Jiffies timer has expired.\\\hline
+SYS\_TMC & 0x0004 & 2 & Timer C has timed out.\\\hline
+SYS\_TMB & 0x0008 & 3 & Timer C has timed out.\\\hline
+SYS\_TMA & 0x0010 & 4 & Timer C has timed out.\\\hline
+SYS\_AUX & 0x0020 & 5 & The auxilliary interrupt controller sends an interrupt\\\hline
+SYS\_EXT & 0x0040 & 6 & A Bus interrupt has tripped. \\\hline
+SYS\_PPS & 0x0080 & 7 & An interrupt marking the top of the second\\\hline
+SYS\_GPSRX & 0x0100 & 8& A character has been received via GPS\\\hline
+SYS\_NETRX & 0x0200 & 9 & A packet has been received via the network\\\hline
+SYS\_NETTX & 0x0400 & 10 & The network controller is idle, having sent its
+ last packet\\\hline
+SYS\_UARTRX & 0x0800 & 11 & A character has been received via the UART\\\hline
+SYS\_UARTTX & 0x1000 & 12 & The transmit UART is idle, and ready for its next
+ character.\\\hline
+SYS\_SDCARD & 0x2000 & 13 & The SD-Card controller has become idle\\\hline
+SYS\_BUTTON & 0x4000 & 14 & A Button has been pressed. \\\hline
+\end{tabular}
+\caption{Primary System Interrupts}\label{tbl:sys-ints}
+\end{center}\end{table}
+%%%%%%%%%%%%%
+\begin{table}[htbp]
+\begin{center}\begin{tabular}{|p{0.9in}|p{0.75in}|p{0.75in}|p{3.00in}|}\hline
+\rowcolor[gray]{0.85} Name & Bit Mask & DMAC ID &Description \\\hline\hline
+AUX\_UIC & 0x0001 & 16 & The user instruction counter has overflowed.\\\hline
+AUX\_UPC & 0x0002 & 17 & The user prefetch stall counter has overflowed.\\\hline
+AUX\_UOC & 0x0004 & 18 & The user ops stall counter has overflowed.\\\hline
+AUX\_UTC & 0x0008 & 19 & The user clock tick counter has overflowed.\\\hline
+AUX\_MIC & 0x0010 & 20 & The supervisor instruction counter has overflowed.\\\hline
+AUX\_MPC & 0x0020 & 21 & The supervisor prefetch stall counter has overflowed.\\\hline
+AUX\_MOC & 0x0040 & 22 & The supervisor ops stall counter has overflowed.\\\hline
+AUX\_MTC & 0x0080 & 23 & The supervisor clock tick counter has overflowed.\\\hline
+AUX\_SWITCH & 0x0100 & 24 & A switch has changed state\\\hline
+AUX\_FLASH & 0x0200 & 25 & The flash controller has completed a write/erase cycle\\\hline
+AUX\_SCOPE & 0x0400 & 26 & The Scope has completed its collection\\\hline
+AUX\_RTC & 0x0800 & 27& An alarm or timer has taken place (assuming the RTC
+ is installed, and includes both alarm or timer)\\\hline
+AUX\_GPIO & 0x1000 & 28 & The GPIO input lines have changed values.\\\hline
+AUX\_OLED & 0x2000 & 29 & The OLED driver is idle\\\hline
+\end{tabular}
+\caption{Auxilliary System Interrupts}\label{tbl:aux-ints}
+\end{center}\end{table}
+
+\begin{table}[htbp]
+\begin{center}\begin{tabular}{|p{0.9in}|p{0.75in}|p{3.75in}|}\hline
+\rowcolor[gray]{0.85} Name & Bit Mask & Description \\\hline\hline
+BUS\_BUTTON & 0x0001 & A Button has been pressed. \\\hline
+BUS\_SWITCH & 0x0002 & The Scope has completed its collection\\\hline
+BUS\_PPS & 0x0004 & Top of the second\\\hline
+BUS\_RTC & 0x0008 & An alarm or timer has taken place (assuming the RTC
+ is installed, and includes both alarm or timer)\\\hline
+BUS\_NETRX & 0x0010 & A packet has been received via the network\\\hline
+BUS\_NETTX & 0x0020 & The network controller is idle, having sent its
+ last packet\\\hline
+BUS\_UARTRX & 0x0040 & A character has been received via the UART\\\hline
+BUS\_UARTTX & 0x0080 & The transmit UART is idle, and ready for its next
+ character.\\\hline
+BUS\_GPIO & 0x0100 & The GPIO input lines have changed values.\\\hline
+BUS\_FLASH & 0x0200 & The flash device has finished either its erase or
+ write cycle, and is ready for its next command. (Alternate
+ config only.)\\\hline
+BUS\_SCOPE & 0x0400 & A scope has completed collecting.\\\hline
+BUS\_GPSRX & 0x0800 & A character has been received via GPS\\\hline
+BUS\_SDCARD & 0x1000 & The SD-Card controller has become idle\\\hline
+BUS\_OLED & 0x2000 & The OLED interface has become idle\\\hline
+BUS\_ZIP & 0x4000 & True if the ZipCPU has come to a halt\\\hline
+\end{tabular}
+\caption{Bus Interrupts}\label{tbl:bus-ints}
+\end{center}\end{table}
+
+\subsection{Last Bus Error Address}
+\subsection{General Purpose I/O}
+\subsection{UART Data Register}
+\section{Debugging Scopes}
+\section{Internal Configuration Access Port}
+\section{Real--Time Clock}
+\section{On-Chip Block RAM}
+\section{Flash Memory}
+\begin{table}
+\begin{center}\begin{reglist}
+ewreg &\scalebox{0.8}{\tt 0x0180} & 32 & R & Erase/write control and status\\\hline
+status &\scalebox{0.8}{\tt 0x0181} & 8 & R/W & Bus Interrupt Controller \\\hline
+nvconf &\scalebox{0.8}{\tt 0x0182} & 16 & R & Last Bus Error Address\\\hline
+vconf &\scalebox{0.8}{\tt 0x0183} & 8 & R & Ticks since startup\\\hline
+evonc &\scalebox{0.8}{\tt 0x0184} & 8 & R/W & Button/Switch controller\\\hline
+lock &\scalebox{0.8}{\tt 0x0185} & 8 & R/W & LED Controller \\\hline
+flagstatus&\scalebox{0.8}{\tt 0x0186} & 8 & R/W & Auxilliary UART config\\\hline
+clear &\scalebox{0.8}{\tt 0x0187} & 8 & R/W & Clear status on write\\\hline
+Device ID &\scalebox{0.8}{\tt 0x0188-}\hfill & 5x32 & R & Device ID\\
+ &\scalebox{0.8}{\tt -0x018c}\hfill & & & \\\hline
+% asyncID &\scalebox{0.8}{\tt 0x018d} & 32 & R/W & Asynch Read ID. Write starts the ASynch read, 0xff returned until complete\\\hline
+asyncOTP &\scalebox{0.8}{\tt 0x18e} & 32 & W & Asynch Read OTP. Write starts the ASynch read, 0xff returned until complete\\\hline
+OTP &\scalebox{0.8}{\tt 0x0190-}\hfill &16x32 & R/W & OTP Memory\\
+ &\scalebox{0.8}{\hfill\tt -0x19f} & & & \\\hline
+% 0x010c-0x010f
+\end{reglist}
+\caption{Flash control registers}\label{tbl:flctl}
+\end{center}\end{table}
+
+\chapter{Wishbone}
+
+The master and slave interfaces have been simplified with the following
+requirement: the {\tt STB} line is not allowed to be high unless the {\tt CYC}
+line is high. In this fashion, a slave may often be able to ignore {\tt CYC}
+and only act on the presence of {\tt STB}, knowing that {\tt CYC} must be
+active at the same time.
+
+\chapter{Clocks}
+\begin{table}\begin{center}
+\begin{clocklist}
+{\tt i\_clk\_100mhz} & Ext & \multicolumn{2}{c|}{100~MHz} &
+ 100~MHz Crystal Oscillator \\\hline
+{\tt s\_clk} & PLL & 200~MHz & & Internal Logic, Wishbone Clock \\\hline
+{\tt ram\_clk} & PLL & 200~MHz & & DDR3 SDRAM Clock \\\hline
+{\tt o\_sck} & Logic & 108~MHz & 50~MHz & QSPI Flash clock \\\hline
+{\tt o\_sdclk} & Logic & 50~MHz & 100~kHz & SD--Card clock \\\hline
+\end{clocklist}
+\caption{OpenArty clocks}\label{tbl:clocks}
+\end{center}\end{table}
+
+\chapter{I/O Ports}
+
+Table.~\ref{tbl:ioports}
+\begin{table}[htbp]
+\begin{center}
+\begin{portlist}
+i\_clk\_100mhz & 1 & Input & Clock\\\hline
+o\_qspi\_cs\_n & 1 & Output & Quad SPI Flash chip select\\\hline
+o\_qspi\_sck & 1 & Output & Quad SPI Flash clock\\\hline
+io\_qspi\_dat & 4 & Input/Output & Four-wire SPI flash data bus\\\hline
+i\_btn & 4 & Input & Inputs from the two on-board push-buttons\\\hline
+i\_sw & 4 & Input & Inputs from the two on-board push-buttons\\\hline
+o\_led & 4 & Output & Outputs controlling the four on-board LED's\\\hline
+o\_clr\_led0 & 3 & Output & \\\hline
+o\_clr\_led1 & 3 & Output & \\\hline
+o\_clr\_led2 & 3 & Output & \\\hline
+o\_clr\_led3 & 3 & Output & \\\hline
+i\_uart\_rx & 1 & Input & UART receive input\\\hline
+o\_uart\_tx & 1 & Output & UART transmit output\\\hline\hline
+i\_aux\_rx & 1 & Input & Auxiliary/Pmod UART receive input\\\hline
+o\_aux\_tx & 1 & Output & Auxiliary/Pmod UART transmit output\\\hline
+i\_aux\_rts & 1 & Input & Auxiliary/Pmod UART receive input\\\hline
+o\_aux\_cts & 1 & Output & Auxiliary/Pmod UART transmit output\\\hline\hline
+i\_gps\_rx & 1 & Input & GPS/Pmod UART receive input\\\hline
+o\_gps\_tx & 1 & Output & GPS/Pmod UART transmit output\\\hline
+i\_gps\_pps & 1 & Input & GPS Part-per-second (PPS) signal\\\hline
+i\_gps\_3df & 1 & Input & GPS\\\hline\hline
+o\_oled\_cs\_n & 1 & Output & \\\hline
+o\_oled\_sck & 1 & Output & \\\hline
+o\_oled\_mosi & 1 & Output & \\\hline
+i\_oled\_miso & 1 & Input & \\\hline
+o\_oled\_reset & 1 & Output & \\\hline
+o\_oled\_dc & 1 & Output & \\\hline
+o\_oled\_en & 1 & Output & \\\hline
+o\_oled\_pmen & 1 & Output & \\\hline\hline
+o\_sd\_sck & 1 & Output & SD Clock\\\hline
+i\_sd\_cd & 1 & Input & Card Detect\\\hline
+i\_sd\_wp & 1 & Input & Write Protect\\\hline
+io\_cmd & 1 & In/Output & SD Bi-directional command wire\\\hline
+io\_sd & 4 & In/Output & SD Bi-directional data lines\\\hline\hline
+o\_cls\_cs\_n & 1 & Output & CLS Display chip select\\\hline
+o\_cls\_sck & 1 & Output & CLS Display clock\\\hline
+o\_cls\_mosi & 1 & Output & CLS Display MOSI\\\hline
+i\_cls\_miso & 1 & Input & CLS Display MISO\\\hline\hline
+\end{portlist}
+\caption{List of IO ports}\label{tbl:ioports}
+\end{center}\end{table}
+lists the various I/O ports associated with OpenArty.
+
+
+% Appendices
+% Index
+\end{document}
+
+
Index: trunk/doc/gpl-3.0.pdf
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===================================================================
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+################################################################################
+##
+## Filename: Makefile
+##
+## Project: OpenArty, an entirely open SoC based upon the Arty platform
+##
+## Purpose: To coordinate the build of documentation PDFs from their
+## LaTeX sources.
+##
+## Targets include:
+## all Builds all documents
+##
+## gpl-3.0.pdf Builds the GPL license these files are released
+## under.
+##
+## spec.pdf Builds the specification for the SDSPI
+## controller.
+##
+## Creator: Dan Gisselquist, Ph.D.
+## Gisselquist Technology, LLC
+##
+################################################################################
+##
+## Copyright (C) 2015-2016, Gisselquist Technology, LLC
+##
+## This program is free software (firmware): you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or (at
+## your option) any later version.
+##
+## This program is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with this program. (It's in the $(ROOT)/doc directory, run make with no
+## target there if the PDF file isn't present.) If not, see
+##