URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

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```
/openarty
```
from Rev 4 to Rev 5
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Compare Path: Rev

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Rev 4 → Rev 5

/trunk/bench/cpp/enetctrlsim.h

0,0 → 1,59

/trunk/bench/cpp/eqspiflash_tb.cpp

0,0 → 1,619

/trunk/bench/cpp/enetctrl_tb.cpp

0,0 → 1,275

/trunk/bench/cpp/eqspiflashsim.cpp

0,0 → 1,704

/trunk/bench/cpp/enetctrlsim.cpp

0,0 → 1,133

/trunk/bench/cpp/Makefile

0,0 → 1,58

/trunk/bench/cpp/eqspiflashsim.h

0,0 → 1,117

/trunk/mkdatev.pl

0,0 → 1,89

trunk/mkdatev.pl Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/arty.xdc =================================================================== --- trunk/arty.xdc (nonexistent) +++ trunk/arty.xdc (revision 5) @@ -0,0 +1,292 @@ +## This file is a general .xdc for the ARTY Rev. B +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +# Config setup +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] + +## Clock signal + +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { i_clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { i_clk_100mhz }]; + +##Switches + +set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { i_sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0] +set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { i_sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1] +set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { i_sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2] +set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { i_sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3] + +##RGB LEDs + +set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led0[0] }]; #IO_L18N_T2_35 Sch=led0_b +set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led0[1] }]; #IO_L19N_T3_VREF_35 Sch=led0_g +set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led0[2] }]; #IO_L19P_T3_35 Sch=led0_r +set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led1[0] }]; #IO_L20P_T3_35 Sch=led1_b +set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led1[1] }]; #IO_L21P_T3_DQS_35 Sch=led1_g +set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led1[2] }]; #IO_L20N_T3_35 Sch=led1_r +set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led2[0] }]; #IO_L21N_T3_DQS_35 Sch=led2_b +set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led2[1] }]; #IO_L22N_T3_35 Sch=led2_g +set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led2[2] }]; #IO_L22P_T3_35 Sch=led2_r +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led3[0] }]; #IO_L23P_T3_35 Sch=led3_b +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led3[1] }]; #IO_L24P_T3_35 Sch=led3_g +set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { o_clr_led3[2] }]; #IO_L23N_T3_35 Sch=led3_r + +##LEDs + +set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { o_led[0] }]; #IO_L24N_T3_35 Sch=led[4] +set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_25_35 Sch=led[5] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { o_led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6] +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { o_led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7] + +##Buttons + +set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { i_btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0] +set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { i_btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] +set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { i_btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2] +set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { i_btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3] + +##Pmod Header JA: PModCLS (bottom) + +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4] +#-- set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { o_cls_ss_n }]; #IO_L6N_T0_VREF_15 Sch=ja[7] +#-- set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { o_cls_mosi }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] +#-- set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { i_cls_miso }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] +#-- set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { o_cls_sck }]; #IO_25_15 Sch=ja[10] + +##Pmod Header JB: OLEDrgb + +set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { o_oled_cs_n }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1] +set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { o_oled_mosi }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1] +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { i_oled_nc }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2] +set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { o_oled_sck }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2] +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { o_oled_dcn }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { o_oled_reset_n }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { o_oled_vccen }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { o_oled_pmoden }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4] + +##Pmod Header JC: GPS (top), UART (bottom) + +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { i_gps_3df }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { o_gps_tx }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { i_gps_rx }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { i_gps_pps }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { i_aux_rts }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { o_aux_tx }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { i_aux_rx }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { o_aux_cts }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4] + +##Pmod Header JD: SD-Card + +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { io_sd[3] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1] +set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { io_sd_cmd }]; #IO_L12N_T1_MRCC_35 Sch=jd[2] +set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { io_sd[0] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3] +set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { o_sd_sck }]; #IO_L13N_T2_MRCC_35 Sch=jd[4] +set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { io_sd[1] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7] +set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { io_sd[2] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8] +set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { i_sd_cs }]; #IO_L15P_T2_DQS_35 Sch=jd[9] +set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { i_sd_wp }]; #IO_L15N_T2_DQS_35 Sch=jd[10] + +##USB-UART Interface +# THESE ARE CORRECT +set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { o_uart_tx }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out +set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { i_uart_rx }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in +# + +##ChipKit Single Ended Analog Inputs +##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5). +## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19]. + +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] +#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] + +##ChipKit Digital I/O Low + +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0] +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L8N_T1_D12_14 Sch=ck_io[2] +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3] +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L5P_T0_D06_14 Sch=ck_io[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5] +#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6] +#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[7] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7] +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[8] }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8] +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[9] }]; #IO_L10P_T1_D14_14 Sch=ck_io[9] +#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[10] }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10] +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[11] }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11] +#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[12] }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12] +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[13] }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13] + +##ChipKit Digital I/O On Outer Analog Header +##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 14-19) + +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[14] }]; #IO_0_35 Sch=ck_a[0] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[15] }]; #IO_L4P_T0_35 Sch=ck_a[1] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[16] }]; #IO_L4N_T0_35 Sch=ck_a[2] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[17] }]; #IO_L6P_T0_35 Sch=ck_a[3] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[18] }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[19] }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5] + +##ChipKit Digital I/O On Inner Analog Header +##NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11) + +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[20] }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[21] }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[22] }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[23] }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_io[24] }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_io[25] }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] + +##ChipKit Digital I/O High + +#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27] +#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[28] }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28] +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[29] }]; #IO_25_14 Sch=ck_io[29] +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[30] }]; #IO_0_14 Sch=ck_io[30] +#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[31] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31] +#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[32] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32] +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[33] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33] +#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[34] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34] +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[35] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35] +#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[36] }]; #IO_L8P_T1_D11_14 Sch=ck_io[36] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[37] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[38] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38] +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[39] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[40] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40] +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[41] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41] + +## ChipKit SPI + +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss + +## ChipKit I2C + +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup + +##Misc. ChipKit signals + +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa +set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { i_reset_btn }]; #IO_L16P_T2_35 Sch=ck_rst + +##SMSC Ethernet PHY + +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs +set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { o_eth_mdclk }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { io_eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3] +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3] + +##Quad SPI Flash + +set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { o_qspi_cs_n }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs +set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { io_qspi_dat[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { o_qspi_sck }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] + +##Power Measurements + +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2] +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1] +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1] +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10] + +## Memory + +# Memory address lines +set_property -dict { PACKAGE_PIN R2 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[0] }]; +set_property -dict { PACKAGE_PIN M6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[1] }]; +set_property -dict { PACKAGE_PIN N4 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[2] }]; +set_property -dict { PACKAGE_PIN T1 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[3] }]; +set_property -dict { PACKAGE_PIN N6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[4] }]; +set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[5] }]; +set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[6] }]; +set_property -dict { PACKAGE_PIN U7 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[7] }]; +set_property -dict { PACKAGE_PIN R8 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[8] }]; +set_property -dict { PACKAGE_PIN V7 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[9] }]; +set_property -dict { PACKAGE_PIN R6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[10] }]; +set_property -dict { PACKAGE_PIN U6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[11] }]; +set_property -dict { PACKAGE_PIN T6 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[12] }]; +set_property -dict { PACKAGE_PIN T8 IOSTANDARD SSTL135 } [get_ports { o_ddr_addr[13] }]; +set_property -dict { PACKAGE_PIN R1 IOSTANDARD SSTL135 } [get_ports { o_ddr_ba[0] }]; +set_property -dict { PACKAGE_PIN P4 IOSTANDARD SSTL135 } [get_ports { o_ddr_ba[1] }]; +set_property -dict { PACKAGE_PIN P2 IOSTANDARD SSTL135 } [get_ports { o_ddr_ba[2] }]; +# +set_property -dict { PACKAGE_PIN M4 IOSTANDARD SSTL135 } [get_ports { o_ddr_cas_n }]; +# Clock lines +set_property -dict { PACKAGE_PIN V9 IOSTANDARD DIFF_SSTL135 } [get_ports { o_ddr_ck_n }]; +set_property -dict { PACKAGE_PIN U9 IOSTANDARD DIFF_SSTL135 } [get_ports { o_ddr_ck_p }]; +# +set_property -dict { PACKAGE_PIN N5 IOSTANDARD SSTL135 } [get_ports { o_ddr_cke }]; +set_property -dict { PACKAGE_PIN U8 IOSTANDARD SSTL135 } [get_ports { o_ddr_cs_n }]; +set_property -dict { PACKAGE_PIN L1 IOSTANDARD SSTL135 } [get_ports { o_ddr_dm[0] }]; +set_property -dict { PACKAGE_PIN U1 IOSTANDARD SSTL135 } [get_ports { o_ddr_dm[1] }]; +# Data (DQ) lines +set_property -dict { PACKAGE_PIN K5 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[0] }]; +set_property -dict { PACKAGE_PIN L3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[1] }]; +set_property -dict { PACKAGE_PIN K3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[2] }]; +set_property -dict { PACKAGE_PIN L6 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[3] }]; +set_property -dict { PACKAGE_PIN M3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[4] }]; +set_property -dict { PACKAGE_PIN M1 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[5] }]; +set_property -dict { PACKAGE_PIN L4 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[6] }]; +set_property -dict { PACKAGE_PIN M2 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[7] }]; +set_property -dict { PACKAGE_PIN V4 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[8] }]; +set_property -dict { PACKAGE_PIN T5 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[9] }]; +set_property -dict { PACKAGE_PIN U4 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[10] }]; +set_property -dict { PACKAGE_PIN V5 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[11] }]; +set_property -dict { PACKAGE_PIN V1 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[12] }]; +set_property -dict { PACKAGE_PIN T3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[13] }]; +set_property -dict { PACKAGE_PIN U3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[14] }]; +set_property -dict { PACKAGE_PIN R3 IOSTANDARD SSTL135 } [get_ports { io_ddr_data[15] }]; +# DQS +set_property -dict { PACKAGE_PIN N1 IOSTANDARD DIFF_SSTL135 } [get_ports { io_ddr_dqs_n[0] }]; +set_property -dict { PACKAGE_PIN V2 IOSTANDARD DIFF_SSTL135 } [get_ports { io_ddr_dqs_n[1] }]; +set_property -dict { PACKAGE_PIN N2 IOSTANDARD DIFF_SSTL135 } [get_ports { io_ddr_dqs_p[0] }]; +set_property -dict { PACKAGE_PIN U2 IOSTANDARD DIFF_SSTL135 } [get_ports { io_ddr_dqs_p[1] }]; +set_property -dict { PACKAGE_PIN R5 IOSTANDARD SSTL135 } [get_ports { o_ddr_odt }]; +set_property -dict { PACKAGE_PIN P3 IOSTANDARD SSTL135 } [get_ports { o_ddr_ras_n }]; +set_property -dict { PACKAGE_PIN K6 IOSTANDARD SSTL135 } [get_ports { o_ddr_reset_n }]; +set_property -dict { PACKAGE_PIN P5 IOSTANDARD SSTL135 } [get_ports { o_ddr_we_n }]; +#Internal VREF +set_property INTERNAL_VREF 0.675 [ get_iobanks 34 ]; Index: trunk/Makefile =================================================================== --- trunk/Makefile (nonexistent) +++ trunk/Makefile (revision 5) @@ -0,0 +1,80 @@ +################################################################################ +## +## Filename: Makefile +## +## Project: OpenArty, an entirely open SoC based upon the Arty platform +## +## Purpose: A master project makefile. It tries to build all targets +## within the project, mostly by directing subdirectory makes. +## +## +## Creator: Dan Gisselquist, Ph.D. +## Gisselquist Technology, LLC +## +################################################################################ +## +## Copyright (C) 2015, Gisselquist Technology, LLC +## +## This program is free software (firmware): you can redistribute it and/or +## modify it under the terms of the GNU General Public License as published +## by the Free Software Foundation, either version 3 of the License, or (at +## your option) any later version. +## +## This program is distributed in the hope that it will be useful, but WITHOUT +## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## License: GPL, v3, as defined and found on www.gnu.org, +## http:##www.gnu.org/licenses/gpl.html +## +## +################################################################################ +## +## +.PHONY: all +all: archive datestamp +# all: verilated sw bench bit +# +# Could also depend upon load, if desired, but not necessary +BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"` +RTL := `find rtl -name "*.v"` `find rtl -name Makefile` +NOTES := `find . -name "*.txt"` `find . -name "*.html"` +SW := `find sw -name "*.cpp"` `find sw -name "*.h"` \ + `find sw -name "*.sh"` `find sw -name "*.py"` \ + `find sw -name "*.pl"` `find sw -name Makefile` +DEVSW := `find sw-board -name "*.cpp"` `find sw-board -name "*.h"` \ + `find sw-board -name Makefile` +PROJ := +BIN := `find xilinx -name "*.bit"` +CONSTRAINTS := arty.xdc +YYMMDD:=`date +%Y%m%d` + +.PHONY: datestamp +datestamp: + @bash -c 'if [ ! -e $(YYMMDD)-build.v ]; then rm 20??????-build.v; perl mkdatev.pl > $(YYMMDD)-build.v; rm -f rtl/builddate.v; fi' + @bash -c 'if [ ! -e rtl/builddate.v ]; then cd rtl; cp ../$(YYMMDD)-build.v builddate.v; fi' + +.PHONY: archive +archive: + tar --transform s,^,$(YYMMDD)-xula/, -chjf $(YYMMDD)-xula.tjz $(BENCH) $(SW) $(RTL) $(NOTES) $(PROJ) $(BIN) $(CONSTRAINTS) + +.PHONY: verilated +verilated: + cd rtl ; $(MAKE) --no-print-directory + +.PHONY: rtl +rtl: verilated + +# .PHONY: bench +# bench: +# cd bench ; $(MAKE) --no-print-directory + +# .PHONY: sw +# sw: +# cd sw ; $(MAKE) --no-print-directory + +# .PHONY: bit +# bit: +# cd xilinx ; $(MAKE) --no-print-directory xula.bit +

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