URL
https://opencores.org/ocsvn/openarty/openarty/trunk
Subversion Repositories openarty
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- This comparison shows the changes necessary to convert path
/openarty
- from Rev 49 to Rev 50
- ↔ Reverse comparison
Rev 49 → Rev 50
/trunk/rtl/Makefile
1,4 → 1,4
##########################################################################/ |
################################################################################ |
## |
## Filename: Makefile |
## |
12,9 → 12,9
## Creator: Dan Gisselquist, Ph.D. |
## Gisselquist Technology, LLC |
## |
##########################################################################/ |
################################################################################ |
## |
## Copyright (C) 2015, Gisselquist Technology, LLC |
## Copyright (C) 2015-2017, Gisselquist Technology, LLC |
## |
## This program is free software (firmware): you can redistribute it and/or |
## modify it under the terms of the GNU General Public License as published |
26,11 → 26,16
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with this program. (It's in the $(ROOT)/doc directory. Run make with no |
## target there if the PDF file isn't present.) If not, see |
## <http://www.gnu.org/licenses/> for a copy. |
## |
## License: GPL, v3, as defined and found on www.gnu.org, |
## http:##www.gnu.org/licenses/gpl.html |
## http://www.gnu.org/licenses/gpl.html |
## |
## |
##########################################################################/ |
################################################################################ |
## |
## |
all: test |
61,7 → 66,7
wbicapetwo.v sdspi.v gpsclock_tb.v gpsclock.v wboled.v lloled.v \ |
wbscopc.v wbscope.v memdev.v addepreamble.v addemac.v addecrc.v \ |
addepad.v rxecrc.v rxepreambl.v rxehwmac.v rxewrite.v \ |
rxemin.v rxeipchk.v |
rxemin.v rxeipchk.v clrled.v wbuart.v ufifo.v |
BIGMATH:= bigadd.v bigsmpy.v bigsub.v |
SOURCES := fastmaster.v builddate.v \ |
$(CPUSOURCES) $(JTAGBUS) $(PERIPHERALS) $(BIGMATH) |
79,7 → 84,7
$(VDIRFB)/Venetctrl.h $(VDIRFB)/Venetctrl.cpp $(VDIRFB)/Venetctrl.mk: enetctrl.v |
$(VDIRFB)/Veqspiflash.h $(VDIRFB)/Veqspiflash.cpp $(VDIRFB)/Veqspiflash.mk: eqspiflash.v lleqspi.v |
$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v |
verilator -cc -y $(CPUDR) $*.v |
verilator -trace -cc -y $(CPUDR) $*.v |
|
|
$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk |
/trunk/rtl/builddate.v
38,4 → 38,4
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define DATESTAMP 32'h20161123 |
`define DATESTAMP 32'h20170324 |
/trunk/rtl/busmaster.v
14,7 → 14,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
27,7 → 27,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
113,18 → 113,25
i_sw, i_btn, o_led, |
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, |
// PMod I/O |
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx, |
i_aux_rx, o_aux_tx, i_aux_cts_n, o_aux_rts_n, i_gps_rx, o_gps_tx, |
// The Quad SPI Flash |
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod, |
// |
// The DDR3 SDRAM |
// |
// The actual wires need to be controlled from the device |
// dependent file. In order to keep this device independent, |
// we export only the wishbone interface to the RAM. |
// |
// o_ddr_ck_p, o_ddr_ck_n, o_ddr_reset_n, o_ddr_cke, |
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n, |
// o_ddr_ba, o_ddr_addr, o_ddr_odt, o_ddr_dm, |
// io_ddr_dqs_p, io_ddr_dqs_n, io_ddr_data, |
o_ram_cyc, o_ram_stb, o_ram_we, o_ram_addr, o_ram_wdata, |
// o_ddr_dqs, i_ddr_data, o_ddr_data, |
// |
// These wires allow us to push how we deal with the RAM |
// to the next level up, where they'll be use to interact |
// with a Xilinx specific core. |
o_ram_cyc, o_ram_stb, o_ram_we, o_ram_addr, o_ram_wdata, o_ram_sel, |
i_ram_ack, i_ram_stall, i_ram_rdata, i_ram_err, |
i_ram_dbg, |
// The SD Card |
139,9 → 146,12
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, |
o_oled_reset_n, o_oled_vccen, o_oled_pmoden, |
// The GPS PMod |
i_gps_pps, i_gps_3df |
i_gps_pps, i_gps_3df, |
// Other GPIO wires |
i_gpio, o_gpio |
); |
parameter ZA=28, ZIPINTS=15, RESET_ADDRESS=28'h04e0000; |
parameter ZA=28, ZIPINTS=14, RESET_ADDRESS=32'h01380000, |
NGPI = 4, NGPO = 1; |
input i_clk, i_rst; |
// The bus commander, via an external uart port |
input i_rx_stb; |
155,8 → 165,8
output wire [3:0] o_led; // 16 wide LED's |
output wire [2:0] o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3; |
// PMod UARTs |
input i_aux_rx; |
output wire o_aux_tx, o_aux_cts; |
input i_aux_rx, i_aux_cts_n; |
output wire o_aux_tx, o_aux_rts_n; |
input i_gps_rx; |
output wire o_gps_tx; |
// Quad-SPI flash control |
172,19 → 182,21
// logic dependent. Therefore, this interface as it exists cannot |
// exist here. Instead, we export a device independent wishbone to |
// the RAM rather than the RAM wires themselves. |
// |
|
// output wire o_ddr_ck_p, o_ddr_ck_n,o_ddr_reset_n, o_ddr_cke, |
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n; |
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n; |
// output wire [2:0] o_ddr_ba; |
// output wire [13:0] o_ddr_addr; |
// output wire o_ddr_odt; |
// output wire [1:0] o_ddr_dm; |
// inout wire [1:0] io_ddr_dqs_p, io_ddr_dqs_n; |
// inout wire [15:0] io_ddr_data; |
// output wire [1:0] o_ddr_dqs; |
// input wire [15:0] i_ddr_data; |
// output wire [15:0] o_ddr_data; |
// |
output wire o_ram_cyc, o_ram_stb, o_ram_we; |
output wire [25:0] o_ram_addr; |
output wire [31:0] o_ram_wdata; |
output wire [3:0] o_ram_sel; |
input i_ram_ack, i_ram_stall; |
input [31:0] i_ram_rdata; |
input i_ram_err; |
214,6 → 226,9
// GPS PMod (GPS UART above) |
input i_gps_pps; |
input i_gps_3df; |
// Other GPIO wires |
input [(NGPI-1):0] i_gpio; |
output wire [(NGPO-1):0] o_gpio; |
|
// |
// |
221,7 → 236,9
// |
// |
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_err, ram_err; |
wire [31:0] wb_data, wb_addr; |
wire [31:0] wb_data; |
wire [(ZA-1):0] wb_addr; |
wire [3:0] wb_sel; |
reg wb_ack; |
reg [31:0] wb_idata; |
|
228,6 → 245,7
// Interrupts |
wire gpio_int, oled_int, flash_int, scop_int; |
wire enet_tx_int, enet_rx_int, sdcard_int, rtc_int, rtc_pps, |
auxrxf_int, auxtxf_int, gpsrxf_int, gpstxf_int, |
auxrx_int, auxtx_int, gpsrx_int, gpstx_int, |
sw_int, btn_int; |
|
241,11 → 259,12
// Wires going to devices |
wire wbu_cyc, wbu_stb, wbu_we; |
wire [31:0] wbu_addr, wbu_data; |
wire [3:0] wbu_sel; |
// and then coming from devices |
wire wbu_ack, wbu_stall, wbu_err; |
wire [31:0] wbu_idata; |
// And then headed back home |
wire w_interrupt; |
wire w_bus_interrupt; |
// Oh, and the debug control for the ZIP CPU |
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall; |
wire [31:0] zip_dbg_data; |
258,10 → 277,11
(wbu_zip_sel)?zip_dbg_stall:wbu_stall, |
wbu_err, |
(wbu_zip_sel)?zip_dbg_data:wbu_idata, |
w_interrupt, |
w_bus_interrupt, |
o_tx_stb, o_tx_data, i_tx_busy |
// , wbu_debug |
); |
assign wbu_sel = 4'hf; |
|
`ifdef WBU_SCOPE |
// assign o_dbg = (wbu_ack)&&(wbu_cyc); |
284,9 → 304,10
// Second BUS master source: The ZipCPU |
// |
// |
wire zip_cyc, zip_stb, zip_we; |
wire [(ZA-1):0] w_zip_addr; |
wire [31:0] zip_data, zip_scope_data; |
wire zip_cyc, zip_stb, zip_we; |
wire [(ZA-1):0] zip_addr; |
wire [31:0] zip_data, zip_scope_data; |
wire [3:0] zip_sel; |
// and then coming from devices |
wire zip_ack, zip_stall, zip_err; |
|
293,11 → 314,13
`ifdef ZIP_SYSTEM |
wire [(ZIPINTS-1):0] zip_interrupt_vec = { |
// Lazy(ier) interrupts |
gpio_int, scop_int, flash_int, sw_int, btn_int, rtc_int, |
// Fast interrupts |
oled_int, sdcard_int, |
gpstx_int, gpsrx_int, |
auxtx_int, auxrx_int, |
rtc_ppd, |
// Fast interrupts |
oled_int, w_bus_interrupt, |
gpstxf_int, gpsrxf_int, |
auxtxf_int, auxrxf_int, |
enet_tx_int, enet_rx_int, rtc_pps |
}; |
|
305,11 → 328,10
.ADDRESS_WIDTH(ZA), |
.LGICACHE(10), |
.START_HALTED(1), |
.EXTERNAL_INTERRUPTS(ZIPINTS), |
.HIGHSPEED_CPU(0)) |
zippy(i_clk, i_rst, |
.EXTERNAL_INTERRUPTS(ZIPINTS)) |
swic(i_clk, i_rst, |
// Zippys wishbone interface |
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data, |
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel, |
zip_ack, zip_stall, dwb_idata, zip_err, |
zip_interrupt_vec, zip_cpu_int, |
// Debug wishbone interface |
326,13 → 348,12
zipbones #( .RESET_ADDRESS(RESET_ADDRESS), |
.ADDRESS_WIDTH(ZA), |
.LGICACHE(10), |
.START_HALTED(1), |
.HIGHSPEED_CPU(0)) |
zippy(i_clk, i_rst, |
.START_HALTED(1)) |
swic(i_clk, i_rst, |
// Zippys wishbone interface |
zip_cyc, zip_stb, zip_we, w_zip_addr, zip_data, |
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel, |
zip_ack, zip_stall, dwb_idata, zip_err, |
w_interrupt, w_zip_cpu_int_ignored, |
w_bus_interrupt, w_zip_cpu_int_ignored, |
// Debug wishbone interface |
((wbu_cyc)&&(wbu_zip_sel)), |
((wbu_stb)&&(wbu_zip_sel)),wbu_we, wbu_addr[0], |
345,14 → 366,6
assign zip_cpu_int = 1'b0; |
`endif // ZIP_SYSTEM v ZIP_BONES |
|
wire [31:0] zip_addr; |
generate |
if (ZA < 32) |
assign zip_addr = { {(32-ZA){1'b0}}, w_zip_addr}; |
else |
assign zip_addr = w_zip_addr; |
endgenerate |
|
// |
// |
// And an arbiter to decide who gets to access the bus |
359,30 → 372,32
// |
// |
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err; |
wire [31:0] dwb_addr, dwb_odata; |
wbpriarbiter #(32,32) wbu_zip_arbiter(i_clk, |
wire [(ZA-1):0] dwb_addr; |
wire [31:0] dwb_odata; |
wire [3:0] dwb_sel; |
wbpriarbiter #(32,ZA) wbu_zip_arbiter(i_clk, |
// The ZIP CPU Master -- Gets the priority slot |
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, |
zip_cyc, zip_stb, zip_we, zip_addr, zip_data, zip_sel, |
zip_ack, zip_stall, zip_err, |
// The UART interface Master |
(wbu_cyc)&&(!wbu_zip_sel), (wbu_stb)&&(!wbu_zip_sel), wbu_we, |
wbu_addr, wbu_data, |
wbu_addr[(ZA-1):0], wbu_data, wbu_sel, |
wbu_ack, wbu_stall, wbu_err, |
// Common bus returns |
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, |
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, dwb_sel, |
dwb_ack, dwb_stall, dwb_err); |
|
// |
// |
// |
// |
// And because the ZIP CPU and the Arbiter create an unacceptable |
// delay, we fail timing. So we add in a delay cycle ... |
// |
// |
// |
// |
assign wbu_idata = dwb_idata; |
busdelay wbu_zip_delay(i_clk, |
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, |
busdelay #(ZA) wbu_zip_delay(i_clk, |
dwb_cyc, dwb_stb, dwb_we, dwb_addr, dwb_odata, dwb_sel, |
dwb_ack, dwb_stall, dwb_idata, dwb_err, |
wb_cyc, wb_stb, wb_we, wb_addr, wb_data, |
wb_cyc, wb_stb, wb_we, wb_addr, wb_data, wb_sel, |
wb_ack, wb_stall, wb_idata, wb_err); |
|
`else // ZIPCPU |
397,6 → 412,7
assign wb_we = wbu_we; |
assign wb_addr = wbu_addr; |
assign wb_data = wbu_data; |
assign wb_sel = wbu_sel; |
assign wbu_idata = wb_idata; |
assign wbu_ack = wb_ack; |
assign wbu_stall = wb_stall; |
417,38 → 433,46
// selected or many devices are selected. Such problems will lead to |
// bus errors (below). |
// |
wire io_sel, scop_sel, netb_sel, |
flctl_sel, rtc_sel, sdcard_sel, netp_sel, |
oled_sel, gps_sel, mio_sel, cfg_sel, |
mem_sel, flash_sel, ram_sel, |
wire io_sel, scop_sel, rtc_sel, oled_sel, uart_sel, gpsu_sel, |
sdcard_sel, gps_sel, netp_sel, mio_sel, cfg_sel, |
ram_sel, flash_sel, flctl_sel, mem_sel, netb_sel, |
none_sel, many_sel; |
|
wire idle_n; |
`ifdef ZERO_ON_IDLE |
assign idle_n = wb_stb; |
`else |
assign idle_n = 1'b1; |
`endif |
wire [4:0] skipaddr; |
assign skipaddr = { wb_addr[26], wb_addr[22], wb_addr[15], wb_addr[11], |
~wb_addr[8] }; |
assign ram_sel = (skipaddr[4]); |
assign flash_sel = (skipaddr[4:3]==2'b01); |
assign mem_sel = (skipaddr[4:2]==3'b001); |
assign netb_sel = (skipaddr[4:1]==4'b0001); |
assign io_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b000); |
assign scop_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b0010_0); |
assign rtc_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0010_10); |
assign sdcard_sel= (~|skipaddr)&&(wb_addr[7:2]==6'b0010_11); |
//assign gps_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0011_00); |
assign oled_sel = (~|skipaddr)&&(wb_addr[7:2]==6'b0011_01); |
assign netp_sel = (~|skipaddr)&&(wb_addr[7:3]==5'b0011_1); |
assign gps_sel = (~|skipaddr)&&( (wb_addr[7:2]==6'b0011_00) |
|| (wb_addr[7:3]==5'b0100_0)); |
assign mio_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b101); |
assign flctl_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b110); |
assign cfg_sel = (~|skipaddr)&&(wb_addr[7:5]==3'b111); |
assign ram_sel = (idle_n)&&(skipaddr[4]); |
assign flash_sel = (idle_n)&&(skipaddr[4:3]==2'b01); |
assign mem_sel = (idle_n)&&(skipaddr[4:2]==3'b001); |
assign netb_sel = (idle_n)&&(skipaddr[4:1]==4'b0001); |
assign io_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b00_0); |
assign scop_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:3]==5'b00_100); |
assign rtc_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1010); |
assign oled_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1011); |
assign uart_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1100); |
assign gpsu_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1101); |
assign sdcard_sel= (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1110); |
//assign unused_ = (idle_n)&&(~|skipaddr)&&(wb_addr[7:2]==6'b00_1111); |
assign gps_sel = (idle_n)&&(~|skipaddr)&&((wb_addr[7:2]==6'b01_0000) |
||(wb_addr[7:3]==5'b01_001)); |
assign netp_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:3]==5'b01_010); |
assign mio_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b01_1); |
assign flctl_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b10_0); |
assign cfg_sel = (idle_n)&&(~|skipaddr)&&(wb_addr[7:5]==3'b10_1); |
|
wire skiperr; |
assign skiperr = (|wb_addr[31:27]) |
assign skiperr = (idle_n)&&((|wb_addr[(ZA-1):27]) |
||(~skipaddr[4])&&(|wb_addr[25:23]) |
||(skipaddr[4:3]==2'b00)&&(|wb_addr[21:16]) |
||(skipaddr[4:2]==3'b000)&&(|wb_addr[14:12]) |
||(skipaddr[4:1]==4'b0000)&&(|wb_addr[10:9]); |
||(skipaddr[4:1]==4'b0000)&&(|wb_addr[10:9]) |
||(skipaddr[4:0]==5'b00001)); |
|
|
// |
458,10 → 482,10
// ACK for both flctl_sel (the control line select), as well as the |
// flash_sel (the memory line select). Hence we have one fewer ack |
// line. |
wire io_ack, oled_ack, |
rtc_ack, sdcard_ack, |
net_ack, gps_ack, mio_ack, cfg_ack, |
wire io_ack, rtc_ack, oled_ack, uart_ack, gpsu_ack, sdcard_ack, |
gps_ack, net_ack, mio_ack, cfg_ack, |
mem_ack, flash_ack, ram_ack; |
|
reg many_ack, slow_many_ack; |
reg slow_ack, scop_ack; |
wire [4:0] ack_list; |
474,27 → 498,22
&&(ack_list != 5'h2) |
&&(ack_list != 5'h1) |
&&(ack_list != 5'h0)); |
/* |
assign many_ack = ( { 2'h0, ram_ack} |
+{2'h0, flash_ack } |
+{2'h0, mem_ack } |
+{2'h0, slow_ack } > 3'h1 ); |
*/ |
|
wire [7:0] slow_ack_list; |
assign slow_ack_list = { cfg_ack, mio_ack, gps_ack, |
wire [9:0] slow_ack_list; |
assign slow_ack_list = { cfg_ack, mio_ack, gps_ack, uart_ack, gpsu_ack, |
sdcard_ack, rtc_ack, scop_ack, oled_ack, io_ack }; |
initial slow_many_ack = 1'b0; |
always @(posedge i_clk) |
slow_many_ack <= ((slow_ack_list != 8'h80) |
&&(slow_ack_list != 8'h40) |
&&(slow_ack_list != 8'h20) |
&&(slow_ack_list != 8'h10) |
&&(slow_ack_list != 8'h08) |
&&(slow_ack_list != 8'h04) |
&&(slow_ack_list != 8'h02) |
&&(slow_ack_list != 8'h01) |
&&(slow_ack_list != 8'h00)); |
slow_many_ack <= ((slow_ack_list != 10'h200) |
&&(slow_ack_list != 10'h100) |
&&(slow_ack_list != 10'h080) |
&&(slow_ack_list != 10'h040) |
&&(slow_ack_list != 10'h020) |
&&(slow_ack_list != 10'h010) |
&&(slow_ack_list != 10'h008) |
&&(slow_ack_list != 10'h004) |
&&(slow_ack_list != 10'h002) |
&&(slow_ack_list != 10'h001) |
&&(slow_ack_list != 10'h000)); |
|
always @(posedge i_clk) |
wb_ack <= (wb_cyc)&&(|ack_list); |
504,13 → 523,13
// |
// Peripheral data lines |
// |
wire [31:0] io_data, oled_data, |
rtc_data, sdcard_data, |
wire [31:0] io_data, rtc_data, oled_data, uart_data, gpsu_data, |
sdcard_data, |
net_data, gps_data, mio_data, cfg_data, |
mem_data, flash_data, ram_data; |
reg [31:0] slow_data, scop_data; |
|
// 4 control lines, 5x32 data lines ... |
// 4 control lines, 5x32 data lines ... |
always @(posedge i_clk) |
if ((ram_ack)||(flash_ack)) |
wb_idata <= (ram_ack)?ram_data:flash_data; |
519,10 → 538,12
else |
wb_idata <= slow_data; |
|
// 7 control lines, 8x32 data lines |
// 9 control lines, 10x32 data lines |
always @(posedge i_clk) |
if ((cfg_ack)||(mio_ack)) |
slow_data <= (cfg_ack) ? cfg_data : mio_data; |
else if ((uart_ack)||(gpsu_ack)) |
slow_data <= (uart_ack)?uart_data : gpsu_data; |
else if ((sdcard_ack)||(rtc_ack)) |
slow_data <= (sdcard_ack)?sdcard_data : rtc_data; |
else if ((scop_ack)|(oled_ack)) |
537,7 → 558,7
// *must* be done via combinatorial logic. |
// |
wire io_stall, scop_stall, oled_stall, |
rtc_stall, sdcard_stall, |
rtc_stall, sdcard_stall, uart_stall, gpsu_stall, |
net_stall, gps_stall, mio_stall, cfg_stall, netb_stall, |
mem_stall, flash_stall, ram_stall, |
many_stall; |
545,10 → 566,12
((io_sel)&&(io_stall)) // Never stalls |
||((scop_sel)&&(scop_stall)) // Never stalls |
||((rtc_sel)&&(rtc_stall)) // Never stalls |
||((oled_sel)&&(oled_stall)) // Never stalls |
||((uart_sel)&&(uart_stall)) // Never stalls |
||((gpsu_sel)&&(gpsu_stall)) // Never stalls |
||((sdcard_sel)&&(sdcard_stall))// Never stalls |
||((netp_sel)&&(net_stall)) // Never stalls |
||((gps_sel)&&(gps_stall)) //(maybe? never stalls?) |
||((oled_sel)&&(oled_stall)) // Never stalls |
||((mio_sel)&&(mio_stall)) |
||((cfg_sel)&&(cfg_stall)) |
||((netb_sel)&&(net_stall)) // Never stalls |
576,7 → 599,7
// it. Still, having this logic in place has saved my tush more than |
// once. |
// |
reg [31:0] sel_addr; |
reg [(ZA-1):0] sel_addr; |
always @(posedge i_clk) |
sel_addr <= wb_addr; |
|
586,16 → 609,24
last_stb <= wb_stb; |
|
single_sel_a <= (wb_stb)&&((ram_sel)|(flash_sel) |
|(mem_sel)|(netb_sel)|(cfg_sel)); |
|(mem_sel)|(netb_sel)|(cfg_sel) |
|(uart_sel)|(gpsu_sel)); |
many_sel_a <= 1'b0; |
if ((ram_sel)&&((flash_sel)||(mem_sel)||(netb_sel)||cfg_sel)) |
if ((ram_sel)&&((flash_sel)||(mem_sel)||(netb_sel)||(cfg_sel) |
||(uart_sel)||(gpsu_sel))) |
many_sel_a <= 1'b1; |
else if ((flash_sel)&&((mem_sel)||(netb_sel)||cfg_sel)) |
else if ((flash_sel)&&((mem_sel)||(netb_sel)||(cfg_sel) |
||(uart_sel)||(gpsu_sel))) |
many_sel_a <= 1'b1; |
else if ((mem_sel)&&((netb_sel)||cfg_sel)) |
else if ((mem_sel)&&((netb_sel)||(cfg_sel) |
||(uart_sel)||(gpsu_sel))) |
many_sel_a <= 1'b1; |
else if ((netb_sel)&&(cfg_sel)) |
else if ((netb_sel)&&((cfg_sel)||(uart_sel)||(gpsu_sel))) |
many_sel_a <= 1'b1; |
else if ((cfg_sel)&&((uart_sel)||(gpsu_sel))) |
many_sel_a <= 1'b1; |
else if ((uart_sel)&&(gpsu_sel)) |
many_sel_a <= 1'b1; |
|
single_sel_b <= (wb_stb)&&((mio_sel)||(gps_sel)||(netp_sel) |
||(sdcard_sel)||(rtc_sel)||(flctl_sel) |
624,7 → 655,7
end |
|
wire sel_err; // 5 inputs |
assign sel_err = ( (last_stb)&&(~single_sel_a)&&(~single_sel_b)) |
assign sel_err = ( (last_stb)&&(!single_sel_a)&&(!single_sel_b)) |
||((single_sel_a)&&(single_sel_b)) |
||((single_sel_a)&&(many_sel_a)) |
||((single_sel_b)&&(many_sel_b)); |
637,11 → 668,16
// the address that caused an error: in the case of none_sel it will |
// be, but if many_ack or slow_many_ack are true then we might just be |
// looking at an address on the bus that was nearby the one requested. |
reg [31:0] bus_err_addr; |
initial bus_err_addr = 32'h00; |
reg [(ZA-1):0] r_bus_err_addr; |
initial r_bus_err_addr = 0; |
always @(posedge i_clk) |
if (wb_err) |
bus_err_addr <= sel_addr; |
r_bus_err_addr <= sel_addr; |
wire [31:0] bus_err_addr; |
assign bus_err_addr[(ZA+1):0] = { r_bus_err_addr, 2'b00 }; |
generate if (ZA < 30) |
assign bus_err_addr[31:(ZA+2)] = 0; |
endgenerate |
|
// |
// I/O peripheral |
648,64 → 684,34
// |
// The I/O processor, herein called an fastio. This is a unique |
// set of peripherals--these are all of the peripherals that can answer |
// in a single clock--or, rather, they are the peripherals that can |
// in a single clock--or, rather, they are the peripherals that can |
// answer the bus before their clock. Hence, the fastio simply consists |
// of a mux that selects between various peripheral responses. Further, |
// these peripherals are not allowed to stall the bus. |
// |
// There is no option for turning these off--they will always be on. |
wire [8:0] master_ints; |
assign master_ints = { zip_cpu_int, oled_int, rtc_int, sdcard_int, |
wire [11:0] master_ints; |
assign master_ints = { zip_cpu_int, |
gpsrx_int, auxtx_int, auxrx_int, |
oled_int, rtc_int, sdcard_int, |
enet_tx_int, enet_rx_int, |
scop_int, flash_int, rtc_pps }; |
wire [6:0] board_ints; |
wire [2:0] board_ints; |
wire [3:0] w_led; |
wire rtc_ppd; |
fastio #( |
.AUXUART_SETUP(30'd705), // 115200 Baud, 8N1, from 81.25M |
.GPSUART_SETUP(30'd8464), // 9600 Baud, 8N1 |
.EXTRACLOCK(0) |
.EXTRACLOCK(0), .NGPI(NGPI), .NGPO(NGPO) |
) runio(i_clk, i_sw, i_btn, |
w_led, o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, |
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx, |
i_gpio, o_gpio, |
wb_cyc, (io_sel)&&(wb_stb), wb_we, wb_addr[4:0], |
wb_data, io_ack, io_stall, io_data, |
rtc_ppd, |
bus_err_addr, gps_now[63:32], gps_step[47:16], |
master_ints, w_interrupt, |
master_ints, w_bus_interrupt, |
board_ints); |
assign { gpio_int, auxrx_int, auxtx_int, gpsrx_int, gpstx_int, sw_int, btn_int } = board_ints; |
assign { gpio_int, sw_int, btn_int } = board_ints; |
|
/* |
reg [25:0] dbg_counter_err, dbg_counter_cyc, dbg_counter_sel, |
dbg_counter_many; |
// assign wb_err = (wb_cyc)&&(sel_err || many_ack || slow_many_ack); |
always @(posedge i_clk) |
if (wbu_cyc) |
dbg_counter_cyc <= 0; |
else if (!dbg_counter_cyc[25]) |
dbg_counter_cyc <= dbg_counter_cyc+26'h1; |
always @(posedge i_clk) |
if (wbu_err) |
dbg_counter_err <= 0; |
else if (!dbg_counter_err[25]) |
dbg_counter_err <= dbg_counter_err+26'h1; |
always @(posedge i_clk) |
if ((wb_cyc)&&(sel_err)) |
dbg_counter_sel <= 0; |
else if (!dbg_counter_sel[25]) |
dbg_counter_sel <= dbg_counter_sel+26'h1; |
always @(posedge i_clk) |
if ((wb_cyc)&&(many_ack)) |
dbg_counter_many <= 0; |
else if (!dbg_counter_many[25]) |
dbg_counter_many <= dbg_counter_many+26'h1; |
assign o_led = { |
(!dbg_counter_many[25])|w_led[3], |
(!dbg_counter_sel[25])|w_led[2], |
(!dbg_counter_cyc[25])|w_led[1], |
(!dbg_counter_err[25])|w_led[0] }; |
*/ |
assign o_led = w_led; |
|
|
742,6 → 748,32
|
// |
// |
// Auxilliary UART (console port) |
// |
// |
wbuart #(31'd705) // 115200 Baud, 8N1, from 81.25M |
console(i_clk, 1'b0, |
wb_cyc, (wb_stb)&&(uart_sel), wb_we, wb_addr[1:0], wb_data, |
uart_ack, uart_stall, uart_data, |
i_aux_rx, o_aux_tx, i_aux_cts_n, o_aux_rts_n, |
auxrx_int, auxtx_int, auxrxf_int, auxtxf_int); |
|
// |
// |
// GPS Data UART |
// |
// |
wire gps_rts_n_ignored; |
wbuart #(.INITIAL_SETUP(31'd8464), // 9600 Baud, 8N1 |
.HARDWARE_FLOW_CONTROL_PRESENT(1'b0)) |
gpsdata(i_clk, 1'b0, |
wb_cyc, (wb_stb)&&(gpsu_sel), wb_we, wb_addr[1:0], wb_data, |
gpsu_ack, gpsu_stall, gpsu_data, |
i_gps_rx, o_gps_tx, 1'b0, gps_rts_n_ignored, |
gpsrx_int, gpstx_int, gpsrxf_int, gpstxf_int); |
|
// |
// |
// SDCard device level access |
// |
// |
754,7 → 786,7
wb_cyc, (wb_stb)&&(sdcard_sel), wb_we, |
wb_addr[1:0], wb_data, |
sdcard_ack, sdcard_stall, sdcard_data, |
w_sd_cs_n, o_sd_sck, w_sd_mosi, w_sd_miso, |
w_sd_cs_n, o_sd_sck, w_sd_mosi, w_sd_miso, |
sdcard_int, 1'b1, sd_dbg); |
assign w_sd_miso = i_sd_data[0]; |
assign o_sd_data = { w_sd_cs_n, 3'b111 }; |
820,7 → 852,7
wire [1:0] gps_dbg_tick; |
|
gpsclock_tb ppscktb(i_clk, ck_pps, tb_pps, |
(wb_stb)&&(gps_sel)&&(!wb_addr[4]), |
(wb_stb)&&(gps_sel)&&(wb_addr[3]), |
wb_we, wb_addr[2:0], |
wb_data, gtb_ack, gtb_stall, gtb_data, |
gps_err, gps_now, gps_step); |
837,7 → 869,7
gpsclock #( |
.DEFAULT_STEP(32'h834d_c736) |
) ppsck(i_clk, 1'b0, gps_pps, ck_pps, gps_led, |
(wb_stb)&&(gps_sel)&&(wb_addr[4]), |
(wb_stb)&&(gps_sel)&&(!wb_addr[3]), |
wb_we, wb_addr[1:0], |
wb_data, gck_ack, gck_stall, gck_data, |
gps_tracking, gps_now, gps_step, gps_err, gps_locked, |
879,7 → 911,7
|
enetpackets #(12) |
netctrl(i_clk, i_rst, wb_cyc,(wb_stb)&&((netp_sel)||(netb_sel)), |
wb_we, { (netb_sel), wb_addr[10:0] }, wb_data, |
wb_we, { (netb_sel), wb_addr[10:0] }, wb_data, wb_sel, |
net_ack, net_stall, net_data, |
o_net_reset_n, |
i_net_rx_clk, i_net_col, i_net_crs, i_net_dv, i_net_rxd, |
910,18 → 942,18
assign enet_tx_int = 1'b0; |
|
// |
// 2kW memory, 1kW for each of transmit and receive. (Max pkt length |
// 8kW memory, 4kW for each of transmit and receive. (Max pkt length |
// is 512W, so this allows for two 512W in memory.) Since we don't |
// really have ethernet without ETHERNET_ACCESS defined, this just |
// consumes resources for us so we have an idea of what might be |
// consumes resources for us so we have an idea of what might be |
// available when we do have ETHERNET_ACCESS defined. |
// |
memdev #(11) enet_buffers(i_clk, wb_cyc, (wb_stb)&&((netb_sel)||(netp_sel)), wb_we, |
wb_addr[10:0], wb_data, net_ack, net_stall, net_data); |
memdev #(13) enet_buffers(i_clk, wb_cyc, |
(wb_stb)&&((netb_sel)||(netp_sel)), wb_we, |
wb_addr[10:0], wb_data, wb_sel, net_ack, net_stall, net_data); |
assign o_mdclk = 1'b1; |
assign o_mdio = 1'b1; |
assign o_mdwe = 1'b1; |
|
`endif |
|
|
948,10 → 980,10
// |
// There is no option to turn this off--this RAM must always be |
// present in the design. |
memdev #(.AW(15), |
memdev #(.LGMEMSZ(17), |
.EXTRACLOCK(0)) // 32kW, or 128kB, 15 address lines |
blkram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we, wb_addr[14:0], |
wb_data, mem_ack, mem_stall, mem_data); |
wb_data, wb_sel, mem_ack, mem_stall, mem_data); |
|
// |
// FLASH MEMORY ACCESS |
993,19 → 1025,24
// |
// |
`ifdef SDRAM_ACCESS |
//wbddrsdram rami(i_clk, |
// wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data, |
// ram_ack, ram_stall, ram_data, |
// o_ddr_reset_n, o_ddr_cke, |
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n, |
// o_ddr_dqs, |
// o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data); |
|
/* |
wire [31:0] i_ram_dbg; |
assign i_ram_dbg = 0; |
wire [1:0] o_ddr_dqs; |
wbddrsdram rami(i_clk, |
wb_cyc, (wb_stb)&&(ram_sel), wb_we, wb_addr[25:0], wb_data, |
wb_sel, ram_ack, ram_stall, ram_data, |
o_ddr_reset_n, o_ddr_cke, |
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n, |
o_ddr_dqs, |
o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data); |
*/ |
assign o_ram_cyc = wb_cyc; |
assign o_ram_stb = (wb_stb)&&(ram_sel); |
assign o_ram_we = wb_we; |
assign o_ram_addr = wb_addr[25:0]; |
assign o_ram_wdata = wb_data; |
assign o_ram_sel = wb_sel; |
assign ram_ack = i_ram_ack; |
assign ram_stall = i_ram_stall; |
assign ram_data = i_ram_rdata; |
1038,7 → 1075,7
assign o_ddr_reset_n = 1'b0; // Leave the SDRAM in reset |
assign o_ddr_cke = 1'b0; // Disable the SDRAM clock |
// DQS |
assign o_ddr_dqs = 3'b100; // Leave DQS pins in high impedence |
assign o_ddr_dqs = 2'b11; // Leave DQS pins in high impedence |
// DDR3 control wires (not enabled if CKE=0) |
assign o_ddr_cs_n = 1'b0; // NOOP command |
assign o_ddr_ras_n = 1'b1; |
1047,7 → 1084,7
// (Unused) data wires |
assign o_ddr_addr = 14'h00; |
assign o_ddr_ba = 3'h0; |
assign o_ddr_data = 32'h00; |
assign o_ddr_data = 16'h00; |
`endif |
|
|
1257,7 → 1294,6
assign scop_d_stall = scop_net_stall; |
assign scop_d_data = scop_net_data; |
assign scop_d_interrupt = scop_net_interrupt; |
|
`else |
assign scop_d_data = 32'h00; |
assign scop_d_stall = 1'b0; |
/trunk/rtl/clrled.v
0,0 → 1,130
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: clrled.v |
// |
// Project: OpenArty, an entirely open SoC based upon the Arty platform |
// |
// Purpose: The ARTY contains 4 Color LEDs. Each color LED is composed of |
// three LEDs: one red, one blue, and one green. These LEDs need |
// to be toggled in a PWM manner in order to create varying amounts of |
// reds, blues, greens, and other colors with varying components of red, |
// green, and blue. This Verilog core creates a bus controlled core |
// so that these LEDs can be controlled by any bus master. While the core |
// is ostensibly controlled via a wishbone bus, none of the control wires |
// are wishbone wires, save the i_stb wire. Address wires are not needed, |
// as this core only implements a single address. Stall is permanently |
// set to zero. Ack is always on the clock after STB is true (but not set |
// here), and the output data is given by o_data. See fastio.v for how to |
// connect this to a wishbone bus. |
// |
// The core also accepts 9-bits from a counter created elsewhere. This |
// counter is created quite simply, and phase is irrelevant for our |
// purposes here. Thy reason why we don't create the counter within this |
// core is because the same counter can also be shared with the other |
// clrled cores. The code to generate this counter is quite simple: |
// |
// reg [8:0] counter; |
// always @(posedge i_clk) |
// counter <= counter + 9'h1; |
// |
// |
// The core creates and maintains one 32-bit register on the bus. This |
// register contains four bytes: |
// |
// Byte 0 (MSB) |
// Contains the most significant bits of the red, green, and blue |
// color. Since using these bits sets the CLRLED to be *very* |
// bright, the design is set to assume they will rarely be used. |
// |
// Byte 1 |
// The red control. The higher the value, the brighter the red |
// component will be. |
// |
// Byte 2 Blue control. |
// Byte 3 Green control. |
// |
// As examples, setting this register to 0x0ffffff will produce a bright |
// white light from the color LED. Setting it to 0x070000 will produce |
// a dimmer red light. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module clrled(i_clk, i_stb, i_data, i_counter, o_data, o_led); |
input i_clk, i_stb; |
input [31:0] i_data; |
input [8:0] i_counter; |
output wire [31:0] o_data; |
output reg [2:0] o_led; |
|
// |
// |
// If i_counter isn't available, just build one as in: |
// |
// reg [8:0] counter; |
// always @(posedge i_clk) counter <= counter + 1'b1; |
// |
|
wire [31:0] w_clr_led; |
reg [8:0] r_clr_led_r, r_clr_led_g, r_clr_led_b; |
|
initial r_clr_led_r = 9'h003; // Color LED on the far right |
initial r_clr_led_g = 9'h000; |
initial r_clr_led_b = 9'h000; |
|
always @(posedge i_clk) |
if (i_stb) |
begin |
r_clr_led_r <= { i_data[26], i_data[23:16] }; |
r_clr_led_g <= { i_data[25], i_data[15: 8] }; |
r_clr_led_b <= { i_data[24], i_data[ 7: 0] }; |
end |
|
assign o_data = { 5'h0, |
r_clr_led_r[8], r_clr_led_g[8], r_clr_led_b[8], |
r_clr_led_r[7:0], r_clr_led_g[7:0], r_clr_led_b[7:0] |
}; |
|
wire [8:0] rev_counter; |
assign rev_counter[8] = i_counter[0]; |
assign rev_counter[7] = i_counter[1]; |
assign rev_counter[6] = i_counter[2]; |
assign rev_counter[5] = i_counter[3]; |
assign rev_counter[4] = i_counter[4]; |
assign rev_counter[3] = i_counter[5]; |
assign rev_counter[2] = i_counter[6]; |
assign rev_counter[1] = i_counter[7]; |
assign rev_counter[0] = i_counter[8]; |
|
always @(posedge i_clk) |
o_led <= { (rev_counter[8:0] < r_clr_led_r), |
(rev_counter[8:0] < r_clr_led_g), |
(rev_counter[8:0] < r_clr_led_b) }; |
|
endmodule |
/trunk/rtl/cpu/busdelay.v
37,7 → 37,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
49,6 → 49,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
55,12 → 60,13
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module busdelay(i_clk, |
// The input bus |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel, |
o_wb_ack, o_wb_stall, o_wb_data, o_wb_err, |
// The delayed bus |
o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data, |
o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr,o_dly_data,o_dly_sel, |
i_dly_ack, i_dly_stall, i_dly_data, i_dly_err); |
parameter AW=32, DW=32, DELAY_STALL = 0; |
input i_clk; |
68,6 → 74,7
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [(AW-1):0] i_wb_addr; |
input [(DW-1):0] i_wb_data; |
input [(DW/8-1):0] i_wb_sel; |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [(DW-1):0] o_wb_data; |
76,6 → 83,7
output reg o_dly_cyc, o_dly_stb, o_dly_we; |
output reg [(AW-1):0] o_dly_addr; |
output reg [(DW-1):0] o_dly_data; |
output reg [(DW/8-1):0] o_dly_sel; |
input i_dly_ack; |
input i_dly_stall; |
input [(DW-1):0] i_dly_data; |
85,8 → 93,9
if (DELAY_STALL != 0) |
begin |
reg r_stb, r_we, r_rtn_stall, r_rtn_err; |
reg [(AW-1):0] r_addr; |
reg [(DW-1):0] r_data; |
reg [(AW-1):0] r_addr; |
reg [(DW/8-1):0] r_sel; |
|
initial o_dly_cyc = 1'b0; |
initial r_rtn_stall= 1'b0; |
100,6 → 109,7
r_we <= i_wb_we; |
r_addr <= i_wb_addr; |
r_data <= i_wb_data; |
r_sel <= i_wb_sel; |
|
if (r_stb) |
begin |
106,6 → 116,7
o_dly_we <= r_we; |
o_dly_addr <= r_addr; |
o_dly_data <= r_data; |
o_dly_sel <= r_sel; |
o_dly_stb <= 1'b1; |
r_rtn_stall <= 1'b0; |
r_stb <= 1'b0; |
113,6 → 124,7
o_dly_we <= i_wb_we; |
o_dly_addr <= i_wb_addr; |
o_dly_data <= i_wb_data; |
o_dly_sel <= i_wb_sel; |
o_dly_stb <= i_wb_stb; |
r_stb <= 1'b0; |
r_rtn_stall <= 1'b0; |
122,6 → 134,7
r_we <= i_wb_we; |
r_addr <= i_wb_addr; |
r_data <= i_wb_data; |
r_sel <= i_wb_sel; |
r_stb <= i_wb_stb; |
|
r_rtn_stall <= i_wb_stb; |
165,6 → 178,9
if (~o_wb_stall) |
o_dly_data <= i_wb_data; |
always @(posedge i_clk) |
if (~o_wb_stall) |
o_dly_sel <= i_wb_sel; |
always @(posedge i_clk) |
o_wb_ack <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc); |
always @(posedge i_clk) |
o_wb_data <= i_dly_data; |
/trunk/rtl/cpu/cpudefs.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpudefs.v |
// |
33,7 → 33,7
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
47,11 → 47,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`ifndef CPUDEFS_H |
`define CPUDEFS_H |
// |
108,7 → 115,7
// |
// |
// OPT_IMPLEMENT_FPU will (one day) control whether or not the floating point |
// unit (once I have one) is built and included into the ZipCPU by default. |
// unit (once I have one) is built and included into the ZipCPU by default. |
// At that time, if this option is set then a parameter will be set that |
// causes the floating point unit to be included. (This parameter may |
// still be overridden, as with any parameter ...) If the floating point unit |
121,32 → 128,12
// |
// |
// |
// OPT_NEW_INSTRUCTION_SET controls whether or not the new instruction set |
// is in use. The new instruction set contains space for floating point |
// operations, signed and unsigned divide instructions, as well as bit reversal |
// and ... at least two other operations yet to be defined. The decoder alone |
// uses about 70 fewer LUTs, although in practice this works out to 12 fewer |
// when all works out in the wash. Further, floating point and divide |
// instructions will cause an illegal instruction exception if they are not |
// implemented--so software capability can be built to use these instructions |
// immediately, even if the hardware is not yet ready. |
// |
// This option is likely to go away in the future, obsoleting the previous |
// instruction set, so I recommend setting this option and switching to the |
// new instruction set as soon as possible. |
// |
`define OPT_NEW_INSTRUCTION_SET |
// |
// |
// |
// |
// |
// |
// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and |
// OPT_SINGLE_FETCH controls whether or not the prefetch has a cache, and |
// whether or not it can issue one instruction per clock. When set, the |
// prefetch has no cache, and only one instruction is fetched at a time. |
// This effectively sets the CPU so that only one instruction is ever |
// in the pipeline at once, and hence you may think of this as a "kill |
// This effectively sets the CPU so that only one instruction is ever |
// in the pipeline at once, and hence you may think of this as a "kill |
// pipeline" option. However, since the pipelined fetch component uses so |
// much area on the FPGA, this is an important option to use in trimming down |
// used area if necessary. Hence, it needs to be maintained for that purpose. |
155,7 → 142,7
// |
// We can either pipeline our fetches, or issue one fetch at a time. Pipelined |
// fetches are more complicated and therefore use more FPGA resources, while |
// single fetches will cause the CPU to stall for about 5 stalls each |
// single fetches will cause the CPU to stall for about 5 stalls each |
// instruction cycle, effectively reducing the instruction count per clock to |
// about 0.2. However, the area cost may be worth it. Consider: |
// |
180,9 → 167,9
// |
// |
// |
// OPT_PIPELINED is the natural result and opposite of using the single |
// OPT_PIPELINED is the natural result and opposite of using the single |
// instruction fetch unit. If you are not using that unit, the ZipCPU will |
// be pipelined. The option is defined here more for readability than |
// be pipelined. The option is defined here more for readability than |
// anything else, since OPT_PIPELINED makes more sense than OPT_SINGLE_FETCH, |
// well ... that and it does a better job of explaining what is going on. |
// |
236,36 → 223,30
// |
// |
// |
`ifdef OPT_NEW_INSTRUCTION_SET |
// |
// |
// The instruction set defines an optional compressed instruction set (CIS) |
// complement. These were at one time erroneously called Very Long Instruction |
// Words. They are more appropriately referred to as compressed instructions. |
// The compressed instruction format allows two instructions to be packed into |
// the same instruction word. Some instructions can be compressed, not all. |
// Compressed instructions take the same time to complete. Set OPT_CIS to |
// include these double instructions as part of the instruction set. These |
// instructions are designed to get more code density from the instruction set, |
// and to hopefully take some pain off of the performance of the pre-fetch and |
// instruction cache. |
// |
// The new instruction set also defines a set of very long instruction words. |
// Well, calling them "very long" instruction words is probably a misnomer, |
// although we're going to do it. They're really 2x16-bit instructions--- |
// instruction words that pack two instructions into one word. (2x14 bit |
// really--'cause you need a bit to note the instruction is a 2x instruction, |
// and then 3-bits for the condition codes ...) Set OPT_VLIW to include these |
// double instructions as part of the new instruction set. These allow a single |
// instruction to contain two instructions within. These instructions are |
// designed to get more code density from the instruction set, and to hopefully |
// take some pain off of the performance of the pre-fetch and instruction cache. |
// |
// These new instructions, however, also necessitate a change in the Zip |
// CPU--the Zip CPU can no longer execute instructions atomically. It must |
// now execute non-VLIW instructions, or VLIW instruction pairs, atomically. |
// now execute non-CIS instructions, or CIS instruction pairs, atomically. |
// This logic has been added into the ZipCPU, but it has not (yet) been |
// tested thoroughly. |
// |
// Oh, and the assembler, the debugger, and the object file dumper, and the |
// simulator all need to be updated as well .... |
// |
`define OPT_VLIW |
`define OPT_CIS |
// |
// |
`endif // OPT_NEW_INSTRUCTION_SET |
// |
// |
`endif // OPT_SINGLE_FETCH |
// |
// |
/trunk/rtl/cpu/cpuops.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: cpuops.v |
// |
12,9 → 12,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
26,11 → 26,16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
`include "cpudefs.v" |
// |
45,12 → 50,6
output reg o_valid; |
output wire o_busy; |
|
// Rotate-left pre-logic |
wire [63:0] w_rol_tmp; |
assign w_rol_tmp = { i_a, i_a } << i_b[4:0]; |
wire [31:0] w_rol_result; |
assign w_rol_result = w_rol_tmp[63:32]; // Won't set flags |
|
// Shift register pre-logic |
wire [32:0] w_lsr_result, w_asr_result, w_lsl_result; |
wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted; |
75,28 → 74,20
assign w_brev_result[k] = i_b[31-k]; |
end endgenerate |
|
// Popcount pre-logic |
wire [31:0] w_popc_result; |
assign w_popc_result[5:0]= |
({5'h0,i_b[ 0]}+{5'h0,i_b[ 1]}+{5'h0,i_b[ 2]}+{5'h0,i_b[ 3]}) |
+({5'h0,i_b[ 4]}+{5'h0,i_b[ 5]}+{5'h0,i_b[ 6]}+{5'h0,i_b[ 7]}) |
+({5'h0,i_b[ 8]}+{5'h0,i_b[ 9]}+{5'h0,i_b[10]}+{5'h0,i_b[11]}) |
+({5'h0,i_b[12]}+{5'h0,i_b[13]}+{5'h0,i_b[14]}+{5'h0,i_b[15]}) |
+({5'h0,i_b[16]}+{5'h0,i_b[17]}+{5'h0,i_b[18]}+{5'h0,i_b[19]}) |
+({5'h0,i_b[20]}+{5'h0,i_b[21]}+{5'h0,i_b[22]}+{5'h0,i_b[23]}) |
+({5'h0,i_b[24]}+{5'h0,i_b[25]}+{5'h0,i_b[26]}+{5'h0,i_b[27]}) |
+({5'h0,i_b[28]}+{5'h0,i_b[29]}+{5'h0,i_b[30]}+{5'h0,i_b[31]}); |
assign w_popc_result[31:6] = 26'h00; |
|
// Prelogic for our flags registers |
wire z, n, v; |
reg c, pre_sign, set_ovfl; |
reg c, pre_sign, set_ovfl, keep_sgn_on_ovfl; |
always @(posedge i_clk) |
if (i_ce) // 1 LUT |
set_ovfl =(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD |
||(i_op == 4'h6) // LSL |
||(i_op == 4'h5)); // LSR |
always @(posedge i_clk) |
if (i_ce) // 1 LUT |
keep_sgn_on_ovfl<= |
(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP |
||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD |
|
wire [63:0] mpy_result; // Where we dump the multiply result |
reg mpyhi; // Return the high half of the multiply |
110,7 → 101,7
// this will cost a minimum of 132 6-LUTs. |
|
wire this_is_a_multiply_op; |
assign this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'h8)); |
assign this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc)); |
|
generate |
if (IMPLEMENT_MPY == 0) |
137,8 → 128,8
assign mpy_result = r_mpy_a_input * r_mpy_b_input; |
assign mpybusy = 1'b0; |
|
reg mpypipe; |
initial mpypipe = 1'b0; |
reg mpypipe; |
always @(posedge i_clk) |
if (i_rst) |
mpypipe <= 1'b0; |
214,6 → 205,7
reg [2:0] mpypipe; |
|
// First clock, latch in the inputs |
initial mpypipe = 3'b0; |
always @(posedge i_clk) |
begin |
// mpypipe indicates we have a multiply in the |
333,13 → 325,11
4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR |
4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL |
4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR |
4'b1000: o_c <= mpy_result[31:0]; // MPY |
4'b1000: o_c <= w_brev_result; // BREV |
4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO |
4'b1010: o_c <= mpy_result[63:32]; // MPYHU |
4'b1011: o_c <= mpy_result[63:32]; // MPYHS |
4'b1100: o_c <= w_brev_result; // BREV |
4'b1101: o_c <= w_popc_result; // POPC |
4'b1110: o_c <= w_rol_result; // ROL |
4'b1010: o_c <= mpy_result[63:32]; // MPYHU |
4'b1011: o_c <= mpy_result[63:32]; // MPYHS |
4'b1100: o_c <= mpy_result[31:0]; // MPY |
default: o_c <= i_b; // MOV, LDI |
endcase |
end else // if (mpydone) |
359,8 → 349,9
assign z = (o_c == 32'h0000); |
assign n = (o_c[31]); |
assign v = (set_ovfl)&&(pre_sign != o_c[31]); |
wire vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]); |
|
assign o_f = { v, n, c, z }; |
assign o_f = { v, n^vx, c, z }; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
/trunk/rtl/cpu/div.v
1,18 → 1,77
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: div.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
// |
// Purpose: Provide an Integer divide capability to the Zip CPU. |
// Purpose: Provide an Integer divide capability to the Zip CPU. Provides |
// for both signed and unsigned divide. |
// |
// Steps: |
// i_rst The DIVide unit starts in idle. It can also be placed into an |
// idle by asserting the reset input. |
// |
// i_wr When i_rst is asserted, a divide begins. On the next clock: |
// |
// o_busy is set high so everyone else knows we are at work and they can |
// wait for us to complete. |
// |
// pre_sign is set to true if we need to do a signed divide. In this |
// case, we take a clock cycle to turn the divide into an unsigned |
// divide. |
// |
// o_quotient, a place to store our result, is initialized to all zeros. |
// |
// r_dividend is set to the numerator |
// |
// r_divisor is set to 2^31 * the denominator (shift left by 31, or add |
// 31 zeros to the right of the number. |
// |
// pre_sign When true (clock cycle after i_wr), a clock cycle is used |
// to take the absolute value of the various arguments (r_dividend |
// and r_divisor), and to calculate what sign the output result |
// should be. |
// |
// |
// At this point, the divide is has started. The divide works by walking |
// through every shift of the |
// |
// DIVIDEND over the |
// DIVISOR |
// |
// If the DIVISOR is bigger than the dividend, the divisor is shifted |
// right, and nothing is done to the output quotient. |
// |
// DIVIDEND |
// DIVISOR |
// |
// This repeats, until DIVISOR is less than or equal to the divident, as in |
// |
// DIVIDEND |
// DIVISOR |
// |
// At this point, if the DIVISOR is less than the dividend, the |
// divisor is subtracted from the dividend, and the DIVISOR is again |
// shifted to the right. Further, a '1' bit gets set in the output |
// quotient. |
// |
// Once we've done this for 32 clocks, we've accumulated our answer into |
// the output quotient, and we can proceed to the next step. If the |
// result will be signed, the next step negates the quotient, otherwise |
// it returns the result. |
// |
// On the clock when we are done, o_busy is set to false, and o_valid set |
// to true. (It is a violation of the ZipCPU internal protocol for both |
// busy and valid to ever be true on the same clock. It is also a |
// violation for busy to be false with valid true thereafter.) |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
24,12 → 83,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// `include "cpudefs.v" |
// |
module div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator, |
56,12 → 121,13
|
reg r_sign, pre_sign, r_z, r_c, last_bit; |
reg [(LGBW-1):0] r_bit; |
|
reg zero_divisor; |
initial zero_divisor = 1'b0; |
always @(posedge i_clk) |
zero_divisor <= (r_divisor == 0)&&(r_busy); |
|
// The Divide logic begins with r_busy. We use r_busy to determine |
// whether or not the divide is in progress, vs being complete. |
// Here, we clear r_busy on any reset and set it on i_wr (the request |
// do to a divide). The divide ends when we are on the last bit, |
// or equivalently when we discover we are dividing by zero. |
initial r_busy = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
71,6 → 137,12
else if ((last_bit)||(zero_divisor)) |
r_busy <= 1'b0; |
|
// o_busy is very similar to r_busy, save for some key differences. |
// Primary among them is that o_busy needs to (possibly) be true |
// for an extra clock after r_busy clears. This would be that extra |
// clock where we negate the result (assuming a signed divide, and that |
// the result is supposed to be negative.) Otherwise, the two are |
// identical. |
initial o_busy = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
82,19 → 154,50
else if (~r_busy) |
o_busy <= 1'b0; |
|
// If we are asked to divide by zero, we need to halt. The sooner |
// we halt and report the error, the better. Hence, here we look |
// for a zero divisor while being busy. The always above us will then |
// look at this and halt a divide in the middle if we are trying to |
// divide by zero. |
// |
// Note that this works off of the 2BW-1 length vector. If we can |
// simplify that, it should simplify our logic as well. |
initial zero_divisor = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(i_wr)) |
// zero_divisor <= (r_divisor == 0)&&(r_busy); |
if (i_rst) |
zero_divisor <= 1'b0; |
else if (i_wr) |
zero_divisor <= (i_denominator == 0); |
else if (!r_busy) |
zero_divisor <= 1'b0; |
|
// o_valid is part of the ZipCPU protocol. It will be set to true |
// anytime our answer is valid and may be used by the calling module. |
// Indeed, the ZipCPU will halt (and ignore us) once the i_wr has been |
// set until o_valid gets set. |
// |
// Here, we clear o_valid on a reset, and any time we are on the last |
// bit while busy (provided the sign is zero, or we are dividing by |
// zero). Since o_valid is self-clearing, we don't need to clear |
// it on an i_wr signal. |
initial o_valid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
o_valid <= 1'b0; |
else if (r_busy) |
begin |
if ((last_bit)||(zero_divisor)) |
o_valid <= (zero_divisor)||(~r_sign); |
o_valid <= (zero_divisor)||(!r_sign); |
end else if (r_sign) |
begin |
o_valid <= (~zero_divisor); // 1'b1; |
o_valid <= (!zero_divisor); // 1'b1; |
end else |
o_valid <= 1'b0; |
|
// Division by zero error reporting. Anytime we detect a zero divisor, |
// we set our output error, and then hold it until we are valid and |
// everything clears. |
initial o_err = 1'b0; |
always @(posedge i_clk) |
if((i_rst)||(o_valid)) |
104,91 → 207,145
else |
o_err <= 1'b0; |
|
// r_bit |
// |
// Keep track of which "bit" of our divide we are on. This number |
// ranges from 31 down to zero. On any write, we set ourselves to |
// 5'h1f. Otherwise, while we are busy (but not within the pre-sign |
// adjustment stage), we subtract one from our value on every clock. |
always @(posedge i_clk) |
if ((r_busy)&&(!pre_sign)) |
r_bit <= r_bit + {(LGBW){1'b1}}; |
else |
r_bit <= {(LGBW){1'b1}}; |
|
// last_bit |
// |
// This logic replaces a lot of logic that was inside our giant state |
// machine with ... something simpler. In particular, we'll use this |
// logic to determine we are processing our last bit. The only trick |
// is, this bit needs to be set whenever (r_busy) and (r_bit == 0), |
// hence we need to set on (r_busy) and (r_bit == 1) so as to be set |
// when (r_bit == 0). |
initial last_bit = 1'b0; |
always @(posedge i_clk) |
if ((i_wr)||(pre_sign)||(i_rst)) |
if (r_busy) |
last_bit <= (r_bit == {{(LGBW-1){1'b0}},1'b1}); |
else |
last_bit <= 1'b0; |
else if (r_busy) |
last_bit <= (r_bit == {{(LGBW-1){1'b0}},1'b1}); |
|
// pre_sign |
// |
// This is part of the state machine. pre_sign indicates that we need |
// a extra clock to take the absolute value of our inputs. It need only |
// be true for the one clock, and then it must clear itself. |
initial pre_sign = 1'b0; |
always @(posedge i_clk) |
// if (i_rst) r_busy <= 1'b0; |
// else |
if (i_wr) |
begin |
// |
// Set our values upon an initial command. Here's |
// where we come in and start. |
// |
// r_busy <= 1'b1; |
// |
o_quotient <= 0; |
r_bit <= {(LGBW){1'b1}}; |
r_divisor <= { i_denominator, {(BW-1){1'b0}} }; |
r_dividend <= i_numerator; |
r_sign <= 1'b0; |
pre_sign <= i_signed; |
else |
pre_sign <= 1'b0; |
|
// As a result of our operation, we need to set the flags. The most |
// difficult of these is the "Z" flag indicating that the result is |
// zero. Here, we'll use the same logic that sets the low-order |
// bit to clear our zero flag, and leave the zero flag set in all |
// other cases. Well ... not quite. If we need to flip the sign of |
// our value, then we can't quite clear the zero flag ... yet. |
always @(posedge i_clk) |
if((r_busy)&&(r_divisor[(2*BW-2):(BW)] == 0)&&(!diff[BW])) |
// If we are busy, the upper bits of our divisor are |
// zero (i.e., we got the shift right), and the top |
// (carry) bit of the difference is zero (no overflow), |
// then we could subtract our divisor from our dividend |
// and hence we add a '1' to the quotient, while setting |
// the zero flag to false. |
r_z <= 1'b0; |
else if ((!r_busy)&&(!r_sign)) |
r_z <= 1'b1; |
end else if (pre_sign) |
|
// r_dividend |
// This is initially the numerator. On a signed divide, it then becomes |
// the absolute value of the numerator. We'll subtract from this value |
// the divisor shifted as appropriate for every output bit we are |
// looking for--just as with traditional long division. |
always @(posedge i_clk) |
if (pre_sign) |
begin |
// |
// Note that we only come in here, for one clock, if |
// our initial value may have been signed. If we are |
// doing an unsigned divide, we then skip this step. |
// |
r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)])); |
// Negate our dividend if necessary so that it becomes |
// a magnitude only value |
// If we are doing a signed divide, then take the |
// absolute value of the dividend |
if (r_dividend[BW-1]) |
r_dividend <= -r_dividend; |
// Do the same with the divisor--rendering it into |
// a magnitude only. |
// The begin/end block is important so we don't lose |
// the fact that on an else we don't do anything. |
end else if((r_busy)&&(r_divisor[(2*BW-2):(BW)]==0)&&(!diff[BW])) |
// This is the condition whereby we set a '1' in our |
// output quotient, and we subtract the (current) |
// divisor from our dividend. (The difference is |
// already kept in the diff vector above.) |
r_dividend <= diff[(BW-1):0]; |
else if (!r_busy) |
// Once we are done, and r_busy is no longer high, we'll |
// always accept new values into our dividend. This |
// guarantees that, when i_wr is set, the new value |
// is already set as desired. |
r_dividend <= i_numerator; |
|
initial r_divisor = 0; |
always @(posedge i_clk) |
if (pre_sign) |
begin |
if (r_divisor[(2*BW-2)]) |
r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)]; |
// |
// We only do this stage for a single clock, so go on |
// with the rest of the divide otherwise. |
pre_sign <= 1'b0; |
r_divisor[(2*BW-2):(BW-1)] |
<= -r_divisor[(2*BW-2):(BW-1)]; |
end else if (r_busy) |
r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] }; |
else |
r_divisor <= { i_denominator, {(BW-1){1'b0}} }; |
|
// r_sign |
// is a flag for our state machine control(s). r_sign will be set to |
// true any time we are doing a signed divide and the result must be |
// negative. In that case, we take a final logic stage at the end of |
// the divide to negate the output. This flag is what tells us we need |
// to do that. r_busy will be true during the divide, then when r_busy |
// goes low, r_sign will be checked, then the idle/reset stage will have |
// been reached. For this reason, we cannot set r_sign unless we are |
// up to something. |
initial r_sign = 1'b0; |
always @(posedge i_clk) |
if (pre_sign) |
r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)])); |
else if (r_busy) |
r_sign <= (r_sign)&&(!zero_divisor); |
else |
r_sign <= 1'b0; |
|
always @(posedge i_clk) |
if (r_busy) |
begin |
// While the divide is taking place, we examine each bit |
// in turn here. |
// |
r_bit <= r_bit + {(LGBW){1'b1}}; // r_bit = r_bit - 1; |
r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] }; |
if (|r_divisor[(2*BW-2):(BW)]) |
o_quotient <= { o_quotient[(BW-2):0], 1'b0 }; |
if ((r_divisor[(2*BW-2):(BW)] == 0)&&(!diff[BW])) |
begin |
end else if (diff[BW]) |
begin |
// |
// diff = r_dividend - r_divisor[(BW-1):0]; |
// |
// If this value was negative, there wasn't |
// enough value in the dividend to support |
// pulling off a bit. We'll move down a bit |
// therefore and try again. |
// |
end else begin |
// |
// Put a '1' into our output accumulator. |
// Subtract the divisor from the dividend, |
// and then move on to the next bit |
// |
r_dividend <= diff[(BW-1):0]; |
o_quotient[r_bit[(LGBW-1):0]] <= 1'b1; |
r_z <= 1'b0; |
o_quotient[0] <= 1'b1; |
end |
r_sign <= (r_sign)&&(~zero_divisor); |
end else if (r_sign) |
begin |
r_sign <= 1'b0; |
o_quotient <= -o_quotient; |
end |
else |
o_quotient <= 0; |
|
// Set Carry on an exact divide |
wire w_n; |
// Perhaps nothing uses this, but ... well, I suppose we could remove |
// this logic eventually, just ... not yet. |
always @(posedge i_clk) |
r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0)); |
|
// The last flag: Negative. This flag is set assuming that the result |
// of the divide was negative (i.e., the high order bit is set). This |
// will also be true of an unsigned divide--if the high order bit is |
// ever set upon completion. Indeed, you might argue that there's no |
// logic involved. |
wire w_n; |
assign w_n = o_quotient[(BW-1)]; |
|
assign o_flags = { 1'b0, w_n, r_c, r_z }; |
/trunk/rtl/cpu/icontrol.v
52,7 → 52,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
64,6 → 64,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
70,6 → 75,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module icontrol(i_clk, i_reset, i_wr, i_proc_bus, o_proc_bus, |
i_brd_ints, o_interrupt); |
parameter IUSED = 15; |
/trunk/rtl/cpu/idecode.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: idecode.v |
// |
17,9 → 17,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
31,14 → 31,20
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`define CPU_SP_REG 4'hd |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
// |
49,6 → 55,7
module idecode(i_clk, i_rst, i_ce, i_stalled, |
i_instruction, i_gie, i_pc, i_pf_valid, |
i_illegal, |
o_valid, |
o_phase, o_illegal, |
o_pc, o_gie, |
o_dcdR, o_dcdA, o_dcdB, o_I, o_zI, |
56,7 → 63,8
o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock, |
o_wR, o_rA, o_rB, |
o_early_branch, o_branch_pc, o_ljmp, |
o_pipe |
o_pipe, |
o_sim, o_sim_immv |
); |
parameter ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1, |
IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH; |
65,9 → 73,9
input i_gie; |
input [(AW-1):0] i_pc; |
input i_pf_valid, i_illegal; |
output wire o_phase; |
output wire o_valid, o_phase; |
output reg o_illegal; |
output reg [(AW-1):0] o_pc; |
output reg [AW:0] o_pc; |
output reg o_gie; |
output reg [6:0] o_dcdR, o_dcdA, o_dcdB; |
output wire [31:0] o_I; |
82,6 → 90,8
output wire [(AW-1):0] o_branch_pc; |
output wire o_ljmp; |
output wire o_pipe; |
output reg o_sim /* verilator public_flat */; |
output reg [22:0] o_sim_immv /* verilator public_flat */; |
|
wire dcdA_stall, dcdB_stall, dcdF_stall; |
wire o_dcd_early_branch; |
96,25 → 106,25
|
|
wire [4:0] w_op; |
wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop, |
w_mpy; |
wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, |
w_noop, w_lock; |
wire [4:0] w_dcdR, w_dcdB, w_dcdA; |
wire w_dcdR_pc, w_dcdR_cc; |
wire w_dcdA_pc, w_dcdA_cc; |
wire w_dcdB_pc, w_dcdB_cc; |
wire [3:0] w_cond; |
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP, w_sto; |
wire w_wF, w_mem, w_sto, w_div, w_fpu; |
wire w_wR, w_rA, w_rB, w_wR_n; |
wire w_ljmp, w_ljmp_dly; |
wire w_ljmp, w_ljmp_dly, w_cis_ljmp; |
wire [31:0] iword; |
|
|
`ifdef OPT_VLIW |
reg [16:0] r_nxt_half; |
`ifdef OPT_CIS |
reg [15:0] r_nxt_half; |
assign iword = (o_phase) |
// set second half as a NOOP ... but really |
// set second half as a NOOP ... but really |
// shouldn't matter |
? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 } |
? { r_nxt_half[15:0], i_instruction[15:0] } |
: i_instruction; |
`else |
assign iword = { 1'b0, i_instruction[30:0] }; |
122,52 → 132,110
|
generate |
if (EARLY_BRANCHING != 0) |
begin |
`ifdef OPT_CIS |
reg r_pre_ljmp; |
always @(posedge i_clk) |
if ((i_rst)||(o_early_branch)) |
r_pre_ljmp <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_pre_ljmp <= (!o_phase)&&(i_instruction[31]) |
&&(i_instruction[14:0] == 15'h7cf8); |
else if (i_ce) |
r_pre_ljmp <= 1'b0; |
|
assign w_cis_ljmp = r_pre_ljmp; |
`else |
assign w_cis_ljmp = 1'b0; |
`endif |
// 0.1111.10010.000.1.1111.000000000... |
// 0111.1100.1000.0111.11000.... |
assign w_ljmp = (iword == 32'h7c87c000); |
else |
end else begin |
assign w_cis_ljmp = 1'b0; |
assign w_ljmp = 1'b0; |
end |
endgenerate |
|
`ifdef OPT_CIS |
`ifdef VERILATOR |
wire [4:0] w_cis_op; |
always @(iword) |
if (!iword[31]) |
w_cis_op = w_op; |
else case(iword[26:24]) |
3'h0: w_cis_op = 5'h00; |
3'h1: w_cis_op = 5'h01; |
3'h2: w_cis_op = 5'h02; |
3'h3: w_cis_op = 5'h10; |
3'h4: w_cis_op = 5'h12; |
3'h5: w_cis_op = 5'h13; |
3'h6: w_cis_op = 5'h18; |
3'h7: w_cis_op = 5'h0d; |
endcase |
`else |
reg [4:0] w_cis_op; |
always @(iword,w_op) |
if (!iword[31]) |
w_cis_op <= w_op; |
else case(iword[26:24]) |
3'h0: w_cis_op <= 5'h00; |
3'h1: w_cis_op <= 5'h01; |
3'h2: w_cis_op <= 5'h02; |
3'h3: w_cis_op <= 5'h10; |
3'h4: w_cis_op <= 5'h12; |
3'h5: w_cis_op <= 5'h13; |
3'h6: w_cis_op <= 5'h18; |
3'h7: w_cis_op <= 5'h0d; |
endcase |
`endif |
`else |
wire [4:0] w_cis_op; |
assign w_cis_op = w_op; |
`endif |
|
assign w_op= iword[26:22]; |
assign w_mov = (w_op == 5'h0f); |
assign w_ldi = (w_op[4:1] == 4'hb); |
assign w_brev = (w_op == 5'hc); |
assign w_cmptst = (w_op[4:1] == 4'h8); |
assign w_ldilo = (w_op[4:0] == 5'h9); |
assign w_mpy = ((w_op[4:1]==4'h5)||(w_op[4:0]==5'h08)); |
assign w_ALU = (~w_op[4]); |
assign w_mov = (w_cis_op == 5'h0d); |
assign w_ldi = (w_cis_op[4:1] == 4'hc); |
assign w_brev = (w_cis_op == 5'h8); |
assign w_cmptst = (w_cis_op[4:1] == 4'h8); |
assign w_ldilo = (w_cis_op[4:0] == 5'h9); |
assign w_ALU = (!w_cis_op[4]) // anything with [4]==0, but ... |
&&(w_cis_op[3:1] != 3'h7); // not the divide |
|
// 4 LUTs |
|
// w_dcdR (4 LUTs) |
// |
// What register will we be placing results into (if at all)? |
// |
// Two parts to the result register: the register set, given for |
// moves in iword[18] but only for the supervisor, and the other |
// four bits encoded in the instruction. |
// |
`ifdef OPT_NO_USERMODE |
assign w_dcdR = { 1'b0, iword[30:27] }; |
`else |
assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
assign w_dcdR = { ((!iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie, |
iword[30:27] }; |
`endif |
// 2 LUTs |
// |
// If the result register is either CC or PC, and this would otherwise |
// be a floating point instruction with floating point opcode of 0, |
// then this is a NOOP. |
assign w_noop = (w_op[4:0] == 5'h18)&&( |
assign w_lock = (!iword[31])&&(w_op[4:0]==5'h1d)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7)) |
||(IMPLEMENT_FPU==0)); |
assign w_noop = (!iword[31])&&(w_op[4:0] == 5'h1f)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1] == 3'h7)) |
||(IMPLEMENT_FPU==0)); |
|
`ifdef OPT_NO_USERMODE |
assign w_dcdB = { 1'b0, iword[17:14] }; |
`else |
// 4 LUTs |
assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie, |
iword[17:14] }; |
`endif |
// dcdB - What register is used in the opB? |
// |
assign w_dcdB[4] = ((!iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie; |
assign w_dcdB[3:0]= (iword[31]) |
? (((!iword[23])&&(iword[26:25]==2'b10)) |
? `CPU_SP_REG : iword[22:19]) |
: iword[17:14]; |
|
// 0 LUTs |
assign w_dcdA = w_dcdR; |
assign w_dcdA = w_dcdR; // on ZipCPU, A is always result reg |
// 2 LUTs, 1 delay each |
assign w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG}); |
assign w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG}); |
175,8 → 243,8
assign w_dcdA_pc = w_dcdR_pc; |
assign w_dcdA_cc = w_dcdR_cc; |
// 2 LUTs, 1 delays each |
assign w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG); |
assign w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG); |
assign w_dcdB_pc = (w_rB)&&(w_dcdB[3:0] == `CPU_PC_REG); |
assign w_dcdB_cc = (w_rB)&&(w_dcdB[3:0] == `CPU_CC_REG); |
|
// Under what condition will we execute this |
// instruction? Only the load immediate instruction |
183,46 → 251,54
// is completely unconditional. |
// |
// 3+4 LUTs |
assign w_cond = (w_ldi) ? 4'h8 : |
(iword[31])?{(iword[20:19]==2'b00), |
1'b0,iword[20:19]} |
: { (iword[21:19]==3'h0), iword[21:19] }; |
assign w_cond = ((w_ldi)||(iword[31])) ? 4'h8 : |
{ (iword[21:19]==3'h0), iword[21:19] }; |
|
// 1 LUT |
assign w_dcdM = (w_op[4:1] == 4'h9); |
assign w_sto = (w_dcdM)&&(w_op[0]); |
assign w_mem = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00); |
assign w_sto = (w_mem)&&( w_cis_op[0]); |
// 1 LUT |
assign w_dcdDV = (w_op[4:1] == 4'ha); |
// 1 LUT |
assign w_dcdFP = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7); |
// 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before) |
// Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV |
assign w_rA = (w_dcdFP) |
// Divide's read A |
||(w_dcdDV) |
// ALU read's A, unless it's a MOV to A |
// This includes LDIHI/LDILO |
||((~w_op[4])&&(w_op[3:0]!=4'hf)&&(!w_brev)) |
// STO's read A |
||((w_dcdM)&&(w_op[0])) |
// Test/compares |
assign w_div = (!iword[31])&&(w_op[4:1] == 4'h7); |
// 2 LUTs |
assign w_fpu = (!iword[31])&&(w_op[4:3] == 2'b11) |
&&(w_dcdR[3:1] != 3'h7)&&(w_op[2:1] != 2'b00); |
// |
// rA - do we need to read register A? |
assign w_rA = // Floating point reads reg A |
((w_fpu)&&(w_cis_op[4:1] != 4'hf)) |
// Divide's read A |
||(w_div) |
// ALU ops read A, |
// except for MOV's and BREV's which don't |
||((w_ALU)&&(!w_brev)&&(!w_mov)) |
// STO's read A |
||(w_sto) |
// Test/compares |
||(w_cmptst); |
// rB -- do we read a register for operand B? Specifically, do we |
// add the registers value to the immediate to create opB? |
assign w_rB = (w_mov) |
||((!iword[31])&&(iword[18])&&(!w_ldi)) |
||(( iword[31])&&(iword[23])&&(!w_ldi)) |
// If using compressed instruction sets, |
// we *always* read on memory operands. |
||(( iword[31])&&(w_mem)); |
// wR -- will we be writing our result back? |
// wR_n = !wR |
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR |
assign w_wR_n = (w_sto) |
||((!iword[31])&&(w_cis_op[4:3]==2'b11) |
&&(w_cis_op[2:1]!=2'b00) |
&&(w_dcdR[3:1]==3'h7)) |
||(w_cmptst); |
// 1 LUTs -- do we read a register for operand B? Specifically, do |
// we need to stall if the register is not (yet) ready? |
assign w_rB = (w_mov)||((iword[18])&&(~w_ldi)); |
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR |
assign w_wR_n = (w_sto)||(w_cmptst) |
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)); |
assign w_wR = ~w_wR_n; |
// |
// 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits) |
// |
// This'd be 4 LUTs, save that we have the carve out for NOOPs |
// and writes to the PC/CC register(s). |
// wF -- do we write flags when we are done? |
// |
assign w_wF = (w_cmptst) |
||((w_cond[3])&&((w_dcdFP)||(w_dcdDV) |
||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev) |
&&(iword[30:28] != 3'h7)))); |
||((w_cond[3])&&((w_fpu)||(w_div) |
||((w_ALU)&&(!w_mov)&&(!w_ldilo)&&(!w_brev) |
&&(w_dcdR[3:1] != 3'h7)))); |
|
// Bottom 13 bits: no LUT's |
// w_dcd[12: 0] -- no LUTs |
234,16 → 310,23
wire w_Iz; |
|
assign w_fullI = (w_ldi) ? { iword[22:0] } // LDI |
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move |
// MOVE immediates have one less bit |
:((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } |
// Normal Op-B immediate ... 18 or 14 bits |
:((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] } |
: { {(23-14){iword[13]}}, iword[13:0] } |
)); |
|
`ifdef OPT_VLIW |
wire [5:0] w_halfI; |
assign w_halfI = (w_ldi) ? iword[5:0] |
:((iword[5]) ? 6'h00 : {iword[4],iword[4:0]}); |
assign w_I = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI; |
`ifdef OPT_CIS |
wire [7:0] w_halfbits; |
assign w_halfbits = iword[23:16]; |
|
wire [7:0] w_halfI; |
assign w_halfI = (iword[26:24]==3'h6) ? w_halfbits[7:0] |
:(w_halfbits[7])? |
{ {(6){w_halfbits[2]}}, w_halfbits[1:0]} |
:{ w_halfbits[6], w_halfbits[6:0] }; |
assign w_I = (iword[31])?{{(23-8){w_halfI[7]}}, w_halfI }:w_fullI; |
`else |
assign w_I = w_fullI; |
`endif |
250,12 → 333,12
assign w_Iz = (w_I == 0); |
|
|
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
// |
// The o_phase parameter is special. It needs to let the software |
// following know that it cannot break/interrupt on an o_phase asserted |
// instruction, lest the break take place between the first and second |
// half of a VLIW instruction. To do this, o_phase must be asserted |
// half of a CIS instruction. To do this, o_phase must be asserted |
// when the first instruction half is valid, but not asserted on either |
// a 32-bit instruction or the second half of a 2x16-bit instruction. |
reg r_phase; |
265,7 → 348,10
||(o_early_branch)||(w_ljmp_dly)) |
r_phase <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_phase <= (o_phase)? 1'b0:(i_instruction[31]); |
r_phase <= (o_phase)? 1'b0 |
: ((i_instruction[31])&&(i_pf_valid)); |
else if (i_ce) |
r_phase <= 1'b0; |
// Phase is '1' on the first instruction of a two-part set |
// But, due to the delay in processing, it's '1' when our output is |
// valid for that first part, but that'll be the same time we |
284,32 → 370,32
o_illegal <= 1'b0; |
else if (i_ce) |
begin |
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
o_illegal <= (i_illegal); |
`else |
o_illegal <= ((i_illegal) || (i_instruction[31])); |
`endif |
if ((IMPLEMENT_MPY==0)&&(w_mpy)) |
if ((IMPLEMENT_MPY==0)&&((w_cis_op[4:1]==4'h5)||(w_cis_op[4:0]==5'h0c))) |
o_illegal <= 1'b1; |
|
if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV)) |
if ((IMPLEMENT_DIVIDE==0)&&(w_div)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7)) |
else if ((IMPLEMENT_DIVIDE!=0)&&(w_div)&&(w_dcdR[3:1]==3'h7)) |
o_illegal <= 1'b1; |
|
|
if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7)) |
if ((IMPLEMENT_FPU==0)&&(w_fpu)) |
o_illegal <= 1'b1; |
else if ((IMPLEMENT_FPU==0)&&(w_dcdFP)) |
o_illegal <= 1'b1; |
|
if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7) |
if ((w_cis_op[4:3]==2'b11)&&(w_cis_op[2:1]!=2'b00) |
&&(w_dcdR[3:1]==3'h7) |
&&( |
(w_op[2:0] != 3'h1) // BREAK |
(w_cis_op[2:0] != 3'h4) // BREAK |
`ifdef OPT_PIPELINED |
&&(w_op[2:0] != 3'h2) // LOCK |
&&(w_cis_op[2:0] != 3'h5) // LOCK |
`endif |
&&(w_op[2:0] != 3'h0))) // NOOP |
// SIM instructions are always illegal |
&&(w_cis_op[2:0] != 3'h7))) // NOOP |
o_illegal <= 1'b1; |
end |
|
317,16 → 403,23
always @(posedge i_clk) |
if (i_ce) |
begin |
`ifdef OPT_VLIW |
if (~o_phase) |
`ifdef OPT_CIS |
if (!o_phase) |
o_gie<= i_gie; |
|
if (iword[31]) |
begin |
o_gie<= i_gie; |
// i.e. dcd_pc+1 |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
if (o_phase) |
o_pc <= o_pc + 1'b1; |
else if (i_pf_valid) |
o_pc <= { i_pc, 1'b1 }; |
end else begin |
// The normal, non-CIS case |
o_pc <= { i_pc + 1'b1, 1'b0 }; |
end |
`else |
o_gie<= i_gie; |
o_pc <= i_pc+{{(AW-1){1'b0}},1'b1}; |
o_pc <= { i_pc + 1'b1, 1'b0 }; |
`endif |
|
// Under what condition will we execute this |
344,12 → 437,12
// the ALU. Likewise, the two compare instructions |
// CMP and TST becomes SUB and AND here as well. |
// We keep only the bottom four bits, since we've |
// already done the rest of the decode necessary to |
// already done the rest of the decode necessary to |
// settle between the other instructions. For example, |
// o_FP plus these four bits uniquely defines the FP |
// instruction, o_DV plus the bottom of these defines |
// the divide, etc. |
o_op <= (w_ldi)||(w_noop)? 4'hf:w_op[3:0]; |
o_op <= ((w_ldi)||(w_noop))? 4'hd : w_cis_op[3:0]; |
|
// Default values |
o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR}; |
361,29 → 454,34
r_I <= w_I; |
o_zI <= w_Iz; |
|
// Turn a NOOP into an ALU operation--subtract in |
// Turn a NOOP into an ALU operation--subtract in |
// particular, although it doesn't really matter as long |
// as it doesn't take longer than one clock. Note |
// also that this depends upon not setting any registers |
// or flags, which should already be true. |
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT |
o_M <= w_dcdM; |
o_DV <= w_dcdDV; |
o_FP <= w_dcdFP; |
|
o_break <= (w_op[4:0]==5'b11001)&&( |
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); |
o_M <= w_mem; |
o_DV <= w_div; |
o_FP <= w_fpu; |
|
o_break <= (!iword[31])&&(w_op[4:0]==5'h1c)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7)) |
||(IMPLEMENT_FPU==0)); |
`ifdef OPT_PIPELINED |
r_lock <= (w_op[4:0]==5'b11010)&&( |
((IMPLEMENT_FPU>0)&&(w_dcdR[3:1]==3'h7)) |
||(IMPLEMENT_FPU==0)); |
r_lock <= w_lock; |
`endif |
`ifdef OPT_VLIW |
r_nxt_half <= { iword[31], iword[13:5], |
((iword[21])? iword[20:19] : 2'h0), |
iword[4:0] }; |
`ifdef OPT_CIS |
r_nxt_half <= { iword[31], iword[14:0] }; |
`endif |
|
`ifdef VERILATOR |
// Support the SIM instruction(s) |
o_sim <= (!iword[31])&&(w_op[4:1] == 4'hf) |
&&(w_dcdR[3:1] == 3'h7); |
`else |
o_sim <= 1'b0; |
`endif |
o_sim_immv <= iword[22:0]; |
end |
|
`ifdef OPT_PIPELINED |
402,6 → 500,10
always @(posedge i_clk) |
if (i_rst) |
r_ljmp <= 1'b0; |
`ifdef OPT_CIS |
else if ((i_ce)&&(o_phase)) |
r_ljmp <= w_cis_ljmp; |
`endif |
else if ((i_ce)&&(i_pf_valid)) |
r_ljmp <= (w_ljmp); |
assign o_ljmp = r_ljmp; |
414,17 → 516,14
if (r_ljmp) |
// LOD (PC),PC |
r_early_branch <= 1'b1; |
else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3])) |
else if ((!iword[31])&&(iword[30:27]==`CPU_PC_REG) |
&&(w_cond[3])) |
begin |
if (w_op[4:1] == 4'hb) // LDI to PC |
// LDI x,PC |
r_early_branch <= 1'b1; |
else if ((w_op[4:0]==5'h02)&&(~iword[18])) |
if ((w_op[4:0]==5'h02)&&(!iword[18])) |
// Add x,PC |
r_early_branch <= 1'b1; |
else begin |
else |
r_early_branch <= 1'b0; |
end |
end else |
r_early_branch <= 1'b0; |
end else if (i_ce) |
434,12 → 533,10
if (i_ce) |
begin |
if (r_ljmp) |
r_branch_pc <= iword[(AW-1):0]; |
else if (w_ldi) // LDI |
r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]}; |
r_branch_pc <= iword[(AW+1):2]; |
else // Add x,PC |
r_branch_pc <= i_pc |
+ {{(AW-17){iword[17]}},iword[16:0]} |
+ {{(AW-15){iword[17]}},iword[16:2]} |
+ {{(AW-1){1'b0}},1'b1}; |
end |
|
469,15 → 566,26
initial r_pipe = 1'b0; |
always @(posedge i_clk) |
if (i_ce) |
r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31]) |
&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22]) |
&&(i_instruction[17:14] == o_dcdB[3:0]) |
&&(i_instruction[17:14] != o_dcdA[3:0]) |
r_pipe <= (r_valid)&&((i_pf_valid)||(o_phase)) |
// Both must be memory operations |
&&(w_mem)&&(o_M) |
// Both must be writes, or both stores |
&&(o_op[0] == w_cis_op[0]) |
// Both must be register ops |
&&(w_rB) |
// Both must use the same register for B |
&&(w_dcdB[3:0] == o_dcdB[3:0]) |
// But ... the result can never be B |
&&((o_op[0]) |
||(w_dcdB[3:0] != o_dcdA[3:0])) |
// Needs to be to the mode, supervisor or user |
&&(i_gie == o_gie) |
// Same condition, or no condition before |
&&((i_instruction[21:19]==o_cond[2:0]) |
||(o_cond[2:0] == 3'h0)) |
&&((i_instruction[13:0]==r_I[13:0]) |
||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1))); |
// Same immediate |
&&((w_I[13:2]==r_I[13:2]) |
||({1'b0, w_I[13:2]}==(r_I[13:2]+12'h1))); |
assign o_pipe = r_pipe; |
`else |
assign o_pipe = 1'b0; |
486,14 → 594,15
always @(posedge i_clk) |
if (i_rst) |
r_valid <= 1'b0; |
else if ((i_ce)&&(o_ljmp)) |
else if (i_ce) |
r_valid <= ((i_pf_valid)||(o_phase)||(i_illegal)) |
&&(!o_ljmp)&&(!o_early_branch); |
else if (!i_stalled) |
r_valid <= 1'b0; |
else if ((i_ce)&&(i_pf_valid)) |
r_valid <= 1'b1; |
else if (~i_stalled) |
r_valid <= 1'b0; |
|
|
assign o_valid = r_valid; |
|
|
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] }; |
|
endmodule |
/trunk/rtl/cpu/memops.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: memops.v |
// |
17,9 → 17,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
31,25 → 31,31
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module memops(i_clk, i_rst, i_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0; |
parameter ADDRESS_WIDTH=30, IMPLEMENT_LOCK=0, WITH_LOCAL_BUS=0; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_stb, i_lock; |
// CPU interface |
input i_op; |
input [2:0] i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [4:0] i_oreg; |
67,6 → 73,7
output reg o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
output reg [3:0] o_wb_sel; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
73,8 → 80,8
|
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_stb)&&(i_addr[31:24]==8'hff); |
assign gbl_stb = (i_stb)&&(i_addr[31:24]!=8'hff); |
assign lcl_stb = (i_stb)&&(WITH_LOCAL_BUS!=0)&&(i_addr[31:24]==8'hff); |
assign gbl_stb = (i_stb)&&((WITH_LOCAL_BUS==0)||(i_addr[31:24]!=8'hff)); |
|
initial r_wb_cyc_gbl = 1'b0; |
initial r_wb_cyc_lcl = 1'b0; |
105,20 → 112,61
o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall); |
else |
o_wb_stb_lcl <= lcl_stb; // Grab wishbone on new operation |
|
reg [3:0] r_op; |
always @(posedge i_clk) |
if (i_stb) |
begin |
o_wb_we <= i_op; |
o_wb_data <= i_data; |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_we <= i_op[0]; |
casez({ i_op[2:1], i_addr[1:0] }) |
`ifdef ZERO_ON_IDLE |
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 }; |
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] }; |
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 }; |
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 }; |
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 }; |
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] }; |
`else |
4'b10??: o_wb_data <= { (2){ i_data[15:0] } }; |
4'b11??: o_wb_data <= { (4){ i_data[7:0] } }; |
`endif |
default: o_wb_data <= i_data; |
endcase |
|
o_wb_addr <= i_addr[(AW+1):2]; |
`ifdef SET_SEL_ON_READ |
if (i_op[0] == 1'b0) |
o_wb_sel <= 4'hf; |
else |
`endif |
casez({ i_op[2:1], i_addr[1:0] }) |
4'b01??: o_wb_sel <= 4'b1111; |
4'b100?: o_wb_sel <= 4'b1100; |
4'b101?: o_wb_sel <= 4'b0011; |
4'b1100: o_wb_sel <= 4'b1000; |
4'b1101: o_wb_sel <= 4'b0100; |
4'b1110: o_wb_sel <= 4'b0010; |
4'b1111: o_wb_sel <= 4'b0001; |
default: o_wb_sel <= 4'b1111; |
endcase |
r_op <= { i_op[2:1] , i_addr[1:0] }; |
end |
`ifdef ZERO_ON_IDLE |
else if ((!o_wb_cyc_gbl)&&(!o_wb_cyc_lcl)) |
begin |
o_wb_we <= 1'b0; |
o_wb_addr <= 0; |
o_wb_data <= 32'h0; |
o_wb_sel <= 4'h0; |
end |
`endif |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we); |
o_valid <= (!i_rst)&&((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we); |
initial o_err = 1'b0; |
always @(posedge i_clk) |
o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err); |
o_err <= (!i_rst)&&((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err); |
assign o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl); |
|
always @(posedge i_clk) |
125,8 → 173,21
if (i_stb) |
o_wreg <= i_oreg; |
always @(posedge i_clk) |
if (i_wb_ack) |
o_result <= i_wb_data; |
`ifdef ZERO_ON_IDLE |
if (!i_wb_ack) |
o_result <= 32'h0; |
else |
`endif |
casez(r_op) |
4'b01??: o_result <= i_wb_data; |
4'b100?: o_result <= { 16'h00, i_wb_data[31:16] }; |
4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] }; |
4'b1100: o_result <= { 24'h00, i_wb_data[31:24] }; |
4'b1101: o_result <= { 24'h00, i_wb_data[23:16] }; |
4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] }; |
4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] }; |
default: o_result <= i_wb_data; |
endcase |
|
generate |
if (IMPLEMENT_LOCK != 0) |
/trunk/rtl/cpu/pfcache.v
13,7 → 13,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
25,6 → 25,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
31,6 → 36,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module pfcache(i_clk, i_rst, i_new_pc, i_clear_cache, |
// i_early_branch, i_from_addr, |
i_stall_n, i_pc, o_i, o_pc, o_v, |
/trunk/rtl/cpu/pipefetch.v
30,7 → 30,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
42,6 → 42,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
48,6 → 53,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc, |
o_i, o_pc, o_v, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
/trunk/rtl/cpu/pipemem.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: pipemem.v |
// |
15,9 → 15,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
29,25 → 29,31
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock, |
i_op, i_addr, i_data, i_oreg, |
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result, |
o_wb_cyc_gbl, o_wb_cyc_lcl, |
o_wb_stb_gbl, o_wb_stb_lcl, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=32, IMPLEMENT_LOCK=0; |
parameter ADDRESS_WIDTH=30, IMPLEMENT_LOCK=0; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
input i_pipe_stb, i_lock; |
// CPU interface |
input i_op; |
input [2:0] i_op; |
input [31:0] i_addr; |
input [31:0] i_data; |
input [4:0] i_oreg; |
65,6 → 71,7
output reg o_wb_stb_lcl, o_wb_we; |
output reg [(AW-1):0] o_wb_addr; |
output reg [31:0] o_wb_data; |
output reg [3:0] o_wb_sel; |
// Wishbone inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
73,22 → 80,24
reg r_wb_cyc_gbl, r_wb_cyc_lcl; |
reg [3:0] rdaddr, wraddr; |
wire [3:0] nxt_rdaddr; |
reg [(5-1):0] fifo_oreg [0:15]; |
reg [(4+5-1):0] fifo_oreg [0:15]; |
initial rdaddr = 0; |
initial wraddr = 0; |
|
always @(posedge i_clk) |
fifo_oreg[wraddr] <= i_oreg; |
fifo_oreg[wraddr] <= { i_oreg, i_op[2:1], i_addr[1:0] }; |
|
always @(posedge i_clk) |
if ((i_rst)||(i_wb_err)) |
wraddr <= 0; |
else if (i_pipe_stb) |
wraddr <= wraddr + 4'h1; |
wraddr <= wraddr + 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||(i_wb_err)) |
rdaddr <= 0; |
else if ((i_wb_ack)&&(cyc)) |
rdaddr <= rdaddr + 4'h1; |
assign nxt_rdaddr = rdaddr + 4'h1; |
rdaddr <= rdaddr + 1'b1; |
assign nxt_rdaddr = rdaddr + 1'b1; |
|
wire gbl_stb, lcl_stb; |
assign lcl_stb = (i_addr[31:24]==8'hff); |
136,19 → 145,36
// o_wb_we <= i_op |
end |
always @(posedge i_clk) |
if ((cyc)&&(i_pipe_stb)&&(~i_wb_stall)) |
if ((!cyc)||(!i_wb_stall)) |
begin |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_data <= i_data; |
end else if ((~cyc)&&(i_pipe_stb)) |
begin |
o_wb_addr <= i_addr[(AW-1):0]; |
o_wb_data <= i_data; |
o_wb_addr <= i_addr[(AW+1):2]; |
if (!i_op[0]) // Always select everything on reads |
o_wb_sel <= 4'b1111; // Op is even |
else casez({ i_op[2:1], i_addr[1:0] }) |
4'b100?: o_wb_sel <= 4'b1100; // Op = 5 |
4'b101?: o_wb_sel <= 4'b0011; // Op = 5 |
4'b1100: o_wb_sel <= 4'b1000; // Op = 5 |
4'b1101: o_wb_sel <= 4'b0100; // Op = 7 |
4'b1110: o_wb_sel <= 4'b0010; // Op = 7 |
4'b1111: o_wb_sel <= 4'b0001; // Op = 7 |
default: o_wb_sel <= 4'b1111; // Op = 7 |
endcase |
|
casez({ i_op[2:1], i_addr[1:0] }) |
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 }; |
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] }; |
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 }; |
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 }; |
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 }; |
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] }; |
default: o_wb_data <= i_data; |
endcase |
|
end |
|
|
always @(posedge i_clk) |
if ((i_pipe_stb)&&(~cyc)) |
o_wb_we <= i_op; |
o_wb_we <= i_op[0]; |
|
initial o_valid = 1'b0; |
always @(posedge i_clk) |
158,12 → 184,20
o_err <= (cyc)&&(i_wb_err); |
assign o_busy = cyc; |
|
wire [8:0] w_wreg; |
assign w_wreg = fifo_oreg[rdaddr]; |
always @(posedge i_clk) |
o_wreg <= fifo_oreg[rdaddr]; |
o_wreg <= w_wreg[8:4]; |
always @(posedge i_clk) |
// if (i_wb_ack) isn't necessary, since o_valid won't be true |
// then either. |
o_result <= i_wb_data; |
casez(w_wreg[3:0]) |
4'b1100: o_result = { 24'h00, i_wb_data[31:24] }; |
4'b1101: o_result = { 24'h00, i_wb_data[23:16] }; |
4'b1110: o_result = { 24'h00, i_wb_data[15: 8] }; |
4'b1111: o_result = { 24'h00, i_wb_data[ 7: 0] }; |
4'b100?: o_result = { 16'h00, i_wb_data[31:16] }; |
4'b101?: o_result = { 16'h00, i_wb_data[15: 0] }; |
default: o_result = i_wb_data[31:0]; |
endcase |
|
assign o_pipe_stalled = (cyc) |
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl))); |
178,7 → 212,7
always @(posedge i_clk) |
begin |
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl)); |
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_gbl)); |
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl)); |
end |
|
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl); |
/trunk/rtl/cpu/prefetch.v
24,7 → 24,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
36,6 → 36,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
42,23 → 47,24
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Flash requires a minimum of 4 clocks per byte to read, so that would be |
// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline |
// mode which this prefetch does not support. In non--pipelined mode, the |
// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read, |
// or 72 clocks to fetch one instruction. |
module prefetch(i_clk, i_rst, i_ce, i_stalled_n, i_pc, i_aux, |
o_i, o_pc, o_aux, o_valid, o_illegal, |
module prefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stalled_n, i_pc, |
o_i, o_pc, o_valid, o_illegal, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data); |
parameter ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH; |
input i_clk, i_rst, i_ce, i_stalled_n; |
parameter ADDRESS_WIDTH=32; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst, i_new_pc, i_clear_cache, |
i_stalled_n; |
input [(AW-1):0] i_pc; |
input [(AUX_WIDTH-1):0] i_aux; |
output reg [31:0] o_i; |
output reg [(AW-1):0] o_pc; |
output reg [(AUX_WIDTH-1):0] o_aux; |
output reg o_valid, o_illegal; |
output wire [(AW-1):0] o_pc; |
output reg o_valid; |
// Wishbone outputs |
output reg o_wb_cyc, o_wb_stb; |
output wire o_wb_we; |
65,8 → 71,9
output reg [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
// And return inputs |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
input i_wb_ack, i_wb_stall, i_wb_err; |
input [31:0] i_wb_data; |
output reg o_illegal; |
|
assign o_wb_we = 1'b0; |
assign o_wb_data = 32'h0000; |
78,47 → 85,54
initial o_wb_stb = 1'b0; |
initial o_wb_addr= 0; |
always @(posedge i_clk) |
if ((i_rst)||(i_wb_ack)) |
if ((i_rst)||(i_wb_ack)||(i_wb_err)) |
begin |
o_wb_cyc <= 1'b0; |
o_wb_stb <= 1'b0; |
end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle |
begin |
end else if ((!o_wb_cyc)&&((i_stalled_n)||(!o_valid))) |
begin // Initiate a bus cycle |
o_wb_cyc <= 1'b1; |
o_wb_stb <= 1'b1; |
end else if (o_wb_cyc) // Independent of ce |
begin |
if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)) |
if (~i_wb_stall) |
o_wb_stb <= 1'b0; |
if (i_wb_ack) |
o_wb_cyc <= 1'b0; |
end |
|
reg invalid; |
initial invalid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) // Set the address to guarantee the result is invalid |
o_wb_addr <= {(AW){1'b1}}; |
else if ((i_ce)&&(~o_wb_cyc)) |
if (!o_wb_cyc) |
invalid <= 1'b0; |
else if ((i_new_pc)||(i_clear_cache)) |
invalid <= (!o_wb_stb); |
|
always @(posedge i_clk) |
if (i_new_pc) |
o_wb_addr <= i_pc; |
else if ((!o_wb_cyc)&&(i_stalled_n)&&(!invalid)) |
o_wb_addr <= o_wb_addr + 1'b1; |
|
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
o_aux <= i_aux; |
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
o_i <= i_wb_data; |
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
o_pc <= o_wb_addr; |
|
initial o_valid = 1'b0; |
initial o_illegal = 1'b0; |
always @(posedge i_clk) |
if ((o_wb_cyc)&&(i_wb_ack)) |
if (i_rst) |
begin |
o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err); |
o_illegal <= i_wb_err; |
end else if (i_stalled_n) |
o_valid <= 1'b0; |
o_illegal <= 1'b0; |
end else if ((o_wb_cyc)&&(i_wb_ack)) |
begin |
o_valid <= (!i_wb_err)&&(!invalid); |
o_illegal <= ( i_wb_err)&&(!invalid); |
end else if ((i_stalled_n)||(i_clear_cache)) |
begin |
o_valid <= 1'b0; |
o_illegal <= 1'b0; |
end |
|
assign o_pc = o_wb_addr; |
endmodule |
/trunk/rtl/cpu/wbarbiter.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbarbiter.v |
// |
34,9 → 34,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
48,20 → 48,26
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// `define WBA_ALTERNATING |
// |
`define WBA_ALTERNATING |
module wbarbiter(i_clk, i_rst, |
// Bus A -- gets priority when not alternating |
i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall, o_a_err, |
// Bus A |
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall, o_b_err, |
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall, i_err); |
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err); |
// 18 bits will address one GB, 4 bytes at a time. |
// 19 bits will allow the ability to address things other than just |
// the 1GB of memory we are expecting. |
71,6 → 77,7
input i_clk, i_rst; |
input [(AW-1):0] i_a_adr, i_b_adr; |
input [(DW-1):0] i_a_dat, i_b_dat; |
input [(DW/8-1):0] i_a_sel, i_b_sel; |
input i_a_we, i_a_stb, i_a_cyc; |
input i_b_we, i_b_stb, i_b_cyc; |
output wire o_a_ack, o_b_ack, o_a_stall, o_b_stall, |
77,6 → 84,7
o_a_err, o_b_err; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
output wire [(DW/8-1):0] o_sel; |
output wire o_we, o_stb, o_cyc; |
input i_ack, i_stall, i_err; |
|
159,11 → 167,12
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on the various lines are |
// irrelevant. |
// irrelevant. (This allows us to get two outputs per Xilinx 6-LUT) |
assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb); |
assign o_we = (w_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (w_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (w_a_owner) ? i_a_dat : i_b_dat; |
assign o_we = (w_a_owner) ? i_a_we : i_b_we; |
assign o_stb = (o_cyc) && ((w_a_owner) ? i_a_stb : i_b_stb); |
assign o_sel = (w_a_owner) ? i_a_sel : i_b_sel; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
/trunk/rtl/cpu/wbdblpriarb.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbdblpriarb.v |
// |
42,9 → 42,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
56,19 → 56,25
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module wbdblpriarb(i_clk, i_rst, |
// |
module wbdblpriarb(i_clk, i_rst, |
// Bus A |
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err, |
i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err, |
i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, |
o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, o_sel, |
i_ack, i_stall, i_err); |
parameter DW=32, AW=32; |
// Wishbone doesn't use an i_ce signal. While it could, they dislike |
78,28 → 84,31
input i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we; |
input [(AW-1):0] i_a_adr; |
input [(DW-1):0] i_a_dat; |
input [(DW/8-1):0] i_a_sel; |
output wire o_a_ack, o_a_stall, o_a_err; |
// Bus B |
input i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we; |
input [(AW-1):0] i_b_adr; |
input [(DW-1):0] i_b_dat; |
input [(DW/8-1):0] i_b_sel; |
output wire o_b_ack, o_b_stall, o_b_err; |
// |
// |
output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
output wire [(DW/8-1):0] o_sel; |
input i_ack, i_stall, i_err; |
|
// All of our logic is really captured in the 'r_a_owner' register. |
// This register determines who owns the bus. If no one is requesting |
// the bus, ownership goes to A on the next clock. Otherwise, if B is |
// the bus, ownership goes to A on the next clock. Otherwise, if B is |
// requesting the bus and A is not, then ownership goes to not A on |
// the next clock. (Sounds simple ...) |
// |
// The CYC logic is here to make certain that, by the time we determine |
// who the bus owner is, we can do so based upon determined criteria. |
assign o_cyc_a = (~i_rst)&&((r_a_owner) ? i_a_cyc_a : i_b_cyc_a); |
assign o_cyc_b = (~i_rst)&&((r_a_owner) ? i_a_cyc_b : i_b_cyc_b); |
assign o_cyc_a = ((r_a_owner) ? i_a_cyc_a : i_b_cyc_a); |
assign o_cyc_b = ((r_a_owner) ? i_a_cyc_b : i_b_cyc_b); |
reg r_a_owner; |
initial r_a_owner = 1'b1; |
always @(posedge i_clk) |
109,9 → 118,34
r_a_owner <= ((i_b_cyc_a)||(i_b_cyc_b))? 1'b0:1'b1; |
|
|
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
`ifdef ZERO_ON_IDLE |
// |
// ZERO_ON_IDLE uses more logic than the alternative. It should be |
// useful for reducing power, as these circuits tend to drive wires |
// all the way across the design, but it may also slow down the master |
// clock. I've used it as an option when using VERILATOR, 'cause |
// zeroing things on idle can make them stand out all the more when |
// staring at wires and dumps and such. |
// |
wire o_cyc, o_stb; |
assign o_cyc = ((o_cyc_a)||(o_cyc_b)); |
assign o_stb = (o_cyc)&&((o_stb_a)||(o_stb_b)); |
assign o_stb_a = (r_a_owner) ? (i_a_stb_a)&&(o_cyc_a) : (i_b_stb_a)&&(o_cyc_a); |
assign o_stb_b = (r_a_owner) ? (i_a_stb_b)&&(o_cyc_b) : (i_b_stb_b)&&(o_cyc_b); |
assign o_adr = ((o_stb_a)|(o_stb_b))?((r_a_owner) ? i_a_adr : i_b_adr):0; |
assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0; |
assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0; |
assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (o_cyc)&&(~r_a_owner) ? i_ack : 1'b0; |
assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (o_cyc)&&(~r_a_owner) ? i_stall : 1'b1; |
assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (o_cyc)&&(~r_a_owner) ? i_err : 1'b0; |
`else |
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on these various lines are |
// irrelevant. |
assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a; |
119,6 → 153,7
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; |
assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
137,6 → 172,7
// |
assign o_a_err = ( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (~r_a_owner) ? i_err : 1'b0; |
`endif |
|
endmodule |
|
/trunk/rtl/cpu/wbdmac.v
1,6 → 1,5
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// Filename: wbdmac.v |
// |
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core |
78,12 → 77,12
// buffer by reading from bits 25..16 of this control/status |
// register. |
// |
// Creator: Dan Gisselquist |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
95,11 → 94,16
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define DMA_IDLE 3'b000 |
168,7 → 172,7
|
reg last_read_request, last_read_ack, |
last_write_request, last_write_ack; |
reg trigger, abort; |
reg trigger, abort, user_halt; |
|
initial dma_state = `DMA_IDLE; |
initial o_interrupt = 1'b0; |
193,7 → 197,7
begin |
case(i_swb_addr) |
2'b00: begin |
if ((i_swb_data[27:16] == 12'hfed) |
if ((i_swb_data[31:16] == 16'h0fed) |
&&(cfg_len_nonzero)) |
dma_state <= `DMA_WAIT; |
cfg_blocklen_sub_one |
221,6 → 225,8
nread <= 0; |
if (abort) |
dma_state <= `DMA_IDLE; |
else if (user_halt) |
dma_state <= `DMA_IDLE; |
else if (trigger) |
dma_state <= `DMA_READ_REQ; |
end |
240,11 → 246,14
+ {{(AW-1){1'b0}},1'b1}; |
end |
|
if (user_halt) |
dma_state <= `DMA_READ_ACK; |
if (i_mwb_err) |
begin |
cfg_len <= 0; |
dma_state <= `DMA_IDLE; |
end |
|
if (abort) |
dma_state <= `DMA_IDLE; |
if (i_mwb_ack) |
266,6 → 275,8
nread <= nread+1; |
if (last_read_ack) // (nread+1 == nracks) |
dma_state <= `DMA_PRE_WRITE; |
if (user_halt) |
dma_state <= `DMA_IDLE; |
if (cfg_incs) |
cfg_raddr <= cfg_raddr |
+ {{(AW-1){1'b0}},1'b1}; |
303,6 → 314,8
nwacks <= nwacks+1; |
cfg_len <= cfg_len +{(AW){1'b1}}; // -1 |
end |
if (user_halt) |
dma_state <= `DMA_WRITE_ACK; |
if (abort) |
dma_state <= `DMA_IDLE; |
end |
467,5 → 480,12
&&(i_swb_addr == 2'b00) |
&&(i_swb_data == 32'hffed0000)); |
|
initial user_halt = 1'b0; |
always @(posedge i_clk) |
user_halt <= ((user_halt)&&(dma_state != `DMA_IDLE)) |
||((i_swb_stb)&&(i_swb_we)&&(dma_state != `DMA_IDLE) |
&&(i_swb_addr == 2'b00) |
&&(i_swb_data == 32'hafed0000)); |
|
endmodule |
|
/trunk/rtl/cpu/wbpriarbiter.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbpriarbiter.v |
// |
25,9 → 25,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
39,19 → 39,25
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
module wbpriarbiter(i_clk, |
// |
module wbpriarbiter(i_clk, |
// Bus A |
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err, |
i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err, |
// Bus B |
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err, |
i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err, |
// Both buses |
o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err); |
o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err); |
parameter DW=32, AW=32; |
// |
input i_clk; |
59,16 → 65,19
input i_a_cyc, i_a_stb, i_a_we; |
input [(AW-1):0] i_a_adr; |
input [(DW-1):0] i_a_dat; |
input [(DW/8-1):0] i_a_sel; |
output wire o_a_ack, o_a_stall, o_a_err; |
// Bus B |
input i_b_cyc, i_b_stb, i_b_we; |
input [(AW-1):0] i_b_adr; |
input [(DW-1):0] i_b_dat; |
input [(DW/8-1):0] i_b_sel; |
output wire o_b_ack, o_b_stall, o_b_err; |
// |
// |
output wire o_cyc, o_stb, o_we; |
output wire [(AW-1):0] o_adr; |
output wire [(DW-1):0] o_dat; |
output wire [(DW/8-1):0] o_sel; |
input i_ack, i_stall, i_err; |
|
// Go high immediately (new cycle) if ... |
89,13 → 98,34
|
// Realistically, if neither master owns the bus, the output is a |
// don't care. Thus we trigger off whether or not 'A' owns the bus. |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// If 'B' owns it all we care is that 'A' does not. Likewise, if |
// neither owns the bus than the values on the various lines are |
// irrelevant. |
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
`ifdef ZERO_ON_IDLE |
// |
// ZERO_ON_IDLE will use up more logic and may even slow down the master |
// clock if set. However, it may also reduce the power used by the |
// FPGA by preventing things from toggling when the bus isn't in use. |
// The option is here because it also makes it a lot easier to look |
// for when things happen on the bus via VERILATOR when timing and |
// logic counts don't matter. |
// |
assign o_stb = (o_cyc)?((r_a_owner) ? i_a_stb : i_b_stb):0; |
assign o_adr = (o_stb)?((r_a_owner) ? i_a_adr : i_b_adr):0; |
assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0; |
assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0; |
assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0; |
assign o_b_ack = (o_cyc)&&(~r_a_owner) ? i_ack : 1'b0; |
assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (o_cyc)&&(~r_a_owner) ? i_stall : 1'b1; |
assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (o_cyc)&&(~r_a_owner) ? i_err : 1'b0; |
`else |
assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb; |
assign o_we = (r_a_owner) ? i_a_we : i_b_we; |
assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; |
assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; |
assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel; |
|
// We cannot allow the return acknowledgement to ever go high if |
// the master in question does not own the bus. Hence we force it |
108,10 → 138,11
assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1; |
assign o_b_stall = (~r_a_owner) ? i_stall : 1'b1; |
|
// |
// |
// |
// |
assign o_a_err = ( r_a_owner) ? i_err : 1'b0; |
assign o_b_err = (~r_a_owner) ? i_err : 1'b0; |
`endif |
|
endmodule |
|
/trunk/rtl/cpu/wbwatchdog.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbwatchdog.v |
// |
29,9 → 29,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
43,12 → 43,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module wbwatchdog(i_clk, i_rst, i_ce, i_timeout, o_int); |
parameter BW = 32; |
input i_clk, i_rst, i_ce; |
/trunk/rtl/cpu/zipbones.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipbones.v |
// |
11,9 → 11,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015, 2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
25,17 → 25,23
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`include "cpudefs.v" |
// |
module zipbones(i_clk, i_rst, |
// Wishbone master interface from the CPU |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err, |
// Incoming interrupts |
i_ext_int, |
48,14 → 54,15
, o_zip_debug |
`endif |
); |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32, |
LGICACHE=6, START_HALTED=0, |
AW=ADDRESS_WIDTH, HIGHSPEED_CPU=1; |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30, |
LGICACHE=8, START_HALTED=0; |
localparam AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
// Wishbone master |
output wire o_wb_cyc, o_wb_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
output wire [3:0] o_wb_sel; |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
input i_wb_err; |
170,7 → 177,10
generate |
if (HIGHSPEED_CPU==0) |
begin |
zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE) |
zipcpu #(.RESET_ADDRESS(RESET_ADDRESS), |
.ADDRESS_WIDTH(ADDRESS_WIDTH), |
.LGICACHE(LGICACHE), |
.WITH_LOCAL_BUS(0)) |
thecpu(i_clk, cpu_reset, i_ext_int, |
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we, |
i_dbg_data, cpu_dbg_stall, cpu_dbg_data, |
177,7 → 187,7
cpu_dbg_cc, cpu_break, |
o_wb_cyc, o_wb_stb, |
cpu_lcl_cyc, cpu_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, |
(i_wb_err)||(cpu_lcl_cyc), |
cpu_op_stall, cpu_pf_stall, cpu_i_count |
186,7 → 196,10
`endif |
); |
end else begin |
zipcpu #(RESET_ADDRESS,ADDRESS_WIDTH,LGICACHE) |
zipcpu #(.RESET_ADDRESS(RESET_ADDRESS), |
.ADDRESS_WIDTH(ADDRESS_WIDTH), |
.LGICACHE(LGICACHE), |
.WITH_LOCAL_BUS(0)) |
thecpu(i_clk, cpu_reset, i_ext_int, |
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we, |
i_dbg_data, cpu_dbg_stall, cpu_dbg_data, |
193,7 → 206,7
cpu_dbg_cc, cpu_break, |
o_wb_cyc, o_wb_stb, |
cpu_lcl_cyc, cpu_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, |
(i_wb_err)||((cpu_lcl_cyc)&&(cpu_lcl_stb)), |
cpu_op_stall, cpu_pf_stall, cpu_i_count |
/trunk/rtl/cpu/zipcounter.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipcounter.v |
// |
25,9 → 25,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
39,12 → 39,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module zipcounter(i_clk, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
/trunk/rtl/cpu/zipcpu.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipcpu.v |
// |
18,7 → 18,7
// |
// The Zip CPU is fully pipelined with the following pipeline stages: |
// |
// 1. Prefetch, returns the instruction from memory. |
// 1. Prefetch, returns the instruction from memory. |
// |
// 2. Instruction Decode |
// |
45,7 → 45,7
// as: |
// |
// |
// assign (n)_ce = (n-1)_valid && (~(n)_stall) |
// assign (n)_ce = (n-1)_valid && (!(n)_stall) |
// |
// |
// always @(posedge i_clk) |
72,9 → 72,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
86,28 → 86,23
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// We can either pipeline our fetches, or issue one fetch at a time. Pipelined |
// fetches are more complicated and therefore use more FPGA resources, while |
// single fetches will cause the CPU to stall for about 5 stalls each |
// instruction cycle, effectively reducing the instruction count per clock to |
// about 0.2. However, the area cost may be worth it. Consider: |
// |
// Slice LUTs ZipSystem ZipCPU |
// Single Fetching 2521 1734 |
// Pipelined fetching 2796 2046 |
// |
// |
// |
`define CPU_CC_REG 4'he |
`define CPU_PC_REG 4'hf |
`define CPU_CLRCACHE_BIT 14 // Set to clear the I-cache, automatically clears |
`define CPU_PHASE_BIT 13 // Set if we are executing the latter half of a VLIW |
`define CPU_PHASE_BIT 13 // Set if we are executing the latter half of a CIS |
`define CPU_FPUERR_BIT 12 // Floating point error flag, set on error |
`define CPU_DIVERR_BIT 11 // Divide error flag, set on divide by zero |
`define CPU_BUSERR_BIT 10 // Bus error flag, set on error |
114,7 → 109,7
`define CPU_TRAP_BIT 9 // User TRAP has taken place |
`define CPU_ILL_BIT 8 // Illegal instruction |
`define CPU_BREAK_BIT 7 |
`define CPU_STEP_BIT 6 // Will step one or two (VLIW) instructions |
`define CPU_STEP_BIT 6 // Will step one (or two CIS) instructions |
`define CPU_GIE_BIT 5 |
`define CPU_SLEEP_BIT 4 |
// Compile time defines |
130,7 → 125,7
// CPU interface to the wishbone bus |
o_wb_gbl_cyc, o_wb_gbl_stb, |
o_wb_lcl_cyc, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, |
i_wb_err, |
// Accounting/CPU usage interface |
139,7 → 134,8
, o_debug |
`endif |
); |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32, |
parameter [31:0] RESET_ADDRESS=32'h0100000; |
parameter ADDRESS_WIDTH=30, |
LGICACHE=8; |
`ifdef OPT_MULTIPLY |
parameter IMPLEMENT_MPY = `OPT_MULTIPLY; |
162,7 → 158,9
`else |
parameter EARLY_BRANCHING = 0; |
`endif |
parameter WITH_LOCAL_BUS = 1; |
localparam AW=ADDRESS_WIDTH; |
localparam [(AW-1):0] RESET_BUS_ADDRESS = RESET_ADDRESS[(AW+1):2]; |
input i_clk, i_rst, i_interrupt; |
// Debug interface -- inputs |
input i_halt, i_clear_pf_cache; |
179,6 → 177,7
output wire o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
output wire [3:0] o_wb_sel; |
// Wishbone interface -- inputs |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
216,11 → 215,7
reg break_en, step, sleep, r_halted; |
wire break_pending, trap, gie, ubreak; |
wire w_clear_icache, ill_err_u; |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg ill_err_i; |
`else |
wire ill_err_i; |
`endif |
reg ibus_err_flag; |
wire ubus_err_flag; |
wire idiv_err_flag, udiv_err_flag; |
235,7 → 230,7
// PIPELINE STAGE #1 :: Prefetch |
// Variable declarations |
// |
reg [(AW-1):0] pf_pc; |
reg [(AW+1):0] pf_pc; |
reg new_pc; |
wire clear_pipeline; |
assign clear_pipeline = new_pc; |
244,9 → 239,9
wire pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err; |
wire [(AW-1):0] pf_addr; |
wire [31:0] pf_data; |
wire [31:0] instruction; |
wire [(AW-1):0] instruction_pc; |
wire pf_valid, instruction_gie, pf_illegal; |
wire [31:0] pf_instruction; |
wire [(AW-1):0] pf_instruction_pc; |
wire pf_valid, pf_gie, pf_illegal; |
|
// |
// |
254,29 → 249,32
// Variable declarations |
// |
// |
reg opvalid, opvalid_mem, opvalid_alu; |
reg opvalid_div, opvalid_fpu; |
reg op_valid /* verilator public_flat */, |
op_valid_mem, op_valid_alu; |
reg op_valid_div, op_valid_fpu; |
wire op_stall, dcd_ce, dcd_phase; |
wire [3:0] dcdOp; |
wire [4:0] dcdA, dcdB, dcdR; |
wire dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc; |
wire [3:0] dcdF; |
wire dcdR_wr, dcdA_rd, dcdB_rd, |
dcdALU, dcdM, dcdDV, dcdFP, |
dcdF_wr, dcd_gie, dcd_break, dcd_lock, |
wire [3:0] dcd_opn; |
wire [4:0] dcd_A, dcd_B, dcd_R; |
wire dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc; |
wire [3:0] dcd_F; |
wire dcd_wR, dcd_rA, dcd_rB, |
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, |
dcd_wF, dcd_gie, dcd_break, dcd_lock, |
dcd_pipe, dcd_ljmp; |
reg r_dcdvalid; |
wire dcdvalid; |
wire [(AW-1):0] dcd_pc; |
wire [31:0] dcdI; |
wire dcd_zI; // true if dcdI == 0 |
wire dcdA_stall, dcdB_stall, dcdF_stall; |
wire dcd_valid; |
wire [AW:0] dcd_pc /* verilator public_flat */; |
wire [31:0] dcd_I; |
wire dcd_zI; // true if dcd_I == 0 |
wire dcd_A_stall, dcd_B_stall, dcd_F_stall; |
|
wire dcd_illegal; |
wire dcd_early_branch; |
wire [(AW-1):0] dcd_branch_pc; |
|
wire dcd_sim; |
wire [22:0] dcd_sim_immv; |
|
|
// |
// |
// PIPELINE STAGE #3 :: Read Operands |
286,33 → 284,29
// |
// Now, let's read our operands |
reg [4:0] alu_reg; |
wire [3:0] opn; |
wire [4:0] opR; |
reg [31:0] r_opA, r_opB; |
wire [3:0] op_opn; |
wire [4:0] op_R; |
reg [31:0] r_op_Av, r_op_Bv; |
reg [(AW-1):0] op_pc; |
wire [31:0] w_opA, w_opB; |
wire [31:0] opA_nowait, opB_nowait, opA, opB; |
reg opR_wr, opF_wr; |
wire op_gie, opR_cc; |
wire [14:0] opFl; |
reg [5:0] r_opF; |
wire [7:0] opF; |
wire [31:0] w_op_Av, w_op_Bv; |
wire [31:0] op_A_nowait, op_B_nowait, op_Av, op_Bv; |
reg op_wR, op_wF; |
wire op_gie, op_Rcc; |
wire [14:0] op_Fl; |
reg [6:0] r_op_F; |
wire [7:0] op_F; |
wire op_ce, op_phase, op_pipe, op_change_data_ce; |
// Some pipeline control wires |
`ifdef OPT_PIPELINED |
reg opA_alu, opA_mem; |
reg opB_alu, opB_mem; |
`endif |
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg op_illegal; |
`else |
wire op_illegal; |
assign op_illegal = 1'b0; |
`endif |
wire op_break; |
wire op_lock; |
|
`ifdef VERILATOR |
reg op_sim /* verilator public_flat */; |
reg [22:0] op_sim_immv /* verilator public_flat */; |
`endif |
|
|
// |
// |
// PIPELINE STAGE #4 :: ALU / Memory |
323,12 → 317,12
reg r_alu_pc_valid, mem_pc_valid; |
wire alu_pc_valid; |
wire alu_phase; |
wire alu_ce, alu_stall; |
wire alu_ce /* verilator public_flat */, alu_stall; |
wire [31:0] alu_result; |
wire [3:0] alu_flags; |
wire alu_valid, alu_busy; |
wire set_cond; |
reg alu_wr, alF_wr; |
reg alu_wR, alu_wF; |
wire alu_gie, alu_illegal; |
|
|
342,13 → 336,14
wire mem_busy, mem_rdbusy; |
wire [(AW-1):0] mem_addr; |
wire [31:0] mem_data, mem_result; |
wire [3:0] mem_sel; |
|
wire div_ce, div_error, div_busy, div_valid; |
wire [31:0] div_result; |
wire [3:0] div_flags; |
|
assign div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
assign div_ce = (master_ce)&&(!clear_pipeline)&&(op_valid_div) |
&&(!mem_rdbusy)&&(!div_busy)&&(!fpu_busy) |
&&(set_cond); |
|
wire fpu_ce, fpu_error, fpu_busy, fpu_valid; |
355,8 → 350,8
wire [31:0] fpu_result; |
wire [3:0] fpu_flags; |
|
assign fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu) |
&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy) |
assign fpu_ce = (master_ce)&&(!clear_pipeline)&&(op_valid_fpu) |
&&(!mem_rdbusy)&&(!div_busy)&&(!fpu_busy) |
&&(set_cond); |
|
wire adf_ce_unconditional; |
371,8 → 366,8
wire [4:0] wr_reg_id; |
wire [31:0] wr_gpreg_vl, wr_spreg_vl; |
wire w_switch_to_interrupt, w_release_from_interrupt; |
reg [(AW-1):0] ipc; |
wire [(AW-1):0] upc; |
reg [(AW+1):0] ipc; |
wire [(AW+1):0] upc; |
|
|
|
379,7 → 374,7
// |
// MASTER: clock enable. |
// |
assign master_ce = (~i_halt)&&(~o_break)&&(~sleep); |
assign master_ce = ((!i_halt)||(alu_phase))&&(!o_break)&&(!sleep); |
|
|
// |
392,33 → 387,29
// |
// PIPELINE STAGE #2 :: Instruction Decode |
// Calculate stall conditions |
assign dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline); |
|
`ifdef OPT_PIPELINED |
assign dcd_stalled = (dcdvalid)&&(op_stall); |
`else |
// If not pipelined, there will be no opvalid_ anything, and the |
// op_stall will be false, dcdX_stall will be false, thus we can simply |
// do a ... |
assign dcd_stalled = 1'b0; |
assign dcd_stalled = (dcd_valid)&&(op_stall); |
`else // Not pipelined -- either double or single fetch |
assign dcd_stalled = (dcd_valid)&&(op_stall); |
`endif |
// |
// PIPELINE STAGE #3 :: Read Operands |
// Calculate stall conditions |
wire op_lock_stall; |
wire prelock_stall; |
`ifdef OPT_PIPELINED |
reg cc_invalid_for_dcd; |
always @(posedge i_clk) |
cc_invalid_for_dcd <= (wr_flags_ce) |
||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG) |
||(opvalid)&&((opF_wr)||((opR_wr)&&(opR[3:0] == `CPU_CC_REG))) |
||((alF_wr)||((alu_wr)&&(alu_reg[3:0] == `CPU_CC_REG))) |
||(op_valid)&&((op_wF)||((op_wR)&&(op_R[3:0] == `CPU_CC_REG))) |
||((alu_wF)||((alu_wR)&&(alu_reg[3:0] == `CPU_CC_REG))) |
||(mem_busy)||(div_busy)||(fpu_busy); |
|
assign op_stall = (opvalid)&&( // Only stall if we're loaded w/validins |
assign op_stall = (op_valid)&&( // Only stall if we're loaded w/validins |
// Stall if we're stopped, and not allowed to execute |
// an instruction |
// (~master_ce) // Already captured in alu_stall |
// (!master_ce) // Already captured in alu_stall |
// |
// Stall if going into the ALU and the ALU is stalled |
// i.e. if the memory is busy, or we are single |
428,40 → 419,42
// This also includes whether or not the divide or |
// floating point units are busy. |
(alu_stall) |
||(((op_valid_div)||(op_valid_fpu)) |
&&(!adf_ce_unconditional)) |
// |
// Stall if we are going into memory with an operation |
// that cannot be pipelined, and the memory is |
// already busy |
||(mem_stalled) // &&(opvalid_mem) part of mem_stalled |
||(opR_cc) |
||(mem_stalled) // &&(op_valid_mem) part of mem_stalled |
||(op_Rcc) |
) |
||(dcdvalid)&&( |
||(dcd_valid)&&( |
// Stall if we need to wait for an operand A |
// to be ready to read |
(dcdA_stall) |
(dcd_A_stall) |
// Likewise for B, also includes logic |
// regarding immediate offset (register must |
// be in register file if we need to add to |
// an immediate) |
||(dcdB_stall) |
||(dcd_B_stall) |
// Or if we need to wait on flags to work on the |
// CC register |
||(dcdF_stall) |
||(dcd_F_stall) |
); |
assign op_ce = ((dcdvalid)||(dcd_illegal)||(dcd_early_branch))&&(~op_stall)&&(~clear_pipeline); |
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall); |
|
`else |
assign op_stall = (alu_busy)||(div_busy)||(fpu_busy)||(wr_reg_ce) |
||(mem_busy)||(op_valid)||(!master_ce)||(wr_flags_ce); |
assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall); |
`endif |
|
// BUT ... op_ce is too complex for many of the data operations. So |
// let's make their circuit enable code simpler. In particular, if |
// op_ doesn't need to be preserved, we can change it all we want |
// ... right? The clear_pipeline code, for example, really only needs |
// to determine whether opvalid is true. |
assign op_change_data_ce = (~op_stall); |
`else |
assign op_stall = (opvalid)&&(~master_ce); |
assign op_ce = ((dcdvalid)||(dcd_illegal)||(dcd_early_branch))&&(~clear_pipeline); |
assign op_change_data_ce = 1'b1; |
`endif |
// to determine whether op_valid is true. |
assign op_change_data_ce = (!op_stall); |
|
// |
// PIPELINE STAGE #4 :: ALU / Memory |
468,7 → 461,7
// Calculate stall conditions |
// |
// 1. Basic stall is if the previous stage is valid and the next is |
// busy. |
// busy. |
// 2. Also stall if the prior stage is valid and the master clock enable |
// is de-selected |
// 3. Stall if someone on the other end is writing the CC register, |
477,16 → 470,16
// through the ALU. Break instructions are not allowed through |
// the ALU. |
`ifdef OPT_PIPELINED |
assign alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2 |
||((opvalid)&&(op_lock)&&(op_lock_stall)) |
||((opvalid)&&(op_break)) |
assign alu_stall = (((!master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2 |
||(prelock_stall) |
||((op_valid)&&(op_break)) |
||(wr_reg_ce)&&(wr_write_cc) |
||(div_busy)||(fpu_busy); |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall) |
&&(~clear_pipeline); |
assign alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall) |
&&(!clear_pipeline); |
`else |
assign alu_stall = (opvalid_alu)&&((~master_ce)||(op_break)); |
assign alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline); |
assign alu_stall = (op_valid_alu)&&((!master_ce)||(op_break)); |
assign alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall)&&(!clear_pipeline); |
`endif |
// |
|
494,25 → 487,14
// Note: if you change the conditions for mem_ce, you must also change |
// alu_pc_valid. |
// |
`ifdef OPT_PIPELINED |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
`else |
// If we aren't pipelined, then no one will be changing what's in the |
// pipeline (i.e. clear_pipeline), while our only instruction goes |
// through the ... pipeline. |
// |
// However, in hind sight this logic didn't work. What happens when |
// something gets in the pipeline and then (due to interrupt or some |
// such) needs to be voided? Thus we avoid simplification and keep |
// what worked here. |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
`endif |
assign mem_ce = (master_ce)&&(op_valid_mem)&&(!mem_stalled) |
&&(!clear_pipeline); |
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&( |
assign mem_stalled = (!master_ce)||(alu_busy)||((op_valid_mem)&&( |
(mem_pipe_stalled) |
||((~op_pipe)&&(mem_busy)) |
||(prelock_stall) |
||((!op_pipe)&&(mem_busy)) |
||(div_busy) |
||(fpu_busy) |
// Stall waiting for flags to be valid |
523,8 → 505,8
&&((wr_write_pc)||(wr_write_cc))))); |
`else |
`ifdef OPT_PIPELINED |
assign mem_stalled = (mem_busy)||((opvalid_mem)&&( |
(~master_ce) |
assign mem_stalled = (mem_busy)||((op_valid_mem)&&( |
(!master_ce) |
// Stall waiting for flags to be valid |
// Or waiting for a write to the PC register |
// Or CC register, since that can change the |
531,15 → 513,15
// PC as well |
||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc))))); |
`else |
assign mem_stalled = (opvalid_mem)&&(~master_ce); |
assign mem_stalled = (op_valid_mem)&&(!master_ce); |
`endif |
`endif |
|
// ALU, DIV, or FPU CE ... equivalent to the OR of all three of these |
assign adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid) |
&&(~opvalid_mem)&&(~mem_rdbusy) |
&&((~opvalid_alu)||(~alu_stall))&&(~op_break) |
&&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline); |
assign adf_ce_unconditional = (master_ce)&&(!clear_pipeline)&&(op_valid) |
&&(!op_valid_mem)&&(!mem_rdbusy) |
&&((!op_valid_alu)||(!alu_stall))&&(!op_break) |
&&(!div_busy)&&(!fpu_busy)&&(!clear_pipeline); |
|
// |
// |
546,117 → 528,93
// PIPELINE STAGE #1 :: Prefetch |
// |
// |
wire pf_stalled; |
assign pf_stalled = (dcd_stalled)||(dcd_phase); |
|
wire pf_new_pc; |
assign pf_new_pc = (new_pc)||((dcd_early_branch)&&(!clear_pipeline)); |
|
wire [(AW-1):0] pf_request_address; |
assign pf_request_address = ((dcd_early_branch)&&(!clear_pipeline)) |
? dcd_branch_pc:pf_pc[(AW+1):2]; |
assign pf_gie = gie; |
`ifdef OPT_SINGLE_FETCH |
wire pf_ce; |
|
assign pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid); |
prefetch #(ADDRESS_WIDTH) |
pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie, |
instruction, instruction_pc, instruction_gie, |
pf(i_clk, (i_rst), pf_new_pc, w_clear_icache, |
(!pf_stalled), |
pf_request_address, |
pf_instruction, pf_instruction_pc, |
pf_valid, pf_illegal, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data); |
|
initial r_dcdvalid = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)||(pf_illegal); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
`else |
`ifdef OPT_DOUBLE_FETCH |
|
`else // Pipe fetch |
wire [1:0] pf_dbg; |
dblfetch #(ADDRESS_WIDTH) |
pf(i_clk, i_rst, pf_new_pc, |
w_clear_icache, |
(!pf_stalled), |
pf_request_address, |
pf_instruction, pf_instruction_pc, |
pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
pf_illegal); |
|
`else // Not single fetch and not double fetch |
|
`ifdef OPT_TRADITIONAL_PFCACHE |
pfcache #(LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)), |
w_clear_icache, |
pf(i_clk, i_rst, pf_new_pc, w_clear_icache, |
// dcd_pc, |
~dcd_stalled, |
((dcd_early_branch)&&(~clear_pipeline)) |
? dcd_branch_pc:pf_pc, |
instruction, instruction_pc, pf_valid, |
(!pf_stalled), |
pf_request_address, |
pf_instruction, pf_instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
pf_illegal); |
`else |
pipefetch #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, (new_pc)||(dcd_early_branch), |
w_clear_icache, ~dcd_stalled, |
(new_pc)?pf_pc:dcd_branch_pc, |
instruction, instruction_pc, pf_valid, |
pipefetch #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH) |
pf(i_clk, i_rst, pf_new_pc, |
w_clear_icache, (!pf_stalled), |
(new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc, |
pf_instruction, pf_instruction_pc, pf_valid, |
pf_cyc, pf_stb, pf_we, pf_addr, pf_data, |
pf_ack, pf_stall, pf_err, i_wb_data, |
//`ifdef OPT_PRECLEAR_BUS |
//((dcd_clear_bus)&&(dcdvalid)) |
//||((op_clear_bus)&&(opvalid)) |
//|| |
//`endif |
(mem_cyc_lcl)||(mem_cyc_gbl), |
pf_illegal); |
`endif |
`ifdef OPT_NO_USERMODE |
assign instruction_gie = 1'b0; |
`else |
assign instruction_gie = gie; |
`endif |
`endif // OPT_TRADITIONAL_CACHE |
`endif // OPT_DOUBLE_FETCH |
`endif // OPT_SINGLE_FETCH |
|
initial r_dcdvalid = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)||(w_clear_icache)) |
r_dcdvalid <= 1'b0; |
else if (dcd_ce) |
r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&(~dcd_early_branch); |
else if (op_ce) |
r_dcdvalid <= 1'b0; |
assign dcdvalid = r_dcdvalid; |
`endif |
|
`ifdef OPT_NEW_INSTRUCTION_SET |
|
// If not pipelined, there will be no opvalid_ anything, and the |
assign dcd_ce = (!dcd_valid)||(!dcd_stalled); |
idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
(~dcdvalid)||(~op_stall), dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
instruction_decoder(i_clk, |
(clear_pipeline)||(w_clear_icache), |
dcd_ce, |
dcd_stalled, pf_instruction, pf_gie, |
pf_instruction_pc, pf_valid, pf_illegal, |
dcd_valid, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcd_Rcc, dcd_Rpc, dcd_R }, |
{ dcd_Acc, dcd_Apc, dcd_A }, |
{ dcd_Bcc, dcd_Bpc, dcd_B }, |
dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn, |
dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock, |
dcd_wR,dcd_rA, dcd_rB, |
dcd_early_branch, |
dcd_branch_pc, dcd_ljmp, |
dcd_pipe); |
`else |
idecode_deprecated |
#(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE, |
IMPLEMENT_FPU) |
instruction_decoder(i_clk, (i_rst)||(clear_pipeline), |
dcd_ce, dcd_stalled, instruction, instruction_gie, |
instruction_pc, pf_valid, pf_illegal, dcd_phase, |
dcd_illegal, dcd_pc, dcd_gie, |
{ dcdR_cc, dcdR_pc, dcdR }, |
{ dcdA_cc, dcdA_pc, dcdA }, |
{ dcdB_cc, dcdB_pc, dcdB }, |
dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp, |
dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock, |
dcdR_wr,dcdA_rd, dcdB_rd, |
dcd_early_branch, |
dcd_branch_pc, |
dcd_pipe); |
assign dcd_ljmp = 1'b0; |
`endif |
dcd_pipe, |
dcd_sim, dcd_sim_immv); |
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
reg r_op_pipe; |
|
initial r_op_pipe = 1'b0; |
// To be a pipeable operation, there must be |
// To be a pipeable operation, there must be |
// two valid adjacent instructions |
// Both must be memory instructions |
// Both must be writes, or both must be reads |
666,7 → 624,9
// However ... we need to know this before this clock, hence this is |
// calculated in the instruction decoder. |
always @(posedge i_clk) |
if (op_ce) |
if (clear_pipeline) |
r_op_pipe <= 1'b0; |
else if (op_ce) |
r_op_pipe <= dcd_pipe; |
else if (mem_ce) // Clear us any time an op_ is clocked in |
r_op_pipe <= 1'b0; |
681,35 → 641,19
// |
// |
`ifdef OPT_NO_USERMODE |
assign w_opA = regset[dcdA[3:0]]; |
assign w_opB = regset[dcdB[3:0]]; |
assign w_op_Av = regset[dcd_A[3:0]]; |
assign w_op_Bv = regset[dcd_B[3:0]]; |
`else |
assign w_opA = regset[dcdA]; |
assign w_opB = regset[dcdB]; |
assign w_op_Av = regset[dcd_A]; |
assign w_op_Bv = regset[dcd_B]; |
`endif |
|
wire [8:0] w_cpu_info; |
assign w_cpu_info = { |
`ifdef OPT_ILLEGAL_INSTRUCTION |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_MULTIPLY |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_DIVIDE |
1'b1, |
`else |
1'b0, |
`endif |
`ifdef OPT_IMPLEMENT_FPU |
1'b1, |
`else |
1'b0, |
`endif |
(IMPLEMENT_MPY >0)? 1'b1:1'b0, |
(IMPLEMENT_DIVIDE >0)? 1'b1:1'b0, |
(IMPLEMENT_FPU >0)? 1'b1:1'b0, |
`ifdef OPT_PIPELINED |
1'b1, |
`else |
730,7 → 674,7
`else |
1'b0, |
`endif |
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
1'b1 |
`else |
1'b0 |
738,79 → 682,79
}; |
|
wire [31:0] w_pcA_v; |
assign w_pcA_v[(AW+1):0] = { (dcd_A[4] == dcd_gie) |
? { dcd_pc[AW:1], 2'b00 } |
: { upc[(AW+1):2], uhalt_phase, 1'b0 } }; |
generate |
if (AW < 32) |
assign w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc; |
if (AW < 30) |
assign w_pcA_v[31:(AW+2)] = 0; |
endgenerate |
|
`ifdef OPT_PIPELINED |
reg [4:0] opA_id, opB_id; |
reg opA_rd, opB_rd; |
reg [4:0] op_Aid, op_Bid; |
reg op_rA, op_rB; |
always @(posedge i_clk) |
if (op_ce) |
begin |
opA_id <= dcdA; |
opB_id <= dcdB; |
opA_rd <= dcdA_rd; |
opB_rd <= dcdB_rd; |
op_Aid <= dcd_A; |
op_Bid <= dcd_B; |
op_rA <= dcd_rA; |
op_rB <= dcd_rB; |
end |
`endif |
|
always @(posedge i_clk) |
`ifdef OPT_PIPELINED |
if (op_change_data_ce) |
`endif |
if (op_ce) |
begin |
`ifdef OPT_PIPELINED |
if ((wr_reg_ce)&&(wr_reg_id == dcdA)) |
r_opA <= wr_gpreg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == dcd_A)) |
r_op_Av <= wr_gpreg_vl; |
else |
`endif |
if (dcdA_pc) |
r_opA <= w_pcA_v; |
else if (dcdA_cc) |
r_opA <= { w_cpu_info, w_opA[22:16], 1'b0, (dcdA[4])?w_uflags:w_iflags }; |
if (dcd_Apc) |
r_op_Av <= w_pcA_v; |
else if (dcd_Acc) |
r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags }; |
else |
r_opA <= w_opA; |
r_op_Av <= w_op_Av; |
`ifdef OPT_PIPELINED |
end else |
begin // We were going to pick these up when they became valid, |
// but for some reason we're stuck here as they became |
// valid. Pick them up now anyway |
// if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid))) |
// r_opA <= wr_gpreg_vl; |
if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd)) |
r_opA <= wr_gpreg_vl; |
begin |
if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA)) |
r_op_Av <= wr_gpreg_vl; |
`endif |
end |
|
wire [31:0] w_opBnI, w_pcB_v; |
wire [31:0] w_op_BnI, w_pcB_v; |
assign w_pcB_v[(AW+1):0] = { (dcd_B[4] == dcd_gie) |
? { dcd_pc[AW:1], 2'b00 } |
: { upc[(AW+1):2], uhalt_phase, 1'b0 } }; |
generate |
if (AW < 32) |
assign w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc }; |
else |
assign w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc; |
if (AW < 30) |
assign w_pcB_v[31:(AW+2)] = 0; |
endgenerate |
|
assign w_opBnI = (~dcdB_rd) ? 32'h00 |
assign w_op_BnI = (!dcd_rB) ? 32'h00 |
`ifdef OPT_PIPELINED |
: ((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl |
: ((wr_reg_ce)&&(wr_reg_id == dcd_B)) ? wr_gpreg_vl |
`endif |
: ((dcdB_pc) ? w_pcB_v |
: ((dcdB_cc) ? { w_cpu_info, w_opB[22:16], // w_opB[31:14], |
1'b0, (dcdB[4])?w_uflags:w_iflags} |
: w_opB)); |
: ((dcd_Bcc) ? { w_cpu_info, w_op_Bv[22:16], // w_op_B[31:14], |
1'b0, (dcd_B[4])?w_uflags:w_iflags} |
: w_op_Bv); |
|
always @(posedge i_clk) |
`ifdef OPT_PIPELINED |
if (op_change_data_ce) |
r_opB <= w_opBnI + dcdI; |
else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd)) |
r_opB <= wr_gpreg_vl; |
if ((op_ce)&&(dcd_Bpc)&&(dcd_rB)) |
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 }; |
else if (op_ce) |
r_op_Bv <= w_op_BnI + dcd_I; |
else if ((wr_reg_ce)&&(op_Bid == wr_reg_id)&&(op_rB)) |
r_op_Bv <= wr_gpreg_vl; |
`else |
r_opB <= w_opBnI + dcdI; |
if ((dcd_Bpc)&&(dcd_rB)) |
r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 }; |
else |
r_op_Bv <= w_op_BnI + dcd_I; |
`endif |
|
// The logic here has become more complex than it should be, no thanks |
821,54 → 765,40
// conditions checking those bits. Therefore, Vivado complains that |
// these two bits are redundant. Hence the convoluted expression |
// below, arriving at what we finally want in the (now wire net) |
// opF. |
// op_F. |
always @(posedge i_clk) |
`ifdef OPT_PIPELINED |
if (op_ce) // Cannot do op_change_data_ce here since opF depends |
if (op_ce) // Cannot do op_change_data_ce here since op_F depends |
// upon being either correct for a valid op, or correct |
// for the last valid op |
`endif |
begin // Set the flag condition codes, bit order is [3:0]=VNCZ |
case(dcdF[2:0]) |
3'h0: r_opF <= 6'h00; // Always |
`ifdef OPT_NEW_INSTRUCTION_SET |
// These were remapped as part of the new instruction |
// set in order to make certain that the low order |
// two bits contained the most commonly used |
// conditions: Always, LT, Z, and NZ. |
3'h1: r_opF <= 6'h24; // LT |
3'h2: r_opF <= 6'h11; // Z |
3'h3: r_opF <= 6'h10; // NE |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h20; // GE (!N) |
`else |
3'h1: r_opF <= 6'h11; // Z |
3'h2: r_opF <= 6'h10; // NE |
3'h3: r_opF <= 6'h20; // GE (!N) |
3'h4: r_opF <= 6'h30; // GT (!N&!Z) |
3'h5: r_opF <= 6'h24; // LT |
`endif |
3'h6: r_opF <= 6'h02; // C |
3'h7: r_opF <= 6'h08; // V |
case(dcd_F[2:0]) |
3'h0: r_op_F <= 7'h00; // Always |
3'h1: r_op_F <= 7'h11; // Z |
3'h2: r_op_F <= 7'h44; // LT |
3'h3: r_op_F <= 7'h22; // C |
3'h4: r_op_F <= 7'h08; // V |
3'h5: r_op_F <= 7'h10; // NE |
3'h6: r_op_F <= 7'h40; // GE (!N) |
3'h7: r_op_F <= 7'h20; // NC |
endcase |
end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value } |
assign opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] }; |
assign op_F = { r_op_F[3], r_op_F[6:0] }; |
|
wire w_opvalid; |
assign w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp)&&(!dcd_early_branch); |
initial opvalid = 1'b0; |
initial opvalid_alu = 1'b0; |
initial opvalid_mem = 1'b0; |
initial opvalid_div = 1'b0; |
initial opvalid_fpu = 1'b0; |
wire w_op_valid; |
assign w_op_valid = (!clear_pipeline)&&(dcd_valid)&&(!dcd_ljmp)&&(!dcd_early_branch); |
initial op_valid = 1'b0; |
initial op_valid_alu = 1'b0; |
initial op_valid_mem = 1'b0; |
initial op_valid_div = 1'b0; |
initial op_valid_fpu = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
opvalid_div <= 1'b0; |
opvalid_fpu <= 1'b0; |
op_valid <= 1'b0; |
op_valid_alu <= 1'b0; |
op_valid_mem <= 1'b0; |
op_valid_div <= 1'b0; |
op_valid_fpu <= 1'b0; |
end else if (op_ce) |
begin |
// Do we have a valid instruction? |
879,26 → 809,19
// Hence, the test on dcd_stalled here. If we must |
// wait until our operands are valid, then we aren't |
// valid yet until then. |
opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid)||(dcd_early_branch); |
`ifdef OPT_ILLEGAL_INSTRUCTION |
opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal) |
op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch); |
op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal) |
||(dcd_early_branch)); |
opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid); |
`else |
opvalid_alu <= (dcdALU)&&(w_opvalid)||(dcd_early_branch); |
opvalid_mem <= (dcdM)&&(w_opvalid); |
opvalid_div <= (dcdDV)&&(w_opvalid); |
opvalid_fpu <= (dcdFP)&&(w_opvalid); |
`endif |
op_valid_mem <= (dcd_M)&&(!dcd_illegal)&&(w_op_valid); |
op_valid_div <= (dcd_DIV)&&(!dcd_illegal)&&(w_op_valid); |
op_valid_fpu <= (dcd_FP)&&(!dcd_illegal)&&(w_op_valid); |
end else if ((adf_ce_unconditional)||(mem_ce)) |
begin |
opvalid <= 1'b0; |
opvalid_alu <= 1'b0; |
opvalid_mem <= 1'b0; |
opvalid_div <= 1'b0; |
opvalid_fpu <= 1'b0; |
op_valid <= 1'b0; |
op_valid_alu <= 1'b0; |
op_valid_mem <= 1'b0; |
op_valid_div <= 1'b0; |
op_valid_fpu <= 1'b0; |
end |
|
// Here's part of our debug interface. When we recognize a break |
909,52 → 832,37
// condition, replace the break instruction with what it is supposed |
// to be, step through it, and then replace it back. In this fashion, |
// a debugger can step through code. |
// assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001); |
`ifdef OPT_PIPELINED |
// assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001); |
reg r_op_break; |
|
initial r_op_break = 1'b0; |
always @(posedge i_clk) |
if (i_rst) r_op_break <= 1'b0; |
else if (op_ce) r_op_break <= (dcd_break); |
else if ((clear_pipeline)||(~opvalid)) |
r_op_break <= 1'b0; |
if ((i_rst)||(clear_pipeline)) r_op_break <= 1'b0; |
else if (op_ce) |
r_op_break <= (dcd_break); |
else if (!op_valid) |
r_op_break <= 1'b0; |
assign op_break = r_op_break; |
`else |
assign op_break = dcd_break; |
`endif |
|
`ifdef OPT_PIPELINED |
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_op_lock, r_op_lock_stall; |
reg r_op_lock; |
|
initial r_op_lock_stall = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_op_lock_stall <= 1'b0; |
else |
r_op_lock_stall <= (~opvalid)||(~op_lock) |
||(~dcdvalid)||(~pf_valid); |
|
assign op_lock_stall = r_op_lock_stall; |
|
initial r_op_lock = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
r_op_lock <= 1'b0; |
else if (op_ce) |
r_op_lock <= (dcd_lock)&&(~clear_pipeline); |
r_op_lock <= (dcd_valid)&&(dcd_lock)&&(!clear_pipeline); |
assign op_lock = r_op_lock; |
|
end else begin |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
end endgenerate |
|
`else |
assign op_lock_stall = 1'b0; |
assign op_lock = 1'b0; |
`endif |
|
961,13 → 869,13
`ifdef OPT_ILLEGAL_INSTRUCTION |
initial op_illegal = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
op_illegal <= 1'b0; |
else if(op_ce) |
`ifdef OPT_PIPELINED |
op_illegal <= (dcdvalid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0))); |
op_illegal <= (dcd_valid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0))); |
`else |
op_illegal <= (dcdvalid)&&((dcd_illegal)||(dcd_lock)); |
op_illegal <= (dcd_valid)&&((dcd_illegal)||(dcd_lock)); |
`endif |
else if(alu_ce) |
op_illegal <= 1'b0; |
980,70 → 888,73
always @(posedge i_clk) |
if (op_ce) |
begin |
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr)) |
&&(~dcd_early_branch)&&(~dcd_illegal); |
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal); |
op_wF <= (dcd_wF)&&((!dcd_Rcc)||(!dcd_wR)) |
&&(!dcd_early_branch)&&(!dcd_illegal); |
op_wR <= (dcd_wR)&&(!dcd_early_branch)&&(!dcd_illegal); |
end |
`else |
always @(posedge i_clk) |
begin |
opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr)) |
&&(~dcd_early_branch)&&(~dcd_illegal); |
opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal); |
op_wF <= (dcd_wF)&&((!dcd_Rcc)||(!dcd_wR)) |
&&(!dcd_early_branch)&&(!dcd_illegal); |
op_wR <= (dcd_wR)&&(!dcd_early_branch)&&(!dcd_illegal); |
end |
`endif |
|
`ifdef OPT_PIPELINED |
reg [3:0] r_opn; |
reg [4:0] r_opR; |
reg r_opR_cc; |
`ifdef VERILATOR |
`ifdef SINGLE_FETCH |
always @(*) |
begin |
op_sim = dcd_sim; |
op_sim_immv = dcd_sim_immv; |
end |
`else |
always @(posedge i_clk) |
if (op_change_data_ce) |
begin |
op_sim <= dcd_sim; |
op_sim_immv <= dcd_sim_immv; |
end |
`endif |
`endif |
|
reg [3:0] r_op_opn; |
reg [4:0] r_op_R; |
reg r_op_Rcc; |
reg r_op_gie; |
|
initial r_op_gie = 1'b0; |
always @(posedge i_clk) |
if (op_change_data_ce) |
begin |
// Which ALU operation? Early branches are |
// unimplemented moves |
r_opn <= (dcd_early_branch) ? 4'hf : dcdOp; |
// opM <= dcdM; // Is this a memory operation? |
r_op_opn <= (dcd_early_branch) ? 4'hf : dcd_opn; |
// opM <= dcd_M; // Is this a memory operation? |
// What register will these results be written into? |
r_opR <= dcdR; |
r_opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie); |
r_op_R <= dcd_R; |
r_op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie); |
// User level (1), vs supervisor (0)/interrupts disabled |
r_op_gie <= dcd_gie; |
|
// |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1]; |
end |
assign opn = r_opn; |
assign opR = r_opR; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign op_opn = r_op_opn; |
assign op_R = r_op_R; |
assign op_gie = r_op_gie; |
`endif |
assign opR_cc = r_opR_cc; |
`else |
assign opn = dcdOp; |
assign opR = dcdR; |
`ifdef OPT_NO_USERMODE |
assign op_gie = 1'b0; |
`else |
assign op_gie = dcd_gie; |
`endif |
// With no pipelining, there is no early branching. We keep it |
always @(posedge i_clk) |
op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc; |
`endif |
assign opFl = (op_gie)?(w_uflags):(w_iflags); |
assign op_Rcc = r_op_Rcc; |
|
`ifdef OPT_VLIW |
assign op_Fl = (op_gie)?(w_uflags):(w_iflags); |
|
`ifdef OPT_CIS |
reg r_op_phase; |
initial r_op_phase = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
r_op_phase <= 1'b0; |
else if (op_change_data_ce) |
r_op_phase <= dcd_phase; |
r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc)); |
assign op_phase = r_op_phase; |
`else |
assign op_phase = 1'b0; |
1062,10 → 973,10
// define this flag to something other than just plain zero, then |
// the stalls will already be in place. |
`ifdef OPT_PIPELINED |
assign opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd)) |
? wr_gpreg_vl : r_opA; |
assign op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid)) // &&(op_rA)) |
? wr_gpreg_vl : r_op_Av; |
`else |
assign opA = r_opA; |
assign op_Av = r_op_Av; |
`endif |
|
`ifdef OPT_PIPELINED |
1075,21 → 986,21
// The operation might set flags, and we wish to read the |
// CC register |
// OR ... (No other conditions) |
assign dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere |
&&((opvalid)||(mem_rdbusy) |
assign dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere |
&&((op_valid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)) |
&&(((opF_wr)||(cc_invalid_for_dcd))&&(dcdA_cc)) |
||((dcdA_rd)&&(dcdA_cc)&&(cc_invalid_for_dcd)); |
&&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc)) |
||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd)); |
`else |
// There are no pipeline hazards, if we aren't pipelined |
assign dcdA_stall = 1'b0; |
assign dcd_A_stall = 1'b0; |
`endif |
|
`ifdef OPT_PIPELINED |
assign opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd)) |
? wr_gpreg_vl: r_opB; |
assign op_Bv = ((wr_reg_ce)&&(wr_reg_id == op_Bid)&&(op_rB)) |
? wr_gpreg_vl: r_op_Bv; |
`else |
assign opB = r_opB; |
assign op_Bv = r_op_Bv; |
`endif |
|
`ifdef OPT_PIPELINED |
1100,12 → 1011,12
// CC register |
// OR the operation might set register B, and we still need |
// a clock to add the offset to it |
assign dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere |
assign dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere |
// If the op stage isn't valid, yet something |
// is running, then it must have been valid. |
// We'll use the last values from that stage |
// (opR_wr, opF_wr, opR) in our logic below. |
&&((opvalid)||(mem_rdbusy) |
// (op_wR, op_wF, op_R) in our logic below. |
&&((op_valid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)||(alu_busy)) |
&&( |
// Okay, what happens if the result register |
1112,13 → 1023,13
// from instruction 1 becomes the input for |
// instruction two, *and* there's an immediate |
// offset in instruction two? In that case, we |
// need an extra clock between the two |
// instructions to calculate the base plus |
// need an extra clock between the two |
// instructions to calculate the base plus |
// offset. |
// |
// What if instruction 1 (or before) is in a |
// memory pipeline? We may no longer know what |
// the register was! We will then need to |
// the register was! We will then need to |
// blindly wait. We'll temper this only waiting |
// if we're not piping this new instruction. |
// If we were piping, the pipe logic in the |
1125,29 → 1036,29
// decode circuit has told us that the hazard |
// is clear, so we're okay then. |
// |
((~dcd_zI)&&( |
((opR == dcdB)&&(opR_wr)) |
||((mem_rdbusy)&&(~dcd_pipe)) |
((!dcd_zI)&&( |
((op_R == dcd_B)&&(op_wR)) |
||((mem_rdbusy)&&(!dcd_pipe)) |
)) |
// Stall following any instruction that will |
// set the flags, if we're going to need the |
// flags (CC) register for opB. |
||(((opF_wr)||(cc_invalid_for_dcd))&&(dcdB_cc)) |
// flags (CC) register for op_B. |
||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc)) |
// Stall on any ongoing memory operation that |
// will write to opB -- captured above |
// ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI)) |
// will write to op_B -- captured above |
// ||((mem_busy)&&(!mem_we)&&(mem_last_reg==dcd_B)&&(!dcd_zI)) |
) |
||((dcdB_rd)&&(dcdB_cc)&&(cc_invalid_for_dcd)); |
assign dcdF_stall = ((~dcdF[3]) |
||((dcdA_rd)&&(dcdA_cc)) |
||((dcdB_rd)&&(dcdB_cc))) |
&&(opvalid)&&(opR_cc); |
// &&(dcdvalid) is checked for elsewhere |
||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd)); |
assign dcd_F_stall = ((!dcd_F[3]) |
||((dcd_rA)&&(dcd_Acc)) |
||((dcd_rB)&&(dcd_Bcc))) |
&&(op_valid)&&(op_Rcc); |
// &&(dcd_valid) is checked for elsewhere |
`else |
// No stalls without pipelining, 'cause how can you have a pipeline |
// hazard without the pipeline? |
assign dcdB_stall = 1'b0; |
assign dcdF_stall = 1'b0; |
assign dcd_B_stall = 1'b0; |
assign dcd_F_stall = 1'b0; |
`endif |
// |
// |
1154,15 → 1065,15
// PIPELINE STAGE #4 :: Apply Instruction |
// |
// |
cpuops #(IMPLEMENT_MPY) doalu(i_clk, (i_rst)||(clear_pipeline), |
alu_ce, opn, opA, opB, |
cpuops #(IMPLEMENT_MPY) doalu(i_clk, (clear_pipeline), |
alu_ce, op_opn, op_Av, op_Bv, |
alu_result, alu_flags, alu_valid, alu_busy); |
|
generate |
if (IMPLEMENT_DIVIDE != 0) |
begin |
div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0], |
opA, opB, div_busy, div_valid, div_error, div_result, |
div thedivide(i_clk, (clear_pipeline), div_ce, op_opn[0], |
op_Av, op_Bv, div_busy, div_valid, div_error, div_result, |
div_flags); |
end else begin |
assign div_error = 1'b0; // Can't be high unless div_valid |
1177,7 → 1088,7
begin |
// |
// sfpu thefpu(i_clk, i_rst, fpu_ce, |
// opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result, |
// op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result, |
// fpu_flags); |
// |
assign fpu_error = 1'b0; // Must only be true if fpu_valid |
1194,27 → 1105,27
end endgenerate |
|
|
assign set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]); |
initial alF_wr = 1'b0; |
initial alu_wr = 1'b0; |
assign set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]); |
initial alu_wF = 1'b0; |
initial alu_wR = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
alu_wr <= 1'b0; |
alF_wr <= 1'b0; |
alu_wR <= 1'b0; |
alu_wF <= 1'b0; |
end else if (alu_ce) |
begin |
// alu_reg <= opR; |
alu_wr <= (opR_wr)&&(set_cond); |
alF_wr <= (opF_wr)&&(set_cond); |
end else if (~alu_busy) begin |
// alu_reg <= op_R; |
alu_wR <= (op_wR)&&(set_cond); |
alu_wF <= (op_wF)&&(set_cond); |
end else if (!alu_busy) begin |
// These are strobe signals, so clear them if not |
// set for any particular clock |
alu_wr <= (i_halt)&&(i_dbg_we); |
alF_wr <= 1'b0; |
alu_wR <= (i_halt)&&(i_dbg_we); |
alu_wF <= 1'b0; |
end |
|
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
reg r_alu_phase; |
initial r_alu_phase = 1'b0; |
always @(posedge i_clk) |
1230,7 → 1141,7
`ifdef OPT_PIPELINED |
always @(posedge i_clk) |
if (adf_ce_unconditional) |
alu_reg <= opR; |
alu_reg <= op_R; |
else if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
`else |
1238,7 → 1149,7
if ((i_halt)&&(i_dbg_we)) |
alu_reg <= i_dbg_reg; |
else |
alu_reg <= opR; |
alu_reg <= op_R; |
`endif |
|
// |
1247,7 → 1158,7
reg dbgv; |
initial dbgv = 1'b0; |
always @(posedge i_clk) |
dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted); |
dbgv <= (!i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted); |
reg [31:0] dbg_val; |
always @(posedge i_clk) |
dbg_val <= i_dbg_data; |
1270,8 → 1181,8
reg [(AW-1):0] r_alu_pc; |
always @(posedge i_clk) |
if ((adf_ce_unconditional) |
||((master_ce)&&(opvalid_mem)&&(~clear_pipeline) |
&&(~mem_stalled))) |
||((master_ce)&&(op_valid_mem)&&(!clear_pipeline) |
&&(!mem_stalled))) |
r_alu_pc <= op_pc; |
assign alu_pc = r_alu_pc; |
`else |
1278,11 → 1189,10
assign alu_pc = op_pc; |
`endif |
|
`ifdef OPT_ILLEGAL_INSTRUCTION |
reg r_alu_illegal; |
initial r_alu_illegal = 0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)) |
if (clear_pipeline) |
r_alu_illegal <= 1'b0; |
else if (alu_ce) |
r_alu_illegal <= op_illegal; |
1289,20 → 1199,17
else |
r_alu_illegal <= 1'b0; |
assign alu_illegal = (r_alu_illegal); |
`else |
assign alu_illegal = 1'b0; |
`endif |
|
initial r_alu_pc_valid = 1'b0; |
initial mem_pc_valid = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
if (clear_pipeline) |
r_alu_pc_valid <= 1'b0; |
else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline) |
else if ((adf_ce_unconditional)&&(!op_phase)) |
r_alu_pc_valid <= 1'b1; |
else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline)) |
else if (((!alu_busy)&&(!div_busy)&&(!fpu_busy))||(clear_pipeline)) |
r_alu_pc_valid <= 1'b0; |
assign alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy)); |
assign alu_pc_valid = (r_alu_pc_valid)&&((!alu_busy)&&(!div_busy)&&(!fpu_busy)); |
always @(posedge i_clk) |
if (i_rst) |
mem_pc_valid <= 1'b0; |
1314,17 → 1221,43
generate |
if (IMPLEMENT_LOCK != 0) |
begin |
reg r_prelock_stall; |
|
initial r_prelock_stall = 1'b0; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_prelock_stall <= 1'b0; |
else if ((op_valid)&&(op_lock)&&(op_ce)) |
r_prelock_stall <= 1'b1; |
else if ((op_valid)&&(dcd_valid)&&(pf_valid)) |
r_prelock_stall <= 1'b0; |
|
assign prelock_stall = r_prelock_stall; |
|
reg r_prelock_primed; |
always @(posedge i_clk) |
if (clear_pipeline) |
r_prelock_primed <= 1'b0; |
else if (r_prelock_stall) |
r_prelock_primed <= 1'b1; |
else if ((adf_ce_unconditional)||(mem_ce)) |
r_prelock_primed <= 1'b0; |
|
reg [1:0] r_bus_lock; |
initial r_bus_lock = 2'b00; |
always @(posedge i_clk) |
if (i_rst) |
if (clear_pipeline) |
r_bus_lock <= 2'b00; |
else if ((op_ce)&&(op_lock)) |
r_bus_lock <= 2'b11; |
else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce))) |
r_bus_lock <= r_bus_lock + 2'b11; |
else if ((op_valid)&&((adf_ce_unconditional)||(mem_ce))) |
begin |
if (r_prelock_primed) |
r_bus_lock <= 2'b10; |
else if (r_bus_lock != 2'h0) |
r_bus_lock <= r_bus_lock + 2'b11; |
end |
assign bus_lock = |r_bus_lock; |
end else begin |
assign prelock_stall = 1'b0; |
assign bus_lock = 1'b0; |
end endgenerate |
`else |
1333,39 → 1266,50
|
`ifdef OPT_PIPELINED_BUS_ACCESS |
pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(opn[0]), opB, opA, opR, |
(op_opn[2:0]), op_Bv, op_Av, op_R, |
mem_busy, mem_pipe_stalled, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, i_wb_data); |
|
|
`else // PIPELINED_BUS_ACCESS |
memops #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock, |
(opn[0]), opB, opA, opR, |
memops #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst, |
(mem_ce)&&(set_cond), bus_lock, |
(op_opn[2:0]), op_Bv, op_Av, op_R, |
mem_busy, |
mem_valid, bus_err, mem_wreg, mem_result, |
mem_cyc_gbl, mem_cyc_lcl, |
mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, i_wb_data); |
assign mem_pipe_stalled = 1'b0; |
`endif // PIPELINED_BUS_ACCESS |
assign mem_rdbusy = ((mem_busy)&&(~mem_we)); |
assign mem_rdbusy = ((mem_busy)&&(!mem_we)); |
|
// Either the prefetch or the instruction gets the memory bus, but |
// Either the prefetch or the instruction gets the memory bus, but |
// never both. |
wbdblpriarb #(32,AW) pformem(i_clk, i_rst, |
// Memory access to the arbiter, priority position |
mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, |
mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err, |
mem_we, mem_addr, mem_data, mem_sel, |
mem_ack, mem_stall, mem_err, |
// Prefetch access to the arbiter |
pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, |
// |
// At a first glance, we might want something like: |
// |
// pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf, |
// |
// However, we know that the prefetch will not generate any |
// writes. Therefore, the write specific lines (mem_data and |
// mem_sel) can be shared with the memory in order to ease |
// timing and LUT usage. |
pf_cyc,1'b0,pf_stb, 1'b0, pf_we, pf_addr, mem_data, mem_sel, |
pf_ack, pf_stall, pf_err, |
// Common wires, in and out, of the arbiter |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, |
o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb, |
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_err); |
|
|
1392,19 → 1336,12
// When shall we write back? On one of two conditions |
// Note that the flags needed to be checked before issuing the |
// bus instruction, so they don't need to be checked here. |
// Further, alu_wr includes (set_cond), so we don't need to |
// Further, alu_wR includes (set_cond), so we don't need to |
// check for that here either. |
`ifdef OPT_ILLEGAL_INSTRUCTION |
assign wr_reg_ce = (dbgv)||(mem_valid) |
||((~clear_pipeline)&&(~alu_illegal) |
&&(((alu_wr)&&(alu_valid)) |
||((!clear_pipeline)&&(!alu_illegal) |
&&(((alu_wR)&&(alu_valid)) |
||(div_valid)||(fpu_valid))); |
`else |
assign wr_reg_ce = (dbgv)||(mem_valid) |
||((~clear_pipeline) |
&&(((alu_wr)&&(alu_valid)) |
||(div_valid)||(fpu_valid))); |
`endif |
// Which register shall be written? |
// COULD SIMPLIFY THIS: by adding three bits to these registers, |
// One or PC, one for CC, and one for GIE match |
1411,11 → 1348,11
// Note that the alu_reg is the register to write on a divide or |
// FPU operation. |
`ifdef OPT_NO_USERMODE |
assign wr_reg_id[3:0] = (alu_wr|div_valid|fpu_valid) |
assign wr_reg_id[3:0] = (alu_wR|div_valid|fpu_valid) |
? alu_reg[3:0]:mem_wreg[3:0]; |
assign wr_reg_id[4] = 1'b0; |
`else |
assign wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg; |
assign wr_reg_id = (alu_wR|div_valid|fpu_valid)?alu_reg:mem_wreg; |
`endif |
|
// Are we writing to the CC register? |
1442,9 → 1379,9
|
// |
// Write back to the condition codes/flags register ... |
// When shall we write to our flags register? alF_wr already |
// When shall we write to our flags register? alu_wF already |
// includes the set condition ... |
assign wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal); |
assign wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(!clear_pipeline)&&(!alu_illegal); |
assign w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag, |
udiv_err_flag, ubus_err_flag, trap, ill_err_u, |
ubreak, step, 1'b1, sleep, |
1452,7 → 1389,7
assign w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag, |
idiv_err_flag, ibus_err_flag, trap, ill_err_i, |
break_en, 1'b0, 1'b0, sleep, |
((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags }; |
((wr_flags_ce)&&(!alu_gie))?alu_flags:iflags }; |
|
|
// What value to write? |
1468,7 → 1405,7
always @(posedge i_clk) |
if ((wr_reg_ce)&&(wr_write_scc)) |
iflags <= wr_gpreg_vl[3:0]; |
else if ((wr_flags_ce)&&(~alu_gie)) |
else if ((wr_flags_ce)&&(!alu_gie)) |
iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags |
: alu_flags); |
|
1478,7 → 1415,7
// |
// The goal, upon encountering a break is that the CPU should stop and |
// not execute the break instruction, choosing instead to enter into |
// either interrupt mode or halt first. |
// either interrupt mode or halt first. |
// if ((break_en) AND (break_instruction)) // user mode or not |
// HALT CPU |
// else if (break_instruction) // only in user mode |
1499,10 → 1436,10
|
initial r_break_pending = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(clear_pipeline)||(~opvalid)) |
if ((clear_pipeline)||(!op_valid)) |
r_break_pending <= 1'b0; |
else if (op_break) |
r_break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy)&&(!wr_reg_ce); |
r_break_pending <= (!alu_busy)&&(!div_busy)&&(!fpu_busy)&&(!mem_busy)&&(!wr_reg_ce); |
else |
r_break_pending <= 1'b0; |
assign break_pending = r_break_pending; |
1511,18 → 1448,18
`endif |
|
|
assign o_break = ((break_en)||(~op_gie))&&(break_pending) |
&&(~clear_pipeline) |
||((~alu_gie)&&(bus_err)) |
||((~alu_gie)&&(div_error)) |
||((~alu_gie)&&(fpu_error)) |
||((~alu_gie)&&(alu_illegal)&&(!clear_pipeline)); |
assign o_break = ((break_en)||(!op_gie))&&(break_pending) |
&&(!clear_pipeline) |
||((!alu_gie)&&(bus_err)) |
||((!alu_gie)&&(div_error)) |
||((!alu_gie)&&(fpu_error)) |
||((!alu_gie)&&(alu_illegal)&&(!clear_pipeline)); |
|
// The sleep register. Setting the sleep register causes the CPU to |
// sleep until the next interrupt. Setting the sleep register within |
// interrupt mode causes the processor to halt until a reset. This is |
// a panic/fault halt. The trick is that you cannot be allowed to |
// set the sleep bit and switch to supervisor mode in the same |
// set the sleep bit and switch to supervisor mode in the same |
// instruction: users are not allowed to halt the CPU. |
initial sleep = 1'b0; |
`ifdef OPT_NO_USERMODE |
1533,7 → 1470,7
r_sleep_is_halt <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc) |
&&(wr_spreg_vl[`CPU_SLEEP_BIT]) |
&&(~wr_spreg_vl[`CPU_GIE_BIT])) |
&&(!wr_spreg_vl[`CPU_GIE_BIT])) |
r_sleep_is_halt <= 1'b1; |
|
// Trying to switch to user mode, either via a WAIT or an RTU |
1549,7 → 1486,7
always @(posedge i_clk) |
if ((i_rst)||(w_switch_to_interrupt)) |
sleep <= 1'b0; |
else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie)) |
else if ((wr_reg_ce)&&(wr_write_cc)&&(!alu_gie)) |
// In supervisor mode, we have no protections. The |
// supervisor can set the sleep bit however he wants. |
// Well ... not quite. Switching to user mode and |
1559,7 → 1496,7
// don't set the sleep bit |
// otherwise however it would o.w. be set |
sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT]) |
&&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT])); |
&&((!i_interrupt)||(!wr_spreg_vl[`CPU_GIE_BIT])); |
else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT])) |
// In user mode, however, you can only set the sleep |
// mode while remaining in user mode. You can't switch |
1571,7 → 1508,7
always @(posedge i_clk) |
if (i_rst) |
step <= 1'b0; |
else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc)) |
else if ((wr_reg_ce)&&(!alu_gie)&&(wr_write_ucc)) |
step <= wr_spreg_vl[`CPU_STEP_BIT]; |
|
// The GIE register. Only interrupts can disable the interrupt register |
1581,16 → 1518,14
`else |
assign w_switch_to_interrupt = (gie)&&( |
// On interrupt (obviously) |
((i_interrupt)&&(~alu_phase)&&(~bus_lock)) |
((i_interrupt)&&(!alu_phase)&&(!bus_lock)) |
// If we are stepping the CPU |
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock)) |
||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(!alu_phase)&&(!bus_lock)) |
// If we encounter a break instruction, if the break |
// enable isn't set. |
||((master_ce)&&(break_pending)&&(~break_en)) |
`ifdef OPT_ILLEGAL_INSTRUCTION |
||((master_ce)&&(break_pending)&&(!break_en)) |
// On an illegal instruction |
||((alu_illegal)&&(!clear_pipeline)) |
`endif |
// On division by zero. If the divide isn't |
// implemented, div_valid and div_error will be short |
// circuited and that logic will be bypassed |
1599,13 → 1534,13
// fpu_error must *never* be set unless fpu_valid is |
// also set as well, else this will fail. |
||(fpu_error) |
// |
// |
||(bus_err) |
// If we write to the CC register |
||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT]) |
||((wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_reg_id[4])&&(wr_write_cc)) |
); |
assign w_release_from_interrupt = (~gie)&&(~i_interrupt) |
assign w_release_from_interrupt = (!gie)&&(!i_interrupt) |
// Then if we write the sCC register |
&&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_scc)) |
1638,10 → 1573,10
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_trap <= 1'b0; |
else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT]) |
else if ((alu_gie)&&(wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT]) |
&&(wr_write_ucc)) // &&(wr_reg_id[4]) implied |
r_trap <= 1'b1; |
else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie)) |
else if ((wr_reg_ce)&&(wr_write_ucc)&&(!alu_gie)) |
r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]); |
|
reg r_ubreak; |
1652,7 → 1587,7
r_ubreak <= 1'b0; |
else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt)) |
r_ubreak <= 1'b1; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]); |
|
assign trap = r_trap; |
1668,7 → 1603,7
// Only the debug interface can clear this bit |
else if ((dbgv)&&(wr_write_scc)) |
ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]); |
else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline)) |
else if ((alu_illegal)&&(!alu_gie)&&(!clear_pipeline)) |
ill_err_i <= 1'b1; |
|
`ifdef OPT_NO_USERMODE |
1684,10 → 1619,12
r_ill_err_u <= 1'b0; |
// If the supervisor (or debugger) writes to this register, |
// clearing the bit, then clear it |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT])); |
else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline)) |
r_ill_err_u <= 1'b1; |
|
assign ill_err_u = r_ill_err_u; |
`endif |
`else |
assign ill_err_u = 1'b0; |
1701,11 → 1638,11
ibus_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_write_scc)) |
ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
else if ((bus_err)&&(~alu_gie)) |
else if ((bus_err)&&(!alu_gie)) |
ibus_err_flag <= 1'b1; |
// User bus error flag -- if ever set, it will cause an interrupt to |
// supervisor mode. |
`ifdef OPT_NO_USERMODE |
`ifdef OPT_NO_USERMODE |
assign ubus_err_flag = 1'b0; |
`else |
reg r_ubus_err_flag; |
1714,7 → 1651,7
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_ubus_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) |
r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]); |
else if ((bus_err)&&(alu_gie)) |
r_ubus_err_flag <= 1'b1; |
1736,7 → 1673,7
r_idiv_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_write_scc)) |
r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]); |
else if ((div_error)&&(~alu_gie)) |
else if ((div_error)&&(!alu_gie)) |
r_idiv_err_flag <= 1'b1; |
|
assign idiv_err_flag = r_idiv_err_flag; |
1744,12 → 1681,12
assign udiv_err_flag = 1'b0; |
`else |
// User divide (by zero) error flag -- if ever set, it will |
// cause a sudden switch interrupt to supervisor mode. |
// cause a sudden switch interrupt to supervisor mode. |
initial r_udiv_err_flag = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)||(w_release_from_interrupt)) |
r_udiv_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce) |
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce) |
&&(wr_write_ucc)) |
r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]); |
else if ((div_error)&&(alu_gie)) |
1774,15 → 1711,15
r_ifpu_err_flag <= 1'b0; |
else if ((dbgv)&&(wr_write_scc)) |
r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]); |
else if ((fpu_error)&&(fpu_valid)&&(~alu_gie)) |
else if ((fpu_error)&&(fpu_valid)&&(!alu_gie)) |
r_ifpu_err_flag <= 1'b1; |
// User floating point error flag -- if ever set, it will cause |
// a sudden switch interrupt to supervisor mode. |
// a sudden switch interrupt to supervisor mode. |
initial r_ufpu_err_flag = 1'b0; |
always @(posedge i_clk) |
if ((i_rst)&&(w_release_from_interrupt)) |
r_ufpu_err_flag <= 1'b0; |
else if (((~alu_gie)||(dbgv))&&(wr_reg_ce) |
else if (((!alu_gie)||(dbgv))&&(wr_reg_ce) |
&&(wr_write_ucc)) |
r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]); |
else if ((fpu_error)&&(alu_gie)&&(fpu_valid)) |
1795,7 → 1732,7
assign ufpu_err_flag = 1'b0; |
end endgenerate |
|
`ifdef OPT_VLIW |
`ifdef OPT_CIS |
reg r_ihalt_phase; |
|
initial r_ihalt_phase = 0; |
1802,7 → 1739,7
always @(posedge i_clk) |
if (i_rst) |
r_ihalt_phase <= 1'b0; |
else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline)) |
else if ((!alu_gie)&&(alu_pc_valid)&&(!clear_pipeline)) |
r_ihalt_phase <= alu_phase; |
|
assign ihalt_phase = r_ihalt_phase; |
1818,7 → 1755,7
r_uhalt_phase <= 1'b0; |
else if ((alu_gie)&&(alu_pc_valid)) |
r_uhalt_phase <= alu_phase; |
else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc)) |
else if ((!alu_gie)&&(wr_reg_ce)&&(wr_write_ucc)) |
r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT]; |
|
assign uhalt_phase = r_uhalt_phase; |
1835,56 → 1772,51
// the instruction writes the PC, we write whichever PC is appropriate. |
// |
// Do we need to all our partial results from the pipeline? |
// What happens when the pipeline has gie and ~gie instructions within |
// What happens when the pipeline has gie and !gie instructions within |
// it? Do we clear both? What if a gie instruction tries to clear |
// a non-gie instruction? |
`ifdef OPT_NO_USERMODE |
assign upc = {(AW){1'b0}}; |
assign upc = {(AW+2){1'b0}}; |
`else |
reg [(AW-1):0] r_upc; |
reg [(AW+1):0] r_upc; |
|
always @(posedge i_clk) |
if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc)) |
r_upc <= wr_spreg_vl[(AW-1):0]; |
r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
else if ((alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
(((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal)) |
||(mem_pc_valid))) |
r_upc <= alu_pc; |
r_upc <= { alu_pc, 2'b00 }; |
assign upc = r_upc; |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
ipc <= RESET_ADDRESS; |
else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc)) |
ipc <= wr_spreg_vl[(AW-1):0]; |
else if ((~alu_gie)&& |
(((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal)) |
ipc <= { RESET_BUS_ADDRESS, 2'b00 }; |
else if ((wr_reg_ce)&&(!wr_reg_id[4])&&(wr_write_pc)) |
ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
else if ((!alu_gie)&&(!alu_phase)&& |
(((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal)) |
||(mem_pc_valid))) |
ipc <= alu_pc; |
ipc <= { alu_pc, 2'b00 }; |
|
always @(posedge i_clk) |
if (i_rst) |
pf_pc <= RESET_ADDRESS; |
else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache))) |
pf_pc <= ipc; |
pf_pc <= { RESET_BUS_ADDRESS, 2'b00 }; |
else if ((w_switch_to_interrupt)||((!gie)&&(w_clear_icache))) |
pf_pc <= { ipc[(AW+1):2], 2'b00 }; |
else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache))) |
pf_pc <= upc; |
pf_pc <= { upc[(AW+1):2], 2'b00 }; |
else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) |
pf_pc <= wr_spreg_vl[(AW-1):0]; |
`ifdef OPT_PIPELINED |
else if ((dcd_early_branch)&&(~clear_pipeline)) |
pf_pc <= dcd_branch_pc + 1; |
else if ((new_pc)||((~dcd_stalled)&&(pf_valid))) |
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1}; |
`else |
else if ((alu_gie==gie)&&( |
((alu_pc_valid)&&(~clear_pipeline)) |
||(mem_pc_valid))) |
pf_pc <= alu_pc; |
`endif |
pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; |
else if ((dcd_early_branch)&&(!clear_pipeline)) |
pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 }; |
else if ((new_pc)||((!pf_stalled)&&(pf_valid))) |
pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 }; |
|
`ifdef OPT_PIPELINED |
// If we aren't pipelined, or equivalently if we have no cache, these |
// instructions will get quietly (or not so quietly) ignored by the |
// optimizer. |
reg r_clear_icache; |
initial r_clear_icache = 1'b1; |
always @(posedge i_clk) |
1895,9 → 1827,6
else |
r_clear_icache <= 1'b0; |
assign w_clear_icache = r_clear_icache; |
`else |
assign w_clear_icache = i_clear_pf_cache; |
`endif |
|
initial new_pc = 1'b1; |
always @(posedge i_clk) |
1915,20 → 1844,18
// |
// The debug interface |
wire [31:0] w_debug_pc; |
generate |
`ifdef OPT_NO_USERMODE |
if (AW<32) |
assign w_debug_pc = {{(32-AW){1'b0}},ipc}; |
else |
assign w_debug_pc = ipc; |
assign w_debug_pc[(AW+1):0] = { ipc, 2'b00 }; |
`else |
if (AW<32) |
assign w_debug_pc = {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc}; |
else |
assign w_debug_pc = (i_dbg_reg[4])?upc:ipc; |
assign w_debug_pc[(AW+1):0] = { (i_dbg_reg[4]) |
? { upc[(AW+1):2], uhalt_phase, 1'b0 } |
: { ipc[(AW+1):2], ihalt_phase, 1'b0 } }; |
`endif |
generate |
if (AW<30) |
assign w_debug_pc[31:(AW+2)] = 0; |
endgenerate |
|
|
always @(posedge i_clk) |
begin |
`ifdef OPT_NO_USERMODE |
1964,17 → 1891,17
r_halted <= (i_halt)&&( |
// To be halted, any long lasting instruction must |
// be completed. |
(~pf_cyc)&&(~mem_busy)&&(~alu_busy) |
&&(~div_busy)&&(~fpu_busy) |
(!pf_cyc)&&(!mem_busy)&&(!alu_busy) |
&&(!div_busy)&&(!fpu_busy) |
// Operations must either be valid, or illegal |
&&((opvalid)||(i_rst)||(dcd_illegal)) |
&&((op_valid)||(i_rst)||(dcd_illegal)) |
// Decode stage must be either valid, in reset, or ill |
&&((dcdvalid)||(i_rst)||(pf_illegal))); |
&&((dcd_valid)||(i_rst)||(pf_illegal))); |
`else |
always @(posedge i_clk) |
r_halted <= (i_halt)&&((opvalid)||(i_rst)); |
r_halted <= (i_halt)&&((op_valid)||(i_rst)); |
`endif |
assign o_dbg_stall = ~r_halted; |
assign o_dbg_stall = !r_halted; |
|
// |
// |
1983,19 → 1910,16
// |
// |
assign o_op_stall = (master_ce)&&(op_stall); |
assign o_pf_stall = (master_ce)&&(~pf_valid); |
assign o_i_count = (alu_pc_valid)&&(~clear_pipeline); |
assign o_pf_stall = (master_ce)&&(!pf_valid); |
assign o_i_count = (alu_pc_valid)&&(!clear_pipeline); |
|
`ifdef DEBUG_SCOPE |
// CLRPIP: If clear_pipeline, produce address ... can be 28 bits |
// DATWR: If write value, produce 4-bits of register ID, 27 bits of value |
// STALL: If neither, produce pipeline stall information |
// ADDR: If bus is valid, no ack, return the bus address |
wire this_write; |
assign this_write = ((mem_valid)||((~clear_pipeline)&&(~alu_illegal) |
&&(((alu_wr)&&(alu_valid)) |
||(div_valid)||(fpu_valid)))); |
reg last_write; |
wire this_write; |
assign this_write = ((mem_valid)||((!clear_pipeline)&&(!alu_illegal) |
&&(((alu_wR)&&(alu_valid)) |
||(div_valid)||(fpu_valid)))); |
reg last_write; |
|
always @(posedge i_clk) |
last_write <= this_write; |
|
2010,7 → 1934,7
halt_primed <= 1'b1; |
else if (debug_trigger) |
halt_primed <= 1'b0; |
|
|
reg [6:0] halt_count; |
initial halt_count = 0; |
always @(posedge i_clk) |
2044,9 → 1968,9
master_ce, i_halt, o_break, sleep, |
gie, ibus_err_flag, trap, ill_err_i, |
w_clear_icache, pf_valid, pf_illegal, dcd_ce, |
dcdvalid, dcd_stalled, op_ce, opvalid, |
op_pipe, alu_ce, alu_busy, alu_wr, |
alu_illegal, alF_wr, mem_ce, mem_we, |
dcd_valid, dcd_stalled, op_ce, op_valid, |
op_pipe, alu_ce, alu_busy, alu_wR, |
alu_illegal, alu_wF, mem_ce, mem_we, |
mem_busy, mem_pipe_stalled, (new_pc), (dcd_early_branch) }; |
|
wire [25:0] bus_debug; |
2059,17 → 1983,27
mem_cyc_gbl, mem_stb_gbl, mem_cyc_lcl, mem_stb_lcl, |
mem_we, mem_ack, mem_stall, mem_err |
}; |
|
|
wire [27:0] dbg_pc; |
generate if (AW-1 < 27) |
begin |
assign dbg_pc[(AW-1):0] = pf_pc[(AW+1):2]; |
assign dbg_pc[27:(AW-1)] = 0; |
end else // if (AW-1 >= 27) |
begin |
assign dbg_pc[27:0] = pf_pc[29:2]; |
end endgenerate |
|
always @(posedge i_clk) |
begin |
if ((i_halt)||(!master_ce)||(debug_trigger)||(o_break)) |
o_debug <= debug_flags; |
else if ((mem_valid)||((~clear_pipeline)&&(~alu_illegal) |
&&(((alu_wr)&&(alu_valid)) |
&&(((alu_wR)&&(alu_valid)) |
||(div_valid)||(fpu_valid)))) |
o_debug <= { debug_trigger, 1'b0, wr_reg_id[3:0], wr_gpreg_vl[25:0]}; |
else if (clear_pipeline) |
o_debug <= { debug_trigger, 3'b100, pf_pc[27:0] }; |
o_debug <= { debug_trigger, 3'b100, dbg_pc }; |
else if ((o_wb_gbl_stb)|(o_wb_lcl_stb)) |
o_debug <= {debug_trigger, 2'b11, o_wb_gbl_stb, o_wb_we, |
(o_wb_we)?o_wb_data[26:0] : o_wb_addr[26:0] }; |
/trunk/rtl/cpu/zipjiffies.v
45,7 → 45,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
57,6 → 57,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
63,6 → 68,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module zipjiffies(i_clk, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
/trunk/rtl/cpu/zipsystem.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: zipsystem.v |
// |
62,9 → 62,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
76,12 → 76,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`include "cpudefs.v" |
// |
// While I hate adding delays to any bus access, this next delay is required |
157,7 → 163,7
// |
module zipsystem(i_clk, i_rst, |
// Wishbone master interface from the CPU |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, i_wb_err, |
// Incoming interrupts |
i_ext_int, |
170,7 → 176,7
, o_cpu_debug |
`endif |
); |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32, |
parameter RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30, |
LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1, |
`ifdef OPT_MULTIPLY |
IMPLEMENT_MPY = `OPT_MULTIPLY, |
187,9 → 193,8
`else |
IMPLEMENT_FPU=0, |
`endif |
IMPLEMENT_LOCK=1, |
HIGHSPEED_CPU=0, |
// Derived parameters |
IMPLEMENT_LOCK=1; |
localparam // Derived parameters |
AW=ADDRESS_WIDTH; |
input i_clk, i_rst; |
// Wishbone master |
196,6 → 201,7
output wire o_wb_cyc, o_wb_stb, o_wb_we; |
output wire [(AW-1):0] o_wb_addr; |
output wire [31:0] o_wb_data; |
output wire [3:0] o_wb_sel; |
input i_wb_ack, i_wb_stall; |
input [31:0] i_wb_data; |
input i_wb_err; |
221,16 → 227,16
wire ctri_int, tma_int, tmb_int, tmc_int, jif_int, dmac_int; |
wire mtc_int, moc_int, mpc_int, mic_int, |
utc_int, uoc_int, upc_int, uic_int; |
|
assign main_int_vector[5:0] = { ctri_int, tma_int, tmb_int, tmc_int, |
jif_int, dmac_int }; |
|
generate |
if (EXTERNAL_INTERRUPTS < 9) |
assign main_int_vector = { {(9-EXTERNAL_INTERRUPTS){1'b0}}, |
i_ext_int, ctri_int, |
tma_int, tmb_int, tmc_int, |
jif_int, dmac_int }; |
assign main_int_vector[14:6] = { {(9-EXTERNAL_INTERRUPTS){1'b0}}, |
i_ext_int }; |
else |
assign main_int_vector = { i_ext_int[8:0], ctri_int, |
tma_int, tmb_int, tmc_int, |
jif_int, dmac_int }; |
assign main_int_vector[14:6] = i_ext_int[8:0]; |
endgenerate |
generate |
if (EXTERNAL_INTERRUPTS <= 9) |
252,8 → 258,8
i_ext_int[(EXTERNAL_INTERRUPTS-1):9] }; |
`endif |
endgenerate |
|
|
|
// Delay the debug port by one clock, to meet timing requirements |
wire dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall; |
wire [31:0] dbg_idata, dbg_odata; |
260,11 → 266,12
reg dbg_ack; |
`ifdef DELAY_DBG_BUS |
wire dbg_err, no_dbg_err; |
wire [3:0] dbg_sel; |
assign dbg_err = 1'b0; |
busdelay #(1,32) wbdelay(i_clk, |
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, |
i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, 4'hf, |
o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err, |
dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, |
dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, dbg_sel, |
dbg_ack, dbg_stall, dbg_odata, dbg_err); |
`else |
assign dbg_cyc = i_dbg_cyc; |
672,14 → 679,11
wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb, |
cpu_we, cpu_dbg_we; |
wire [31:0] cpu_data, wb_data; |
wire [3:0] cpu_sel; |
wire cpu_ack, cpu_stall, cpu_err; |
wire [31:0] cpu_dbg_data; |
assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5]) |
&&(dbg_we)&&(dbg_addr)); |
|
generate |
if (HIGHSPEED_CPU==0) |
begin |
zipcpu #( |
.RESET_ADDRESS(RESET_ADDRESS), |
.ADDRESS_WIDTH(ADDRESS_WIDTH), |
695,7 → 699,7
cpu_dbg_cc, cpu_break, |
cpu_gbl_cyc, cpu_gbl_stb, |
cpu_lcl_cyc, cpu_lcl_stb, |
cpu_we, cpu_addr, cpu_data, |
cpu_we, cpu_addr, cpu_data, cpu_sel, |
cpu_ack, cpu_stall, wb_data, |
cpu_err, |
cpu_op_stall, cpu_pf_stall, cpu_i_count |
703,31 → 707,6
, o_cpu_debug |
`endif |
); |
end else begin |
zipcpu #( |
.RESET_ADDRESS(RESET_ADDRESS), |
.ADDRESS_WIDTH(ADDRESS_WIDTH), |
.LGICACHE(LGICACHE), |
.IMPLEMENT_MPY(IMPLEMENT_MPY), |
.IMPLEMENT_DIVIDE(IMPLEMENT_DIVIDE), |
.IMPLEMENT_FPU(IMPLEMENT_FPU), |
.IMPLEMENT_LOCK(IMPLEMENT_LOCK) |
) |
thecpu(i_clk, cpu_reset, pic_interrupt, |
cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we, |
dbg_idata, cpu_dbg_stall, cpu_dbg_data, |
cpu_dbg_cc, cpu_break, |
cpu_gbl_cyc, cpu_gbl_stb, |
cpu_lcl_cyc, cpu_lcl_stb, |
cpu_we, cpu_addr, cpu_data, |
cpu_ack, cpu_stall, wb_data, |
cpu_err, |
cpu_op_stall, cpu_pf_stall, cpu_i_count |
`ifdef DEBUG_SCOPE |
, o_cpu_debug |
`endif |
); |
end endgenerate |
|
// Now, arbitrate the bus ... first for the local peripherals |
// For the debugger to have access to the local system bus, the |
774,12 → 753,13
cpu_ext_err; |
wire [(AW-1):0] ext_addr; |
wire [31:0] ext_odata; |
wire [3:0] ext_sel; |
wbpriarbiter #(32,AW) dmacvcpu(i_clk, |
cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data, |
cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data, cpu_sel, |
cpu_ext_ack, cpu_ext_stall, cpu_ext_err, |
dc_cyc, dc_stb, dc_we, dc_addr, dc_data, |
dc_cyc, dc_stb, dc_we, dc_addr, dc_data, 4'hf, |
dc_ack, dc_stall, dc_err, |
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, |
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel, |
ext_ack, ext_stall, ext_err); |
|
`ifdef DELAY_EXT_BUS |
786,18 → 766,19
busdelay #(AW,32) extbus(i_clk, |
ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, |
ext_ack, ext_stall, ext_idata, ext_err, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, |
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, |
i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int)); |
`else |
assign o_wb_cyc = ext_cyc; |
assign o_wb_stb = ext_stb; |
assign o_wb_we = ext_we; |
assign o_wb_addr = ext_addr; |
assign o_wb_data = ext_odata; |
assign ext_ack = i_wb_ack; |
assign ext_stall = i_wb_stall; |
assign ext_idata = i_wb_data; |
assign ext_err = (i_wb_err)||(wdbus_int); |
assign o_wb_cyc = ext_cyc; |
assign o_wb_stb = ext_stb; |
assign o_wb_we = ext_we; |
assign o_wb_addr = ext_addr; |
assign o_wb_data = ext_odata; |
assign o_wb_sel = ext_sel; |
assign ext_ack = i_wb_ack; |
assign ext_stall = i_wb_stall; |
assign ext_idata = i_wb_data; |
assign ext_err = (i_wb_err)||(wdbus_int); |
`endif |
|
wire tmr_ack; |
/trunk/rtl/cpu/ziptimer.v
1,4 → 1,4
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: ziptimer.v |
// |
43,9 → 43,9
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015,2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
57,12 → 57,18
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module ziptimer(i_clk, i_rst, i_ce, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
/trunk/rtl/enetpackets.v
146,7 → 146,7
`define TXCLK i_net_tx_clk |
`endif |
module enetpackets(i_wb_clk, i_reset, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel, |
o_wb_ack, o_wb_stall, o_wb_data, |
// |
o_net_reset_n, |
165,6 → 165,7
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [(MAW+1):0] i_wb_addr; // 1-bit for ctrl/data, 1 for tx/rx |
input [31:0] i_wb_data; |
input [3:0] i_wb_sel; |
// |
output reg o_wb_ack; |
output wire o_wb_stall; |
187,11 → 188,13
reg wr_ctrl; |
reg [2:0] wr_addr; |
reg [31:0] wr_data; |
reg [3:0] wr_sel; |
always @(posedge i_wb_clk) |
begin |
wr_ctrl<=((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b00)); |
wr_addr <= i_wb_addr[2:0]; |
wr_data <= i_wb_data; |
wr_sel <= i_wb_sel; |
end |
|
reg [31:0] txmem [0:((1<<MAW)-1)]; |
243,8 → 246,18
begin |
// if (i_wb_addr[(MAW+1):MAW] == 2'b10) |
// Writes to rx memory not allowed here |
if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11)) |
txmem[i_wb_addr[(MAW-1):0]] <= i_wb_data; |
if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11) |
&&(i_wb_sel[3])) |
txmem[i_wb_addr[(MAW-1):0]][31:24] <= i_wb_data[31:24]; |
if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11) |
&&(i_wb_sel[2])) |
txmem[i_wb_addr[(MAW-1):0]][23:16] <= i_wb_data[23:16]; |
if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11) |
&&(i_wb_sel[1])) |
txmem[i_wb_addr[(MAW-1):0]][15:8] <= i_wb_data[15:8]; |
if ((i_wb_stb)&&(i_wb_we)&&(i_wb_addr[(MAW+1):MAW] == 2'b11) |
&&(i_wb_sel[0])) |
txmem[i_wb_addr[(MAW-1):0]][7:0] <= i_wb_data[7:0]; |
|
// Set the err bits on these conditions (filled out below) |
if (rx_err_stb) |
/trunk/rtl/fastio.v
47,10 → 47,7
i_sw, i_btn, o_led, |
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, |
// Board level PMod I/O |
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx, |
`ifdef USE_GPIO |
i_gpio, o_gpio, |
`endif |
// Wishbone control |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, |
i_wb_data, o_wb_ack, o_wb_stall, o_wb_data, |
65,25 → 62,15
input [3:0] i_sw; |
input [3:0] i_btn; |
output wire [3:0] o_led; |
output reg [2:0] o_clr_led0; |
output reg [2:0] o_clr_led1; |
output reg [2:0] o_clr_led2; |
output reg [2:0] o_clr_led3; |
output wire [2:0] o_clr_led0; |
output wire [2:0] o_clr_led1; |
output wire [2:0] o_clr_led2; |
output wire [2:0] o_clr_led3; |
// Board level PMod I/O |
// |
// Auxilliary UART I/O |
input i_aux_rx; |
output wire o_aux_tx, o_aux_cts; |
// |
// GPS UART I/O |
input i_gps_rx; |
output wire o_gps_tx; |
// |
`ifdef USE_GPIO |
// GPIO |
input [(NGPI-1):0] i_gpio; |
output reg [(NGPO-1):0] o_gpio; |
`endif |
output wire [(NGPO-1):0] o_gpio; |
// |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
103,9 → 90,9
// Interrupts -- both the output bus interrupt, as well as those |
// internally generated interrupts which may be used elsewhere |
// in the design |
input wire [8:0] i_other_ints; |
input wire [11:0] i_other_ints; |
output wire o_bus_int; |
output wire [6:0] o_board_ints; // Button and switch interrupts |
output wire [2:0] o_board_ints; // Button and switch interrupts |
|
wire [31:0] w_wb_data; |
wire [4:0] w_wb_addr; |
137,9 → 124,12
wire [31:0] pic_data; |
reg sw_int, btn_int; |
wire pps_int, rtc_int, netrx_int, nettx_int, |
auxrx_int, auxtx_int, gpio_int, flash_int, scop_int, |
gpsrx_int, gpstx_int, sd_int, oled_int, zip_int; |
assign { zip_int, oled_int, rtc_int, sd_int, |
gpsrx_int, auxrx_int, auxtx_int, |
gpio_int, flash_int, scop_int, |
sdcard_int, oled_int, zip_int; |
assign { zip_int, |
gpsrx_int, auxtx_int, auxrx_int, |
oled_int, rtc_int, sdcard_int, |
nettx_int, netrx_int, scop_int, flash_int, |
pps_int } = i_other_ints; |
|
149,7 → 139,7
icontrol #(15) buspic(i_clk, 1'b0, |
(w_wb_stb)&&(w_wb_addr==5'h1), |
i_wb_data, pic_data, |
{ zip_int, oled_int, sd_int, |
{ zip_int, oled_int, sdcard_int, |
gpsrx_int, scop_int, flash_int, gpio_int, |
auxtx_int, auxrx_int, nettx_int, netrx_int, |
rtc_int, pps_int, sw_int, btn_int }, |
240,126 → 230,11
// selectable.) |
// |
wire [31:0] gpio_data; |
`ifdef USE_GPIO |
wbgpio #(NIN, NOUT) |
gpioi(i_clk, w_wb_cyc, (w_wb_stb)&&(w_wb_addr == 5'hd), 1'b1, |
wbgpio #(NGPI, NGPO) |
gpioi(i_clk, 1'b1, (w_wb_stb)&&(w_wb_addr == 5'h6), 1'b1, |
w_wb_data, gpio_data, i_gpio, o_gpio, gpio_int); |
`else |
assign gpio_data = 32'h00; |
assign gpio_int = 1'b0; |
`endif |
|
// |
// AUX (UART) SETUP |
// |
// Set us up for 4Mbaud, 8 data bits, no stop bits. |
reg [29:0] aux_setup; |
initial aux_setup = AUXUART_SETUP; |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'h6)) |
aux_setup[29:0] <= w_wb_data[29:0]; |
|
// |
// GPSSETUP |
// |
// Set us up for 9600 kbaud, 8 data bits, no stop bits. |
reg [29:0] gps_setup; |
initial gps_setup = GPSUART_SETUP; |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'h7)) |
gps_setup[29:0] <= w_wb_data[29:0]; |
|
// |
// CLR LEDs |
// |
|
// CLR LED 0 |
wire [31:0] w_clr_led0; |
reg [8:0] r_clr_led0_r, r_clr_led0_g, r_clr_led0_b; |
initial r_clr_led0_r = 9'h003; // Color LED on the far right |
initial r_clr_led0_g = 9'h000; |
initial r_clr_led0_b = 9'h000; |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'h8)) |
begin |
r_clr_led0_r <= { w_wb_data[26], w_wb_data[23:16] }; |
r_clr_led0_g <= { w_wb_data[25], w_wb_data[15: 8] }; |
r_clr_led0_b <= { w_wb_data[24], w_wb_data[ 7: 0] }; |
end |
assign w_clr_led0 = { 5'h0, |
r_clr_led0_r[8], r_clr_led0_g[8], r_clr_led0_b[8], |
r_clr_led0_r[7:0], r_clr_led0_g[7:0], r_clr_led0_b[7:0] |
}; |
always @(posedge i_clk) |
o_clr_led0 <= { (rev_pwr_counter[8:0] < r_clr_led0_r), |
(rev_pwr_counter[8:0] < r_clr_led0_g), |
(rev_pwr_counter[8:0] < r_clr_led0_b) }; |
|
// CLR LED 1 |
wire [31:0] w_clr_led1; |
reg [8:0] r_clr_led1_r, r_clr_led1_g, r_clr_led1_b; |
initial r_clr_led1_r = 9'h007; |
initial r_clr_led1_g = 9'h000; |
initial r_clr_led1_b = 9'h000; |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'h9)) |
begin |
r_clr_led1_r <= { w_wb_data[26], w_wb_data[23:16] }; |
r_clr_led1_g <= { w_wb_data[25], w_wb_data[15: 8] }; |
r_clr_led1_b <= { w_wb_data[24], w_wb_data[ 7: 0] }; |
end |
assign w_clr_led1 = { 5'h0, |
r_clr_led1_r[8], r_clr_led1_g[8], r_clr_led1_b[8], |
r_clr_led1_r[7:0], r_clr_led1_g[7:0], r_clr_led1_b[7:0] |
}; |
always @(posedge i_clk) |
o_clr_led1 <= { (rev_pwr_counter[8:0] < r_clr_led1_r), |
(rev_pwr_counter[8:0] < r_clr_led1_g), |
(rev_pwr_counter[8:0] < r_clr_led1_b) }; |
// CLR LED 0 |
wire [31:0] w_clr_led2; |
reg [8:0] r_clr_led2_r, r_clr_led2_g, r_clr_led2_b; |
initial r_clr_led2_r = 9'h00f; |
initial r_clr_led2_g = 9'h000; |
initial r_clr_led2_b = 9'h000; |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'ha)) |
begin |
r_clr_led2_r <= { w_wb_data[26], w_wb_data[23:16] }; |
r_clr_led2_g <= { w_wb_data[25], w_wb_data[15: 8] }; |
r_clr_led2_b <= { w_wb_data[24], w_wb_data[ 7: 0] }; |
end |
assign w_clr_led2 = { 5'h0, |
r_clr_led2_r[8], r_clr_led2_g[8], r_clr_led2_b[8], |
r_clr_led2_r[7:0], r_clr_led2_g[7:0], r_clr_led2_b[7:0] |
}; |
always @(posedge i_clk) |
o_clr_led2 <= { (rev_pwr_counter[8:0] < r_clr_led2_r), |
(rev_pwr_counter[8:0] < r_clr_led2_g), |
(rev_pwr_counter[8:0] < r_clr_led2_b) }; |
// CLR LED 3 |
wire [31:0] w_clr_led3; |
reg [8:0] r_clr_led3_r, r_clr_led3_g, r_clr_led3_b; |
initial r_clr_led3_r = 9'h01f; // LED is on far left |
initial r_clr_led3_g = 9'h000; |
initial r_clr_led3_b = 9'h000; |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'hb)) |
begin |
r_clr_led3_r <= { w_wb_data[26], w_wb_data[23:16] }; |
r_clr_led3_g <= { w_wb_data[25], w_wb_data[15: 8] }; |
r_clr_led3_b <= { w_wb_data[24], w_wb_data[ 7: 0] }; |
end |
assign w_clr_led3 = { 5'h0, |
r_clr_led3_r[8], r_clr_led3_g[8], r_clr_led3_b[8], |
r_clr_led3_r[7:0], r_clr_led3_g[7:0], r_clr_led3_b[7:0] |
}; |
always @(posedge i_clk) |
o_clr_led3 <= { (rev_pwr_counter[8:0] < r_clr_led3_r), |
(rev_pwr_counter[8:0] < r_clr_led3_g), |
(rev_pwr_counter[8:0] < r_clr_led3_b) }; |
|
// |
// The Calendar DATE |
// |
wire [31:0] date_data; |
367,128 → 242,29
`ifdef GET_DATE |
wire date_ack, date_stall; |
rtcdate thedate(i_clk, i_rtc_ppd, |
i_wb_cyc, w_wb_stb, (w_wb_addr==5'hc), w_wb_data, |
i_wb_cyc, w_wb_stb, (w_wb_addr==5'h7), w_wb_data, |
date_ack, date_stall, date_data); |
`else |
assign date_data = 32'h20160000; |
assign date_data = 32'h20170000; |
`endif |
|
////// |
// |
// The auxilliary UART |
// CLR LEDs |
// |
////// |
wire [31:0] w_clr_led0, w_clr_led1, w_clr_led2, w_clr_led3; |
clrled clrled0(i_clk, (w_wb_stb)&&(w_wb_addr==5'h8), w_wb_data, |
pwr_counter[8:0], w_clr_led0, o_clr_led0); |
clrled clrled1(i_clk, (w_wb_stb)&&(w_wb_addr==5'h9), w_wb_data, |
pwr_counter[8:0], w_clr_led1, o_clr_led1); |
clrled clrled2(i_clk, (w_wb_stb)&&(w_wb_addr==5'ha), w_wb_data, |
pwr_counter[8:0], w_clr_led2, o_clr_led2); |
clrled clrled3(i_clk, (w_wb_stb)&&(w_wb_addr==5'hb), w_wb_data, |
pwr_counter[8:0], w_clr_led3, o_clr_led3); |
|
// |
// First the Auxilliary UART receiver |
// |
wire auxrx_stb, auxrx_break, auxrx_perr, auxrx_ferr, auxck_uart; |
wire [7:0] rx_data_aux_port; |
rxuart auxrx(i_clk, 1'b0, aux_setup, i_aux_rx, |
auxrx_stb, rx_data_aux_port, auxrx_break, |
auxrx_perr, auxrx_ferr, auxck_uart); |
|
wire [31:0] auxrx_data; |
reg [11:0] r_auxrx_data; |
always @(posedge i_clk) |
if (auxrx_stb) |
begin |
r_auxrx_data[11] <= auxrx_break; |
r_auxrx_data[10] <= auxrx_ferr; |
r_auxrx_data[ 9] <= auxrx_perr; |
r_auxrx_data[7:0]<= rx_data_aux_port; |
end |
always @(posedge i_clk) |
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h0e))||(auxrx_stb)) |
r_auxrx_data[8] <= !auxrx_stb; |
assign o_aux_cts = auxrx_stb; |
assign auxrx_data = { 20'h00, r_auxrx_data }; |
assign auxrx_int = !r_auxrx_data[8]; |
|
// |
// Then the auxilliary UART transmitter |
// |
wire auxtx_busy; |
reg [7:0] r_auxtx_data; |
reg r_auxtx_stb, r_auxtx_break; |
wire [31:0] auxtx_data; |
txuart auxtx(i_clk, 1'b0, aux_setup, |
r_auxtx_break, r_auxtx_stb, r_auxtx_data, |
o_aux_tx, auxtx_busy); |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'h0f)) |
begin |
r_auxtx_stb <= (!r_auxtx_break)&&(!w_wb_data[9]); |
r_auxtx_data <= w_wb_data[7:0]; |
r_auxtx_break<= w_wb_data[9]; |
end else if (~auxtx_busy) |
begin |
r_auxtx_stb <= 1'b0; |
r_auxtx_data <= 8'h0; |
end |
assign auxtx_data = { 20'h00, |
1'b0, o_aux_tx, r_auxtx_break, auxtx_busy, |
r_auxtx_data }; |
assign auxtx_int = ~auxtx_busy; |
|
////// |
// |
// The GPS UART |
// |
////// |
|
// First the receiver |
wire gpsrx_stb, gpsrx_break, gpsrx_perr, gpsrx_ferr, gpsck_uart; |
wire [7:0] rx_data_gps_port; |
rxuart gpsrx(i_clk, 1'b0, gps_setup, i_gps_rx, |
gpsrx_stb, rx_data_gps_port, gpsrx_break, |
gpsrx_perr, gpsrx_ferr, gpsck_uart); |
|
wire [31:0] gpsrx_data; |
reg [11:0] r_gpsrx_data; |
always @(posedge i_clk) |
if (gpsrx_stb) |
begin |
r_gpsrx_data[11] <= gpsrx_break; |
r_gpsrx_data[10] <= gpsrx_ferr; |
r_gpsrx_data[ 9] <= gpsrx_perr; |
r_gpsrx_data[7:0]<= rx_data_gps_port; |
end |
always @(posedge i_clk) |
if(((i_wb_stb)&&(~i_wb_we)&&(i_wb_addr == 5'h10))||(gpsrx_stb)) |
r_gpsrx_data[8] <= !gpsrx_stb; |
assign gpsrx_data = { 20'h00, r_gpsrx_data }; |
assign gpsrx_int = !r_gpsrx_data[8]; |
|
|
// Then the transmitter |
reg r_gpstx_break, r_gpstx_stb; |
reg [7:0] r_gpstx_data; |
wire gpstx_busy; |
wire [31:0] gpstx_data; |
txuart gpstx(i_clk, 1'b0, gps_setup, |
r_gpstx_break, r_gpstx_stb, r_gpstx_data, |
o_gps_tx, gpstx_busy); |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'h11)) |
begin |
r_gpstx_stb <= 1'b1; |
r_gpstx_data <= w_wb_data[7:0]; |
r_gpstx_break<= w_wb_data[9]; |
end else if (~gpstx_busy) |
begin |
r_gpstx_stb <= 1'b0; |
r_gpstx_data <= 8'h0; |
end |
assign gpstx_data = { 20'h00, |
gpsck_uart, o_gps_tx, r_gpstx_break, gpstx_busy, |
r_gpstx_data }; |
assign gpstx_int = !gpstx_busy; |
|
reg [32:0] sec_step; |
initial sec_step = 33'h1; |
always @(posedge i_clk) |
if ((w_wb_stb)&&(w_wb_addr == 5'h12)) |
if ((w_wb_stb)&&(w_wb_addr == 5'h0c)) |
sec_step <= { 1'b1, w_wb_data }; |
else if (!pps_int) |
sec_step <= 33'h1; |
509,21 → 285,15
5'h03: o_wb_data <= pwr_counter; |
5'h04: o_wb_data <= w_btnsw; |
5'h05: o_wb_data <= w_ledreg; |
5'h06: o_wb_data <= { 2'b00, aux_setup }; |
5'h07: o_wb_data <= { 2'b00, gps_setup }; |
5'h06: o_wb_data <= date_data; |
5'h07: o_wb_data <= gpio_data; |
5'h08: o_wb_data <= w_clr_led0; |
5'h09: o_wb_data <= w_clr_led1; |
5'h0a: o_wb_data <= w_clr_led2; |
5'h0b: o_wb_data <= w_clr_led3; |
5'h0c: o_wb_data <= date_data; |
5'h0d: o_wb_data <= gpio_data; |
5'h0e: o_wb_data <= auxrx_data; |
5'h0f: o_wb_data <= auxtx_data; |
5'h10: o_wb_data <= gpsrx_data; |
5'h11: o_wb_data <= gpstx_data; |
5'h12: o_wb_data <= time_now_secs; |
5'h13: o_wb_data <= i_gps_sub; |
5'h14: o_wb_data <= i_gps_step; |
5'h0c: o_wb_data <= time_now_secs; |
5'h0d: o_wb_data <= i_gps_sub; |
5'h0e: o_wb_data <= i_gps_step; |
default: o_wb_data <= 32'h00; |
endcase |
|
530,8 → 300,7
assign o_wb_stall = 1'b0; |
always @(posedge i_clk) |
o_wb_ack <= (i_wb_stb); |
assign o_board_ints = { gpio_int, auxrx_int, auxtx_int, |
gpsrx_int, gpstx_int, sw_int, btn_int }; |
assign o_board_ints = { gpio_int, sw_int, btn_int }; |
|
|
endmodule |
/trunk/rtl/gpsclock.v
106,7 → 106,7
i_wb_cyc_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_tracking, o_count, o_step, o_err, o_locked, o_dbg); |
parameter DEFAULT_STEP = 32'h834d_c736;//2^64/81.25 MHz |
parameter [31:0] DEFAULT_STEP = 32'h834d_c736;//2^64/81.25 MHz |
parameter RW=64, // Needs to be 2ceil(Log_2(i_clk frequency)) |
DW=32, // The width of our data bus |
ONE_SECOND = 0, |
438,8 → 438,8
|
wire [31:0] initial_default_step = DEFAULT_STEP; |
// initial o_step = 64'h002af31dc461; // 100MHz |
initial o_step = { 16'h00, (({ initial_default_step[27:0], 20'h00 }) |
>> initial_default_step[31:28])}; |
initial o_step = { 16'h00, (({ DEFAULT_STEP[27:0], 20'h00 }) |
>> DEFAULT_STEP[31:28])}; |
always @(posedge i_clk) |
if ((i_rst)||(dly_config)) |
o_step <= pre_step; |
/trunk/rtl/memdev.v
18,7 → 18,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
30,6 → 30,11
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
37,12 → 42,14
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
module memdev(i_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel, |
o_wb_ack, o_wb_stall, o_wb_data); |
parameter AW=15, DW=32, EXTRACLOCK= 0; |
parameter LGMEMSZ=15, DW=32, EXTRACLOCK= 0; |
localparam AW = LGMEMSZ - 2; |
input i_clk, i_wb_cyc, i_wb_stb, i_wb_we; |
input [(AW-1):0] i_wb_addr; |
input [(DW-1):0] i_wb_data; |
input [(DW/8-1):0] i_wb_sel; |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [(DW-1):0] o_wb_data; |
50,6 → 57,7
wire w_wstb, w_stb; |
wire [(DW-1):0] w_data; |
wire [(AW-1):0] w_addr; |
wire [(DW/8-1):0] w_sel; |
|
generate |
if (EXTRACLOCK == 0) |
59,6 → 67,7
assign w_stb = i_wb_stb; |
assign w_addr = i_wb_addr; |
assign w_data = i_wb_data; |
assign w_sel = i_wb_sel; |
|
end else begin |
|
68,25 → 77,39
always @(posedge i_clk) |
last_stb <= (i_wb_stb); |
|
reg [(AW-1):0] last_addr; |
reg [(DW-1):0] last_data; |
reg [(AW-1):0] last_addr; |
reg [(DW/8-1):0] last_sel; |
always @(posedge i_clk) |
last_data <= i_wb_data; |
always @(posedge i_clk) |
last_addr <= i_wb_addr; |
always @(posedge i_clk) |
last_sel <= i_wb_sel; |
|
assign w_wstb = last_wstb; |
assign w_stb = last_stb; |
assign w_addr = last_addr; |
assign w_data = last_data; |
assign w_sel = last_sel; |
end endgenerate |
|
reg [(DW-1):0] mem [0:((1<<AW)-1)]; |
|
always @(posedge i_clk) |
o_wb_data <= mem[w_addr]; |
always @(posedge i_clk) |
if (w_wstb) |
mem[w_addr] <= w_data; |
begin |
if ((w_wstb)&&(w_sel[3])) |
mem[w_addr][31:24] <= w_data[31:24]; |
if ((w_wstb)&&(w_sel[2])) |
mem[w_addr][23:16] <= w_data[23:16]; |
if ((w_wstb)&&(w_sel[1])) |
mem[w_addr][15: 8] <= w_data[15:8]; |
if ((w_wstb)&&(w_sel[0])) |
mem[w_addr][ 7: 0] <= w_data[7:0]; |
end |
|
always @(posedge i_clk) |
o_wb_ack <= (w_stb); |
assign o_wb_stall = 1'b0; |
/trunk/rtl/rxemin.v
38,7 → 38,7
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module rxemin(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_v, o_d, o_err); |
module rxemin(i_clk, i_ce, i_en, i_cancel, i_v, i_d, o_err); |
parameter MINNIBBLES=120; |
localparam LGNCOUNT=(MINNIBBLES<63)? 6 |
:((MINNIBBLES<127)? 7:((MINNIBBLES<255)? 8:9)); |
49,7 → 49,6
|
reg last_v; |
reg [(LGNCOUNT-1):0] r_ncnt; |
initial o_v = 1'b0; |
initial last_v = 1'b0; |
always @(posedge i_clk) |
if (i_ce) |
56,8 → 55,11
begin |
last_v <= i_v; |
|
if (((!i_v)&&(!o_v))||(i_cancel)) |
if ((!i_v)||(i_cancel)) |
begin |
// Here's our reset. If th input isn't valid (i.e., no |
// packet present), or if we are cancelling the packet, |
// then we come in here and reset our interface. |
r_ncnt <= 0; |
o_err <= 0; |
end else if (i_v) |
/trunk/rtl/rxuart.v
2,7 → 2,7
// |
// Filename: rxuart.v |
// |
// Project: FPGA library |
// Project: wbuart32, a full featured UART with simulator |
// |
// Purpose: Receive and decode inputs from a single UART line. |
// |
19,9 → 19,13
// Now for the setup register. The register is 32 bits, so that this |
// UART may be set up over a 32-bit bus. |
// |
// i_setup[30] True if we are not using hardware flow control. This bit |
// is ignored within this module, as any receive hardware flow |
// control will need to be implemented elsewhere. |
// |
// i_setup[29:28] Indicates the number of data bits per word. This will |
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 |
// for a six bit word, or 2'b11 for a five bit word. |
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 |
// for a six bit word, or 2'b11 for a five bit word. |
// |
// i_setup[27] Indicates whether or not to use one or two stop bits. |
// Set this to one to expect two stop bits, zero for one. |
74,7 → 78,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
90,7 → 94,7
// ..7 Bits arrive |
// 8 Stop bit (x1) |
// 9 Stop bit (x2) |
/// c break condition |
// c break condition |
// d Waiting for the channel to go high |
// e Waiting for the reset to complete |
// f Idle state |
111,15 → 115,13
`define RXU_RESET_IDLE 4'he |
`define RXU_IDLE 4'hf |
|
module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break, |
module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break, |
o_parity_err, o_frame_err, o_ck_uart); |
// parameter // CLOCKS_PER_BAUD = 25'd004340, |
// BREAK_CONDITION = CLOCKS_PER_BAUD * 12, |
// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2; |
parameter [30:0] INITIAL_SETUP = 31'd868; |
// 8 data bits, no parity, (at least 1) stop bit |
input i_clk, i_reset; |
input [29:0] i_setup; |
input i_uart; |
input [30:0] i_setup; |
input i_uart_rx; |
output reg o_wr; |
output reg [7:0] o_data; |
output reg o_break; |
131,7 → 133,10
wire [1:0] data_bits; |
wire use_parity, parity_even, dblstop, fixd_parity; |
reg [29:0] r_setup; |
reg [3:0] state; |
|
assign clocks_per_baud = { 4'h0, r_setup[23:0] }; |
// assign hw_flow_control = !r_setup[30]; |
assign data_bits = r_setup[29:28]; |
assign dblstop = r_setup[27]; |
assign use_parity = r_setup[26]; |
138,8 → 143,15
assign fixd_parity = r_setup[25]; |
assign parity_even = r_setup[24]; |
assign break_condition = { r_setup[23:0], 4'h0 }; |
assign half_baud = { 5'h00, r_setup[23:1] }; |
assign half_baud = { 5'h00, r_setup[23:1] }-28'h1; |
reg [27:0] baud_counter; |
reg zero_baud_counter; |
|
|
// Since this is an asynchronous receiver, we need to register our |
// input a couple of clocks over to avoid any problems with |
// metastability. We do that here, and then ignore all but the |
// ck_uart wire. |
reg q_uart, qq_uart, ck_uart; |
initial q_uart = 1'b0; |
initial qq_uart = 1'b0; |
146,12 → 158,19
initial ck_uart = 1'b0; |
always @(posedge i_clk) |
begin |
q_uart <= i_uart; |
q_uart <= i_uart_rx; |
qq_uart <= q_uart; |
ck_uart <= qq_uart; |
end |
|
// In case anyone else wants this clocked, stabilized value, we |
// offer it on our output. |
assign o_ck_uart = ck_uart; |
|
// Keep track of the number of clocks since the last change. |
// |
// This is used to determine if we are in either a break or an idle |
// condition, as discussed further below. |
reg [27:0] chg_counter; |
initial chg_counter = 28'h00; |
always @(posedge i_clk) |
162,76 → 181,99
else if (chg_counter < break_condition) |
chg_counter <= chg_counter + 1; |
|
reg line_synch; |
initial line_synch = 1'b0; |
// Are we in a break condition? |
// |
// A break condition exists if the line is held low for longer than |
// a data word. Hence, we keep track of when the last change occurred. |
// If it was more than break_condition clocks ago, and the current input |
// value is a 0, then we're in a break--and nothing can be read until |
// the line idles again. |
initial o_break = 1'b0; |
always @(posedge i_clk) |
o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0; |
|
// Are we between characters? |
// |
// The opposite of a break condition is where the line is held high |
// for more clocks than would be in a character. When this happens, |
// we know we have synchronization--otherwise, we might be sampling |
// from within a data word. |
// |
// This logic is used later to hold the RXUART in a reset condition |
// until we know we are between data words. At that point, we should |
// be able to hold on to our synchronization. |
reg line_synch; |
initial line_synch = 1'b0; |
always @(posedge i_clk) |
line_synch <= ((chg_counter >= break_condition)&&(ck_uart)); |
|
reg [3:0] state; |
reg [27:0] baud_counter; |
reg [7:0] data_reg; |
reg calc_parity, zero_baud_counter, half_baud_time; |
initial o_wr = 1'b0; |
// Are we in the middle of a baud iterval? Specifically, are we |
// in the middle of a start bit? Set this to high if so. We'll use |
// this within our state machine to transition out of the IDLE |
// state. |
reg half_baud_time; |
initial half_baud_time = 0; |
always @(posedge i_clk) |
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud); |
|
|
// Allow our controlling processor to change our setup at any time |
// outside of receiving/processing a character. |
initial r_setup = INITIAL_SETUP[29:0]; |
always @(posedge i_clk) |
if (state >= `RXU_RESET_IDLE) |
r_setup <= i_setup[29:0]; |
|
|
// Our monster state machine. YIKES! |
// |
// Yeah, this may be more complicated than it needs to be. The basic |
// progression is: |
// RESET -> RESET_IDLE -> (when line is idle) -> IDLE |
// IDLE -> bit 0 -> bit 1 -> bit_{ndatabits} -> |
// (optional) PARITY -> STOP -> (optional) SECOND_STOP |
// -> IDLE |
// ANY -> (on break) BREAK -> IDLE |
// |
// There are 16 states, although all are not used. These are listed |
// at the top of this file. |
// |
// Logic inputs (12): (I've tried to minimize this number) |
// state (4) |
// i_reset |
// line_synch |
// o_break |
// ckuart |
// half_baud_time |
// zero_baud_counter |
// use_parity |
// dblstop |
// Logic outputs (4): |
// state |
// |
initial state = `RXU_RESET_IDLE; |
initial o_parity_err = 1'b0; |
initial o_frame_err = 1'b0; |
// initial baud_counter = clocks_per_baud; |
always @(posedge i_clk) |
begin |
if (i_reset) |
begin |
o_wr <= 1'b0; |
o_data <= 8'h00; |
state <= `RXU_RESET_IDLE; |
baud_counter <= clocks_per_baud-28'h01;// Set, not reset |
data_reg <= 8'h00; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if (state == `RXU_RESET_IDLE) |
else if (state == `RXU_RESET_IDLE) |
begin |
r_setup <= i_setup; |
data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0; |
baud_counter <= clocks_per_baud-28'h01;// Set, not reset |
if (line_synch) |
// Goto idle state from a reset |
state <= `RXU_IDLE; |
else // Otherwise, stay in this condition 'til reset |
state <= `RXU_RESET_IDLE; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if (o_break) |
begin // We are in a break condition |
state <= `RXU_BREAK; |
o_wr <= 1'b0; |
o_data <= 8'h00; |
baud_counter <= clocks_per_baud-28'h01;// Set, not reset |
data_reg <= 8'h00; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
r_setup <= i_setup; |
end else if (state == `RXU_BREAK) |
begin // Goto idle state following return ck_uart going high |
data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0; |
baud_counter <= clocks_per_baud - 28'h01; |
if (ck_uart) |
state <= `RXU_IDLE; |
else |
state <= `RXU_BREAK; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
r_setup <= i_setup; |
end else if (state == `RXU_IDLE) |
begin // Idle state, independent of baud counter |
r_setup <= i_setup; |
data_reg <= 8'h00; o_data <= 8'h00; o_wr <= 1'b0; |
baud_counter <= clocks_per_baud - 28'h01; |
if ((~ck_uart)&&(half_baud_time)) |
begin |
// We are in the center of a valid start bit |
243,88 → 285,179
endcase |
end else // Otherwise, just stay here in idle |
state <= `RXU_IDLE; |
calc_parity <= 1'b0; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if (zero_baud_counter) |
begin |
baud_counter <= clocks_per_baud-28'h1; |
if (state < `RXU_BIT_SEVEN) |
begin |
// Data arrives least significant bit first. |
// By the time this is clocked in, it's what |
// you'll have. |
data_reg <= { ck_uart, data_reg[7:1] }; |
calc_parity <= calc_parity ^ ck_uart; |
o_data <= 8'h00; |
o_wr <= 1'b0; |
state <= state + 1; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if (state == `RXU_BIT_SEVEN) |
begin |
data_reg <= { ck_uart, data_reg[7:1] }; |
calc_parity <= calc_parity ^ ck_uart; |
o_data <= 8'h00; |
o_wr <= 1'b0; |
else if (state == `RXU_BIT_SEVEN) |
state <= (use_parity) ? `RXU_PARITY:`RXU_STOP; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end else if (state == `RXU_PARITY) |
begin |
if (fixd_parity) |
o_parity_err <= (ck_uart ^ parity_even); |
else |
o_parity_err <= ((parity_even && (calc_parity != ck_uart)) |
||((~parity_even)&&(calc_parity==ck_uart))); |
else if (state == `RXU_PARITY) |
state <= `RXU_STOP; |
o_frame_err <= 1'b0; |
end else if (state == `RXU_STOP) |
else if (state == `RXU_STOP) |
begin // Stop (or parity) bit(s) |
case (data_bits) |
2'b00: o_data <= data_reg; |
2'b01: o_data <= { 1'b0, data_reg[7:1] }; |
2'b10: o_data <= { 2'b0, data_reg[7:2] }; |
2'b11: o_data <= { 3'b0, data_reg[7:3] }; |
endcase |
o_wr <= 1'b1; // Pulse the write |
o_frame_err <= (~ck_uart); |
if (~ck_uart) |
if (~ck_uart) // On frame error, wait 4 ch idle |
state <= `RXU_RESET_IDLE; |
else if (dblstop) |
state <= `RXU_SECOND_STOP; |
else |
state <= `RXU_IDLE; |
// o_parity_err <= 1'b0; |
end else // state must equal RX_SECOND_STOP |
begin |
if (~ck_uart) |
begin |
o_frame_err <= 1'b1; |
if (~ck_uart) // On frame error, wait 4 ch idle |
state <= `RXU_RESET_IDLE; |
end else begin |
else |
state <= `RXU_IDLE; |
o_frame_err <= 1'b0; |
end |
o_parity_err <= 1'b0; |
end |
end else begin |
o_wr <= 1'b0; // data_reg = data_reg |
baud_counter <= baud_counter - 28'd1; |
o_parity_err <= 1'b0; |
o_frame_err <= 1'b0; |
end |
end |
|
// Data bit capture logic. |
// |
// This is drastically simplified from the state machine above, based |
// upon: 1) it doesn't matter what it is until the end of a captured |
// byte, and 2) the data register will flush itself of any invalid |
// data in all other cases. Hence, let's keep it real simple. |
// The only trick, though, is that if we have parity, then the data |
// register needs to be held through that state without getting |
// updated. |
reg [7:0] data_reg; |
always @(posedge i_clk) |
if ((zero_baud_counter)&&(state != `RXU_PARITY)) |
data_reg <= { ck_uart, data_reg[7:1] }; |
|
// Parity calculation logic |
// |
// As with the data capture logic, all that must be known about this |
// bit is that it is the exclusive-OR of all bits prior. The first |
// of those will follow idle, so we set ourselves to zero on idle. |
// Then, as we walk through the states of a bit, all will adjust this |
// value up until the parity bit, where the value will be read. Setting |
// it then or after will be irrelevant, so ... this should be good |
// and simplified. Note--we don't need to adjust this on reset either, |
// since the reset state will lead to the idle state where we'll be |
// reset before any transmission takes place. |
reg calc_parity; |
always @(posedge i_clk) |
if (state == `RXU_IDLE) |
calc_parity <= 0; |
else if (zero_baud_counter) |
calc_parity <= calc_parity ^ ck_uart; |
|
// Parity error logic |
// |
// Set during the parity bit interval, read during the last stop bit |
// interval, cleared on BREAK, RESET_IDLE, or IDLE states. |
initial o_parity_err = 1'b0; |
always @(posedge i_clk) |
if ((zero_baud_counter)&&(state == `RXU_PARITY)) |
begin |
if (fixd_parity) |
// Fixed parity bit--independent of any dat |
// value. |
o_parity_err <= (ck_uart ^ parity_even); |
else if (parity_even) |
// Parity even: The XOR of all bits including |
// the parity bit must be zero. |
o_parity_err <= (calc_parity != ck_uart); |
else |
// Parity odd: the parity bit must equal the |
// XOR of all the data bits. |
o_parity_err <= (calc_parity == ck_uart); |
end else if (state >= `RXU_BREAK) |
o_parity_err <= 1'b0; |
|
// Frame error determination |
// |
// For the purpose of this controller, a frame error is defined as a |
// stop bit (or second stop bit, if so enabled) not being high midway |
// through the stop baud interval. The frame error value is |
// immediately read, so we can clear it under all other circumstances. |
// Specifically, we want it clear in RXU_BREAK, RXU_RESET_IDLE, and |
// most importantly in RXU_IDLE. |
initial o_frame_err = 1'b0; |
always @(posedge i_clk) |
if ((zero_baud_counter)&&((state == `RXU_STOP) |
||(state == `RXU_SECOND_STOP))) |
o_frame_err <= (o_frame_err)||(~ck_uart); |
else if ((zero_baud_counter)||(state >= `RXU_BREAK)) |
o_frame_err <= 1'b0; |
|
// Our data bit logic doesn't need nearly the complexity of all that |
// work above. Indeed, we only need to know if we are at the end of |
// a stop bit, in which case we copy the data_reg into our output |
// data register, o_data. |
// |
// We would also set o_wr to be true when this is the case, but ... we |
// won't know if there is a frame error on the second stop bit for |
// another baud interval yet. So, instead, we set up the logic so that |
// we know on the next zero baud counter that we can write out. That's |
// the purpose of pre_wr. |
initial o_data = 8'h00; |
reg pre_wr; |
initial pre_wr = 1'b0; |
always @(posedge i_clk) |
if (i_reset) |
begin |
pre_wr <= 1'b0; |
o_data <= 8'h00; |
end else if ((zero_baud_counter)&&(state == `RXU_STOP)) |
begin |
pre_wr <= 1'b1; |
case (data_bits) |
2'b00: o_data <= data_reg; |
2'b01: o_data <= { 1'b0, data_reg[7:1] }; |
2'b10: o_data <= { 2'b0, data_reg[7:2] }; |
2'b11: o_data <= { 3'b0, data_reg[7:3] }; |
endcase |
end else if ((zero_baud_counter)||(state == `RXU_IDLE)) |
pre_wr <= 1'b0; |
|
// Create an output strobe, true for one clock only, once we know |
// all we need to know. o_data will be set on the last baud interval, |
// o_parity_err on the last parity baud interval (if it existed, |
// cleared otherwise, so ... we should be good to go here.) |
initial o_wr = 1'b0; |
always @(posedge i_clk) |
if ((zero_baud_counter)||(state == `RXU_IDLE)) |
o_wr <= (pre_wr)&&(!i_reset); |
else |
o_wr <= 1'b0; |
|
// The baud counter |
// |
// This is used as a "clock divider" if you will, but the clock needs |
// to be reset before any byte can be decoded. In all other respects, |
// we set ourselves up for clocks_per_baud counts between baud |
// intervals. |
always @(posedge i_clk) |
if (i_reset) |
baud_counter <= clocks_per_baud-28'h01; |
else if (zero_baud_counter) |
baud_counter <= clocks_per_baud-28'h01; |
else case(state) |
`RXU_RESET_IDLE:baud_counter <= clocks_per_baud-28'h01; |
`RXU_BREAK: baud_counter <= clocks_per_baud-28'h01; |
`RXU_IDLE: baud_counter <= clocks_per_baud-28'h01; |
default: baud_counter <= baud_counter-28'h01; |
endcase |
|
// zero_baud_counter |
// |
// Rather than testing whether or not (baud_counter == 0) within our |
// (already too complicated) state transition tables, we use |
// zero_baud_counter to pre-charge that test on the clock |
// before--cleaning up some otherwise difficult timing dependencies. |
initial zero_baud_counter = 1'b0; |
always @(posedge i_clk) |
if (state == `RXU_IDLE) |
zero_baud_counter <= 1'b0; |
else |
zero_baud_counter <= (baud_counter == 28'h01); |
|
initial half_baud_time = 0; |
always @(posedge i_clk) |
half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud); |
|
|
endmodule |
|
|
/trunk/rtl/toplevel.v
74,7 → 74,9
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, o_oled_reset_n, |
o_oled_vccen, o_oled_pmoden, |
// PMod I/O |
i_aux_rx, i_aux_rts, o_aux_tx, o_aux_cts |
i_aux_rx, i_aux_cts_n, o_aux_tx, o_aux_rts_n, |
// Chip-kit SPI port |
o_ck_csn, o_ck_sck, o_ck_mosi |
); |
input [0:0] sys_clk_i; |
input i_reset_btn; |
126,8 → 128,9
o_oled_dcn, o_oled_reset_n, o_oled_vccen, |
o_oled_pmoden; |
// Aux UART |
input i_aux_rx, i_aux_rts; |
output wire o_aux_tx, o_aux_cts; |
input i_aux_rx, i_aux_cts_n; |
output wire o_aux_tx, o_aux_rts_n; |
output wire o_ck_csn, o_ck_sck, o_ck_mosi; |
|
wire eth_tx_clk, eth_rx_clk; |
`ifdef VERILATOR |
204,9 → 207,10
// UART interface |
// |
// |
wire [29:0] bus_uart_setup; |
// assign bus_uart_setup = 30'h10000014; // ~4MBaud, 7 bits |
assign bus_uart_setup = 30'h10000051; // ~1MBaud, 7 bits |
// localparam BUSUART = 30'h50000014; // ~4MBaud, 7 bits, no flwctrl |
localparam BUSUART = 31'h50000051; // ~1MBaud, 7 bits, no flwctrl |
wire [30:0] bus_uart_setup; |
assign bus_uart_setup = BUSUART; |
|
wire [7:0] rx_data, tx_data; |
wire rx_break, rx_parity_err, rx_frame_err, rx_stb; |
252,25 → 256,15
`endif |
|
wire w_ck_uart, w_uart_tx; |
rxuart rcv(s_clk, s_reset, bus_uart_setup, i_uart_rx, |
rxuart #(BUSUART) rcv(s_clk, s_reset, bus_uart_setup, i_uart_rx, |
rx_stb, rx_data, rx_break, |
rx_parity_err, rx_frame_err, w_ck_uart); |
txuart txv(s_clk, s_reset, bus_uart_setup|30'h8000000, 1'b0, |
tx_stb, tx_data, o_uart_tx, tx_busy); |
txuart #(BUSUART) txv(s_clk, s_reset, bus_uart_setup, 1'b0, |
tx_stb, tx_data, 1'b1, o_uart_tx, tx_busy); |
|
|
wire [3:0] w_led; |
reg [24:0] dbg_counter; |
always @(posedge sys_clk) |
dbg_counter <= dbg_counter + 25'h01; |
assign o_led = { w_led[3:2], |
((!pwr_reset)&(dbg_counter[24])) |
||((pwr_reset)&&(w_led[1])), |
(s_reset & dbg_counter[23]) |
||((!s_reset)&&(w_led[0])) }; |
|
|
|
////// |
// |
// |
286,6 → 280,11
wire [3:0] qspi_dat; |
wire [3:0] i_qspi_dat; |
|
|
wire [1:0] i_gpio; |
wire [3:0] o_gpio; |
assign i_gpio = { o_aux_rts_n, i_aux_cts_n }; |
|
// |
// The SDRAM interface wires |
// |
292,6 → 291,7
wire ram_cyc, ram_stb, ram_we; |
wire [25:0] ram_addr; |
wire [31:0] ram_rdata, ram_wdata; |
wire [3:0] ram_sel; |
wire ram_ack, ram_stall, ram_err; |
wire [31:0] ram_dbg; |
// |
299,14 → 299,17
// |
wire w_sd_cmd; |
wire [3:0] w_sd_data; |
busmaster wbbus(s_clk, s_reset, |
busmaster |
#( |
.NGPI(2), .NGPO(4) |
) wbbus(s_clk, s_reset, |
// External USB-UART bus control |
rx_stb, rx_data, tx_stb, tx_data, tx_busy, |
// Board lights and switches |
i_sw, i_btn, w_led, |
i_sw, i_btn, o_led, |
o_clr_led0, o_clr_led1, o_clr_led2, o_clr_led3, |
// Board level PMod I/O |
i_aux_rx, o_aux_tx, o_aux_cts, i_gps_rx, o_gps_tx, |
i_aux_rx, o_aux_tx, i_aux_cts_n, o_aux_rts_n,i_gps_rx, o_gps_tx, |
// Quad SPI flash |
w_qspi_cs_n, w_qspi_sck, qspi_dat, i_qspi_dat, qspi_bmod, |
// DDR3 SDRAM |
314,7 → 317,7
// o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n, |
// o_ddr_ba, o_ddr_addr, o_ddr_odt, o_ddr_dm, |
// io_ddr_dqs_p, io_ddr_dqs_n, io_ddr_data, |
ram_cyc, ram_stb, ram_we, ram_addr, ram_wdata, |
ram_cyc, ram_stb, ram_we, ram_addr, ram_wdata, ram_sel, |
ram_ack, ram_stall, ram_rdata, ram_err, |
ram_dbg, |
// SD Card |
330,7 → 333,9
o_oled_sck, o_oled_cs_n, o_oled_mosi, o_oled_dcn, |
o_oled_reset_n, o_oled_vccen, o_oled_pmoden, |
// GPS PMod |
i_gps_pps, i_gps_3df |
i_gps_pps, i_gps_3df, |
// Other GPIO wires |
i_gpio, o_gpio |
); |
|
////// |
429,7 → 434,6
// |
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz; |
|
|
// |
// |
// Now, to set up our memory ... |
440,7 → 444,7
.o_sys_clk(s_clk), .i_rst(pwr_reset), .o_sys_reset(s_reset), |
.i_wb_cyc(ram_cyc), .i_wb_stb(ram_stb), .i_wb_we(ram_we), |
.i_wb_addr(ram_addr), .i_wb_data(ram_wdata), |
.i_wb_sel(4'hf), |
.i_wb_sel(ram_sel), |
.o_wb_ack(ram_ack), .o_wb_stall(ram_stall), |
.o_wb_data(ram_rdata), .o_wb_err(ram_err), |
.o_ddr_ck_p(ddr3_ck_p), .o_ddr_ck_n(ddr3_ck_n), |
/trunk/rtl/txuart.v
2,7 → 2,7
// |
// Filename: txuart.v |
// |
// Project: FPGA library |
// Project: wbuart32, a full featured UART with simulator |
// |
// Purpose: Transmit outputs over a single UART line. |
// |
21,9 → 21,16
// Now for the setup register. The register is 32 bits, so that this |
// UART may be set up over a 32-bit bus. |
// |
// i_setup[30] Set this to zero to use hardware flow control, and to |
// one to ignore hardware flow control. Only works if the hardware |
// flow control has been properly wired. |
// |
// If you don't want hardware flow control, fix the i_rts bit to |
// 1'b1, and let the synthesys tools optimize out the logic. |
// |
// i_setup[29:28] Indicates the number of data bits per word. This will |
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 |
// for a six bit word, or 2'b11 for a five bit word. |
// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 |
// for a six bit word, or 2'b11 for a five bit word. |
// |
// i_setup[27] Indicates whether or not to use one or two stop bits. |
// Set this to one to expect two stop bits, zero for one. |
57,13 → 64,12
// 32'h005161 // For 9600 baud, 8 bit, no parity |
// |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
76,7 → 82,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
87,7 → 93,6
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
// |
`define TXU_BIT_ZERO 4'h0 |
`define TXU_BIT_ONE 4'h1 |
`define TXU_BIT_TWO 4'h2 |
106,26 → 111,39
`define TXU_IDLE 4'hf |
// |
// |
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy); |
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, |
i_cts_n, o_uart_tx, o_busy); |
parameter [30:0] INITIAL_SETUP = 31'd868; |
input i_clk, i_reset; |
input [29:0] i_setup; |
input [30:0] i_setup; |
input i_break; |
input i_wr; |
input [7:0] i_data; |
output reg o_uart; |
// Hardware flow control Ready-To-Send bit. Set this to one to use |
// the core without flow control. (A more appropriate name would be |
// the Ready-To-Receive bit ...) |
input i_cts_n; |
// And the UART input line itself |
output reg o_uart_tx; |
// A line to tell others when we are ready to accept data. If |
// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte |
// for transmission. |
output wire o_busy; |
|
wire [27:0] clocks_per_baud, break_condition; |
wire [1:0] data_bits; |
wire use_parity, parity_even, dblstop, fixd_parity; |
reg [29:0] r_setup; |
wire use_parity, parity_even, dblstop, fixd_parity, |
fixdp_value, hw_flow_control; |
reg [30:0] r_setup; |
assign clocks_per_baud = { 4'h0, r_setup[23:0] }; |
assign break_condition = { r_setup[23:0], 4'h0 }; |
assign data_bits = r_setup[29:28]; |
assign dblstop = r_setup[27]; |
assign use_parity = r_setup[26]; |
assign fixd_parity = r_setup[25]; |
assign parity_even = r_setup[24]; |
assign hw_flow_control = !r_setup[30]; |
assign data_bits = r_setup[29:28]; |
assign dblstop = r_setup[27]; |
assign use_parity = r_setup[26]; |
assign fixd_parity = r_setup[25]; |
assign parity_even = r_setup[24]; |
assign fixdp_value = r_setup[24]; |
|
reg [27:0] baud_counter; |
reg [3:0] state; |
132,7 → 150,30
reg [7:0] lcl_data; |
reg calc_parity, r_busy, zero_baud_counter; |
|
initial o_uart = 1'b1; |
|
// First step ... handle any hardware flow control, if so enabled. |
// |
// Clock in the flow control data, two clocks to avoid metastability |
// Default to using hardware flow control (uart_setup[30]==0 to use it). |
// Set this high order bit off if you do not wish to use it. |
reg q_cts_n, qq_cts_n, ck_cts; |
// While we might wish to give initial values to q_rts and ck_cts, |
// 1) it's not required since the transmitter starts in a long wait |
// state, and 2) doing so will prevent the synthesizer from optimizing |
// this pin in the case it is hard set to 1'b1 external to this |
// peripheral. |
// |
// initial q_cts_n = 1'b1; |
// initial qq_cts_n = 1'b1; |
// initial ck_cts = 1'b0; |
always @(posedge i_clk) |
q_cts_n <= i_cts_n; |
always @(posedge i_clk) |
qq_cts_n <= q_cts_n; |
always @(posedge i_clk) |
ck_cts <= (!qq_cts_n)||(!hw_flow_control); |
|
initial o_uart_tx = 1'b1; |
initial r_busy = 1'b1; |
initial state = `TXU_IDLE; |
initial lcl_data= 8'h0; |
142,18 → 183,13
begin |
if (i_reset) |
begin |
o_uart <= 1'b1; |
r_busy <= 1'b1; |
state <= `TXU_IDLE; |
lcl_data <= 8'h0; |
calc_parity <= 1'b0; |
end else if (i_break) |
begin |
o_uart <= 1'b0; |
state <= `TXU_BREAK; |
calc_parity <= 1'b0; |
r_busy <= 1'b1; |
end else if (~zero_baud_counter) |
end else if (!zero_baud_counter) |
begin // r_busy needs to be set coming into here |
r_busy <= 1'b1; |
end else if (state == `TXU_BREAK) |
160,17 → 196,10
begin |
state <= `TXU_IDLE; |
r_busy <= 1'b1; |
o_uart <= 1'b1; |
calc_parity <= 1'b0; |
end else if (state == `TXU_IDLE) // STATE_IDLE |
begin |
// baud_counter <= 0; |
r_setup <= i_setup; |
calc_parity <= 1'b0; |
lcl_data <= i_data; |
if ((i_wr)&&(~r_busy)) |
if ((i_wr)&&(!r_busy)) |
begin // Immediately start us off with a start bit |
o_uart <= 1'b0; |
r_busy <= 1'b1; |
case(data_bits) |
2'b00: state <= `TXU_BIT_ZERO; |
178,11 → 207,8
2'b10: state <= `TXU_BIT_TWO; |
2'b11: state <= `TXU_BIT_THREE; |
endcase |
// baud_counter <= clocks_per_baud-28'h01; |
end else begin // Stay in idle |
o_uart <= 1'b1; |
r_busy <= 0; |
// state <= state; |
r_busy <= !ck_cts; |
end |
end else begin |
// One clock tick in each of these states ... |
190,32 → 216,22
r_busy <= 1'b1; |
if (state[3] == 0) // First 8 bits |
begin |
o_uart <= lcl_data[0]; |
calc_parity <= calc_parity ^ lcl_data[0]; |
if (state == `TXU_BIT_SEVEN) |
state <= (use_parity)?`TXU_PARITY:`TXU_STOP; |
else |
state <= state + 1; |
lcl_data <= { 1'b0, lcl_data[7:1] }; |
end else if (state == `TXU_PARITY) |
begin |
state <= `TXU_STOP; |
if (fixd_parity) |
o_uart <= parity_even; |
else |
o_uart <= calc_parity^((parity_even)? 1'b1:1'b0); |
end else if (state == `TXU_STOP) |
begin // two stop bit(s) |
o_uart <= 1'b1; |
if (dblstop) |
state <= `TXU_SECOND_STOP; |
else |
state <= `TXU_IDLE; |
calc_parity <= 1'b0; |
end else // `TXU_SECOND_STOP and default: |
begin |
state <= `TXU_IDLE; // Go back to idle |
o_uart <= 1'b1; |
// Still r_busy, since we need to wait |
// for the baud clock to finish counting |
// out this last bit. |
223,28 → 239,154
end |
end |
|
// o_busy |
// |
// This is a wire, designed to be true is we are ever busy above. |
// originally, this was going to be true if we were ever not in the |
// idle state. The logic has since become more complex, hence we have |
// a register dedicated to this and just copy out that registers value. |
assign o_busy = (r_busy); |
|
|
initial zero_baud_counter = 1'b1; |
initial baud_counter = 28'd200000; // 1ms @ 200MHz |
// r_setup |
// |
// Our setup register. Accept changes between any pair of transmitted |
// words. The register itself has many fields to it. These are |
// broken out up top, and indicate what 1) our baud rate is, 2) our |
// number of stop bits, 3) what type of parity we are using, and 4) |
// the size of our data word. |
initial r_setup = INITIAL_SETUP; |
always @(posedge i_clk) |
if (state == `TXU_IDLE) |
r_setup <= i_setup; |
|
// lcl_data |
// |
// This is our working copy of the i_data register which we use |
// when transmitting. It is only of interest during transmit, and is |
// allowed to be whatever at any other time. Hence, if r_busy isn't |
// true, we can always set it. On the one clock where r_busy isn't |
// true and i_wr is, we set it and r_busy is true thereafter. |
// Then, on any zero_baud_counter (i.e. change between baud intervals) |
// we simple logically shift the register right to grab the next bit. |
always @(posedge i_clk) |
if (!r_busy) |
lcl_data <= i_data; |
else if (zero_baud_counter) |
lcl_data <= { 1'b0, lcl_data[7:1] }; |
|
// o_uart_tx |
// |
// This is the final result/output desired of this core. It's all |
// centered about o_uart_tx. This is what finally needs to follow |
// the UART protocol. |
// |
// Ok, that said, our rules are: |
// 1'b0 on any break condition |
// 1'b0 on a start bit (IDLE, write, and not busy) |
// lcl_data[0] during any data transfer, but only at the baud |
// change |
// PARITY -- During the parity bit. This depends upon whether or |
// not the parity bit is fixed, then what it's fixed to, |
// or changing, and hence what it's calculated value is. |
// 1'b1 at all other times (stop bits, idle, etc) |
always @(posedge i_clk) |
if (i_reset) |
o_uart_tx <= 1'b1; |
else if ((i_break)||((i_wr)&&(!r_busy))) |
o_uart_tx <= 1'b0; |
else if (zero_baud_counter) |
casez(state) |
4'b0???: o_uart_tx <= lcl_data[0]; |
`TXU_PARITY: o_uart_tx <= calc_parity; |
default: o_uart_tx <= 1'b1; |
endcase |
|
|
// calc_parity |
// |
// Calculate the parity to be placed into the parity bit. If the |
// parity is fixed, then the parity bit is given by the fixed parity |
// value (r_setup[24]). Otherwise the parity is given by the GF2 |
// sum of all the data bits (plus one for even parity). |
always @(posedge i_clk) |
if (fixd_parity) |
calc_parity <= fixdp_value; |
else if (zero_baud_counter) |
begin |
if (state[3] == 0) // First 8 bits of msg |
calc_parity <= calc_parity ^ lcl_data[0]; |
else |
calc_parity <= parity_even; |
end else if (!r_busy) |
calc_parity <= parity_even; |
|
|
// All of the above logic is driven by the baud counter. Bits must last |
// clocks_per_baud in length, and this baud counter is what we use to |
// make certain of that. |
// |
// The basic logic is this: at the beginning of a bit interval, start |
// the baud counter and set it to count clocks_per_baud. When it gets |
// to zero, restart it. |
// |
// However, comparing a 28'bit number to zero can be rather complex-- |
// especially if we wish to do anything else on that same clock. For |
// that reason, we create "zero_baud_counter". zero_baud_counter is |
// nothing more than a flag that is true anytime baud_counter is zero. |
// It's true when the logic (above) needs to step to the next bit. |
// Simple enough? |
// |
// I wish we could stop there, but there are some other (ugly) |
// conditions to deal with that offer exceptions to this basic logic. |
// |
// 1. When the user has commanded a BREAK across the line, we need to |
// wait several baud intervals following the break before we start |
// transmitting, to give any receiver a chance to recognize that we are |
// out of the break condition, and to know that the next bit will be |
// a stop bit. |
// |
// 2. A reset is similar to a break condition--on both we wait several |
// baud intervals before allowing a start bit. |
// |
// 3. In the idle state, we stop our counter--so that upon a request |
// to transmit when idle we can start transmitting immediately, rather |
// than waiting for the end of the next (fictitious and arbitrary) baud |
// interval. |
// |
// When (i_wr)&&(!r_busy)&&(state == `TXU_IDLE) then we're not only in |
// the idle state, but we also just accepted a command to start writing |
// the next word. At this point, the baud counter needs to be reset |
// to the number of clocks per baud, and zero_baud_counter set to zero. |
// |
// The logic is a bit twisted here, in that it will only check for the |
// above condition when zero_baud_counter is false--so as to make |
// certain the STOP bit is complete. |
initial zero_baud_counter = 1'b0; |
initial baud_counter = 28'h05; |
always @(posedge i_clk) |
begin |
zero_baud_counter <= (baud_counter == 28'h01); |
if ((i_reset)||(i_break)) |
begin |
// Give ourselves 16 bauds before being ready |
baud_counter <= break_condition; |
else if (~zero_baud_counter) |
zero_baud_counter <= 1'b0; |
end else if (!zero_baud_counter) |
baud_counter <= baud_counter - 28'h01; |
else if (state == `TXU_BREAK) |
// Give us two stop bits before becoming available |
// Give us four idle baud intervals before becoming |
// available |
baud_counter <= clocks_per_baud<<2; |
else if (state == `TXU_IDLE) |
begin |
if((i_wr)&&(~r_busy)) |
baud_counter <= 28'h0; |
zero_baud_counter <= 1'b1; |
if ((i_wr)&&(!r_busy)) |
begin |
baud_counter <= clocks_per_baud - 28'h01; |
else |
zero_baud_counter <= 1'b1; |
zero_baud_counter <= 1'b0; |
end |
end else |
baud_counter <= clocks_per_baud - 28'h01; |
end |
/trunk/rtl/ufifo.v
0,0 → 1,255
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: ufifo.v |
// |
// Project: wbuart32, a full featured UART with simulator |
// |
// Purpose: |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
module ufifo(i_clk, i_rst, i_wr, i_data, o_empty_n, i_rd, o_data, o_status, o_err); |
parameter BW=8; // Byte/data width |
parameter [3:0] LGFLEN=4; |
parameter RXFIFO=1'b0; |
input i_clk, i_rst; |
input i_wr; |
input [(BW-1):0] i_data; |
output wire o_empty_n; // True if something is in FIFO |
input i_rd; |
output wire [(BW-1):0] o_data; |
output wire [15:0] o_status; |
output wire o_err; |
|
localparam FLEN=(1<<LGFLEN); |
|
reg [(BW-1):0] fifo[0:(FLEN-1)]; |
reg [(LGFLEN-1):0] r_first, r_last, r_next; |
|
wire [(LGFLEN-1):0] w_first_plus_one, w_first_plus_two, |
w_last_plus_one; |
assign w_first_plus_two = r_first + {{(LGFLEN-2){1'b0}},2'b10}; |
assign w_first_plus_one = r_first + {{(LGFLEN-1){1'b0}},1'b1}; |
assign w_last_plus_one = r_next; // r_last + 1'b1; |
|
reg will_overflow; |
initial will_overflow = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
will_overflow <= 1'b0; |
else if (i_rd) |
will_overflow <= (will_overflow)&&(i_wr); |
else if (i_wr) |
will_overflow <= (w_first_plus_two == r_last); |
else if (w_first_plus_one == r_last) |
will_overflow <= 1'b1; |
|
// Write |
reg r_ovfl; |
initial r_first = 0; |
initial r_ovfl = 0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
r_ovfl <= 1'b0; |
r_first <= { (LGFLEN){1'b0} }; |
end else if (i_wr) |
begin // Cowardly refuse to overflow |
if ((i_rd)||(!will_overflow)) // (r_first+1 != r_last) |
r_first <= w_first_plus_one; |
else |
r_ovfl <= 1'b1; |
end |
always @(posedge i_clk) |
if (i_wr) // Write our new value regardless--on overflow or not |
fifo[r_first] <= i_data; |
|
// Reads |
// Following a read, the next sample will be available on the |
// next clock |
// Clock ReadCMD ReadAddr Output |
// 0 0 0 fifo[0] |
// 1 1 0 fifo[0] |
// 2 0 1 fifo[1] |
// 3 0 1 fifo[1] |
// 4 1 1 fifo[1] |
// 5 1 2 fifo[2] |
// 6 0 3 fifo[3] |
// 7 0 3 fifo[3] |
reg will_underflow; |
initial will_underflow = 1'b1; |
always @(posedge i_clk) |
if (i_rst) |
will_underflow <= 1'b1; |
else if (i_wr) |
will_underflow <= (will_underflow)&&(i_rd); |
else if (i_rd) |
will_underflow <= (w_last_plus_one == r_first); |
else |
will_underflow <= (r_last == r_first); |
|
// |
// Don't report FIFO underflow errors. These'll be caught elsewhere |
// in the system, and the logic below makes it hard to reset them. |
// We'll still report FIFO overflow, however. |
// |
// reg r_unfl; |
// initial r_unfl = 1'b0; |
initial r_last = 0; |
always @(posedge i_clk) |
if (i_rst) |
begin |
r_last <= 0; |
r_next <= { {(LGFLEN-1){1'b0}}, 1'b1 }; |
// r_unfl <= 1'b0; |
end else if (i_rd) |
begin |
if ((i_wr)||(!will_underflow)) // (r_first != r_last) |
begin |
r_last <= r_next; |
r_next <= r_last +{{(LGFLEN-2){1'b0}},2'b10}; |
// Last chases first |
// Need to be prepared for a possible two |
// reads in quick succession |
// o_data <= fifo[r_last+1]; |
end |
// else r_unfl <= 1'b1; |
end |
|
reg [7:0] fifo_here, fifo_next, r_data; |
always @(posedge i_clk) |
fifo_here <= fifo[r_last]; |
always @(posedge i_clk) |
fifo_next <= fifo[r_next]; |
always @(posedge i_clk) |
r_data <= i_data; |
|
reg [1:0] osrc; |
always @(posedge i_clk) |
if (will_underflow) |
// o_data <= i_data; |
osrc <= 2'b00; |
else if ((i_rd)&&(r_first == w_last_plus_one)) |
osrc <= 2'b01; |
else if (i_rd) |
osrc <= 2'b11; |
else |
osrc <= 2'b10; |
assign o_data = (osrc[1]) ? ((osrc[0])?fifo_next:fifo_here) : r_data; |
|
// wire [(LGFLEN-1):0] current_fill; |
// assign current_fill = (r_first-r_last); |
|
reg r_empty_n; |
initial r_empty_n = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_empty_n <= 1'b0; |
else case({i_wr, i_rd}) |
2'b00: r_empty_n <= (r_first != r_last); |
2'b11: r_empty_n <= (r_first != r_last); |
2'b10: r_empty_n <= 1'b1; |
2'b01: r_empty_n <= (r_first != w_last_plus_one); |
endcase |
|
wire w_full_n; |
assign w_full_n = will_overflow; |
|
// |
// If this is a receive FIFO, the FIFO count that matters is the number |
// of values yet to be read. If instead this is a transmit FIFO, then |
// the FIFO count that matters is the number of empty positions that |
// can still be filled before the FIFO is full. |
// |
// Adjust for these differences here. |
reg [(LGFLEN-1):0] r_fill; |
always @(posedge i_clk) |
if (RXFIFO!=0) begin |
// Calculate the number of elements in our FIFO |
// |
// Although used for receive, this is actually the more |
// generic answer--should you wish to use the FIFO in |
// another context. |
if (i_rst) |
r_fill <= 0; |
else case({i_wr, i_rd}) |
2'b01: r_fill <= r_first - r_next; |
2'b10: r_fill <= r_first - r_last + 1'b1; |
default: r_fill <= r_first - r_last; |
endcase |
end else begin |
// Calculate the number of elements that are empty and |
// can be filled within our FIFO |
if (i_rst) |
r_fill <= { (LGFLEN){1'b1} }; |
else case({i_wr, i_rd}) |
2'b01: r_fill <= r_last - r_first; |
2'b10: r_fill <= r_last - w_first_plus_two; |
default: r_fill <= r_last - w_first_plus_one; |
endcase |
end |
|
// We don't report underflow errors. These |
assign o_err = (r_ovfl); // || (r_unfl); |
|
wire [3:0] lglen; |
assign lglen = LGFLEN; |
|
wire [9:0] w_fill; |
assign w_fill[(LGFLEN-1):0] = r_fill; |
generate if (LGFLEN < 10) |
assign w_fill[9:(LGFLEN)] = 0; |
endgenerate |
|
wire w_half_full; |
assign w_half_full = r_fill[(LGFLEN-1)]; |
|
assign o_status = { |
// Our status includes a 4'bit nibble telling anyone reading |
// this the size of our FIFO. The size is then given by |
// 2^(this value). Hence a 4'h4 in this position means that the |
// FIFO has 2^4 or 16 values within it. |
lglen, |
// The FIFO fill--for a receive FIFO the number of elements |
// left to be read, and for a transmit FIFO the number of |
// empty elements within the FIFO that can yet be filled. |
w_fill, |
// A '1' here means a half FIFO length can be read (receive |
// FIFO) or written to (not a receive FIFO). |
// receive FIFO), or be written to (if it isn't). |
(RXFIFO!=0)?w_half_full:w_half_full, |
// A '1' here means the FIFO can be read from (if it is a |
// receive FIFO), or be written to (if it isn't). |
(RXFIFO!=0)?r_empty_n:w_full_n |
}; |
|
assign o_empty_n = r_empty_n; |
|
endmodule |
/trunk/rtl/wbgpio.v
2,7 → 2,7
// |
// Filename: wbgpio.v |
// |
// Project: CMod S6 System on a Chip, ZipCPU demonstration project |
// Project: OpenArty, an entirely open SoC based upon the Arty platform |
// |
// Purpose: A General Purpose Input/Output controller. This controller |
// allows a user to read the current state of the 16-GPIO input |
36,7 → 36,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
67,12 → 67,13
o_gpio <= ((o_gpio)&(~i_wb_data[(NOUT+16-1):16])) |
|((i_wb_data[(NOUT-1):0])&(i_wb_data[(NOUT+16-1):16])); |
|
reg [(NIN-1):0] x_gpio, r_gpio; |
reg [(NIN-1):0] x_gpio, q_gpio, r_gpio; |
// 3 LUTs, 33 FF's |
always @(posedge i_clk) |
begin |
x_gpio <= i_gpio; |
r_gpio <= x_gpio; |
q_gpio <= x_gpio; |
r_gpio <= q_gpio; |
o_int <= (x_gpio != r_gpio); |
end |
|
/trunk/rtl/wbscope.v
2,21 → 2,20
// |
// Filename: wbscope.v |
// |
// Project: FPGA Library of Routines |
// Project: WBScope, a wishbone hosted scope |
// |
// Purpose: This is a generic/library routine for providing a bus accessed |
// 'scope' or (perhaps more appropriately) a bus accessed logic |
// analyzer. The general operation is such that this 'scope' can |
// record and report on any 32 bit value transiting through the |
// FPGA. Once started and reset, the scope records a copy of the |
// input data every time the clock ticks with the circuit enabled. |
// That is, it records these values up until the trigger. Once |
// the trigger goes high, the scope will record for bw_holdoff |
// more counts before stopping. Values may then be read from the |
// buffer, oldest to most recent. After reading, the scope may |
// then be reset for another run. |
// 'scope' or (perhaps more appropriately) a bus accessed logic analyzer. |
// The general operation is such that this 'scope' can record and report |
// on any 32 bit value transiting through the FPGA. Once started and |
// reset, the scope records a copy of the input data every time the clock |
// ticks with the circuit enabled. That is, it records these values up |
// until the trigger. Once the trigger goes high, the scope will record |
// for bw_holdoff more counts before stopping. Values may then be read |
// from the buffer, oldest to most recent. After reading, the scope may |
// then be reset for another run. |
// |
// In general, therefore, operation happens in this fashion: |
// In general, therefore, operation happens in this fashion: |
// 1. A reset is issued. |
// 2. Recording starts, in a circular buffer, and continues until |
// 3. The trigger line is asserted. |
60,7 → 59,7
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015, Gisselquist Technology, LLC |
// Copyright (C) 2015-2017, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
73,7 → 72,7
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
114,7 → 113,7
wire [19:0] bw_holdoff; |
initial br_config = DEFAULT_HOLDOFF; |
always @(posedge i_wb_clk) |
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_addr)) |
if ((i_wb_stb)&&(~i_wb_addr)) |
begin |
if (i_wb_we) |
br_config <= { i_wb_data[31], |
200,18 → 199,20
initial counter = 20'h0000; |
always @(posedge i_clk) |
if (dw_reset) |
begin |
counter <= 0; |
dr_stopped <= 1'b0; |
end else if ((i_ce)&&(dr_triggered)) |
else if ((i_ce)&&(dr_triggered)&&(~dr_stopped)) |
begin // MUST BE a < and not <=, so that we can keep this w/in |
// 20 bits. Else we'd need to add a bit to comparison |
// here. |
if (counter < bw_holdoff) |
counter <= counter + 20'h01; |
else |
dr_stopped <= 1'b1; |
counter <= counter + 20'h01; |
end |
always @(posedge i_clk) |
if ((~dr_triggered)||(dw_reset)) |
dr_stopped <= 1'b0; |
else if (i_ce) |
dr_stopped <= (counter+20'd1 >= bw_holdoff); |
else |
dr_stopped <= (counter >= bw_holdoff); |
|
// |
// Actually do our writes to memory. Record, via 'primed' when |
231,7 → 232,7
begin |
waddr <= 0; // upon reset. |
dr_primed <= 1'b0; |
end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff))) |
end else if ((i_ce)&&((~dr_triggered)||(!dr_stopped))) |
begin |
// mem[waddr] <= i_data; |
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1}; |
238,7 → 239,7
dr_primed <= (dr_primed)||(&waddr); |
end |
always @(posedge i_clk) |
if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff))) |
if ((i_ce)&&((~dr_triggered)||(!dr_stopped))) |
mem[waddr] <= i_data; |
|
// |
280,7 → 281,7
reg br_wb_ack; |
initial br_wb_ack = 1'b0; |
wire bw_cyc_stb; |
assign bw_cyc_stb = ((i_wb_cyc)&&(i_wb_stb)); |
assign bw_cyc_stb = (i_wb_stb); |
always @(posedge i_wb_clk) |
begin |
if ((bw_reset_request) |
/trunk/rtl/wbuart.v
0,0 → 1,419
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: wbuart.v |
// |
// Project: wbuart32, a full featured UART with simulator |
// |
// Purpose: Unlilke wbuart-insert.v, this is a full blown wishbone core |
// with integrated FIFO support to support the UART transmitter |
// and receiver found within here. As a result, it's usage may be |
// heavier on the bus than the insert, but it may also be more useful. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory. Run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define UART_SETUP 2'b00 |
`define UART_FIFO 2'b01 |
`define UART_RXREG 2'b10 |
`define UART_TXREG 2'b11 |
module wbuart(i_clk, i_rst, |
// |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
// |
i_uart_rx, o_uart_tx, i_cts_n, o_rts_n, |
// |
o_uart_rx_int, o_uart_tx_int, |
o_uart_rxfifo_int, o_uart_txfifo_int); |
parameter [30:0] INITIAL_SETUP = 31'd25; // 4MB 8N1, when using 100MHz clock |
parameter [3:0] LGFLEN = 4; |
parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1; |
// Perform a simple/quick bounds check on the log FIFO length, to make |
// sure its within the bounds we can support with our current |
// interface. |
localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha |
: ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN); |
// |
input i_clk, i_rst; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [1:0] i_wb_addr; |
input [31:0] i_wb_data; |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [31:0] o_wb_data; |
// |
input i_uart_rx; |
output wire o_uart_tx; |
// RTS is used for hardware flow control. According to Wikipedia, it |
// should probably be renamed RTR for "ready to receive". It tell us |
// whether or not the receiving hardware is ready to accept another |
// byte. If low, the transmitter will pause. |
// |
// If you don't wish to use hardware flow control, just set i_cts_n to |
// 1'b0 and let the optimizer simply remove this logic. |
input i_cts_n; |
// CTS is the "Clear-to-send" signal. We set it anytime our FIFO |
// isn't full. Feel free to ignore this output if you do not wish to |
// use flow control. |
output reg o_rts_n; |
output wire o_uart_rx_int, o_uart_tx_int, |
o_uart_rxfifo_int, o_uart_txfifo_int; |
|
wire tx_busy; |
|
// |
// The UART setup parameters: bits per byte, stop bits, parity, and |
// baud rate are all captured within this uart_setup register. |
// |
reg [30:0] uart_setup; |
initial uart_setup = INITIAL_SETUP; |
always @(posedge i_clk) |
// Under wishbone rules, a write takes place any time i_wb_stb |
// is high. If that's the case, and if the write was to the |
// setup address, then set us up for the new parameters. |
if ((i_wb_stb)&&(i_wb_addr == `UART_SETUP)&&(i_wb_we)) |
uart_setup <= { |
(i_wb_data[30]) |
||(!HARDWARE_FLOW_CONTROL_PRESENT), |
i_wb_data[29:0] }; |
|
///////////////////////////////////////// |
// |
// |
// First, the UART receiver |
// |
// |
///////////////////////////////////////// |
|
// First the wires/registers this receiver depends upon |
wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart; |
wire [7:0] rx_uart_data; |
reg rx_uart_reset; |
|
// Here's our UART receiver. Basically, it accepts our setup wires, |
// the UART input, a clock, and a reset line, and produces outputs: |
// a stb (true when new data is ready), and an 8-bit data out value |
// valid when stb is high. |
`ifdef USE_LITE_UART |
rxuartlite #(INITIAL_SETUP[23:0]) |
rx(i_clk, (i_rst), i_uart_rx, rx_stb, rx_uart_data); |
assign rx_break = 1'b0; |
assign rx_perr = 1'b0; |
assign rx_ferr = 1'b0; |
assign ck_uart = 1'b0; |
`else |
// The full receiver also produces a break value (true during a break |
// cond.), and parity/framing error flags--also valid when stb is true. |
rxuart #(INITIAL_SETUP) rx(i_clk, (i_rst)||(rx_uart_reset), |
uart_setup, i_uart_rx, |
rx_stb, rx_uart_data, rx_break, |
rx_perr, rx_ferr, ck_uart); |
// The real trick is ... now that we have this extra data, what do we do |
// with it? |
`endif |
|
|
// We place it into a receiver FIFO. |
// |
// Here's the declarations for the wires it needs. |
wire rx_empty_n, rx_fifo_err; |
wire [7:0] rxf_wb_data; |
wire [15:0] rxf_status; |
reg rxf_wb_read; |
// |
// And here's the FIFO proper. |
// |
// Note that the FIFO will be cleared upon any reset: either if there's |
// a UART break condition on the line, the receiver is in reset, or an |
// external reset is issued. |
// |
// The FIFO accepts strobe and data from the receiver. |
// We issue another wire to it (rxf_wb_read), true when we wish to read |
// from the FIFO, and we get our data in rxf_wb_data. The FIFO outputs |
// four status-type values: 1) is it non-empty, 2) is the FIFO over half |
// full, 3) a 16-bit status register, containing info regarding how full |
// the FIFO truly is, and 4) an error indicator. |
ufifo #(.LGFLEN(LCLLGFLEN), .RXFIFO(1)) |
rxfifo(i_clk, (i_rst)||(rx_break)||(rx_uart_reset), |
rx_stb, rx_uart_data, |
rx_empty_n, |
rxf_wb_read, rxf_wb_data, |
rxf_status, rx_fifo_err); |
assign o_uart_rxfifo_int = rxf_status[1]; |
|
// We produce four interrupts. One of the receive interrupts indicates |
// whether or not the receive FIFO is non-empty. This should wake up |
// the CPU. |
assign o_uart_rx_int = rxf_status[0]; |
|
// The clear to send line, which may be ignored, but which we set here |
// to be true any time the FIFO has fewer than N-2 items in it. |
// Why N-1? Because at N-1 we are totally full, but already so full |
// that if the transmit end starts sending we won't have a location to |
// receive it. (Transmit might've started on the next character by the |
// time we set this--need to set it to one character before necessary |
always @(posedge i_clk) |
o_rts_n = ((HARDWARE_FLOW_CONTROL_PRESENT) |
&&(!uart_setup[30]) |
&&(rxf_status[(LCLLGFLEN+1):4]=={(LCLLGFLEN-2){1'b1}})); |
|
// If the bus requests that we read from the receive FIFO, we need to |
// tell this to the receive FIFO. Note that because we are using a |
// clock here, the output from the receive FIFO will necessarily be |
// delayed by an extra clock. |
initial rxf_wb_read = 1'b0; |
always @(posedge i_clk) |
rxf_wb_read <= (i_wb_stb)&&(i_wb_addr[1:0]==`UART_RXREG) |
&&(!i_wb_we); |
|
// Now, let's deal with those RX UART errors: both the parity and frame |
// errors. As you may recall, these are valid only when rx_stb is |
// valid, so we need to hold on to them until the user reads them via |
// a UART read request.. |
reg r_rx_perr, r_rx_ferr; |
initial r_rx_perr = 1'b0; |
initial r_rx_ferr = 1'b0; |
always @(posedge i_clk) |
if ((rx_uart_reset)||(rx_break)) |
begin |
// Clear the error |
r_rx_perr <= 1'b0; |
r_rx_ferr <= 1'b0; |
end else if ((i_wb_stb) |
&&(i_wb_addr[1:0]==`UART_RXREG)&&(i_wb_we)) |
begin |
// Reset the error lines if a '1' is ever written to |
// them, otherwise leave them alone. |
// |
r_rx_perr <= (r_rx_perr)&&(~i_wb_data[9]); |
r_rx_ferr <= (r_rx_ferr)&&(~i_wb_data[10]); |
end else if (rx_stb) |
begin |
// On an rx_stb, capture any parity or framing error |
// indications. These aren't kept with the data rcvd, |
// but rather kept external to the FIFO. As a result, |
// if you get a parity or framing error, you will never |
// know which data byte it was associated with. |
// For now ... that'll work. |
r_rx_perr <= (r_rx_perr)||(rx_perr); |
r_rx_ferr <= (r_rx_ferr)||(rx_ferr); |
end |
|
initial rx_uart_reset = 1'b1; |
always @(posedge i_clk) |
if ((i_rst)||((i_wb_stb)&&(i_wb_addr[1:0]==`UART_SETUP)&&(i_wb_we))) |
// The receiver reset, always set on a master reset |
// request. |
rx_uart_reset <= 1'b1; |
else if ((i_wb_stb)&&(i_wb_addr[1:0]==`UART_RXREG)&&(i_wb_we)) |
// Writes to the receive register will command a receive |
// reset anytime bit[12] is set. |
rx_uart_reset <= i_wb_data[12]; |
else |
rx_uart_reset <= 1'b0; |
|
// Finally, we'll construct a 32-bit value from these various wires, |
// to be returned over the bus on any read. These include the data |
// that would be read from the FIFO, an error indicator set upon |
// reading from an empty FIFO, a break indicator, and the frame and |
// parity error signals. |
wire [31:0] wb_rx_data; |
assign wb_rx_data = { 16'h00, |
3'h0, rx_fifo_err, |
rx_break, rx_ferr, r_rx_perr, !rx_empty_n, |
rxf_wb_data}; |
|
///////////////////////////////////////// |
// |
// |
// Then the UART transmitter |
// |
// |
///////////////////////////////////////// |
wire tx_empty_n, txf_err, tx_break; |
wire [7:0] tx_data; |
wire [15:0] txf_status; |
reg txf_wb_write, tx_uart_reset; |
reg [7:0] txf_wb_data; |
|
// Unlike the receiver which goes from RXUART -> UFIFO -> WB, the |
// transmitter basically goes WB -> UFIFO -> TXUART. Hence, to build |
// support for the transmitter, we start with the command to write data |
// into the FIFO. In this case, we use the act of writing to the |
// UART_TXREG address as our indication that we wish to write to the |
// FIFO. Here, we create a write command line, and latch the data for |
// the extra clock that it'll take so that the command and data can be |
// both true on the same clock. |
initial txf_wb_write = 1'b0; |
always @(posedge i_clk) |
begin |
txf_wb_write <= (i_wb_stb)&&(i_wb_addr == `UART_TXREG) |
&&(i_wb_we); |
txf_wb_data <= i_wb_data[7:0]; |
end |
|
// Transmit FIFO |
// |
// Most of this is just wire management. The TX FIFO is identical in |
// implementation to the RX FIFO (theyre both UFIFOs), but the TX |
// FIFO is fed from the WB and read by the transmitter. Some key |
// differences to note: we reset the transmitter on any request for a |
// break. We read from the FIFO any time the UART transmitter is idle. |
// and ... we just set the values (above) for controlling writing into |
// this. |
ufifo #(.LGFLEN(LGFLEN), .RXFIFO(0)) |
txfifo(i_clk, (tx_break)||(tx_uart_reset), |
txf_wb_write, txf_wb_data, |
tx_empty_n, |
(!tx_busy)&&(tx_empty_n), tx_data, |
txf_status, txf_err); |
// Let's create two transmit based interrupts from the FIFO for the CPU. |
// The first will be true any time the FIFO has at least one open |
// position within it. |
assign o_uart_tx_int = txf_status[0]; |
// The second will be true any time the FIFO is less than half |
// full, allowing us a change to always keep it (near) fully |
// charged. |
assign o_uart_txfifo_int = txf_status[1]; |
|
`ifndef USE_LITE_UART |
// Break logic |
// |
// A break in a UART controller is any time the UART holds the line |
// low for an extended period of time. Here, we capture the wb_data[9] |
// wire, on writes, as an indication we wish to break. As long as you |
// write unsigned characters to the interface, this will never be true |
// unless you wish it to be true. Be aware, though, writing a valid |
// value to the interface will bring it out of the break condition. |
reg r_tx_break; |
initial r_tx_break = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_tx_break <= 1'b0; |
else if ((i_wb_stb)&&(i_wb_addr[1:0]==`UART_TXREG)&&(i_wb_we)) |
r_tx_break <= i_wb_data[9]; |
assign tx_break = r_tx_break; |
`else |
assign tx_break = 1'b0; |
`endif |
|
// TX-Reset logic |
// |
// This is nearly identical to the RX reset logic above. Basically, |
// any time someone writes to bit [12] the transmitter will go through |
// a reset cycle. Keep bit [12] low, and everything will proceed as |
// normal. |
initial tx_uart_reset = 1'b1; |
always @(posedge i_clk) |
if((i_rst)||((i_wb_stb)&&(i_wb_addr == `UART_SETUP)&&(i_wb_we))) |
tx_uart_reset <= 1'b1; |
else if ((i_wb_stb)&&(i_wb_addr[1:0]==`UART_TXREG)&&(i_wb_we)) |
tx_uart_reset <= i_wb_data[12]; |
else |
tx_uart_reset <= 1'b0; |
|
`ifdef USE_LITE_UART |
txuart #(INITIAL_SETUP[23:0]) tx(i_clk, (tx_empty_n), tx_data, |
o_uart_tx, tx_busy); |
`else |
wire cts_n; |
assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT)&&(i_cts_n); |
// Finally, the UART transmitter module itself. Note that we haven't |
// connected the reset wire. Transmitting is as simple as setting |
// the stb value (here set to tx_empty_n) and the data. When these |
// are both set on the same clock that tx_busy is low, the transmitter |
// will move on to the next data byte. Really, the only thing magical |
// here is that tx_empty_n wire--thus, if there's anything in the FIFO, |
// we read it here. (You might notice above, we register a read any |
// time (tx_empty_n) and (!tx_busy) are both true---the condition for |
// starting to transmit a new byte.) |
txuart #(INITIAL_SETUP) tx(i_clk, 1'b0, uart_setup, |
r_tx_break, (tx_empty_n), tx_data, |
cts_n, o_uart_tx, tx_busy); |
`endif |
|
// Now that we are done with the chain, pick some wires for the user |
// to read on any read of the transmit port. |
// |
// This port is different from reading from the receive port, since |
// there are no side effects. (Reading from the receive port advances |
// the receive FIFO, here only writing to the transmit port advances the |
// transmit FIFO--hence the read values are free for ... whatever.) |
// We choose here to provide information about the transmit FIFO |
// (txf_err, txf_half_full, txf_full_n), information about the current |
// voltage on the line (o_uart_tx)--and even the voltage on the receive |
// line (ck_uart), as well as our current setting of the break and |
// whether or not we are actively transmitting. |
wire [31:0] wb_tx_data; |
assign wb_tx_data = { 16'h00, |
i_cts_n, txf_status[1:0], txf_err, |
ck_uart, o_uart_tx, tx_break, (tx_busy|txf_status[0]), |
(tx_busy|txf_status[0])?txf_wb_data:8'b00}; |
|
// Each of the FIFO's returns a 16 bit status value. This value tells |
// us both how big the FIFO is, as well as how much of the FIFO is in |
// use. Let's merge those two status words together into a word we |
// can use when reading about the FIFO. |
wire [31:0] wb_fifo_data; |
assign wb_fifo_data = { txf_status, rxf_status }; |
|
// You may recall from above that reads take two clocks. Hence, we |
// need to delay the address decoding for a clock until the data is |
// ready. We do that here. |
reg [1:0] r_wb_addr; |
always @(posedge i_clk) |
r_wb_addr <= i_wb_addr; |
|
// Likewise, the acknowledgement is delayed by one clock. |
reg r_wb_ack; |
always @(posedge i_clk) // We'll ACK in two clocks |
r_wb_ack <= i_wb_stb; |
always @(posedge i_clk) // Okay, time to set the ACK |
o_wb_ack <= r_wb_ack; |
|
// Finally, set the return data. This data must be valid on the same |
// clock o_wb_ack is high. On all other clocks, it is irrelelant--since |
// no one cares, no one is reading it, it gets lost in the mux in the |
// interconnect, etc. For this reason, we can just simplify our logic. |
always @(posedge i_clk) |
casez(r_wb_addr) |
`UART_SETUP: o_wb_data <= { 1'b0, uart_setup }; |
`UART_FIFO: o_wb_data <= wb_fifo_data; |
`UART_RXREG: o_wb_data <= wb_rx_data; |
`UART_TXREG: o_wb_data <= wb_tx_data; |
endcase |
|
// This device never stalls. Sure, it takes two clocks, but they are |
// pipelined, and nothing stalls that pipeline. (Creates FIFO errors, |
// perhaps, but doesn't stall the pipeline.) Hence, we can just |
// set this value to zero. |
assign o_wb_stall = 1'b0; |
|
endmodule |