URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
Compare Revisions
- This comparison shows the changes necessary to convert path
/opencpu32/trunk/hdl/opencpu32
- from Rev 10 to Rev 12
- ↔ Reverse comparison
Rev 10 → Rev 12
/_xmsgs/pn_parser.xmsgs
1,15 → 1,15
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/opencpu32/hdl/opencpu32/testMultiplexer2_1.vhd" into library work</arg> |
</msg> |
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</messages> |
|
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/opencpu32/hdl/opencpu32/testAlu.vhd" into library work</arg> |
</msg> |
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</messages> |
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/testAlu.vhd
30,16 → 30,16
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--Inputs |
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); |
signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); |
signal sel : aluOps := alu_sum; |
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component |
signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component |
signal sel : aluOps := alu_sum; --! Wire to connect Test signal to component |
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--Outputs |
signal S : std_logic_vector((nBits - 1) downto 0); |
signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component |
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BEGIN |
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-- Instantiate the Unit Under Test (UUT) |
--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!) |
uut: Alu PORT MAP ( |
A => A, |
B => B, |
/testMultiplexer2_1.vhd
29,16 → 29,16
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|
--Inputs |
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); |
signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); |
signal sel : std_logic := '0'; |
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component |
signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component |
signal sel : std_logic := '0'; --! Wire to connect Test signal to component |
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--Outputs |
signal S : std_logic_vector((nBits - 1) downto 0); |
signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component |
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BEGIN |
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-- Instantiate the Unit Under Test (UUT) |
--!Instantiate the Unit Under Test (Multiplexer2_1) (Doxygen bug if it's not commented!) |
uut: Multiplexer2_1 PORT MAP ( |
A => A, |
B => B, |