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URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk/hdl
    from Rev 14 to Rev 15
    ↔ Reverse comparison
  •

Rev 14 → Rev 15

/opencpu32/RegisterFile.vhd
53,7 → 53,7
readAProcess : process(Read_A_En,Read_A_Addr)
begin
if (Read_A_En = '1') then
A_Out <= regFile(CONV_INTEGER(reg2Num(writeAddr)));
A_Out <= regFile(CONV_INTEGER(reg2Num(Read_A_Addr)));
else
A_Out <= (others => 'Z');
end if;
63,7 → 63,7
readBProcess : process(Read_B_En,Read_B_Addr)
begin
if (Read_B_En = '1') then
B_Out <= regFile(CONV_INTEGER(reg2Num(writeAddr)));
B_Out <= regFile(CONV_INTEGER(reg2Num(Read_B_Addr)));
else
B_Out <= (others => 'Z');
end if;
/opencpu32/opencpu32.gise
135,6 → 135,7
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
152,7 → 153,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333131714" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333131714">
<transform xil_pn:end_ts="1333132181" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333132181">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
177,7 → 178,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333131714" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333131714">
<transform xil_pn:end_ts="1333132181" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333132181">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
190,19 → 191,23
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333131717" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6640613741745699976" xil_pn:start_ts="1333131714">
<transform xil_pn:end_ts="1333132183" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6640613741745699976" xil_pn:start_ts="1333132181">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testRegisterFile_beh.prj"/>
<outfile xil_pn:name="testRegisterFile_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333131717" xil_pn:in_ck="-8453111789177412509" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="2549364959294095189" xil_pn:start_ts="1333131717">
<transform xil_pn:end_ts="1333132183" xil_pn:in_ck="-8453111789177412509" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="2549364959294095189" xil_pn:start_ts="1333132183">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testRegisterFile_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178">
/opencpu32/testRegisterFile.vhd
67,6 → 67,7
 
--! Process that will stimulate all register assignments, and reads...
stim_proc: process
variable allZ : std_logic_vector((nBits - 1) downto 0) := (others => 'Z');
begin
-- r0=1 ... r15=16---------------------------------------------------------------------------
clk <= '0';
123,6 → 124,7
Read_A_Addr <= r0;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(1, nBits) report "Invalid value r0" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
REPORT "Check r1 = 2" SEVERITY NOTE;
Read_A_En <= '1';
129,6 → 131,7
Read_A_Addr <= r1;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(2, nBits) report "Invalid value r1" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
REPORT "Check r2 = 3" SEVERITY NOTE;
Read_A_En <= '1';
135,6 → 138,7
Read_A_Addr <= r2;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(3, nBits) report "Invalid value r2" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
REPORT "Check r3 = 4" SEVERITY NOTE;
Read_A_En <= '1';
141,6 → 145,7
Read_A_Addr <= r3;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(4, nBits) report "Invalid value r3" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
REPORT "Check r4 = 5" SEVERITY NOTE;
Read_A_En <= '1';
147,6 → 152,7
Read_A_Addr <= r4;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(5, nBits) report "Invalid value r4" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
 
wait;
end process;

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