OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk/hdl
    from Rev 15 to Rev 16
    ↔ Reverse comparison
  •

Rev 15 → Rev 16

/opencpu32/_xmsgs/pn_parser.xmsgs
1,15 → 1,15
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/testRegisterFile.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testAlu.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
/opencpu32/pkgOpenCPU32.vhd
17,7 → 17,7
--! Number of general registers (r0..r15)
constant numGenRegs : integer := 16;
 
type aluOps is (alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and, alu_xor, alu_not);
type aluOps is (alu_pass, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and, alu_xor, alu_not);
type typeEnDis is (enable, disable);
type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
 
72,7 → 72,8
when 12 => valRet := r12;
when 13 => valRet := r13;
when 14 => valRet := r14;
when 15 => valRet := r15;
when 15 => valRet := r15;
when others => valRet := r0;
end case;
return valRet;
end Num2reg;
/opencpu32/Alu.vhd
31,6 → 31,10
process (A,B,sel) is
begin
case sel is
when alu_pass =>
--Pass operation
S <= A;
when alu_sum =>
--Sum operation
S <= A + B;
/opencpu32/testAlu.vhd
50,8 → 50,16
--! Process that will stimulate all of the Alu operations
stim_proc: process
begin
-- AND ---------------------------------------------------------------------------
-- Pass ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Pass input A to output" SEVERITY NOTE;
sel <= alu_pass;
A <= conv_std_logic_vector(22, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (A ) report "Invalid Pass output" severity FAILURE;
-- AND ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "AND without carry 2(10) AND 3(11)" SEVERITY NOTE;
sel <= alu_and;
A <= conv_std_logic_vector(2, nBits);
/opencpu32/opencpu32.gise
136,11 → 136,11
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testAlu_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testAlu_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testRegisterFile_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testRegisterFile_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testTriStateBuffer_isim_beh.exe"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
149,11 → 149,11
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1333115998" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333115998">
<transform xil_pn:end_ts="1333148807" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333148807">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333132181" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333132181">
<transform xil_pn:end_ts="1333151023" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333151023">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
166,19 → 166,19
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333130729" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8486826367021142885" xil_pn:start_ts="1333130729">
<transform xil_pn:end_ts="1333151006" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-892635403352863368" xil_pn:start_ts="1333151006">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333130729" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3768155790739553443" xil_pn:start_ts="1333130729">
<transform xil_pn:end_ts="1333151006" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7876831410930882182" xil_pn:start_ts="1333151006">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333128697" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8786154546671769104" xil_pn:start_ts="1333128697">
<transform xil_pn:end_ts="1333148807" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8786154546671769104" xil_pn:start_ts="1333148807">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333132181" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333132181">
<transform xil_pn:end_ts="1333151023" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333151023">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
191,24 → 191,22
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333132183" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6640613741745699976" xil_pn:start_ts="1333132181">
<transform xil_pn:end_ts="1333151026" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3692595343167413970" xil_pn:start_ts="1333151023">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testRegisterFile_beh.prj"/>
<outfile xil_pn:name="testRegisterFile_isim_beh.exe"/>
<outfile xil_pn:name="testAlu_beh.prj"/>
<outfile xil_pn:name="testAlu_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333132183" xil_pn:in_ck="-8453111789177412509" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="2549364959294095189" xil_pn:start_ts="1333132183">
<transform xil_pn:end_ts="1333151026" xil_pn:in_ck="5430170344901993917" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5331297572704317690" xil_pn:start_ts="1333151026">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testRegisterFile_isim_beh.wdb"/>
<outfile xil_pn:name="testAlu_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
246,15 → 244,8
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="RegisterFile.lso"/>
<outfile xil_pn:name="RegisterFile.ngc"/>
<outfile xil_pn:name="RegisterFile.ngr"/>
<outfile xil_pn:name="RegisterFile.prj"/>
<outfile xil_pn:name="RegisterFile.stx"/>
<outfile xil_pn:name="RegisterFile.syr"/>
<outfile xil_pn:name="RegisterFile.xst"/>
<outfile xil_pn:name="RegisterFile_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
266,49 → 257,38
<transform xil_pn:end_ts="1333128291" xil_pn:in_ck="-3340831830900747050" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="1086960579647177373" xil_pn:start_ts="1333128286">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="RegisterFile.bld"/>
<outfile xil_pn:name="RegisterFile.ngd"/>
<outfile xil_pn:name="RegisterFile_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1333128296" xil_pn:in_ck="6653001400415059737" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1333128291">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="RegisterFile.pcf"/>
<outfile xil_pn:name="RegisterFile_map.map"/>
<outfile xil_pn:name="RegisterFile_map.mrp"/>
<outfile xil_pn:name="RegisterFile_map.ncd"/>
<outfile xil_pn:name="RegisterFile_map.ngm"/>
<outfile xil_pn:name="RegisterFile_map.xrpt"/>
<outfile xil_pn:name="RegisterFile_summary.xml"/>
<outfile xil_pn:name="RegisterFile_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1333128308" xil_pn:in_ck="-1729479595224311388" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1333128296">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="RegisterFile.ncd"/>
<outfile xil_pn:name="RegisterFile.pad"/>
<outfile xil_pn:name="RegisterFile.par"/>
<outfile xil_pn:name="RegisterFile.ptwx"/>
<outfile xil_pn:name="RegisterFile.unroutes"/>
<outfile xil_pn:name="RegisterFile.xpi"/>
<outfile xil_pn:name="RegisterFile_pad.csv"/>
<outfile xil_pn:name="RegisterFile_pad.txt"/>
<outfile xil_pn:name="RegisterFile_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1333128308" xil_pn:in_ck="-2814155899893271411" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1333128305">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="RegisterFile.twr"/>
<outfile xil_pn:name="RegisterFile.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
 
/opencpu32/testRegisterFile.vhd
38,9 → 38,9
signal writeEn : std_logic := '0'; --! Wire to connect Test signal to component
signal writeAddr : generalRegisters := r0; --! Wire to connect Test signal to component
signal input : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal Read_A_En : std_logic := '0'; --! Wire to connect Test signal to component
signal Read_A_En : std_logic := 'X'; --! Wire to connect Test signal to component
signal Read_A_Addr : generalRegisters := r0; --! Wire to connect Test signal to component
signal Read_B_En : std_logic := '0'; --! Wire to connect Test signal to component
signal Read_B_En : std_logic := 'X'; --! Wire to connect Test signal to component
signal Read_B_Addr : generalRegisters := r0; --! Wire to connect Test signal to component
 
--Outputs
69,91 → 69,48
stim_proc: process
variable allZ : std_logic_vector((nBits - 1) downto 0) := (others => 'Z');
begin
-- r0=1 ... r15=16---------------------------------------------------------------------------
clk <= '0';
REPORT "Write r0 := 1" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r0;
input <= conv_std_logic_vector(1, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
 
clk <= '0';
REPORT "Write r1 := 2" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r1;
input <= conv_std_logic_vector(2, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
clk <= '0';
REPORT "Write r2 := 3" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r2;
input <= conv_std_logic_vector(3, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
clk <= '0';
REPORT "Write r3 := 4" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r3;
input <= conv_std_logic_vector(4, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
clk <= '0';
REPORT "Write r4 := 5" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r4;
input <= conv_std_logic_vector(5, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
-- r0=1 ... r15=16---------------------------------------------------------------------------
for i in 0 to (numGenRegs-1) loop
clk <= '0';
REPORT "Write r0 := 1" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= Num2reg(i);
input <= conv_std_logic_vector(i+1, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
end loop;
-- Mark write end....
clk <= '0';
writeEn <= '0';
wait for 1 ns; -- Wait to stabilize the response
-- Read r0..r15 PortA-------------------------------------------------------------------------
REPORT "Check r0 = 1" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r0;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(1, nBits) report "Invalid value r0" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
REPORT "Check r1 = 2" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r1;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(2, nBits) report "Invalid value r1" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
REPORT "Check r2 = 3" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r2;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(3, nBits) report "Invalid value r2" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
REPORT "Check r3 = 4" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r3;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(4, nBits) report "Invalid value r3" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
REPORT "Check r4 = 5" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r4;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(5, nBits) report "Invalid value r4" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
 
-- Read r0..r15 PortA-------------------------------------------------------------------------
for i in 0 to (numGenRegs-1) loop
REPORT "Check r0 = 1" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= Num2reg(i);
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(i+1, nBits) report "Invalid value r0" severity FAILURE;
assert B_Out = allZ report "PortB should be high impedance" severity FAILURE;
end loop;
-- Mark read A end
Read_A_En <= 'X';
-- Read r0..r15 PortB-------------------------------------------------------------------------
for i in 0 to (numGenRegs-1) loop
REPORT "Check r0 = 1" SEVERITY NOTE;
Read_B_En <= '1';
Read_B_Addr <= Num2reg(i);
wait for 1 ns; -- Wait to stabilize the response
assert B_Out = conv_std_logic_vector(i+1, nBits) report "Invalid value r0" severity FAILURE;
assert A_Out = allZ report "PortB should be high impedance" severity FAILURE;
end loop;
-- Mark read B end
Read_B_En <= 'X';
wait;
end process;
 
/opencpu32/opencpu32.xise
20,7 → 20,7
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Multiplexer2_1.vhd" xil_pn:type="FILE_VHDL">
28,7 → 28,7
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
50,11 → 50,11
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/>
85,7 → 85,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
283,8 → 283,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testRegisterFile" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testRegisterFile" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
292,7 → 292,7
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="100 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="80 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
300,7 → 300,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testRegisterFile" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
350,7 → 350,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testRegisterFile|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testAlu|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

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