OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk/hdl
    from Rev 16 to Rev 17
    ↔ Reverse comparison
  •

Rev 16 → Rev 17

/opencpu32/opencpu32.xise
20,8 → 20,8
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="Multiplexer2_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
28,7 → 28,7
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
51,7 → 51,7
</file>
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
59,6 → 59,16
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="DataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="testDataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="137"/>
</file>
</files>
 
<properties>
164,9 → 174,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|RegisterFile|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="RegisterFile.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/RegisterFile" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Alu|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="Alu.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
224,7 → 234,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="RegisterFile" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="Alu" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
236,10 → 246,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="RegisterFile_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="RegisterFile_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="RegisterFile_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="RegisterFile_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Alu_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Alu_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Alu_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Alu_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
259,7 → 269,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="RegisterFile" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Alu" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
283,8 → 293,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
300,7 → 310,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
350,7 → 360,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testAlu|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testDataPath|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testAlu.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testDataPath.vhd&quot; into library work</arg>
</msg>
 
</messages>
/opencpu32/pkgOpenCPU32.vhd
17,7 → 17,8
--! Number of general registers (r0..r15)
constant numGenRegs : integer := 16;
 
type aluOps is (alu_pass, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and, alu_xor, alu_not);
type aluOps is (alu_pass, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and,
alu_xor, alu_not, alu_shfLt, alu_shfRt, alu_roLt, alu_roRt);
type typeEnDis is (enable, disable);
type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
 
/opencpu32/Alu.vhd
29,6 → 29,7
begin
--! Behavior description of combinational circuit (Can not infer any FF(Flip flop)) of the Alu
process (A,B,sel) is
variable mulResult : std_logic_vector(((nBits*2) - 1)downto 0);
begin
case sel is
when alu_pass =>
53,7 → 54,8
when alu_mul =>
--Multiplication operation
S <= A * B;
mulResult := A * B;
S <= mulResult((nBits - 1) downto 0);
when alu_and =>
--And operation
/opencpu32/testAlu.vhd
49,6 → 49,7
 
--! Process that will stimulate all of the Alu operations
stim_proc: process
variable mulResult : std_logic_vector(((nBits*2) - 1)downto 0);
begin
-- Pass ---------------------------------------------------------------------------
wait for 1 ps;
56,8 → 57,52
sel <= alu_pass;
A <= conv_std_logic_vector(22, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (A ) report "Invalid Pass output" severity FAILURE;
assert S = (A ) report "Invalid Pass output" severity FAILURE;
 
-- Sum ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Sum without carry 12 AND 13" SEVERITY NOTE;
sel <= alu_sum;
A <= conv_std_logic_vector(12, nBits);
B <= conv_std_logic_vector(13, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (A + B) report "Invalid Sum output" severity FAILURE;
 
-- Sub ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Sub without carry 34 AND 30" SEVERITY NOTE;
sel <= alu_sub;
A <= conv_std_logic_vector(34, nBits);
B <= conv_std_logic_vector(30, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (A - B) report "Invalid Sum Sub" severity FAILURE;
-- Inc ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Inc without carry 1" SEVERITY NOTE;
sel <= alu_inc;
A <= conv_std_logic_vector(1, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (A + 1) report "Invalid Sum Sub" severity FAILURE;
 
-- Dec ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Dec without carry 1" SEVERITY NOTE;
sel <= alu_dec;
A <= conv_std_logic_vector(1, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (A - 1) report "Invalid Sum Sub" severity FAILURE;
-- Mul ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Sub without carry 34 AND 30" SEVERITY NOTE;
sel <= alu_mul;
A <= conv_std_logic_vector(3, nBits);
B <= conv_std_logic_vector(5, nBits);
wait for 1 ns; -- Wait to stabilize the response
mulResult := (A * B);
assert S = (mulResult((nBits - 1) downto 0)) report "Invalid Sum Sub" severity FAILURE;
-- AND ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "AND without carry 2(10) AND 3(11)" SEVERITY NOTE;
/opencpu32/opencpu32.gise
42,6 → 42,7
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="Alu.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="Alu.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Alu.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Alu_envsettings.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="Alu_fpga_editor.log"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="Alu_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Alu_map.map" xil_pn:subbranch="Map"/>
153,99 → 154,106
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333151023" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333151023">
<transform xil_pn:end_ts="1333221390" xil_pn:in_ck="5896367260640228155" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333221390">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="RegisterFile.vhd"/>
<outfile xil_pn:name="TriStateBuffer.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testDataPath.vhd"/>
<outfile xil_pn:name="testMultiplexer2_1.vhd"/>
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333151006" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-892635403352863368" xil_pn:start_ts="1333151006">
<transform xil_pn:end_ts="1333221353" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3798934868497889219" xil_pn:start_ts="1333221353">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333151006" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7876831410930882182" xil_pn:start_ts="1333151006">
<transform xil_pn:end_ts="1333221353" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-6007724738129030273" xil_pn:start_ts="1333221353">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333148807" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8786154546671769104" xil_pn:start_ts="1333148807">
<transform xil_pn:end_ts="1333220845" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8637507079216041037" xil_pn:start_ts="1333220845">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333151023" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333151023">
<transform xil_pn:end_ts="1333221390" xil_pn:in_ck="5896367260640228155" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333221390">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="RegisterFile.vhd"/>
<outfile xil_pn:name="TriStateBuffer.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testDataPath.vhd"/>
<outfile xil_pn:name="testMultiplexer2_1.vhd"/>
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333151026" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3692595343167413970" xil_pn:start_ts="1333151023">
<status xil_pn:value="SuccessfullyRun"/>
<transform xil_pn:end_ts="1333221392" xil_pn:in_ck="5896367260640228155" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4679725895911349372" xil_pn:start_ts="1333221390">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_beh.prj"/>
<outfile xil_pn:name="testAlu_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333151026" xil_pn:in_ck="5430170344901993917" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5331297572704317690" xil_pn:start_ts="1333151026">
<status xil_pn:value="SuccessfullyRun"/>
<transform xil_pn:end_ts="1333153231" xil_pn:in_ck="5430170344901993917" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5331297572704317690" xil_pn:start_ts="1333153230">
<status xil_pn:value="AbortedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_isim_beh.wdb"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForced"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="2578846049644942698" xil_pn:start_ts="1333126879">
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7863675631946613945" xil_pn:start_ts="1333153349">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8786154546671769104" xil_pn:start_ts="1333126879">
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8637507079216041037" xil_pn:start_ts="1333153349">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333126879">
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333153349">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3693875251935617448" xil_pn:start_ts="1333126879">
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2964161847311656507" xil_pn:start_ts="1333153349">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333126879">
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333153349">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3979640367777479302" xil_pn:start_ts="1333126879">
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="319318766057190551" xil_pn:start_ts="1333153349">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333128266" xil_pn:in_ck="-7301577169810660065" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="4389747016737444173" xil_pn:start_ts="1333128258">
<transform xil_pn:end_ts="1333153355" xil_pn:in_ck="-7301577169810660065" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7168533952405101494" xil_pn:start_ts="1333153349">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.lso"/>
<outfile xil_pn:name="Alu.ngc"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="Alu.prj"/>
<outfile xil_pn:name="Alu.stx"/>
<outfile xil_pn:name="Alu.syr"/>
<outfile xil_pn:name="Alu.xst"/>
<outfile xil_pn:name="Alu_vhdl.prj"/>
<outfile xil_pn:name="Alu_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
253,43 → 261,8
<transform xil_pn:end_ts="1333128286" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3437821219266902819" xil_pn:start_ts="1333128286">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1333128291" xil_pn:in_ck="-3340831830900747050" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="1086960579647177373" xil_pn:start_ts="1333128286">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1333128296" xil_pn:in_ck="6653001400415059737" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1333128291">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1333128308" xil_pn:in_ck="-1729479595224311388" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1333128296">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1333128308" xil_pn:in_ck="-2814155899893271411" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1333128305">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
 
</generated_project>
/opencpu32/DataPath.vhd
0,0 → 1,44
--! @file
--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
 
--! A datapath is a collection of functional units, such as arithmetic logic units or multipliers, that perform data processing operations.\n
--! Most central processing units consist of a datapath and a control unit, with a large part of the control unit dedicated to
--! regulating the interaction between the datapath and main memory.
 
--! The purpose of datapaths is to provide routes for data to travel between functional units.
entity DataPath is
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory
inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
clk : in STD_LOGIC; --! Clock signal
outEn : in typeEnDis; --! Enable/Disable datapath output
aluOp : in aluOps; --! Alu operations
muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
regFileWriteAddr : in generalRegisters; --! General register write address
regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
dpFlags : out STD_LOGIC_VECTOR (n downto 0)); --! Alu Flags
end DataPath;
 
--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
--! @details This description will also show how to instantiate components(Alu, RegisterFile, Multiplexer) on your design
architecture Behavioral of DataPath is
 
begin
 
 
end Behavioral;
 
/opencpu32/testDataPath.vhd
0,0 → 1,90
--! @file
--! @brief Testbench for Alu
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
ENTITY testDataPath IS
END testDataPath;
--! @brief Alu Testbench file
--! @details Exercise each Alu operation to verify if the description work as planned
--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
ARCHITECTURE behavior OF testDataPath IS
--! Component declaration to instantiate the Alu circuit
COMPONENT DataPath
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( inputMm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from main memory
inputImm : in STD_LOGIC_VECTOR (n downto 0); --! Input of Datapath from imediate value (instructions...)
clk : in STD_LOGIC; --! Clock signal
outEn : in typeEnDis; --! Enable/Disable datapath output
aluOp : in aluOps; --! Alu operations
muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
regFileWriteAddr : in generalRegisters; --! General register write address
regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
regFileReadAddrA : in generalRegisters; --! General register read address (PortA)
regFileReadAddrB : in generalRegisters; --! General register read address (PortB)
regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
dpFlags : out STD_LOGIC_VECTOR (n downto 0)); --! Alu Flags
END COMPONENT;
 
--Inputs
signal inputMm : std_logic_vector(31 downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal inputImm : std_logic_vector(31 downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal clk : std_logic := '0'; --! Wire to connect Test signal to component
signal outEn : std_logic := '0'; --! Wire to connect Test signal to component
signal aluOp : std_logic := '0'; --! Wire to connect Test signal to component
signal muxSel : std_logic_vector(2 downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal regFileWriteAddr : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileWriteEn : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileReadAddrA : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileReadAddrB : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileEnB : std_logic := '0'; --! Wire to connect Test signal to component
 
--Outputs
signal outputDp : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
signal dpFlags : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
BEGIN
--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
uut: DataPath PORT MAP (
inputMm => inputMm,
inputImm => inputImm,
clk => clk,
outEn => outEn,
aluOp => aluOp,
muxSel => muxSel,
regFileWriteAddr => regFileWriteAddr,
regFileWriteEn => regFileWriteEn,
regFileReadAddrA => regFileReadAddrA,
regFileReadAddrB => regFileReadAddrB,
regFileEnA => regFileEnA,
regFileEnB => regFileEnB,
outputDp => outputDp,
dpFlags => dpFlags
);
-- Stimulus process
stim_proc: process
begin
 
-- insert stimulus here
 
wait;
end process;
 
END;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.