OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk/hdl
    from Rev 18 to Rev 19
    ↔ Reverse comparison
  •

Rev 18 → Rev 19

/opencpu32/opencpu32.xise
20,11 → 20,11
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
31,7 → 31,7
</file>
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testTriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
41,7 → 41,7
</file>
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
51,7 → 51,7
</file>
<file xil_pn:name="DataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testDataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
60,11 → 60,11
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="Multiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testMultiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="138"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="138"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="138"/>
174,9 → 174,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Alu|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="Alu.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DataPath|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="DataPath.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
234,7 → 234,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="Alu" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="DataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
246,10 → 246,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Alu_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Alu_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Alu_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Alu_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="DataPath_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="DataPath_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="DataPath_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="DataPath_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
269,7 → 269,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Alu" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="DataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
293,8 → 293,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
310,7 → 310,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
360,7 → 360,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testAlu|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testMultiplexer4_1|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/opencpu32/Multiplexer4_1.vhd
18,7 → 18,8
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
sel : in STD_LOGIC_VECTOR (1 downto 0); --! Select inputs (1, 2, 3, 4)
E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
end Multiplexer4_1;
 
28,10 → 29,11
 
begin
with sel select
S <= A when "00",
B when "01",
C when "10",
D when "11",
S <= A when "000",
B when "001",
C when "010",
D when "011",
E when "100",
(others => 'Z') when others;
 
end Behavioral;
/opencpu32/testMultiplexer4_1.vhd
20,12 → 20,13
--! Component declaration to instantiate the Multiplexer circuit
COMPONENT Multiplexer4_1
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
sel : in STD_LOGIC_VECTOR (1 downto 0); --! Select inputs (1, 2, 3, 4)
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
END COMPONENT;
34,8 → 35,9
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal C : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal D : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal sel : STD_LOGIC_VECTOR (1 downto 0) := "00"; --! Wire to connect Test signal to component
signal D : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal E : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal sel : STD_LOGIC_VECTOR (2 downto 0) := "000"; --! Wire to connect Test signal to component
 
--Outputs
signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
47,7 → 49,8
A => A,
B => B,
C => C,
D => D,
D => D,
E => E,
sel => sel,
S => S
);
58,11 → 61,12
-- Sel 0 ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Select first channel" SEVERITY NOTE;
sel <= "00";
sel <= "000";
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
D <= conv_std_logic_vector(3000, nBits);
D <= conv_std_logic_vector(3000, nBits);
E <= conv_std_logic_vector(4000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (A) report "Could not select first channel" severity FAILURE;
69,35 → 73,50
-- Sel 1 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select second channel" SEVERITY NOTE;
sel <= "01";
sel <= "001";
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
D <= conv_std_logic_vector(3000, nBits);
D <= conv_std_logic_vector(3000, nBits);
E <= conv_std_logic_vector(4000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (B) report "Could not select second channel" severity FAILURE;
-- Sel 2 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select second channel" SEVERITY NOTE;
sel <= "10";
REPORT "Select third channel" SEVERITY NOTE;
sel <= "010";
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
D <= conv_std_logic_vector(3000, nBits);
D <= conv_std_logic_vector(3000, nBits);
E <= conv_std_logic_vector(4000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (C) report "Could not select second channel" severity FAILURE;
assert S = (C) report "Could not select third channel" severity FAILURE;
-- Sel 3 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select second channel" SEVERITY NOTE;
sel <= "11";
REPORT "Select forth channel" SEVERITY NOTE;
sel <= "011";
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
D <= conv_std_logic_vector(3000, nBits);
D <= conv_std_logic_vector(3000, nBits);
E <= conv_std_logic_vector(4000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (D) report "Could not select second channel" severity FAILURE;
assert S = (D) report "Could not select forth channel" severity FAILURE;
-- Sel 4 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select fifth channel" SEVERITY NOTE;
sel <= "100";
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
D <= conv_std_logic_vector(3000, nBits);
E <= conv_std_logic_vector(4000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (E) report "Could not select fifth channel" severity FAILURE;
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testMultiplexer4_1.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/DataPath.vhd&quot; into library work</arg>
</msg>
 
</messages>
/opencpu32/opencpu32.gise
60,6 → 60,18
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="Alu_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Alu_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="DataPath.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="DataPath.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="DataPath.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="DataPath.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="DataPath.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="DataPath.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="DataPath.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="DataPath.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="DataPath_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="DataPath_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="DataPath_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="DataPath_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="Multiplexer2_1.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Multiplexer2_1.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Multiplexer2_1.lso"/>
137,11 → 149,11
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testAlu_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testAlu_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testMultiplexer4_1_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer4_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testMultiplexer4_1_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testRegisterFile_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testRegisterFile_isim_beh.wdb"/>
157,9 → 169,13
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333269930" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333269930">
<transform xil_pn:end_ts="1333271356" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333271356">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer4_1.vhd"/>
172,21 → 188,26
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333269950" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-892635403352863368" xil_pn:start_ts="1333269950">
<transform xil_pn:end_ts="1333270410" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="5935414570389784949" xil_pn:start_ts="1333270410">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333269950" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7876831410930882182" xil_pn:start_ts="1333269950">
<transform xil_pn:end_ts="1333270410" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="8016344969543873207" xil_pn:start_ts="1333270410">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333220845" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8637507079216041037" xil_pn:start_ts="1333220845">
<transform xil_pn:end_ts="1333270410" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333270410">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333269930" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333269930">
<transform xil_pn:end_ts="1333271356" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333271356">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer4_1.vhd"/>
199,61 → 220,80
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333269952" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3692595343167413970" xil_pn:start_ts="1333269950">
<transform xil_pn:end_ts="1333271359" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8349402396315676588" xil_pn:start_ts="1333271356">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_beh.prj"/>
<outfile xil_pn:name="testAlu_isim_beh.exe"/>
<outfile xil_pn:name="testMultiplexer4_1_beh.prj"/>
<outfile xil_pn:name="testMultiplexer4_1_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333269953" xil_pn:in_ck="2214679574356920708" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-5331297572704317690" xil_pn:start_ts="1333269952">
<transform xil_pn:end_ts="1333271359" xil_pn:in_ck="2214679574356920708" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="798418853635144160" xil_pn:start_ts="1333271359">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_isim_beh.wdb"/>
<outfile xil_pn:name="testMultiplexer4_1_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7863675631946613945" xil_pn:start_ts="1333153349">
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1242172528803053708" xil_pn:start_ts="1333272481">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8637507079216041037" xil_pn:start_ts="1333153349">
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333272481">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333153349">
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333272481">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2964161847311656507" xil_pn:start_ts="1333153349">
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5860233878951780918" xil_pn:start_ts="1333272481">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333153349">
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333272481">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333153349" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="319318766057190551" xil_pn:start_ts="1333153349">
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-154095565103849252" xil_pn:start_ts="1333272481">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333153355" xil_pn:in_ck="-7301577169810660065" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7168533952405101494" xil_pn:start_ts="1333153349">
<transform xil_pn:end_ts="1333272489" xil_pn:in_ck="-7607935566670155944" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="924943614754068847" xil_pn:start_ts="1333272481">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="DataPath.lso"/>
<outfile xil_pn:name="DataPath.ngc"/>
<outfile xil_pn:name="DataPath.ngr"/>
<outfile xil_pn:name="DataPath.prj"/>
<outfile xil_pn:name="DataPath.stx"/>
<outfile xil_pn:name="DataPath.syr"/>
<outfile xil_pn:name="DataPath.xst"/>
<outfile xil_pn:name="DataPath_vhdl.prj"/>
<outfile xil_pn:name="DataPath_xst.xrpt"/>
<outfile xil_pn:name="RegisterFile.ngr"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1333128286" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3437821219266902819" xil_pn:start_ts="1333128286">
<status xil_pn:value="SuccessfullyRun"/>
/opencpu32/DataPath.vhd
37,8 → 37,96
--! @details This description will also show how to instantiate components(Alu, RegisterFile, Multiplexer) on your design
architecture Behavioral of DataPath is
 
--! Component declaration to instantiate the Multiplexer circuit
COMPONENT Multiplexer4_1
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
END COMPONENT;
 
--! Component declaration to instantiate the Alu circuit
COMPONENT Alu
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
sel : in aluOps); --! Select operation
END COMPONENT;
 
--! Component declaration to instantiate the testRegisterFile circuit
COMPONENT RegisterFile
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the registers)
Port ( clk : in STD_LOGIC; --! Clock signal
writeEn : in STD_LOGIC; --! Write enable
writeAddr : in generalRegisters; --! Write Adress
input : in STD_LOGIC_VECTOR (n downto 0); --! Input
Read_A_En : in STD_LOGIC; --! Enable read A
Read_A_Addr : in generalRegisters; --! Read A adress
Read_B_En : in STD_LOGIC; --! Enable read A
Read_B_Addr : in generalRegisters; --! Read B adress
A_Out : out STD_LOGIC_VECTOR (n downto 0); --! Output A
B_Out : out STD_LOGIC_VECTOR (n downto 0)); --! Output B
END COMPONENT;
 
COMPONENT TriStateBuffer
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
PORT(
A : IN std_logic_vector(n downto 0); --! Buffer Input
sel : IN typeEnDis; --! Enable or Disable the output
S : OUT std_logic_vector(n downto 0) --! Enable or Disable the output
);
END COMPONENT;
 
-- Signals that will connect the various components from the DataPath
signal regFilePortA : STD_LOGIC_VECTOR (n downto 0);
signal regFilePortB : STD_LOGIC_VECTOR (n downto 0);
signal aluOut : STD_LOGIC_VECTOR (n downto 0);
signal muxOut : STD_LOGIC_VECTOR (n downto 0);
begin
--! Instantiate Multiplexer
uMux: Multiplexer4_1 PORT MAP (
A => inputMm,
B => inputImm,
C => regFilePortA,
D => regFilePortB,
E => aluOut,
sel => muxSel,
S => muxOut
);
--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
uAlu: Alu PORT MAP (
A => muxOut,
B => regFilePortA,
S => aluOut,
sel => aluOp
);
--! Instantiate the Unit Under Test (RegisterFile) (Doxygen bug if it's not commented!)
uRegisterFile: RegisterFile PORT MAP (
clk => clk,
writeEn => regFileWriteEn,
writeAddr => regFileWriteAddr,
input => muxOut,
Read_A_En => regFileEnA,
Read_A_Addr => regFileReadAddrA,
Read_B_En => regFileEnB,
Read_B_Addr => regFileReadAddrB,
A_Out => regFilePortA,
B_Out => regFilePortB
);
--!Instantiate the Unit Under Test (Multiplexer2_1) (Doxygen bug if it's not commented!)
uTriState: TriStateBuffer PORT MAP (
A => muxOut,
sel => outEn,
S => outputDp
);
 
 
end Behavioral;
 

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