OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk/hdl
    from Rev 19 to Rev 20
    ↔ Reverse comparison
  •

Rev 19 → Rev 20

/opencpu32/opencpu32.xise
20,7 → 20,7
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
30,7 → 30,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testTriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
40,7 → 40,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL">
50,25 → 50,28
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="DataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testDataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="Multiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testMultiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="138"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="138"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="DataPath.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
 
<properties>
302,7 → 305,7
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="80 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="200 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
360,7 → 363,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testMultiplexer4_1|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testDataPath|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
375,7 → 378,9
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
<bindings>
<binding xil_pn:location="/DataPath" xil_pn:name="DataPath.ucf"/>
</bindings>
 
<libraries/>
 
/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/DataPath.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testDataPath.vhd&quot; into library work</arg>
</msg>
 
</messages>
/opencpu32/pkgOpenCPU32.vhd
17,13 → 17,15
--! Number of general registers (r0..r15)
constant numGenRegs : integer := 16;
 
type aluOps is (alu_pass, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and,
type aluOps is (alu_pass, alu_passB, alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and,
alu_xor, alu_not, alu_shfLt, alu_shfRt, alu_roLt, alu_roRt);
type typeEnDis is (enable, disable);
type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
type dpMuxInputs is (fromMemory, fromImediate, fromRegFileA, fromRegFileB, fromAlu);
 
function reg2Num (a: generalRegisters) return integer;
function Num2reg (a: integer) return generalRegisters;
function muxPos( a: dpMuxInputs) return std_logic_vector;
 
end pkgOpenCPU32;
 
30,6 → 32,19
--! Define functions or procedures
package body pkgOpenCPU32 is
 
function muxPos( a: dpMuxInputs) return std_logic_vector is
variable valRet : std_logic_vector(2 downto 0);
begin
case a is
when fromMemory => valRet := "000";
when fromImediate => valRet := "001";
when fromRegFileA => valRet := "010";
when fromRegFileB => valRet := "011";
when fromAlu => valRet := "100";
end case;
return valRet;
end muxPos;
 
function reg2Num (a: generalRegisters) return integer is
variable valRet : integer;
begin
/opencpu32/Alu.vhd
36,6 → 36,10
--Pass operation
S <= A;
when alu_passB =>
--Pass operation
S <= B;
when alu_sum =>
--Sum operation
S <= A + B;
/opencpu32/opencpu32.gise
45,6 → 45,7
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Alu_envsettings.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="Alu_fpga_editor.log"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="Alu_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Alu_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Alu_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Alu_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Alu_map.ncd" xil_pn:subbranch="Map"/>
60,16 → 61,41
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="Alu_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Alu_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="DataPath.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="DataPath.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="DataPath.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="DataPath.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="DataPath.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="DataPath.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="DataPath.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="DataPath.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="DataPath.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="DataPath.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="DataPath.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="DataPath.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="DataPath.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="DataPath.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="DataPath.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="DataPath.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="DataPath.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="DataPath.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="DataPath.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="DataPath_envsettings.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="DataPath_fpga_editor.log"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="DataPath_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="DataPath_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="DataPath_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="DataPath_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="DataPath_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="DataPath_map.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="DataPath_map_fpga_editor.log"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="DataPath_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="DataPath_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="DataPath_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="DataPath_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="DataPath_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="DataPath_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="DataPath_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="DataPath_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="DataPath_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="Multiplexer2_1.bld"/>
99,6 → 125,7
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Multiplexer2_1_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Multiplexer2_1_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Multiplexer2_1_xst.xrpt"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Multiplexer4_1_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="RegisterFile.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="RegisterFile.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="RegisterFile.lso"/>
149,11 → 176,13
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testDataPath_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDataPath_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testDataPath_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testMultiplexer4_1_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer4_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testMultiplexer4_1_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testRegisterFile_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testRegisterFile_isim_beh.wdb"/>
165,17 → 194,13
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1333148807" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333148807">
<transform xil_pn:end_ts="1333309985" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333309985">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333271356" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333271356">
<transform xil_pn:end_ts="1333312118" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333312118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer4_1.vhd"/>
188,26 → 213,21
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333270410" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="5935414570389784949" xil_pn:start_ts="1333270410">
<transform xil_pn:end_ts="1333309985" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3798934868497889219" xil_pn:start_ts="1333309985">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333270410" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="8016344969543873207" xil_pn:start_ts="1333270410">
<transform xil_pn:end_ts="1333309985" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-6007724738129030273" xil_pn:start_ts="1333309985">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333270410" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333270410">
<transform xil_pn:end_ts="1333309985" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333309985">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333271356" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333271356">
<transform xil_pn:end_ts="1333312118" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333312118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="DataPath.vhd"/>
<outfile xil_pn:name="Multiplexer4_1.vhd"/>
220,62 → 240,52
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333271359" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8349402396315676588" xil_pn:start_ts="1333271356">
<transform xil_pn:end_ts="1333312121" xil_pn:in_ck="2444604816064773119" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4679725895911349372" xil_pn:start_ts="1333312118">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testMultiplexer4_1_beh.prj"/>
<outfile xil_pn:name="testMultiplexer4_1_isim_beh.exe"/>
<outfile xil_pn:name="testDataPath_beh.prj"/>
<outfile xil_pn:name="testDataPath_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333271359" xil_pn:in_ck="2214679574356920708" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="798418853635144160" xil_pn:start_ts="1333271359">
<transform xil_pn:end_ts="1333312121" xil_pn:in_ck="1382727828177144057" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6046575149236642790" xil_pn:start_ts="1333312121">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testMultiplexer4_1_isim_beh.wdb"/>
<outfile xil_pn:name="testDataPath_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178">
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1242172528803053708" xil_pn:start_ts="1333272481">
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1242172528803053708" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333272481">
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333272481">
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5860233878951780918" xil_pn:start_ts="1333272481">
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5860233878951780918" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333272481">
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333272481" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-154095565103849252" xil_pn:start_ts="1333272481">
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-154095565103849252" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333272489" xil_pn:in_ck="-7607935566670155944" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="924943614754068847" xil_pn:start_ts="1333272481">
<transform xil_pn:end_ts="1333309891" xil_pn:in_ck="-7607935566670155944" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="924943614754068847" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
295,10 → 305,9
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1333128286" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3437821219266902819" xil_pn:start_ts="1333128286">
<transform xil_pn:end_ts="1333275886" xil_pn:in_ck="3590950097743327443" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="2103587220659863231" xil_pn:start_ts="1333275886">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
</transforms>
 
/opencpu32/DataPath.vhd
101,8 → 101,8
--! Instantiate the Unit Under Test (Alu) (Doxygen bug if it's not commented!)
uAlu: Alu PORT MAP (
A => muxOut,
B => regFilePortA,
A => regFilePortA,
B => regFilePortB,
S => aluOut,
sel => aluOp
);
/opencpu32/testDataPath.vhd
1,5 → 1,5
--! @file
--! @brief Testbench for Alu
--! @brief Testbench for Datapath
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
13,8 → 13,8
ENTITY testDataPath IS
END testDataPath;
--! @brief Alu Testbench file
--! @details Exercise each Alu operation to verify if the description work as planned
--! @brief Datapath Testbench file
--! @details Attention to this testbench because it will give you hints on how the control circuit must work....
--! for more information: http://vhdlguru.blogspot.com/2010/03/how-to-write-testbench.html
ARCHITECTURE behavior OF testDataPath IS
39,16 → 39,16
 
--Inputs
signal inputMm : std_logic_vector(31 downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal inputImm : std_logic_vector(31 downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal inputMm : std_logic_vector(31 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
signal inputImm : std_logic_vector(31 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
signal clk : std_logic := '0'; --! Wire to connect Test signal to component
signal outEn : std_logic := '0'; --! Wire to connect Test signal to component
signal aluOp : std_logic := '0'; --! Wire to connect Test signal to component
signal muxSel : std_logic_vector(2 downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal regFileWriteAddr : std_logic := '0'; --! Wire to connect Test signal to component
signal outEn : typeEnDis := disable; --! Wire to connect Test signal to component
signal aluOp : aluOps := alu_pass; --! Wire to connect Test signal to component
signal muxSel : std_logic_vector(2 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
signal regFileWriteAddr : generalRegisters := r0; --! Wire to connect Test signal to component
signal regFileWriteEn : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileReadAddrA : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileReadAddrB : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileReadAddrA : generalRegisters := r0; --! Wire to connect Test signal to component
signal regFileReadAddrB : generalRegisters := r0; --! Wire to connect Test signal to component
signal regFileEnA : std_logic := '0'; --! Wire to connect Test signal to component
signal regFileEnB : std_logic := '0'; --! Wire to connect Test signal to component
 
56,6 → 56,8
signal outputDp : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
signal dpFlags : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
76,15 → 78,115
outputDp => outputDp,
dpFlags => dpFlags
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- MOV r0,10d ---------------------------------------------------------------------------------
REPORT "MOV r0,10" SEVERITY NOTE;
inputImm <= conv_std_logic_vector(10, nBits);
regFileWriteAddr <= r0;
aluOp <= alu_pass;
muxSel <= muxPos(fromImediate);
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
-- Read value in r0 to verify if is equal to 20
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileA);
regFileReadAddrA <= r0; -- Read data from r0 and verify if it's 10
regFileEnA <= '1';
outEn <= enable;
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
regFileEnA <= '0';
outEn <= disable;
-- MOV r1,20d ---------------------------------------------------------------------------------
REPORT "MOV r1,20" SEVERITY NOTE;
inputImm <= conv_std_logic_vector(20, nBits);
regFileWriteAddr <= r1;
aluOp <= alu_pass;
muxSel <= muxPos(fromImediate);
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
-- Read value in r1 to verify if is equal to 20
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileA);
regFileReadAddrA <= r1; -- Read data from r0 and verify if it's 10
regFileEnA <= '1';
outEn <= enable;
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
regFileEnA <= '0';
outEn <= disable;
-- MOV r2,r1 (r2 <= r1) --------------------------------------------------------------------
REPORT "MOV r2,r1" SEVERITY NOTE;
regFileReadAddrB <= r1; -- Read data from r1
regFileEnB <= '1';
regFileWriteAddr <= r2; -- Write data in r2
muxSel <= muxPos(fromRegFileB); -- Select the PortB output from regFile
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to write into r2
-- Read value in r2 to verify if is equal to r1(20)
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileA);
regFileReadAddrA <= r2; -- Read data from r0 and verify if it's 10
regFileEnA <= '1';
outEn <= enable;
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
regFileEnA <= '0';
outEn <= disable;
-- ADD r2,r0 (r2 <= r2+r0)
REPORT "ADD r2,r0" SEVERITY NOTE;
regFileReadAddrA <= r2; -- Read data from r2
regFileEnA <= '1';
regFileReadAddrB <= r0; -- Read data from r0
regFileEnB <= '1';
aluOp <= alu_sum;
regFileWriteAddr <= r2; -- Write data in r2
muxSel <= muxPos(fromAlu); -- Select the Alu output
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to write into r2
-- Read value in r2 to verify if is equal to 30(10+20)
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileB); -- Must access from other Port otherwise you will need an extra cycle to change it's address
regFileReadAddrB <= r2; -- Read data from r0 and verify if it's 10
regFileEnB <= '1';
outEn <= enable;
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(30, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
regFileEnA <= '0';
outEn <= disable;
 
-- insert stimulus here
 
wait;
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
wait;
end process;
 
END;

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