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URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk/hdl
    from Rev 28 to Rev 29
    ↔ Reverse comparison
  •

Rev 28 → Rev 29

/opencpu32/opencpu32.xise
20,17 → 20,17
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testTriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
40,7 → 40,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL">
50,17 → 50,17
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="DataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="testDataPath.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="137"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="Multiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testMultiplexer4_1.vhd" xil_pn:type="FILE_VHDL">
80,7 → 80,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="Multiplexer3_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
</files>
307,8 → 307,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
324,7 → 324,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testDataPath" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
374,7 → 374,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testAlu|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testDataPath|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/opencpu32/ControlUnit.vhd
75,12 → 75,16
end if;
end process;
-- States Fetch, decode, execute from the processor
-- States Fetch, decode, execute from the processor (Also handles the execution of jump instructions)
process (currentCpuState)
variable cyclesExecute : integer range 0 to 20; -- Cycles to wait while executing instruction
variable opcodeIR : std_logic_vector(5 downto 0);
variable opcodeIR : std_logic_vector(5 downto 0);
variable operand_reg1 : std_logic_vector(3 downto 0);
variable operand_imm : std_logic_vector(21 downto 0);
begin
opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5));
opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5));
operand_reg1 := IR((IR'HIGH - 6) downto (IR'HIGH - 9)); -- 4 bits register operand1 (Max 16 registers)
operand_imm := IR((IR'HIGH - 10) downto (IR'LOW)); -- 22 bits imediate value (Max value 4194304)
case currentCpuState is
-- Initial state left from reset ...
when initial =>
113,12 → 117,28
nextCpuState <= execute;
cyclesExecute := 3; -- Wait 3 cycles for mov operation
currInstruction <= IR;
when jmp_val | jmpr_val =>
nextCpuState <= execute;
cyclesExecute := 1;
-- Invalid instruction (Now will be ignored, but latter should raise a trap
when others =>
when others =>
null;
end case;
-- Wait while the process that handles the execution works..
when execute =>
-- On the case of jump instructions, it's execution will be handled on this process
case opcodeIR is
when jmp_val =>
PC <= "0000000000" & operand_imm;
when jmpr_val =>
PC <= PC + ("0000000000" & operand_imm);
when others =>
null;
end case;
if cyclesExecute = 0 then
-- Finish the instruction execution get next
nextCpuState <= fetch;
136,7 → 156,7
end case;
end process;
-- Process that handles the execution of each instruction
-- Process that handles the execution of each instruction (Excluding the call and jump instructions)
process (currentExState)
--variable operando1_reg : std_logic_vector(generalRegisters'range);
variable opcodeIR : std_logic_vector(5 downto 0);
/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testAlu.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testDataPath.vhd&quot; into library work</arg>
</msg>
 
</messages>
/opencpu32/pkgOpenCPU32.vhd
30,7 → 30,6
type executionStates is (initInstructionExecution, writeRegister, releaseWriteRead, s3, s4);
 
--! Flags positions
-- Posicoes em bits dos flags (8 bits)
constant flag_sign : integer := 2;
constant flag_zero : integer := 1;
constant flag_carry : integer := 0;
96,8 → 95,8
constant dec_reg : opcodes := conv_std_logic_vector(32,6); -- Decrement register
 
-- Control opcodes
constant nop : opcodes := conv_std_logic_vector(31,6); -- Nop...
constant halt : opcodes := conv_std_logic_vector(32,6); -- Halt processor
constant nop : opcodes := conv_std_logic_vector(33,6); -- Nop...
constant halt : opcodes := conv_std_logic_vector(34,6); -- Halt processor
 
end pkgOpenCPU32;
 
/opencpu32/opencpu32.gise
184,14 → 184,18
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testAlu_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testControlUnit_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testControlUnit_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testControlUnit_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testDataPath_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDataPath_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testDataPath_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer4_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
209,7 → 213,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333907765" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333907765">
<transform xil_pn:end_ts="1333912779" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333912779">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
227,11 → 231,11
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333906140" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-892635403352863368" xil_pn:start_ts="1333906140">
<transform xil_pn:end_ts="1333912779" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3798934868497889219" xil_pn:start_ts="1333912779">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333906140" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7876831410930882182" xil_pn:start_ts="1333906140">
<transform xil_pn:end_ts="1333912779" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-6007724738129030273" xil_pn:start_ts="1333912779">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
239,7 → 243,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333907765" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333907765">
<transform xil_pn:end_ts="1333912779" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333912779">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
257,52 → 261,55
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333907768" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3692595343167413970" xil_pn:start_ts="1333907765">
<status xil_pn:value="FailedRun"/>
<transform xil_pn:end_ts="1333912784" xil_pn:in_ck="300726481020074607" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4679725895911349372" xil_pn:start_ts="1333912779">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testDataPath_beh.prj"/>
<outfile xil_pn:name="testDataPath_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333906575" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8428607755353741456" xil_pn:start_ts="1333906574">
<status xil_pn:value="AbortedRun"/>
<transform xil_pn:end_ts="1333912784" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-6046575149236642790" xil_pn:start_ts="1333912784">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForced"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="testAlu_isim_beh.wdb"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testDataPath_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1333309884" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1333309884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1242172528803053708" xil_pn:start_ts="1333904187">
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1242172528803053708" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333904187">
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8650728850620515758" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333904187">
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5860233878951780918" xil_pn:start_ts="1333904187">
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-5860233878951780918" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333904187">
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333904187" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-154095565103849252" xil_pn:start_ts="1333904187">
<transform xil_pn:end_ts="1333912739" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-154095565103849252" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333905707" xil_pn:in_ck="-296793447880885961" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="924943614754068847" xil_pn:start_ts="1333905699">
<transform xil_pn:end_ts="1333912747" xil_pn:in_ck="-296793447880885961" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="924943614754068847" xil_pn:start_ts="1333912739">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="DataPath.lso"/>
/opencpu32/testDataPath.vhd
35,7 → 35,7
regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
dpFlags : out STD_LOGIC_VECTOR (n downto 0)); --! Alu Flags
dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
END COMPONENT;
 
56,7 → 56,7
 
--Outputs
signal outputDp : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
signal dpFlags : std_logic_vector(31 downto 0); --! Wire to connect Test signal to component
signal dpFlags : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
-- Clock period definitions
constant CLK_period : time := 10 ns;
/opencpu32/DataPath.vhd
31,7 → 31,7
regFileEnA : in STD_LOGIC; --! Enable RegisterFile PortA
regFileEnB : in STD_LOGIC; --! Enable RegisterFile PortB
outputDp : out STD_LOGIC_VECTOR (n downto 0); --! DataPath Output
dpFlags : out STD_LOGIC_VECTOR (n downto 0)); --! Alu Flags
dpFlags : out STD_LOGIC_VECTOR (2 downto 0)); --! Alu Flags
end DataPath;
 
--! @brief DataPath http://en.wikipedia.org/wiki/Datapath
62,11 → 62,12
 
--! Component declaration to instantiate the Alu circuit
COMPONENT Alu
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
sel : in aluOps); --! Select operation
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2
S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output
flagsOut : out STD_LOGIC_VECTOR(2 downto 0); --! Flags from current operation
sel : in aluOps); --! Select operation
END COMPONENT;
 
--! Component declaration to instantiate the testRegisterFile circuit
125,6 → 126,7
A => muxOutReg,
B => regFilePortB,
S => aluOut,
flagsOut => dpFlags,
sel => aluOp
);

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