OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk
    from Rev 9 to Rev 10
    ↔ Reverse comparison
  •

Rev 9 → Rev 10

/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testAlu.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testMultiplexer2_1.vhd&quot; into library work</arg>
</msg>
 
</messages>
/hdl/opencpu32/Alu.vhd
23,7 → 23,7
 
--! @brief Arithmetic logic unit, refer to this page for more information http://en.wikipedia.org/wiki/Arithmetic_logic_unit
--! @details This circuit will be excited by the control unit to perfom some arithimetic, or logic operation (Depending on the opcode selected)
--! You can see some samples on the Internet: http://www.vlsibank.com/sessionspage.asp?titl_id=12222
--! \n You can see some samples on the Internet: http://www.vlsibank.com/sessionspage.asp?titl_id=12222
architecture Behavioral of Alu is
 
begin
/hdl/opencpu32/opencpu32.gise
22,6 → 22,7
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="opencpu32.xise"/>
 
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name=".lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="Alu.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Alu.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Alu.lso"/>
58,6 → 59,17
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="Alu_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Alu_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Multiplexer2_1.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Multiplexer2_1.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="Multiplexer2_1.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="Multiplexer2_1.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Multiplexer2_1.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="Multiplexer2_1.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Multiplexer2_1.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Multiplexer2_1.xst"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Multiplexer2_1_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Multiplexer2_1_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Multiplexer2_1_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
67,10 → 79,10
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testAlu_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testAlu_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testMultiplexer2_1_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testMultiplexer2_1_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
82,7 → 94,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:in_ck="-1820660540775966270" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1332971514">
<transform xil_pn:end_ts="1332975985" xil_pn:in_ck="-4177847064657889201" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1332975985">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
89,20 → 101,21
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testMultiplexer2_1.vhd"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-892635403352863368" xil_pn:start_ts="1332971514">
<transform xil_pn:end_ts="1332975952" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5560548389496876941" xil_pn:start_ts="1332975952">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7876831410930882182" xil_pn:start_ts="1332971514">
<transform xil_pn:end_ts="1332975952" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4712046104738671925" xil_pn:start_ts="1332975952">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8637507079216041037" xil_pn:start_ts="1332971514">
<transform xil_pn:end_ts="1332975281" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="6711552298331853320" xil_pn:start_ts="1332975281">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332971514" xil_pn:in_ck="-1820660540775966270" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1332971514">
<transform xil_pn:end_ts="1332975985" xil_pn:in_ck="-4177847064657889201" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1332975985">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
109,67 → 122,64
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testMultiplexer2_1.vhd"/>
</transform>
<transform xil_pn:end_ts="1332971517" xil_pn:in_ck="-1820660540775966270" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3692595343167413970" xil_pn:start_ts="1332971514">
<transform xil_pn:end_ts="1332975987" xil_pn:in_ck="-4177847064657889201" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6766024878768186600" xil_pn:start_ts="1332975985">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_beh.prj"/>
<outfile xil_pn:name="testAlu_isim_beh.exe"/>
<outfile xil_pn:name="testMultiplexer2_1_beh.prj"/>
<outfile xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1332971517" xil_pn:in_ck="-3984477231246839023" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7365609629158378897" xil_pn:start_ts="1332971517">
<transform xil_pn:end_ts="1332975988" xil_pn:in_ck="2507770055730146729" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="8032999008259990405" xil_pn:start_ts="1332975987">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testAlu_isim_beh.wdb"/>
<outfile xil_pn:name="testMultiplexer2_1_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7863675631946613945" xil_pn:start_ts="1332968178">
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="2905730545275514818" xil_pn:start_ts="1332974939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8637507079216041037" xil_pn:start_ts="1332968178">
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6711552298331853320" xil_pn:start_ts="1332974939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1332968178">
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1332974939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2964161847311656507" xil_pn:start_ts="1332968178">
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-312577025010089088" xil_pn:start_ts="1332974939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1332968178">
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1332974939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="319318766057190551" xil_pn:start_ts="1332968178">
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="2130176180700788754" xil_pn:start_ts="1332974939">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332968184" xil_pn:in_ck="8015792819232243152" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7168533952405101494" xil_pn:start_ts="1332968178">
<transform xil_pn:end_ts="1332975190" xil_pn:in_ck="8015792819232243152" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7037618392410294555" xil_pn:start_ts="1332975185">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="Alu.lso"/>
<outfile xil_pn:name="Alu.ngc"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="Alu.prj"/>
<outfile xil_pn:name="Alu.stx"/>
<outfile xil_pn:name="Alu.syr"/>
<outfile xil_pn:name="Alu.xst"/>
<outfile xil_pn:name="Alu_vhdl.prj"/>
<outfile xil_pn:name="Alu_xst.xrpt"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Multiplexer2_1.lso"/>
<outfile xil_pn:name="Multiplexer2_1.ngc"/>
<outfile xil_pn:name="Multiplexer2_1.ngr"/>
<outfile xil_pn:name="Multiplexer2_1.prj"/>
<outfile xil_pn:name="Multiplexer2_1.stx"/>
<outfile xil_pn:name="Multiplexer2_1.syr"/>
<outfile xil_pn:name="Multiplexer2_1.xst"/>
<outfile xil_pn:name="Multiplexer2_1_vhdl.prj"/>
<outfile xil_pn:name="Multiplexer2_1_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
177,56 → 187,8
<transform xil_pn:end_ts="1332968125" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-1210076599156103590" xil_pn:start_ts="1332968125">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1332968131" xil_pn:in_ck="88312569576" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3676465938101052346" xil_pn:start_ts="1332968125">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="Alu.bld"/>
<outfile xil_pn:name="Alu.ngd"/>
<outfile xil_pn:name="Alu_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1332968137" xil_pn:in_ck="88312569577" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1332968131">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="Alu.pcf"/>
<outfile xil_pn:name="Alu_map.map"/>
<outfile xil_pn:name="Alu_map.mrp"/>
<outfile xil_pn:name="Alu_map.ncd"/>
<outfile xil_pn:name="Alu_map.ngm"/>
<outfile xil_pn:name="Alu_map.xrpt"/>
<outfile xil_pn:name="Alu_summary.xml"/>
<outfile xil_pn:name="Alu_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1332968149" xil_pn:in_ck="104733817618758274" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1332968137">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="Alu.ncd"/>
<outfile xil_pn:name="Alu.pad"/>
<outfile xil_pn:name="Alu.par"/>
<outfile xil_pn:name="Alu.ptwx"/>
<outfile xil_pn:name="Alu.unroutes"/>
<outfile xil_pn:name="Alu.xpi"/>
<outfile xil_pn:name="Alu_pad.csv"/>
<outfile xil_pn:name="Alu_pad.txt"/>
<outfile xil_pn:name="Alu_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1332968149" xil_pn:in_ck="88312569445" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1332968146">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="Alu.twr"/>
<outfile xil_pn:name="Alu.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform>
</transforms>
 
</generated_project>
/hdl/opencpu32/opencpu32.xise
20,19 → 20,25
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Multiplexer2_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="Multiplexer2_1.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="testMultiplexer2_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
</file>
</files>
 
<properties>
45,7 → 51,7
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
138,9 → 144,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Alu|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="Alu.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Multiplexer2_1|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="Multiplexer2_1.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Multiplexer2_1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
198,7 → 204,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="Alu" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="Multiplexer2_1" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
210,10 → 216,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Alu_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Alu_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Alu_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Alu_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Multiplexer2_1_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Multiplexer2_1_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Multiplexer2_1_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Multiplexer2_1_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
233,7 → 239,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Alu" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Multiplexer2_1" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
257,8 → 263,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testMultiplexer2_1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testMultiplexer2_1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
274,7 → 280,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testAlu" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testMultiplexer2_1" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
324,7 → 330,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testAlu|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testMultiplexer2_1|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/hdl/opencpu32/Multiplexer2_1.vhd
6,7 → 6,7
use IEEE.STD_LOGIC_1164.ALL;
 
--! Use CPU Definitions package
library pkgOpenCPU32;
use work.pkgOpenCPU32.all;
 
--! Mux 2->1 circuit can select one of the 2 inputs into one output with some selection signal
 
13,10 → 13,11
--! Detailed description of this
--! mux design element.
entity Multiplexer2_1 is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0); --! First Input
B : in STD_LOGIC_VECTOR (7 downto 0); --! Second Input
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
sel : in STD_LOGIC; --! Select inputs (1 or 2)
S : in STD_LOGIC_VECTOR (7 downto 0)); --! Mux Output
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
end Multiplexer2_1;
 
--! @brief Architure definition of the MUX
24,7 → 25,10
architecture Behavioral of Multiplexer2_1 is
 
begin
with sel select
S <= A when '0',
B when '1',
(others => 'Z') when others;
 
 
end Behavioral;
 
/hdl/opencpu32/testMultiplexer2_1.vhd
0,0 → 1,73
--! @file
--! @brief Testbench for Multiplexer2_1
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
ENTITY testMultiplexer2_1 IS
END testMultiplexer2_1;
--! @brief Multiplexer2_1 Testbench file
--! @details Test multiplexer operations changing the selection signal
--! for more information: http://en.wikipedia.org/wiki/Multiplexer
ARCHITECTURE behavior OF testMultiplexer2_1 IS
--! Component declaration to instantiate the Multiplexer circuit
COMPONENT Multiplexer2_1
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package)
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! First Input
B : in STD_LOGIC_VECTOR (n downto 0); --! Second Input
sel : in STD_LOGIC; --! Select inputs (1 or 2)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
END COMPONENT;
 
--Inputs
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0');
signal B : std_logic_vector((nBits - 1) downto 0) := (others => '0');
signal sel : std_logic := '0';
 
--Outputs
signal S : std_logic_vector((nBits - 1) downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Multiplexer2_1 PORT MAP (
A => A,
B => B,
sel => sel,
S => S
);
--! Process that will change sel signal and verify the Mux outputs
stim_proc: process
begin
-- Sel 0 ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Select first channel" SEVERITY NOTE;
sel <= '0';
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (A) report "Could not select first channel" severity FAILURE;
-- Sel 1 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select second channel" SEVERITY NOTE;
sel <= '1';
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = (B) report "Could not select second channel" severity FAILURE;
 
wait;
end process;
 
END;
/docs/images/Multiplexer2.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/docs/images/Multiplexer2.png
docs/images/Multiplexer2.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: docs/images/Cache.JPG =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: docs/images/Cache.JPG =================================================================== --- docs/images/Cache.JPG (nonexistent) +++ docs/images/Cache.JPG (revision 10)
docs/images/Cache.JPG Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: docs/images/vonNeumann.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: docs/images/vonNeumann.jpg =================================================================== --- docs/images/vonNeumann.jpg (nonexistent) +++ docs/images/vonNeumann.jpg (revision 10)
docs/images/vonNeumann.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: docs/images/Harvard.jpg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: docs/images/Harvard.jpg =================================================================== --- docs/images/Harvard.jpg (nonexistent) +++ docs/images/Harvard.jpg (revision 10)
docs/images/Harvard.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: docs/images/Diagrama_Blocos_2.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: docs/images/Diagrama_Blocos_2.png =================================================================== --- docs/images/Diagrama_Blocos_2.png (nonexistent) +++ docs/images/Diagrama_Blocos_2.png (revision 10)
docs/images/Diagrama_Blocos_2.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property

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