URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
Compare Revisions
- This comparison shows the changes necessary to convert path
/opencpu32/trunk
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/opencpu32/hdl/opencpu32/testAlu.vhd" into library work</arg> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/opencpu32/hdl/opencpu32/testTriStateBuffer.vhd" into library work</arg> |
</msg> |
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</messages> |
/hdl/opencpu32/pkgOpenCPU32.vhd
10,7 → 10,8
--! Declare constants, enums, functions used by the design |
constant nBits : integer := 32; |
|
type aluOps is (alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and, alu_xor, alu_not); |
type aluOps is (alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and, alu_xor, alu_not); |
type typeEnDis is (enable, disable); |
|
end pkgOpenCPU32; |
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/hdl/opencpu32/opencpu32.gise
70,6 → 70,12
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Multiplexer2_1_isim_beh.exe"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Multiplexer2_1_vhdl.prj"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Multiplexer2_1_xst.xrpt"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TriStateBuffer.prj"/> |
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="TriStateBuffer.stx"/> |
<file xil_pn:fileType="FILE_XST" xil_pn:name="TriStateBuffer.xst"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TriStateBuffer_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TriStateBuffer_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="TriStateBuffer_isim_beh.wdb"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
80,9 → 86,7
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testMultiplexer2_1_beh.prj"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/> |
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testMultiplexer2_1_isim_beh.wdb"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> |
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> |
90,54 → 94,58
</files> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"> |
<transform xil_pn:end_ts="1332971514" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1332971514"> |
<transform xil_pn:end_ts="1333115998" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1333115998"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332975985" xil_pn:in_ck="-4177847064657889201" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1332975985"> |
<transform xil_pn:end_ts="1333116287" xil_pn:in_ck="6310421515407944547" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333116287"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="Alu.vhd"/> |
<outfile xil_pn:name="Multiplexer2_1.vhd"/> |
<outfile xil_pn:name="TriStateBuffer.vhd"/> |
<outfile xil_pn:name="pkgOpenCPU32.vhd"/> |
<outfile xil_pn:name="testAlu.vhd"/> |
<outfile xil_pn:name="testMultiplexer2_1.vhd"/> |
<outfile xil_pn:name="testTriStateBuffer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1332975952" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5560548389496876941" xil_pn:start_ts="1332975952"> |
<transform xil_pn:end_ts="1333116287" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="5051190120110013325" xil_pn:start_ts="1333116287"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332975952" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4712046104738671925" xil_pn:start_ts="1332975952"> |
<transform xil_pn:end_ts="1333116287" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="6144079622853425871" xil_pn:start_ts="1333116287"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332975281" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="6711552298331853320" xil_pn:start_ts="1332975281"> |
<transform xil_pn:end_ts="1333115998" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="6711552298331853320" xil_pn:start_ts="1333115998"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332975985" xil_pn:in_ck="-4177847064657889201" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1332975985"> |
<transform xil_pn:end_ts="1333116287" xil_pn:in_ck="6310421515407944547" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333116287"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="Alu.vhd"/> |
<outfile xil_pn:name="Multiplexer2_1.vhd"/> |
<outfile xil_pn:name="TriStateBuffer.vhd"/> |
<outfile xil_pn:name="pkgOpenCPU32.vhd"/> |
<outfile xil_pn:name="testAlu.vhd"/> |
<outfile xil_pn:name="testMultiplexer2_1.vhd"/> |
<outfile xil_pn:name="testTriStateBuffer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1332975987" xil_pn:in_ck="-4177847064657889201" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6766024878768186600" xil_pn:start_ts="1332975985"> |
<transform xil_pn:end_ts="1333116288" xil_pn:in_ck="6310421515407944547" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4911544397197351281" xil_pn:start_ts="1333116287"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="TriStateBuffer_beh.prj"/> |
<outfile xil_pn:name="TriStateBuffer_isim_beh.exe"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="testMultiplexer2_1_beh.prj"/> |
<outfile xil_pn:name="testMultiplexer2_1_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1332975988" xil_pn:in_ck="2507770055730146729" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="8032999008259990405" xil_pn:start_ts="1332975987"> |
<transform xil_pn:end_ts="1333116288" xil_pn:in_ck="-7971658627700057290" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-2498771775477111924" xil_pn:start_ts="1333116288"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="TriStateBuffer_isim_beh.wdb"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="testMultiplexer2_1_isim_beh.wdb"/> |
</transform> |
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178"> |
<status xil_pn:value="SuccessfullyRun"/> |
170,16 → 178,11
<transform xil_pn:end_ts="1332975190" xil_pn:in_ck="8015792819232243152" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7037618392410294555" xil_pn:start_ts="1332975185"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name=".lso"/> |
<outfile xil_pn:name="Multiplexer2_1.lso"/> |
<outfile xil_pn:name="Multiplexer2_1.ngc"/> |
<outfile xil_pn:name="Multiplexer2_1.ngr"/> |
<outfile xil_pn:name="Multiplexer2_1.prj"/> |
<outfile xil_pn:name="Multiplexer2_1.stx"/> |
<outfile xil_pn:name="Multiplexer2_1.syr"/> |
<outfile xil_pn:name="Multiplexer2_1.xst"/> |
<outfile xil_pn:name="Multiplexer2_1_vhdl.prj"/> |
<outfile xil_pn:name="Multiplexer2_1_xst.xrpt"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputAdded"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputRemoved"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
/hdl/opencpu32/opencpu32.xise
24,8 → 24,8
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="Multiplexer2_1.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="testAlu.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
34,11 → 34,21
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/> |
</file> |
<file xil_pn:name="testMultiplexer2_1.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="77"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="77"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/> |
</file> |
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
<file xil_pn:name="testTriStateBuffer.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="75"/> |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="75"/> |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/> |
</file> |
</files> |
|
<properties> |
65,7 → 75,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
263,8 → 273,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testMultiplexer2_1" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testMultiplexer2_1" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testTriStateBuffer/uut" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TriStateBuffer" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
280,7 → 290,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testMultiplexer2_1" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TriStateBuffer" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
330,7 → 340,7
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testMultiplexer2_1|behavior" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TriStateBuffer|Behavioral" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
/hdl/opencpu32/TriStateBuffer.vhd
0,0 → 1,34
--! @file |
--! @brief Tri-State buffer http://en.wikipedia.org/wiki/Three-state_logic |
|
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith) |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
--! Use CPU Definitions package |
use work.pkgOpenCPU32.all; |
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--! In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a \n |
--! high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit. |
|
--! In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a \n |
--! high impedance state in addition to the 0 and 1 logic levels, effectively removing the output from the circuit. |
--! This allows multiple circuits to share the same output line or lines (such as a bus). |
entity TriStateBuffer is |
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package) |
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Buffer Input |
sel : in typeEnDis; --! Enable or Disable the output |
S : out STD_LOGIC_VECTOR (n downto 0)); --! TriState buffer output |
end TriStateBuffer; |
|
--! @brief Architure definition of the TriStateBuffer |
--! @details On this case we're going to use VHDL combinational description (Simple combination circuit) |
architecture Behavioral of TriStateBuffer is |
|
begin |
with sel select |
S <= A when enable, |
(others => 'Z') when disable; |
|
end Behavioral; |
|
/hdl/opencpu32/testTriStateBuffer.vhd
0,0 → 1,69
--! @file |
--! @brief Testbench for TriStateBuffer |
|
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith) |
LIBRARY ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
|
--! Use CPU Definitions package |
use work.pkgOpenCPU32.all; |
|
ENTITY testTriStateBuffer IS |
END testTriStateBuffer; |
|
--! @brief TriStateBuffer Testbench file |
--! @details Test TriStateBuffer by enabling/disabling the sel signal |
ARCHITECTURE behavior OF testTriStateBuffer IS |
|
-- Component Declaration for the Unit Under Test (UUT) |
|
COMPONENT TriStateBuffer |
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the Alu on the package) |
PORT( |
A : IN std_logic_vector(n downto 0); --! Buffer Input |
sel : IN typeEnDis; --! Enable or Disable the output |
S : OUT std_logic_vector(n downto 0) --! Enable or Disable the output |
); |
END COMPONENT; |
|
|
--Inputs |
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); |
signal sel : typeEnDis := disable; |
|
--Outputs |
signal S : std_logic_vector((nBits - 1) downto 0); |
|
BEGIN |
--!Instantiate the Unit Under Test (Multiplexer2_1) (Doxygen bug if it's not commented!) |
uut: TriStateBuffer PORT MAP ( |
A => A, |
sel => sel, |
S => S |
); |
|
--! Process that will change sel signal and verify the Mux outputs |
stim_proc: process |
begin |
-- Sel disable --------------------------------------------------------------------------- |
wait for 1 ps; |
REPORT "Test tristate on disable mode" SEVERITY NOTE; |
sel <= disable; |
A <= conv_std_logic_vector(10, nBits); |
wait for 1 ns; -- Wait to stabilize the response |
assert S = ((others => 'Z')) report "Output should be high impedance..." severity FAILURE; |
|
-- Sel disable --------------------------------------------------------------------------- |
wait for 1 ps; |
REPORT "Test tristate on enable mode" SEVERITY NOTE; |
sel <= enable; |
A <= conv_std_logic_vector(10, nBits); |
wait for 1 ns; -- Wait to stabilize the response |
assert S = (conv_std_logic_vector(10, nBits)) report "Output should be high impedance..." severity FAILURE; |
|
wait; |
end process; |
|
END; |