OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /opencpu32/trunk
    from Rev 13 to Rev 14
    ↔ Reverse comparison
  •

Rev 13 → Rev 14

/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/testTriStateBuffer.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/testRegisterFile.vhd&quot; into library work</arg>
</msg>
 
</messages>
/hdl/opencpu32/pkgOpenCPU32.vhd
1,5 → 1,9
--! @file
--! @brief 2:1 CPU global Definitions
 
--! @mainpage
--! <H1>Main document of the OpenCPU32 project</H1>\n
--! <H2>Features</H2>
 
--! Use standard library
library IEEE;
10,12 → 14,67
--! Declare constants, enums, functions used by the design
constant nBits : integer := 32;
 
--! Number of general registers (r0..r15)
constant numGenRegs : integer := 16;
 
type aluOps is (alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and, alu_xor, alu_not);
type typeEnDis is (enable, disable);
type typeEnDis is (enable, disable);
type generalRegisters is (r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15);
 
function reg2Num (a: generalRegisters) return integer;
function Num2reg (a: integer) return generalRegisters;
 
end pkgOpenCPU32;
 
--! Define functions or procedures
package body pkgOpenCPU32 is
package body pkgOpenCPU32 is
 
function reg2Num (a: generalRegisters) return integer is
variable valRet : integer;
begin
case a is
when r0 => valRet := 0;
when r1 => valRet := 1;
when r2 => valRet := 2;
when r3 => valRet := 3;
when r4 => valRet := 4;
when r5 => valRet := 5;
when r6 => valRet := 6;
when r7 => valRet := 7;
when r8 => valRet := 8;
when r9 => valRet := 9;
when r10 => valRet := 10;
when r11 => valRet := 11;
when r12 => valRet := 12;
when r13 => valRet := 13;
when r14 => valRet := 14;
when r15 => valRet := 15;
end case;
return valRet;
end reg2Num;
function Num2reg (a: integer) return generalRegisters is
variable valRet : generalRegisters;
begin
case a is
when 0 => valRet := r0;
when 1 => valRet := r1;
when 2 => valRet := r2;
when 3 => valRet := r3;
when 4 => valRet := r4;
when 5 => valRet := r5;
when 6 => valRet := r6;
when 7 => valRet := r7;
when 8 => valRet := r8;
when 9 => valRet := r9;
when 10 => valRet := r10;
when 11 => valRet := r11;
when 12 => valRet := r12;
when 13 => valRet := r13;
when 14 => valRet := r14;
when 15 => valRet := r15;
end case;
return valRet;
end Num2reg;
 
end pkgOpenCPU32;
/hdl/opencpu32/opencpu32.gise
59,21 → 59,71
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="Alu_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Alu_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="Multiplexer2_1.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Multiplexer2_1.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Multiplexer2_1.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Multiplexer2_1.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="Multiplexer2_1.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="Multiplexer2_1.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="Multiplexer2_1.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="Multiplexer2_1.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="Multiplexer2_1.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Multiplexer2_1.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="Multiplexer2_1.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Multiplexer2_1.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="Multiplexer2_1.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="Multiplexer2_1.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="Multiplexer2_1.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Multiplexer2_1.xst"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="Multiplexer2_1_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Multiplexer2_1_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Multiplexer2_1_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Multiplexer2_1_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Multiplexer2_1_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="Multiplexer2_1_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="Multiplexer2_1_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="Multiplexer2_1_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Multiplexer2_1_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Multiplexer2_1_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Multiplexer2_1_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="RegisterFile.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="RegisterFile.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="RegisterFile.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="RegisterFile.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="RegisterFile.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="RegisterFile.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="RegisterFile.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="RegisterFile.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="RegisterFile.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="RegisterFile.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="RegisterFile.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="RegisterFile.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="RegisterFile.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="RegisterFile.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="RegisterFile.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="RegisterFile.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="RegisterFile.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="RegisterFile.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="RegisterFile.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="RegisterFile_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="RegisterFile_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="RegisterFile_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="RegisterFile_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="RegisterFile_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="RegisterFile_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="RegisterFile_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="RegisterFile_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="RegisterFile_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="RegisterFile_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="RegisterFile_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="RegisterFile_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="RegisterFile_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="RegisterFile_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="RegisterFile_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="RegisterFile_xst.xrpt"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TriStateBuffer.prj"/>
<file xil_pn:fileType="FILE_XST_STX" xil_pn:name="TriStateBuffer.stx"/>
<file xil_pn:fileType="FILE_XST" xil_pn:name="TriStateBuffer.xst"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TriStateBuffer_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="TriStateBuffer_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="TriStateBuffer_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
87,6 → 137,10
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testAlu_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testMultiplexer2_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testRegisterFile_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testRegisterFile_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testRegisterFile_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testTriStateBuffer_isim_beh.exe"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
98,100 → 152,159
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333116287" xil_pn:in_ck="6310421515407944547" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333116287">
<transform xil_pn:end_ts="1333131714" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1333131714">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="RegisterFile.vhd"/>
<outfile xil_pn:name="TriStateBuffer.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testMultiplexer2_1.vhd"/>
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333116287" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="5051190120110013325" xil_pn:start_ts="1333116287">
<transform xil_pn:end_ts="1333130729" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8486826367021142885" xil_pn:start_ts="1333130729">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333116287" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="6144079622853425871" xil_pn:start_ts="1333116287">
<transform xil_pn:end_ts="1333130729" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3768155790739553443" xil_pn:start_ts="1333130729">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333115998" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="6711552298331853320" xil_pn:start_ts="1333115998">
<transform xil_pn:end_ts="1333128697" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8786154546671769104" xil_pn:start_ts="1333128697">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1333116287" xil_pn:in_ck="6310421515407944547" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333116287">
<transform xil_pn:end_ts="1333131714" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1333131714">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
<outfile xil_pn:name="Multiplexer2_1.vhd"/>
<outfile xil_pn:name="RegisterFile.vhd"/>
<outfile xil_pn:name="TriStateBuffer.vhd"/>
<outfile xil_pn:name="pkgOpenCPU32.vhd"/>
<outfile xil_pn:name="testAlu.vhd"/>
<outfile xil_pn:name="testMultiplexer2_1.vhd"/>
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1333116288" xil_pn:in_ck="6310421515407944547" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-4911544397197351281" xil_pn:start_ts="1333116287">
<transform xil_pn:end_ts="1333131717" xil_pn:in_ck="6397790860624799949" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6640613741745699976" xil_pn:start_ts="1333131714">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="TriStateBuffer_beh.prj"/>
<outfile xil_pn:name="TriStateBuffer_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="testRegisterFile_beh.prj"/>
<outfile xil_pn:name="testRegisterFile_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1333116288" xil_pn:in_ck="-7971658627700057290" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-2498771775477111924" xil_pn:start_ts="1333116288">
<transform xil_pn:end_ts="1333131717" xil_pn:in_ck="-8453111789177412509" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="2549364959294095189" xil_pn:start_ts="1333131717">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="TriStateBuffer_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="testRegisterFile_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1332968178" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332968178">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="2905730545275514818" xil_pn:start_ts="1332974939">
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="2578846049644942698" xil_pn:start_ts="1333126879">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6711552298331853320" xil_pn:start_ts="1332974939">
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8786154546671769104" xil_pn:start_ts="1333126879">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1332974939">
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1333126879">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-312577025010089088" xil_pn:start_ts="1332974939">
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3693875251935617448" xil_pn:start_ts="1333126879">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1332974939">
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1333126879">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332974939" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="2130176180700788754" xil_pn:start_ts="1332974939">
<transform xil_pn:end_ts="1333126879" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3979640367777479302" xil_pn:start_ts="1333126879">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1332975190" xil_pn:in_ck="8015792819232243152" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7037618392410294555" xil_pn:start_ts="1332975185">
<transform xil_pn:end_ts="1333128266" xil_pn:in_ck="-7301577169810660065" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="4389747016737444173" xil_pn:start_ts="1333128258">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="RegisterFile.lso"/>
<outfile xil_pn:name="RegisterFile.ngc"/>
<outfile xil_pn:name="RegisterFile.ngr"/>
<outfile xil_pn:name="RegisterFile.prj"/>
<outfile xil_pn:name="RegisterFile.stx"/>
<outfile xil_pn:name="RegisterFile.syr"/>
<outfile xil_pn:name="RegisterFile.xst"/>
<outfile xil_pn:name="RegisterFile_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1332968125" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-1210076599156103590" xil_pn:start_ts="1332968125">
<transform xil_pn:end_ts="1333128286" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3437821219266902819" xil_pn:start_ts="1333128286">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
</transform>
<transform xil_pn:end_ts="1333128291" xil_pn:in_ck="-3340831830900747050" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="1086960579647177373" xil_pn:start_ts="1333128286">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="RegisterFile.bld"/>
<outfile xil_pn:name="RegisterFile.ngd"/>
<outfile xil_pn:name="RegisterFile_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1333128296" xil_pn:in_ck="6653001400415059737" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1333128291">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="RegisterFile.pcf"/>
<outfile xil_pn:name="RegisterFile_map.map"/>
<outfile xil_pn:name="RegisterFile_map.mrp"/>
<outfile xil_pn:name="RegisterFile_map.ncd"/>
<outfile xil_pn:name="RegisterFile_map.ngm"/>
<outfile xil_pn:name="RegisterFile_map.xrpt"/>
<outfile xil_pn:name="RegisterFile_summary.xml"/>
<outfile xil_pn:name="RegisterFile_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1333128308" xil_pn:in_ck="-1729479595224311388" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1333128296">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="RegisterFile.ncd"/>
<outfile xil_pn:name="RegisterFile.pad"/>
<outfile xil_pn:name="RegisterFile.par"/>
<outfile xil_pn:name="RegisterFile.ptwx"/>
<outfile xil_pn:name="RegisterFile.unroutes"/>
<outfile xil_pn:name="RegisterFile.xpi"/>
<outfile xil_pn:name="RegisterFile_pad.csv"/>
<outfile xil_pn:name="RegisterFile_pad.txt"/>
<outfile xil_pn:name="RegisterFile_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1333128308" xil_pn:in_ck="-2814155899893271411" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1333128305">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="RegisterFile.twr"/>
<outfile xil_pn:name="RegisterFile.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform>
</transforms>
 
</generated_project>
/hdl/opencpu32/RegisterFile.vhd
0,0 → 1,73
--! @file
--! @brief Register File unit http://en.wikipedia.org/wiki/Register_file
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
 
--! A register file is an array of processor registers in a central processing unit (CPU).
 
--! A register file is an array of processor registers in a central processing unit (CPU).\n
--! Modern integrated circuit-based register files are usually implemented by way of fast static RAMs with multiple ports.\n
--! Such RAMs are distinguished by having dedicated read and write ports, whereas ordinary multiported SRAMs will usually read and write\n
--! through the same ports.
entity RegisterFile is
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the registers)
Port ( clk : in STD_LOGIC; --! Clock signal
writeEn : in STD_LOGIC; --! Write enable
writeAddr : in generalRegisters; --! Write Adress
input : in STD_LOGIC_VECTOR (n downto 0); --! Input
Read_A_En : in STD_LOGIC; --! Enable read A
Read_A_Addr : in generalRegisters; --! Read A adress
Read_B_En : in STD_LOGIC; --! Enable read A
Read_B_Addr : in generalRegisters; --! Read B adress
A_Out : out STD_LOGIC_VECTOR (n downto 0); --! Output A
B_Out : out STD_LOGIC_VECTOR (n downto 0)); --! Output B
end RegisterFile;
 
--! @brief This register file will have one input and two ouputs.
--! @details This will permit to read two registers on the same clock, but will need n clock cicles for n register assignments...
 
architecture Behavioral of RegisterFile is
subtype reg is STD_LOGIC_VECTOR (n downto 0); -- Define register type
type regArray is array (0 to (numGenRegs-1)) of reg; -- Define register type array
signal regFile : regArray; -- This signal will infer an FF array if assigned by a clock edge...
begin
-- Write some register value...
writeProcess: process (clk)
begin
if rising_edge(clk) then
if (writeEn = '1') then
regFile(CONV_INTEGER(reg2Num(writeAddr))) <= input;
end if;
end if;
end process;
-- Read some register in port A
readAProcess : process(Read_A_En,Read_A_Addr)
begin
if (Read_A_En = '1') then
A_Out <= regFile(CONV_INTEGER(reg2Num(writeAddr)));
else
A_Out <= (others => 'Z');
end if;
end process;
-- Read some register in port B
readBProcess : process(Read_B_En,Read_B_Addr)
begin
if (Read_B_En = '1') then
B_Out <= regFile(CONV_INTEGER(reg2Num(writeAddr)));
else
B_Out <= (others => 'Z');
end if;
end process;
 
end Behavioral;
 
/hdl/opencpu32/testRegisterFile.vhd
0,0 → 1,154
--! @file
--! @brief Testbench for Alu
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
--! Use CPU Definitions package
use work.pkgOpenCPU32.all;
ENTITY testRegisterFile IS
END testRegisterFile;
--! @brief testRegisterFile Testbench file
--! @details Test read/write on the registers, testing also the dual port reading feature...
ARCHITECTURE behavior OF testRegisterFile IS
--! Component declaration to instantiate the testRegisterFile circuit
COMPONENT RegisterFile
generic (n : integer := nBits - 1); --! Generic value (Used to easily change the size of the registers)
Port ( clk : in STD_LOGIC; --! Clock signal
writeEn : in STD_LOGIC; --! Write enable
writeAddr : in generalRegisters; --! Write Adress
input : in STD_LOGIC_VECTOR (n downto 0); --! Input
Read_A_En : in STD_LOGIC; --! Enable read A
Read_A_Addr : in generalRegisters; --! Read A adress
Read_B_En : in STD_LOGIC; --! Enable read A
Read_B_Addr : in generalRegisters; --! Read B adress
A_Out : out STD_LOGIC_VECTOR (n downto 0); --! Output A
B_Out : out STD_LOGIC_VECTOR (n downto 0)); --! Output B
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0'; --! Wire to connect Test signal to component
signal writeEn : std_logic := '0'; --! Wire to connect Test signal to component
signal writeAddr : generalRegisters := r0; --! Wire to connect Test signal to component
signal input : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal Read_A_En : std_logic := '0'; --! Wire to connect Test signal to component
signal Read_A_Addr : generalRegisters := r0; --! Wire to connect Test signal to component
signal Read_B_En : std_logic := '0'; --! Wire to connect Test signal to component
signal Read_B_Addr : generalRegisters := r0; --! Wire to connect Test signal to component
 
--Outputs
signal A_Out : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
signal B_Out : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
constant num_cycles : integer := 320; --! Number of clock iterations
BEGIN
--! Instantiate the Unit Under Test (RegisterFile) (Doxygen bug if it's not commented!)
uut: RegisterFile PORT MAP (
clk => clk,
writeEn => writeEn,
writeAddr => writeAddr,
input => input,
Read_A_En => Read_A_En,
Read_A_Addr => Read_A_Addr,
Read_B_En => Read_B_En,
Read_B_Addr => Read_B_Addr,
A_Out => A_Out,
B_Out => B_Out
);
 
--! Process that will stimulate all register assignments, and reads...
stim_proc: process
begin
-- r0=1 ... r15=16---------------------------------------------------------------------------
clk <= '0';
REPORT "Write r0 := 1" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r0;
input <= conv_std_logic_vector(1, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
 
clk <= '0';
REPORT "Write r1 := 2" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r1;
input <= conv_std_logic_vector(2, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
clk <= '0';
REPORT "Write r2 := 3" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r2;
input <= conv_std_logic_vector(3, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
clk <= '0';
REPORT "Write r3 := 4" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r3;
input <= conv_std_logic_vector(4, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
clk <= '0';
REPORT "Write r4 := 5" SEVERITY NOTE;
writeEn <= '1';
writeAddr <= r4;
input <= conv_std_logic_vector(5, nBits);
wait for 1 ns;
clk <= '1';
wait for 1 ns; -- Wait to stabilize the response
clk <= '0';
writeEn <= '0';
wait for 1 ns; -- Wait to stabilize the response
-- Read r0..r15 PortA-------------------------------------------------------------------------
REPORT "Check r0 = 1" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r0;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(1, nBits) report "Invalid value r0" severity FAILURE;
REPORT "Check r1 = 2" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r1;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(2, nBits) report "Invalid value r1" severity FAILURE;
REPORT "Check r2 = 3" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r2;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(3, nBits) report "Invalid value r2" severity FAILURE;
REPORT "Check r3 = 4" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r3;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(4, nBits) report "Invalid value r3" severity FAILURE;
REPORT "Check r4 = 5" SEVERITY NOTE;
Read_A_En <= '1';
Read_A_Addr <= r4;
wait for 1 ns; -- Wait to stabilize the response
assert A_Out = conv_std_logic_vector(5, nBits) report "Invalid value r4" severity FAILURE;
 
wait;
end process;
 
END;
/hdl/opencpu32/opencpu32.xise
40,8 → 40,8
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="TriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="testTriStateBuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
49,6 → 49,16
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="RegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="testRegisterFile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="146"/>
</file>
</files>
 
<properties>
154,9 → 164,9
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Multiplexer2_1|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="Multiplexer2_1.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Multiplexer2_1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|RegisterFile|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="RegisterFile.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/RegisterFile" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
214,7 → 224,7
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="Multiplexer2_1" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="RegisterFile" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
226,10 → 236,10
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Multiplexer2_1_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Multiplexer2_1_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Multiplexer2_1_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Multiplexer2_1_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="RegisterFile_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="RegisterFile_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="RegisterFile_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="RegisterFile_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
249,7 → 259,7
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Multiplexer2_1" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="RegisterFile" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
273,8 → 283,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testTriStateBuffer/uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TriStateBuffer" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testRegisterFile" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testRegisterFile" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
290,7 → 300,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TriStateBuffer" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testRegisterFile" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
340,7 → 350,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TriStateBuffer|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testRegisterFile|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/hdl/opencpu32/testTriStateBuffer.vhd
30,11 → 30,11
 
--Inputs
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0');
signal sel : typeEnDis := disable;
signal A : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal sel : typeEnDis := disable; --! Wire to connect Test signal to component
 
--Outputs
signal S : std_logic_vector((nBits - 1) downto 0);
signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
BEGIN
--!Instantiate the Unit Under Test (Multiplexer2_1) (Doxygen bug if it's not commented!)
46,6 → 46,7
--! Process that will change sel signal and verify the Mux outputs
stim_proc: process
variable allZ : std_logic_vector((nBits - 1) downto 0) := (others => 'Z');
begin
-- Sel disable ---------------------------------------------------------------------------
wait for 1 ps;
53,7 → 54,7
sel <= disable;
A <= conv_std_logic_vector(10, nBits);
wait for 1 ns; -- Wait to stabilize the response
assert S = ((others => 'Z')) report "Output should be high impedance..." severity FAILURE;
assert S = allZ report "Output should be high impedance..." severity FAILURE;
-- Sel disable ---------------------------------------------------------------------------
wait for 1 ps;

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