URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
Compare Revisions
- This comparison shows the changes necessary to convert path
/opencpu32/trunk
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
0,0 → 1,15
<?xml version="1.0" encoding="UTF-8"?> |
<!-- IMPORTANT: This is an internal file that has been generated --> |
<!-- by the Xilinx ISE software. Any direct editing or --> |
<!-- changes made to this file may result in unpredictable --> |
<!-- behavior or data corruption. It is strongly advised that --> |
<!-- users do not edit the contents of this file. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/opencpu32/hdl/opencpu32/Multiplexer2_1.vhd" into library work</arg> |
</msg> |
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</messages> |
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/hdl/opencpu32/pkgOpenCPU32.vhd
0,0 → 1,18
--! @file |
--! @brief 2:1 CPU global Definitions |
|
--! Use standard library |
library IEEE; |
use IEEE.STD_LOGIC_1164.all; |
|
package pkgOpenCPU32 is |
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--! Declare constants, enums, functions used by the design |
constant nBits : integer := 32; |
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end pkgOpenCPU32; |
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--! Define functions or procedures |
package body pkgOpenCPU32 is |
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end pkgOpenCPU32; |
/hdl/opencpu32/Alu.vhd
0,0 → 1,29
--! @file |
--! @brief Arithmetic logic unit http://en.wikipedia.org/wiki/Arithmetic_logic_unit |
|
--! Use standard library |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
--! Use CPU Definitions package |
library pkgOpenCPU32; |
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--! ALU is a digital circuit that performs arithmetic and logical operations. |
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--! ALU is a digital circuit that performs arithmetic and logical operations. It's the fundamental part of the CPU |
entity Alu is |
Port ( A : in STD_LOGIC_VECTOR (7 downto 0); --! Alu Operand 1 |
B : in STD_LOGIC_VECTOR (7 downto 0); --! Alu Operand 2 |
S : out STD_LOGIC_VECTOR (7 downto 0); --! Alu Output |
sel : in STD_LOGIC_VECTOR (2 downto 0)); --! Select operation |
end Alu; |
|
--! @brief Architure definition of the ALU |
--! @details More details about this mux element. |
architecture Behavioral of Alu is |
|
begin |
|
|
end Behavioral; |
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/hdl/opencpu32/opencpu32.gise
0,0 → 1,28
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<!-- --> |
|
<!-- For tool use only. Do not edit. --> |
|
<!-- --> |
|
<!-- ProjectNavigator created generated project file. --> |
|
<!-- For use in tracking generated file and other information --> |
|
<!-- allowing preservation of process status. --> |
|
<!-- --> |
|
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version> |
|
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="opencpu32.xise"/> |
|
<files xmlns="http://www.xilinx.com/XMLSchema"/> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"/> |
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</generated_project> |
/hdl/opencpu32/opencpu32.xise
0,0 → 1,386
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
<!-- This file contains project source information including a list of --> |
<!-- project source files, project and process properties. This file, --> |
<!-- along with the project source files, is sufficient to open and --> |
<!-- implement in ISE Project Navigator. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
</header> |
|
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="pkgOpenCPU32.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
</file> |
<file xil_pn:name="Alu.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
</file> |
</files> |
|
<properties> |
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/> |
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/> |
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/> |
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/> |
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> |
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3E Starter Board" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
<property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Alu|Behavioral" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="Alu.vhd" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Alu" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/> |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/> |
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="Alu" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Alu_map.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="Alu_timesim.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Alu_synthesis.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Alu_translate.vhd" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Alu" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> |
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="opencpu32" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-03-27T23:37:50" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F0C0847E59754F76B41EBB8402F9C326" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings/> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
</autoManagedFiles> |
|
</project> |
/hdl/opencpu32/Multiplexer2_1.vhd
0,0 → 1,29
------------------------------------------------------- |
--! @file |
--! @brief 2:1 Mux using with-select |
------------------------------------------------------- |
|
--! Use standard library |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
|
--! Mux entity brief description |
|
--! Detailed description of this |
--! mux design element. |
entity Multiplexer2_1 is |
Port ( A : in STD_LOGIC_VECTOR (7 downto 0); |
B : in STD_LOGIC_VECTOR (7 downto 0); |
sel : in STD_LOGIC; |
S : in STD_LOGIC_VECTOR (7 downto 0)); |
end Multiplexer2_1; |
|
--! @brief Architure definition of the MUX |
--! @details More details about this mux element. |
architecture Behavioral of Multiplexer2_1 is |
|
begin |
|
|
end Behavioral; |
|
/docs/confDoxygen.cnf.txt
0,0 → 1,345
|
#--------------------------------------------------------------------------- |
# Project related configuration options |
#--------------------------------------------------------------------------- |
DOXYFILE_ENCODING = UTF-8 |
PROJECT_NAME = "OpenCPU32 Documentation" |
PROJECT_NUMBER = |
PROJECT_BRIEF = |
PROJECT_LOGO = |
OUTPUT_DIRECTORY = E:/opencpu32/docs/gen |
CREATE_SUBDIRS = NO |
OUTPUT_LANGUAGE = English |
BRIEF_MEMBER_DESC = YES |
REPEAT_BRIEF = YES |
ABBREVIATE_BRIEF = "The $name class" \ |
"The $name widget" \ |
"The $name file" \ |
is \ |
provides \ |
specifies \ |
contains \ |
represents \ |
a \ |
an \ |
the |
ALWAYS_DETAILED_SEC = NO |
INLINE_INHERITED_MEMB = NO |
FULL_PATH_NAMES = YES |
STRIP_FROM_PATH = |
STRIP_FROM_INC_PATH = |
SHORT_NAMES = NO |
JAVADOC_AUTOBRIEF = NO |
QT_AUTOBRIEF = NO |
MULTILINE_CPP_IS_BRIEF = NO |
INHERIT_DOCS = YES |
SEPARATE_MEMBER_PAGES = NO |
TAB_SIZE = 8 |
ALIASES = |
TCL_SUBST = |
OPTIMIZE_OUTPUT_FOR_C = NO |
OPTIMIZE_OUTPUT_JAVA = NO |
OPTIMIZE_FOR_FORTRAN = NO |
OPTIMIZE_OUTPUT_VHDL = YES |
EXTENSION_MAPPING = |
MARKDOWN_SUPPORT = YES |
BUILTIN_STL_SUPPORT = NO |
CPP_CLI_SUPPORT = NO |
SIP_SUPPORT = NO |
IDL_PROPERTY_SUPPORT = YES |
DISTRIBUTE_GROUP_DOC = NO |
SUBGROUPING = YES |
INLINE_GROUPED_CLASSES = NO |
INLINE_SIMPLE_STRUCTS = NO |
TYPEDEF_HIDES_STRUCT = NO |
SYMBOL_CACHE_SIZE = 0 |
LOOKUP_CACHE_SIZE = 0 |
|
#--------------------------------------------------------------------------- |
# Build related configuration options |
#--------------------------------------------------------------------------- |
EXTRACT_ALL = NO |
EXTRACT_PRIVATE = NO |
EXTRACT_PACKAGE = NO |
EXTRACT_STATIC = NO |
EXTRACT_LOCAL_CLASSES = YES |
EXTRACT_LOCAL_METHODS = NO |
EXTRACT_ANON_NSPACES = NO |
HIDE_UNDOC_MEMBERS = NO |
HIDE_UNDOC_CLASSES = NO |
HIDE_FRIEND_COMPOUNDS = NO |
HIDE_IN_BODY_DOCS = NO |
INTERNAL_DOCS = NO |
CASE_SENSE_NAMES = NO |
HIDE_SCOPE_NAMES = NO |
SHOW_INCLUDE_FILES = YES |
FORCE_LOCAL_INCLUDES = NO |
INLINE_INFO = YES |
SORT_MEMBER_DOCS = YES |
SORT_BRIEF_DOCS = NO |
SORT_MEMBERS_CTORS_1ST = NO |
SORT_GROUP_NAMES = NO |
SORT_BY_SCOPE_NAME = NO |
STRICT_PROTO_MATCHING = NO |
GENERATE_TODOLIST = YES |
GENERATE_TESTLIST = YES |
GENERATE_BUGLIST = YES |
GENERATE_DEPRECATEDLIST= YES |
ENABLED_SECTIONS = |
MAX_INITIALIZER_LINES = 30 |
SHOW_USED_FILES = YES |
SHOW_DIRECTORIES = NO |
SHOW_FILES = YES |
SHOW_NAMESPACES = YES |
FILE_VERSION_FILTER = |
LAYOUT_FILE = |
CITE_BIB_FILES = |
|
#--------------------------------------------------------------------------- |
# configuration options related to warning and progress messages |
#--------------------------------------------------------------------------- |
QUIET = NO |
WARNINGS = YES |
WARN_IF_UNDOCUMENTED = YES |
WARN_IF_DOC_ERROR = YES |
WARN_NO_PARAMDOC = NO |
WARN_FORMAT = "$file:$line: $text" |
WARN_LOGFILE = |
|
#--------------------------------------------------------------------------- |
# configuration options related to the input files |
#--------------------------------------------------------------------------- |
INPUT = E:/opencpu32/hdl/opencpu32 |
INPUT_ENCODING = UTF-8 |
FILE_PATTERNS = *.c \ |
*.cc \ |
*.cxx \ |
*.cpp \ |
*.c++ \ |
*.d \ |
*.java \ |
*.ii \ |
*.ixx \ |
*.ipp \ |
*.i++ \ |
*.inl \ |
*.h \ |
*.hh \ |
*.hxx \ |
*.hpp \ |
*.h++ \ |
*.idl \ |
*.odl \ |
*.cs \ |
*.php \ |
*.php3 \ |
*.inc \ |
*.m \ |
*.mm \ |
*.dox \ |
*.py \ |
*.f90 \ |
*.f \ |
*.for \ |
*.vhd \ |
*.vhdl |
RECURSIVE = YES |
EXCLUDE = |
EXCLUDE_SYMLINKS = NO |
EXCLUDE_PATTERNS = |
EXCLUDE_SYMBOLS = |
EXAMPLE_PATH = |
EXAMPLE_PATTERNS = * |
EXAMPLE_RECURSIVE = NO |
IMAGE_PATH = |
INPUT_FILTER = |
FILTER_PATTERNS = |
FILTER_SOURCE_FILES = NO |
FILTER_SOURCE_PATTERNS = |
|
#--------------------------------------------------------------------------- |
# configuration options related to source browsing |
#--------------------------------------------------------------------------- |
SOURCE_BROWSER = YES |
INLINE_SOURCES = NO |
STRIP_CODE_COMMENTS = YES |
REFERENCED_BY_RELATION = NO |
REFERENCES_RELATION = NO |
REFERENCES_LINK_SOURCE = YES |
USE_HTAGS = NO |
VERBATIM_HEADERS = YES |
|
#--------------------------------------------------------------------------- |
# configuration options related to the alphabetical class index |
#--------------------------------------------------------------------------- |
ALPHABETICAL_INDEX = YES |
COLS_IN_ALPHA_INDEX = 5 |
IGNORE_PREFIX = |
|
#--------------------------------------------------------------------------- |
# configuration options related to the HTML output |
#--------------------------------------------------------------------------- |
GENERATE_HTML = YES |
HTML_OUTPUT = html |
HTML_FILE_EXTENSION = .html |
HTML_HEADER = |
HTML_FOOTER = |
HTML_STYLESHEET = |
HTML_EXTRA_FILES = |
HTML_COLORSTYLE_HUE = 220 |
HTML_COLORSTYLE_SAT = 100 |
HTML_COLORSTYLE_GAMMA = 80 |
HTML_TIMESTAMP = YES |
HTML_ALIGN_MEMBERS = YES |
HTML_DYNAMIC_SECTIONS = NO |
GENERATE_DOCSET = NO |
DOCSET_FEEDNAME = "Doxygen generated docs" |
DOCSET_BUNDLE_ID = org.doxygen.Project |
DOCSET_PUBLISHER_ID = org.doxygen.Publisher |
DOCSET_PUBLISHER_NAME = Publisher |
GENERATE_HTMLHELP = NO |
CHM_FILE = |
HHC_LOCATION = |
GENERATE_CHI = NO |
CHM_INDEX_ENCODING = |
BINARY_TOC = NO |
TOC_EXPAND = NO |
GENERATE_QHP = NO |
QCH_FILE = |
QHP_NAMESPACE = org.doxygen.Project |
QHP_VIRTUAL_FOLDER = doc |
QHP_CUST_FILTER_NAME = |
QHP_CUST_FILTER_ATTRS = |
QHP_SECT_FILTER_ATTRS = |
QHG_LOCATION = |
GENERATE_ECLIPSEHELP = NO |
ECLIPSE_DOC_ID = org.doxygen.Project |
DISABLE_INDEX = NO |
GENERATE_TREEVIEW = NO |
ENUM_VALUES_PER_LINE = 4 |
USE_INLINE_TREES = NO |
TREEVIEW_WIDTH = 250 |
EXT_LINKS_IN_WINDOW = NO |
FORMULA_FONTSIZE = 10 |
FORMULA_TRANSPARENT = YES |
USE_MATHJAX = NO |
MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest |
MATHJAX_EXTENSIONS = |
SEARCHENGINE = YES |
SERVER_BASED_SEARCH = NO |
|
#--------------------------------------------------------------------------- |
# configuration options related to the LaTeX output |
#--------------------------------------------------------------------------- |
GENERATE_LATEX = YES |
LATEX_OUTPUT = latex |
LATEX_CMD_NAME = latex |
MAKEINDEX_CMD_NAME = makeindex |
COMPACT_LATEX = NO |
PAPER_TYPE = a4 |
EXTRA_PACKAGES = |
LATEX_HEADER = |
LATEX_FOOTER = |
PDF_HYPERLINKS = YES |
USE_PDFLATEX = YES |
LATEX_BATCHMODE = NO |
LATEX_HIDE_INDICES = NO |
LATEX_SOURCE_CODE = NO |
LATEX_BIB_STYLE = plain |
|
#--------------------------------------------------------------------------- |
# configuration options related to the RTF output |
#--------------------------------------------------------------------------- |
GENERATE_RTF = NO |
RTF_OUTPUT = rtf |
COMPACT_RTF = NO |
RTF_HYPERLINKS = NO |
RTF_STYLESHEET_FILE = |
RTF_EXTENSIONS_FILE = |
|
#--------------------------------------------------------------------------- |
# configuration options related to the man page output |
#--------------------------------------------------------------------------- |
GENERATE_MAN = NO |
MAN_OUTPUT = man |
MAN_EXTENSION = .3 |
MAN_LINKS = NO |
|
#--------------------------------------------------------------------------- |
# configuration options related to the XML output |
#--------------------------------------------------------------------------- |
GENERATE_XML = NO |
XML_OUTPUT = xml |
XML_SCHEMA = |
XML_DTD = |
XML_PROGRAMLISTING = YES |
|
#--------------------------------------------------------------------------- |
# configuration options for the AutoGen Definitions output |
#--------------------------------------------------------------------------- |
GENERATE_AUTOGEN_DEF = NO |
|
#--------------------------------------------------------------------------- |
# configuration options related to the Perl module output |
#--------------------------------------------------------------------------- |
GENERATE_PERLMOD = NO |
PERLMOD_LATEX = NO |
PERLMOD_PRETTY = YES |
PERLMOD_MAKEVAR_PREFIX = |
|
#--------------------------------------------------------------------------- |
# Configuration options related to the preprocessor |
#--------------------------------------------------------------------------- |
ENABLE_PREPROCESSING = YES |
MACRO_EXPANSION = NO |
EXPAND_ONLY_PREDEF = NO |
SEARCH_INCLUDES = YES |
INCLUDE_PATH = |
INCLUDE_FILE_PATTERNS = |
PREDEFINED = |
EXPAND_AS_DEFINED = |
SKIP_FUNCTION_MACROS = YES |
|
#--------------------------------------------------------------------------- |
# Configuration::additions related to external references |
#--------------------------------------------------------------------------- |
TAGFILES = |
GENERATE_TAGFILE = |
ALLEXTERNALS = NO |
EXTERNAL_GROUPS = YES |
PERL_PATH = /usr/bin/perl |
|
#--------------------------------------------------------------------------- |
# Configuration options related to the dot tool |
#--------------------------------------------------------------------------- |
CLASS_DIAGRAMS = YES |
MSCGEN_PATH = |
HIDE_UNDOC_RELATIONS = YES |
HAVE_DOT = NO |
DOT_NUM_THREADS = 0 |
DOT_FONTNAME = Helvetica |
DOT_FONTSIZE = 10 |
DOT_FONTPATH = |
CLASS_GRAPH = YES |
COLLABORATION_GRAPH = YES |
GROUP_GRAPHS = YES |
UML_LOOK = NO |
UML_LIMIT_NUM_FIELDS = 10 |
TEMPLATE_RELATIONS = NO |
INCLUDE_GRAPH = YES |
INCLUDED_BY_GRAPH = YES |
CALL_GRAPH = NO |
CALLER_GRAPH = NO |
GRAPHICAL_HIERARCHY = YES |
DIRECTORY_GRAPH = YES |
DOT_IMAGE_FORMAT = png |
INTERACTIVE_SVG = NO |
DOT_PATH = |
DOTFILE_DIRS = |
MSCFILE_DIRS = |
DOT_GRAPH_MAX_NODES = 50 |
MAX_DOT_GRAPH_DEPTH = 0 |
DOT_TRANSPARENT = NO |
DOT_MULTI_TARGETS = NO |
GENERATE_LEGEND = YES |
DOT_CLEANUP = YES |