URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
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- This comparison shows the changes necessary to convert path
/opencpu32/trunk
- from Rev 43 to Rev 44
- ↔ Reverse comparison
Rev 43 → Rev 44
/hdl/opencpu32/testOpenCpu.vhd
141,6 → 141,13
assert good report "Could not parse the line" severity ERROR; |
mem_data_in <= instructionCode; |
|
wait until mem_rd = '0'; |
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readline(cmdfile,line_in); -- Read a line from the file |
read(line_in,instructionCode,good); -- Read the CI input |
assert good report "Could not parse the line" severity ERROR; |
mem_data_in <= instructionCode; |
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wait for CLK_period; |
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-- Finish simulation |
/hdl/opencpu32/testControlUnit.vhd
296,6 → 296,36
assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE; |
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE; |
assert outEnDp = disable report "Invalid value" severity FAILURE; |
------------------------------------------------------------------------------------------------- |
|
-- sto r2,10 (Store into memory address pointed by r2 the value 50)------------------------------ |
REPORT "STO r2,50" SEVERITY NOTE; |
MemoryDataInput <= stom_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(50, 22); |
wait for CLK_period; -- Fetch |
wait for CLK_period; -- Decode |
wait for CLK_period; -- Execute |
|
-- Write the command to a file (This will be usefull for the top Testing later) |
WRITE (line_out, MemoryDataInput); |
WRITELINE (cmdfile, line_out); |
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-- Verify if signals for the datapath are valid |
assert MemoryDataOut = conv_std_logic_vector(50, 22) report "Invalid value" severity FAILURE; |
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wait for CLK_period; -- Executing ... 1 |
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wait for CLK_period; -- Executing ... 2 |
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wait for CLK_period; -- Executing ... 3 |
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wait for CLK_period; -- Executing ... 4 |
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-- Verify memory strobe signal |
assert MemoryDataWriteEn = '1' report "Invalid value" severity FAILURE; |
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wait for CLK_period; -- Executing ... 3 |
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assert MemoryDataWriteEn = '0' report "Invalid value" severity FAILURE; |
------------------------------------------------------------------------------------------------- |
|
-- Close file |
/hdl/opencpu32/ControlUnit.vhd
79,10 → 79,11
|
-- States Fetch, decode, execute from the processor (Also handles the execution of jump instructions) |
process (currentCpuState) |
variable cyclesExecute : integer range 0 to 20; -- Cycles to wait while executing instruction |
variable cyclesExecute : integer range 0 to 20; -- Cycles to wait while executing instruction |
variable opcodeIR : std_logic_vector(5 downto 0); |
variable operand_reg1 : std_logic_vector(3 downto 0); |
variable operand_imm : std_logic_vector(21 downto 0); |
variable accDp : std_logic_vector(n downto 0); -- Value stored from DataPath |
begin |
opcodeIR := IR((IR'HIGH) downto (IR'HIGH - 5)); |
operand_reg1 := IR((IR'HIGH - 6) downto (IR'HIGH - 9)); -- 4 bits register operand1 (Max 16 registers) |
105,6 → 106,7
MemoryDataRdAddr <= PC; -- Warning PC is not 1 yet... |
IR <= MemoryDataInput; |
MemoryDataReadEn <= '1'; |
MemoryDataWriteEn <= '0'; |
nextCpuState <= decode; |
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-- Detect with instruction came from memory, set the number of cycles to execute... |
114,10 → 116,15
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-- The high attribute points to the highes bit position |
case opcodeIR is |
when mov_reg | mov_val | add_reg | add_val | sub_reg | and_reg | or_reg | xor_reg | ld_reg | ld_val | stom_reg | stom_val => |
when mov_reg | mov_val | add_reg | add_val | sub_reg | and_reg | or_reg | xor_reg => |
nextCpuState <= execute; |
cyclesExecute := 1; -- Wait 1 cycles |
currInstruction <= IR; |
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when ld_reg | ld_val | stom_reg | stom_val => |
nextCpuState <= execute; |
cyclesExecute := 2; -- Wait 2 cycles |
currInstruction <= IR; |
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when jmp_val | jmpr_val => |
nextCpuState <= execute; |
143,11 → 150,18
MemoryDataRdAddr <= "0000000000" & operand_imm; |
MemoryDataReadEn <= '1'; |
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-- STORE r1,10 (Store the value on r1 in the main memory located at address 10) |
when stom_val => |
MemoryDataWrAddr <= "0000000000" & operand_imm; |
MemoryDataWriteEn <= '1'; |
MemoryDataOut <= DataDp; |
-- STORE r1,10 (Store the value 10 on memory address pointed by r1) |
when stom_val => |
-- And put the imediate value ... |
MemoryDataOut <= "0000000000" & operand_imm; |
if cyclesExecute = 1 then |
-- After the register data is avaible in DataDp we put it's address and |
accDp := DataDp; |
MemoryDataWrAddr <= accDp; |
elsif cyclesExecute = 0 then |
-- strobe in to enter the data |
MemoryDataWriteEn <= '1'; |
end if; |
|
when others => |
null; |
157,13 → 171,13
-- Finish the instruction execution get next |
nextCpuState <= fetch; |
else |
nextCpuState <= executing; |
nextCpuState <= executing; |
end if; |
|
-- Just wait a cycle and back again to execute state which verify if still need to wait some cycles |
when executing => |
cyclesExecute := cyclesExecute - 1; |
nextCpuState <= execute; |
nextCpuState <= execute; |
|
when others => |
null; |
191,7 → 205,7
|
when waitToExecute => |
if ( (currentCpuState /= execute) and (currentCpuState /= executing) ) then |
nextExState <= initInstructionExecution; |
nextExState <= initInstructionExecution; |
else |
case opcodeIR is |
-- MOV r2,r1 (See the testDatapath to see how to drive the datapath for this function) |
209,14 → 223,13
-- The part that interface with the memory is located on the first process |
nextExState <= writeRegister; |
|
-- STORE r1,10 (Store the value on r1 in the main memory located at address 10) |
-- STORE r1,10 (Store the value 10 on the main memory pointed by r1) |
when stom_val => |
MuxDp <= fromRegFileB; |
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); |
DpRegFileReadEnB <= '1'; |
nextExState <= readRegisterB; |
DpRegFileReadEnB <= '1'; |
-- The part that interface with the memory is located on the first process |
nextExState <= readRegisterB; |
nextExState <= readRegisterB; |
|
-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function) |
when add_reg | sub_reg | and_reg | or_reg | xor_reg => |
/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/opencpu32/hdl/opencpu32/openCpu.vhd" into library work</arg> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/laraujo/work/opencpu32/hdl/opencpu32/testOpenCpu.vhd" into library work</arg> |
</msg> |
|
</messages> |
/hdl/opencpu32/opencpu32.gise
234,7 → 234,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334652206" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334652206"> |
<transform xil_pn:end_ts="1334673019" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334673019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="Alu.vhd"/> |
254,11 → 254,11
<outfile xil_pn:name="testRegisterFile.vhd"/> |
<outfile xil_pn:name="testTriStateBuffer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1334653088" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334653088"> |
<transform xil_pn:end_ts="1334672343" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334672343"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334653088" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334653088"> |
<transform xil_pn:end_ts="1334672343" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334672343"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
266,7 → 266,7
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334652206" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334652206"> |
<transform xil_pn:end_ts="1334673019" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334673019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="Alu.vhd"/> |
286,7 → 286,7
<outfile xil_pn:name="testRegisterFile.vhd"/> |
<outfile xil_pn:name="testTriStateBuffer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1334653090" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334653088"> |
<transform xil_pn:end_ts="1334673021" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334673019"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
298,7 → 298,7
<outfile xil_pn:name="testOpenCpu_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1334653090" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334653090"> |
<transform xil_pn:end_ts="1334673021" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334673021"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="isim.cmd"/> |
/hdl/opencpu32/testCode/testCodeBin.dat
3,3 → 3,5
00000000100001000000000000000000 |
01101100100000000000000000000000 |
01110000100000000000000000000010 |
01110000100000000000000000000010 |
01110000100000000000000000000010 |