URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
Compare Revisions
- This comparison shows the changes necessary to convert path
/opencpu32/trunk
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/tools/jd-gui-0.3.3.linux.i686.tar.gz
Cannot display: file marked as a binary type.
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tools/jd-gui-0.3.3.linux.i686.tar.gz
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+application/octet-stream
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Index: tools/README
===================================================================
--- tools/README (nonexistent)
+++ tools/README (revision 8)
@@ -0,0 +1,2 @@
+Running ProcSim Mips2000 simulator
+java -cp ProcSim.jar:xercesImpl.jar:xml-apis.jar:. ProcSim
Index: hdl/opencpu32/_xmsgs/pn_parser.xmsgs
===================================================================
--- hdl/opencpu32/_xmsgs/pn_parser.xmsgs (revision 7)
+++ hdl/opencpu32/_xmsgs/pn_parser.xmsgs (revision 8)
@@ -1,15 +1,12 @@
-
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-
-
-
-Parsing VHDL file "E:/opencpu32/hdl/opencpu32/Multiplexer2_1.vhd" into library work
-
-
-
-
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+
Index: hdl/opencpu32/pkgOpenCPU32.vhd
===================================================================
--- hdl/opencpu32/pkgOpenCPU32.vhd (revision 7)
+++ hdl/opencpu32/pkgOpenCPU32.vhd (revision 8)
@@ -8,7 +8,9 @@
package pkgOpenCPU32 is
--! Declare constants, enums, functions used by the design
-constant nBits : integer := 32;
+constant nBits : integer := 32;
+
+type aluOps is (alu_sum, alu_sub, alu_inc, alu_dec, alu_mul, alu_or, alu_and, alu_xor, alu_not);
end pkgOpenCPU32;
/hdl/opencpu32/Alu.vhd
1,21 → 1,24
--! @file |
--! @brief Arithmetic logic unit http://en.wikipedia.org/wiki/Arithmetic_logic_unit |
|
--! Use standard library |
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith) |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.std_logic_arith.all; |
|
--! Use CPU Definitions package |
library pkgOpenCPU32; |
use work.pkgOpenCPU32.all; |
|
--! ALU is a digital circuit that performs arithmetic and logical operations. |
|
--! ALU is a digital circuit that performs arithmetic and logical operations. It's the fundamental part of the CPU |
entity Alu is |
Port ( A : in STD_LOGIC_VECTOR (7 downto 0); --! Alu Operand 1 |
B : in STD_LOGIC_VECTOR (7 downto 0); --! Alu Operand 2 |
S : out STD_LOGIC_VECTOR (7 downto 0); --! Alu Output |
sel : in STD_LOGIC_VECTOR (2 downto 0)); --! Select operation |
generic (n : integer := nBits - 1); |
Port ( A : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 1 |
B : in STD_LOGIC_VECTOR (n downto 0); --! Alu Operand 2 |
S : out STD_LOGIC_VECTOR (n downto 0); --! Alu Output |
sel : in aluOps); --! Select operation |
end Alu; |
|
--! @brief Architure definition of the ALU |
23,7 → 26,35
architecture Behavioral of Alu is |
|
begin |
--! Behavior description of combinational circuit (Can not infer any FF(Flip flop)) |
process (A,B,sel) is |
begin |
case sel is |
when alu_sum => |
S <= A + B; |
|
when alu_sub => |
S <= A - B; |
|
when alu_inc => |
S <= A - B; |
|
when alu_dec => |
S <= A - B; |
|
when alu_and => |
S <= A and B; |
|
when alu_or => |
S <= A or B; |
|
when alu_xor => |
S <= A xor B; |
|
when others => |
S <= (others => 'Z'); |
end case; |
end process; |
|
|
end Behavioral; |
|
/hdl/opencpu32/opencpu32.gise
21,8 → 21,167
|
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="opencpu32.xise"/> |
|
<files xmlns="http://www.xilinx.com/XMLSchema"/> |
<files xmlns="http://www.xilinx.com/XMLSchema"> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="Alu.bld"/> |
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Alu.cmd_log"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Alu.lso"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Alu.ncd" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="Alu.ngc"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="Alu.ngd"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="Alu.ngr"/> |
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="Alu.pad"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="Alu.par" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="Alu.pcf" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Alu.prj"/> |
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="Alu.ptwx"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="Alu.stx"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Alu.syr"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="Alu.twr" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="Alu.twx" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="Alu.unroutes" xil_pn:subbranch="Par"/> |
<file xil_pn:fileType="FILE_XPI" xil_pn:name="Alu.xpi"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Alu.xst"/> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="Alu_fpga_editor.log"/> |
<file xil_pn:fileType="FILE_NCD" xil_pn:name="Alu_guide.ncd" xil_pn:origination="imported"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Alu_map.map" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="Alu_map.mrp" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="Alu_map.ncd" xil_pn:subbranch="Map"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="Alu_map.ngm" xil_pn:subbranch="Map"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_map.xrpt"/> |
<file xil_pn:fileType="FILE_LOG" xil_pn:name="Alu_map_fpga_editor.log"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_ngdbuild.xrpt"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="Alu_pad.csv" xil_pn:subbranch="Par"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="Alu_pad.txt" xil_pn:subbranch="Par"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_par.xrpt"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Alu_summary.html"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="Alu_summary.xml"/> |
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="Alu_usage.xml"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Alu_xst.xrpt"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> |
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> |
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> |
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/> |
</files> |
|
<transforms xmlns="http://www.xilinx.com/XMLSchema"/> |
<transforms xmlns="http://www.xilinx.com/XMLSchema"> |
<transform xil_pn:end_ts="1332929336" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1332929336"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332929336" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-7863675631946613945" xil_pn:start_ts="1332929336"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332929336" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8637507079216041037" xil_pn:start_ts="1332929336"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332929336" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1332929336"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332929336" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2964161847311656507" xil_pn:start_ts="1332929336"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332929336" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3893270297158069842" xil_pn:start_ts="1332929336"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332929336" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="319318766057190551" xil_pn:start_ts="1332929336"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1332940635" xil_pn:in_ck="8015792819232243152" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-7168533952405101494" xil_pn:start_ts="1332940626"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="Alu.lso"/> |
<outfile xil_pn:name="Alu.ngc"/> |
<outfile xil_pn:name="Alu.ngr"/> |
<outfile xil_pn:name="Alu.prj"/> |
<outfile xil_pn:name="Alu.stx"/> |
<outfile xil_pn:name="Alu.syr"/> |
<outfile xil_pn:name="Alu.xst"/> |
<outfile xil_pn:name="Alu_xst.xrpt"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1332956929" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-1210076599156103590" xil_pn:start_ts="1332956929"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputAdded"/> |
</transform> |
<transform xil_pn:end_ts="1332956936" xil_pn:in_ck="88312569576" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3676465938101052346" xil_pn:start_ts="1332956929"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputAdded"/> |
<outfile xil_pn:name="Alu.bld"/> |
<outfile xil_pn:name="Alu.ngd"/> |
<outfile xil_pn:name="Alu_ngdbuild.xrpt"/> |
<outfile xil_pn:name="_ngo"/> |
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1332956943" xil_pn:in_ck="88312569577" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-5849673150125579957" xil_pn:start_ts="1332956936"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputAdded"/> |
<outfile xil_pn:name="Alu.pcf"/> |
<outfile xil_pn:name="Alu_map.map"/> |
<outfile xil_pn:name="Alu_map.mrp"/> |
<outfile xil_pn:name="Alu_map.ncd"/> |
<outfile xil_pn:name="Alu_map.ngm"/> |
<outfile xil_pn:name="Alu_map.xrpt"/> |
<outfile xil_pn:name="Alu_summary.xml"/> |
<outfile xil_pn:name="Alu_usage.xml"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
</transform> |
<transform xil_pn:end_ts="1332956956" xil_pn:in_ck="104733817618758274" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1332956943"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputAdded"/> |
<outfile xil_pn:name="Alu.ncd"/> |
<outfile xil_pn:name="Alu.pad"/> |
<outfile xil_pn:name="Alu.par"/> |
<outfile xil_pn:name="Alu.ptwx"/> |
<outfile xil_pn:name="Alu.unroutes"/> |
<outfile xil_pn:name="Alu.xpi"/> |
<outfile xil_pn:name="Alu_pad.csv"/> |
<outfile xil_pn:name="Alu_pad.txt"/> |
<outfile xil_pn:name="Alu_par.xrpt"/> |
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
</transform> |
<transform xil_pn:in_ck="88312569445" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1332957009"> |
<status xil_pn:value="ExecutingRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputAdded"/> |
</transform> |
<transform xil_pn:end_ts="1332956956" xil_pn:in_ck="88312569445" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1332956953"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="InputAdded"/> |
<outfile xil_pn:name="Alu.twr"/> |
<outfile xil_pn:name="Alu.twx"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
</transform> |
</transforms> |
|
</generated_project> |
/hdl/opencpu32/opencpu32.xise
25,8 → 25,11
</file> |
<file xil_pn:name="Multiplexer2_1.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="Alu.ucf" xil_pn:type="FILE_UCF"> |
<association xil_pn:name="Implementation" xil_pn:seqID="48"/> |
</file> |
</files> |
|
<properties> |
53,7 → 56,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/> |
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> |
275,6 → 278,7
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Target UCF File Name" xil_pn:value="Alu.ucf" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |