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URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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  • This comparison shows the changes necessary to convert path 
    /opencpu32
    from Rev 33 to Rev 34
    ↔ Reverse comparison
  •

Rev 33 → Rev 34

/trunk/hdl/opencpu32/opencpu32.xise
325,7 → 325,7
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="200 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="400 ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
/trunk/hdl/opencpu32/ControlUnit.vhd
116,12 → 116,12
case opcodeIR is
when mov_reg | mov_val | add_reg | sub_reg | and_reg | or_reg | xor_reg | ld_reg | ld_val | stom_reg | stom_val =>
nextCpuState <= execute;
cyclesExecute := 3; -- Wait 3 cycles for mov operation
cyclesExecute := 1; -- Wait 1 cycles
currInstruction <= IR;
when jmp_val | jmpr_val =>
nextCpuState <= execute;
cyclesExecute := 1;
cyclesExecute := 0; -- No Wait cycle
-- Invalid instruction (Now will be ignored, but latter should raise a trap
when others =>
275,7 → 275,7
DpRegFileWriteEn <= '0';
outEnDp <= disable;
-- Come back to waiting state
nextExState <= waitToExecute;
nextExState <= waitToExecute;
when others =>
null;
/trunk/hdl/opencpu32/testControlUnit.vhd
128,9 → 128,28
wait for CLK_period; -- Fetch
wait for CLK_period; -- Decode
wait for CLK_period; -- Execute
-- Verify if signals for the datapath are valid
assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;
assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 1
wait for CLK_period; -- Executing ... 2
-- State writing on the registers
assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)
-- Verify if all lines are unasserted
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
assert outEnDp = disable report "Invalid value" severity FAILURE;
-------------------------------------------------------------------------------------------------
-- MOV r1,20d (Compare control unit outputs with Datapath)--------------------------------------
REPORT "MOV r1,20" SEVERITY NOTE;
MemoryDataInput <= mov_val & conv_std_logic_vector(reg2Num(r1),4) & conv_std_logic_vector(20, 22);
137,10 → 156,89
wait for CLK_period; -- Fetch
wait for CLK_period; -- Decode
wait for CLK_period; -- Execute
-- Verify if signals for the datapath are valid
assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;
assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 1
wait for CLK_period; -- Executing ... 2
-- State writing on the registers
assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)
-- Verify if all lines are unasserted
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
assert outEnDp = disable report "Invalid value" severity FAILURE;
-------------------------------------------------------------------------------------------------
-- MOV r2,r1 (Compare control unit outputs with Datapath)--------------------------------------
REPORT "MOV r2,r1" SEVERITY NOTE;
MemoryDataInput <= mov_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r1),4) & "000000000000000000";
wait for CLK_period; -- Fetch
wait for CLK_period; -- Decode
wait for CLK_period; -- Execute
-- Verify if signals for the datapath are valid
assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;
assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 1
-- State writing on the registers
assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)
-- Verify if all lines are unasserted
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
assert outEnDp = disable report "Invalid value" severity FAILURE;
-------------------------------------------------------------------------------------------------
-- ADD r2,r0 (Compare control unit outputs with Datapath)--------------------------------------
REPORT "ADD r2,r0" SEVERITY NOTE;
MemoryDataInput <= add_reg & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(reg2Num(r0),4) & "000000000000000000";
wait for CLK_period; -- Fetch
wait for CLK_period; -- Decode
wait for CLK_period; -- Execute
-- Verify if signals for the datapath are valid
assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;
assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;
assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnA = '1' report "Invalid value" severity FAILURE;
assert MuxRegDp = muxRegPos(fromRegFileA) report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 1
-- State writing on the registers
assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...)
-- Verify if all lines are unasserted
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE;
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE;
assert outEnDp = disable report "Invalid value" severity FAILURE;
-------------------------------------------------------------------------------------------------
 
wait;
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
wait;
end process;
 
END;
/trunk/hdl/opencpu32/opencpu32.gise
222,7 → 222,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334428831" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334428831">
<transform xil_pn:end_ts="1334437962" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334437962">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
253,7 → 253,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334428831" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334428831">
<transform xil_pn:end_ts="1334437962" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334437962">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
272,7 → 272,7
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334428834" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2461943258679370096" xil_pn:start_ts="1334428831">
<transform xil_pn:end_ts="1334437965" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2461943258679370096" xil_pn:start_ts="1334437962">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="fuse.log"/>
282,7 → 282,7
<outfile xil_pn:name="testControlUnit_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1334428834" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7818598284332786958" xil_pn:start_ts="1334428834">
<transform xil_pn:end_ts="1334437965" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5692602031942061840" xil_pn:start_ts="1334437965">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>

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