URL
https://opencores.org/ocsvn/opencpu32/opencpu32/trunk
Subversion Repositories opencpu32
Compare Revisions
- This comparison shows the changes necessary to convert path
/opencpu32
- from Rev 34 to Rev 35
- ↔ Reverse comparison
Rev 34 → Rev 35
/trunk/hdl/opencpu32/ControlUnit.vhd
114,7 → 114,7
|
-- The high attribute points to the highes bit position |
case opcodeIR is |
when mov_reg | mov_val | add_reg | sub_reg | and_reg | or_reg | xor_reg | ld_reg | ld_val | stom_reg | stom_val => |
when mov_reg | mov_val | add_reg | add_val | sub_reg | and_reg | or_reg | xor_reg | ld_reg | ld_val | stom_reg | stom_val => |
nextCpuState <= execute; |
cyclesExecute := 1; -- Wait 1 cycles |
currInstruction <= IR; |
/trunk/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
|
<messages> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/opencpu32/hdl/opencpu32/testControlUnit.vhd" into library work</arg> |
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "E:/opencpu32/hdl/opencpu32/ControlUnit.vhd" into library work</arg> |
</msg> |
|
</messages> |
/trunk/hdl/opencpu32/testControlUnit.vhd
235,6 → 235,37
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE; |
assert outEnDp = disable report "Invalid value" severity FAILURE; |
------------------------------------------------------------------------------------------------- |
|
-- ADD r2,2 (Compare control unit outputs with Datapath)-------------------------------------- |
REPORT "ADD r2,2" SEVERITY NOTE; |
MemoryDataInput <= add_val & conv_std_logic_vector(reg2Num(r2),4) & conv_std_logic_vector(2, 22); |
wait for CLK_period; -- Fetch |
wait for CLK_period; -- Decode |
wait for CLK_period; -- Execute |
|
-- Verify if signals for the datapath are valid |
assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE; |
assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE; |
assert DpAluOp = alu_sum report "Invalid value" severity FAILURE; |
assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE; |
assert MuxRegDp = muxRegPos(fromImediate) report "Invalid value" severity FAILURE; |
assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE; |
assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE; |
|
wait for CLK_period; -- Executing ... 1 |
|
-- State writing on the registers |
assert DpRegFileWriteEn = '1' report "Invalid value" severity FAILURE; |
|
wait for CLK_period; -- Executing ...2 (Releasing lines.... (Next instruction should come...) |
|
-- Verify if all lines are unasserted |
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE; |
assert DpRegFileReadEnB = '0' report "Invalid value" severity FAILURE; |
assert DpRegFileReadEnA = '0' report "Invalid value" severity FAILURE; |
assert DpRegFileWriteEn = '0' report "Invalid value" severity FAILURE; |
assert outEnDp = disable report "Invalid value" severity FAILURE; |
------------------------------------------------------------------------------------------------- |
|
-- Finish simulation |
assert false report "NONE. End of simulation." severity failure; |
/trunk/hdl/opencpu32/opencpu32.gise
196,6 → 196,7
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="openCpu.stx"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="openCpu.syr"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="openCpu.xst"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="openCpu_envsettings.html"/> |
<file xil_pn:fileType="FILE_HTML" xil_pn:name="openCpu_summary.html"/> |
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="openCpu_vhdl.prj"/> |
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="openCpu_xst.xrpt"/> |
222,9 → 223,13
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334437962" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334437962"> |
<transform xil_pn:end_ts="1334439044" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334439044"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="Alu.vhd"/> |
<outfile xil_pn:name="ControlUnit.vhd"/> |
<outfile xil_pn:name="DataPath.vhd"/> |
253,9 → 258,14
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1334437962" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334437962"> |
<transform xil_pn:end_ts="1334439044" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334439044"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="Alu.vhd"/> |
<outfile xil_pn:name="ControlUnit.vhd"/> |
<outfile xil_pn:name="DataPath.vhd"/> |
272,9 → 282,14
<outfile xil_pn:name="testRegisterFile.vhd"/> |
<outfile xil_pn:name="testTriStateBuffer.vhd"/> |
</transform> |
<transform xil_pn:end_ts="1334437965" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2461943258679370096" xil_pn:start_ts="1334437962"> |
<transform xil_pn:end_ts="1334439047" xil_pn:in_ck="5551394544742288633" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-2461943258679370096" xil_pn:start_ts="1334439044"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="fuse.log"/> |
<outfile xil_pn:name="isim"/> |
<outfile xil_pn:name="isim.log"/> |
282,9 → 297,12
<outfile xil_pn:name="testControlUnit_isim_beh.exe"/> |
<outfile xil_pn:name="xilinxsim.ini"/> |
</transform> |
<transform xil_pn:end_ts="1334437965" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5692602031942061840" xil_pn:start_ts="1334437965"> |
<transform xil_pn:end_ts="1334439047" xil_pn:in_ck="4949781681609100681" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5692602031942061840" xil_pn:start_ts="1334439047"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="isim.cmd"/> |
<outfile xil_pn:name="isim.log"/> |
<outfile xil_pn:name="testControlUnit_isim_beh.wdb"/> |
317,12 → 335,10
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
</transform> |
<transform xil_pn:end_ts="1333983326" xil_pn:in_ck="-3059529097558291903" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-1259764691931299582" xil_pn:start_ts="1333983316"> |
<transform xil_pn:end_ts="1334481587" xil_pn:in_ck="-3059529097558291903" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="-1259764691931299582" xil_pn:start_ts="1334481574"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="InputChanged"/> |
<outfile xil_pn:name=".lso"/> |
<outfile xil_pn:name="Alu.ngr"/> |
<outfile xil_pn:name="ControlUnit.ngr"/> |