OpenCores
URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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  • This comparison shows the changes necessary to convert path 
    /opencpu32
    from Rev 41 to Rev 42
    ↔ Reverse comparison
  •

Rev 41 → Rev 42

/trunk/hdl/opencpu32/opencpu32.xise
119,7 → 119,7
<property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
/trunk/hdl/opencpu32/testOpenCpu.vhd
99,49 → 99,43
rst <= '1';
wait for 2 ns;
rst <= '0';
wait for 2 ns;
 
wait until mem_rd = '1';
wait for 2 ns;
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
wait for CLK_period;
wait until mem_rd = '1';
mem_data_in <= instructionCode;
 
wait until mem_rd = '0';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
 
wait for CLK_period;
wait until mem_rd = '1';
wait until mem_rd = '0';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
mem_data_in <= instructionCode;
wait for CLK_period;
wait until mem_rd = '0';
wait until mem_rd = '1';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
wait for CLK_period;
wait until mem_rd = '0';
wait until mem_rd = '1';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
wait for CLK_period;
wait until mem_rd = '0';
wait until mem_rd = '1';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
/trunk/hdl/opencpu32/openCpu.vhd
36,7 → 36,7
clk : in STD_LOGIC; --! Clock signal
outEn : in typeEnDis; --! Enable/Disable datapath output
aluOp : in aluOps; --! Alu operations
muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
regFileWriteAddr : in generalRegisters; --! General register write address
regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
55,7 → 55,7
FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
outEnDp : out typeEnDis; --! Enable/Disable datapath output
MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
DpAluOp : out aluOps; --! Alu operations
76,7 → 76,7
signal InputImediate : STD_LOGIC_VECTOR (n downto 0);
signal enableOutputDp : typeEnDis;
signal aluOperations : aluOps;
signal InputDataPathSelector : STD_LOGIC_VECTOR (2 downto 0);
signal InputDataPathSelector : dpMuxInputs;
signal InputDataPathAluASelector : STD_LOGIC_VECTOR (1 downto 0);
signal registerFileWriteAddress : generalRegisters;
signal registerFileWriteEnable : STD_LOGIC;
/trunk/hdl/opencpu32/testMultiplexer4_1.vhd
26,7 → 26,7
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
sel : in dpMuxInputs; --! Select inputs (1, 2, 3, 4, 5)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
END COMPONENT;
37,7 → 37,7
signal C : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal D : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal E : std_logic_vector((nBits - 1) downto 0) := (others => '0'); --! Wire to connect Test signal to component
signal sel : STD_LOGIC_VECTOR (2 downto 0) := "000"; --! Wire to connect Test signal to component
signal sel : dpMuxInputs := fromMemory; --! Wire to connect Test signal to component
 
--Outputs
signal S : std_logic_vector((nBits - 1) downto 0); --! Wire to connect Test signal to component
61,7 → 61,7
-- Sel 0 ---------------------------------------------------------------------------
wait for 1 ps;
REPORT "Select first channel" SEVERITY NOTE;
sel <= "000";
sel <= fromMemory;
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
73,7 → 73,7
-- Sel 1 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select second channel" SEVERITY NOTE;
sel <= "001";
sel <= fromImediate;
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
85,7 → 85,7
-- Sel 2 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select third channel" SEVERITY NOTE;
sel <= "010";
sel <= fromRegFileA;
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
97,7 → 97,7
-- Sel 3 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select forth channel" SEVERITY NOTE;
sel <= "011";
sel <= fromRegFileB;
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
109,7 → 109,7
-- Sel 4 ---------------------------------------------------------------------------
wait for 1 ns;
REPORT "Select fifth channel" SEVERITY NOTE;
sel <= "100";
sel <= fromAlu;
A <= conv_std_logic_vector(0, nBits);
B <= conv_std_logic_vector(1000, nBits);
C <= conv_std_logic_vector(2000, nBits);
/trunk/hdl/opencpu32/Multiplexer4_1.vhd
19,7 → 19,7
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
sel : in dpMuxInputs; --! Select inputs (1, 2, 3, 4, 5)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
end Multiplexer4_1;
 
29,11 → 29,11
 
begin
with sel select
S <= A when "000",
B when "001",
C when "010",
D when "011",
E when "100",
S <= A when fromMemory,
B when fromImediate,
C when fromRegFileA,
D when fromRegFileB,
E when fromAlu,
(others => 'Z') when others;
 
end Behavioral;
/trunk/hdl/opencpu32/testControlUnit.vhd
35,7 → 35,7
FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
outEnDp : out typeEnDis; --! Enable/Disable datapath output
MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
DpAluOp : out aluOps; --! Alu operations
63,7 → 63,7
 
--Outputs
signal outEnDp : typeEnDis; --! Wire to connect Test signal to component
signal MuxDp : std_logic_vector(2 downto 0); --! Wire to connect Test signal to component
signal MuxDp : dpMuxInputs; --! Wire to connect Test signal to component
signal MuxRegDp : std_logic_vector(1 downto 0); --! Wire to connect Test signal to component
signal ImmDp : std_logic_vector(n downto 0); --! Wire to connect Test signal to component
signal DpAluOp : aluOps; --! Wire to connect Test signal to component
148,7 → 148,7
assert ImmDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
assert DpRegFileWriteAddr = r0 report "Invalid value" severity FAILURE;
assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
assert MuxDp = fromImediate report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 1
180,7 → 180,7
assert ImmDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
assert DpRegFileWriteAddr = r1 report "Invalid value" severity FAILURE;
assert DpAluOp = alu_pass report "Invalid value" severity FAILURE;
assert MuxDp = muxPos(fromImediate) report "Invalid value" severity FAILURE;
assert MuxDp = fromImediate report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 1
211,7 → 211,7
-- Verify if signals for the datapath are valid
assert DpRegFileReadAddrB = r1 report "Invalid value" severity FAILURE;
assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
assert MuxDp = muxPos(fromRegFileB) report "Invalid value" severity FAILURE;
assert MuxDp = fromRegFileB report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
wait for CLK_period; -- Executing ... 1
243,7 → 243,7
assert DpRegFileReadAddrB = r0 report "Invalid value" severity FAILURE;
assert DpRegFileReadAddrA = r2 report "Invalid value" severity FAILURE;
assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
assert MuxDp = fromAlu report "Invalid value" severity FAILURE;
assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
assert DpRegFileReadEnA = '1' report "Invalid value" severity FAILURE;
278,7 → 278,7
assert ImmDp = conv_std_logic_vector(2, nBits) report "Invalid value" severity FAILURE;
assert DpRegFileWriteAddr = r2 report "Invalid value" severity FAILURE;
assert DpAluOp = alu_sum report "Invalid value" severity FAILURE;
assert MuxDp = muxPos(fromAlu) report "Invalid value" severity FAILURE;
assert MuxDp = fromAlu report "Invalid value" severity FAILURE;
assert MuxRegDp = muxRegPos(fromImediate) report "Invalid value" severity FAILURE;
assert DpRegFileReadAddrB = r2 report "Invalid value" severity FAILURE;
assert DpRegFileReadEnB = '1' report "Invalid value" severity FAILURE;
/trunk/hdl/opencpu32/ControlUnit.vhd
23,7 → 23,7
FlagsDp : in STD_LOGIC_VECTOR (2 downto 0); --! Flags comming from the Datapath
DataDp : in STD_LOGIC_VECTOR (n downto 0); --! Data comming from the Datapath
outEnDp : out typeEnDis; --! Enable/Disable datapath output
MuxDp : out STD_LOGIC_VECTOR (2 downto 0); --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxDp : out dpMuxInputs; --! Select on datapath data from (Memory, Imediate, RegFileA, RegFileB, AluOut)
MuxRegDp : out STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
ImmDp : out STD_LOGIC_VECTOR (n downto 0); --! Imediate value passed to the Datapath
DpAluOp : out aluOps; --! Alu operations
196,7 → 196,7
case opcodeIR is
-- MOV r2,r1 (See the testDatapath to see how to drive the datapath for this function)
when mov_reg =>
MuxDp <= muxPos(fromRegFileB);
MuxDp <= fromRegFileB;
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2)));
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
DpRegFileReadEnB <= '1';
204,7 → 204,7
-- LOAD r1,10 (Load into r1, the value in the main memory located at address 10)
when ld_val =>
MuxDp <= muxPos(fromMemory);
MuxDp <= fromMemory;
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
-- The part that interface with the memory is located on the first process
nextExState <= writeRegister;
211,7 → 211,7
-- STORE r1,10 (Store the value on r1 in the main memory located at address 10)
when stom_val =>
MuxDp <= muxPos(fromRegFileB);
MuxDp <= fromRegFileB;
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
DpRegFileReadEnB <= '1';
nextExState <= readRegisterB;
220,7 → 220,7
-- ADD r2,r0 (See the testDatapath to see how to drive the datapath for this function)
when add_reg | sub_reg | and_reg | or_reg | xor_reg =>
MuxDp <= muxPos(fromAlu);
MuxDp <= fromAlu;
MuxRegDp <= muxRegPos(fromRegFileA);
DpRegFileReadAddrA <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg2))); -- Read second operand
232,7 → 232,7
-- MOV r0,10d (See the testDatapath to see how to drive the datapath for this function)
when mov_val =>
MuxDp <= muxPos(fromImediate);
MuxDp <= fromImediate;
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
ImmDp <= "0000000000" & operand_imm; -- & is used to concatenate signals
nextExState <= writeRegister;
239,7 → 239,7
 
-- ADD r3,2 (r2 <= r2+2) (See the testDatapath to see how to drive the datapath for this function)
when add_val | sub_val | and_val | or_val | xor_val =>
MuxDp <= muxPos(fromAlu);
MuxDp <= fromAlu;
MuxRegDp <= muxRegPos(fromImediate);
DpRegFileWriteAddr <= Num2reg(conv_integer(UNSIGNED(operand_reg1)));
DpRegFileReadAddrB <= Num2reg(conv_integer(UNSIGNED(operand_reg1))); -- Read first operand
/trunk/hdl/opencpu32/_xmsgs/pn_parser.xmsgs
1,15 → 1,15
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/opencpu32/hdl/opencpu32/testControlUnit.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/laraujo/work/opencpu32/hdl/opencpu32/openCpu.vhd&quot; into library work</arg>
</msg>
 
</messages>
 
/trunk/hdl/opencpu32/opencpu32.gise
137,7 → 137,17
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Multiplexer2_1_summary.html"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Multiplexer2_1_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Multiplexer2_1_xst.xrpt"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Multiplexer4_1.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Multiplexer4_1.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="Multiplexer4_1.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="Multiplexer4_1.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Multiplexer4_1.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="Multiplexer4_1.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Multiplexer4_1.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Multiplexer4_1.xst"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Multiplexer4_1_isim_beh.exe"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Multiplexer4_1_summary.html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Multiplexer4_1_xst.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="RegisterFile.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="RegisterFile.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="RegisterFile.lso"/>
224,7 → 234,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334614779" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334614779">
<transform xil_pn:end_ts="1334652206" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334652206">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
244,19 → 254,19
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334614520" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334614520">
<transform xil_pn:end_ts="1334652206" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334652206">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334614520" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334614520">
<transform xil_pn:end_ts="1334652206" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334652206">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334403515" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1334403515">
<transform xil_pn:end_ts="1334652206" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1334652206">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334614779" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334614779">
<transform xil_pn:end_ts="1334652206" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334652206">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
276,9 → 286,11
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334614782" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334614779">
<transform xil_pn:end_ts="1334652208" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334652206">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
286,7 → 298,7
<outfile xil_pn:name="testOpenCpu_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1334614782" xil_pn:in_ck="-7416607345915100494" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334614782">
<transform xil_pn:end_ts="1334652208" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334652208">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
297,40 → 309,51
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1333982866" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6268642977942111103" xil_pn:start_ts="1333982866">
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<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1334652101" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-553081000213050619" xil_pn:start_ts="1334652101">
<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="SuccessfullyRun"/>
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<transform xil_pn:end_ts="1334652101" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4767545221551224753" xil_pn:start_ts="1334652101">
<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name=".lso"/>
<outfile xil_pn:name="Alu.ngr"/>
<outfile xil_pn:name="ControlUnit.ngr"/>
<outfile xil_pn:name="DataPath.ngr"/>
<outfile xil_pn:name="Multiplexer4_1.ngr"/>
<outfile xil_pn:name="RegisterFile.ngr"/>
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/trunk/hdl/opencpu32/DataPath.vhd
22,7 → 22,7
clk : in STD_LOGIC; --! Clock signal
outEn : in typeEnDis; --! Enable/Disable datapath output
aluOp : in aluOps; --! Alu operations
muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
regFileWriteAddr : in generalRegisters; --! General register write address
regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
46,7 → 46,7
C : in STD_LOGIC_VECTOR (n downto 0); --! Third Input
D : in STD_LOGIC_VECTOR (n downto 0); --! Forth Input
E : in STD_LOGIC_VECTOR (n downto 0); --! Fifth Input
sel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs (1, 2, 3, 4, 5)
sel : in dpMuxInputs; --! Select inputs (1, 2, 3, 4, 5)
S : out STD_LOGIC_VECTOR (n downto 0)); --! Mux Output
END COMPONENT;
 
/trunk/hdl/opencpu32/testDataPath.vhd
27,7 → 27,7
clk : in STD_LOGIC; --! Clock signal
outEn : in typeEnDis; --! Enable/Disable datapath output
aluOp : in aluOps; --! Alu operations
muxSel : in STD_LOGIC_VECTOR (2 downto 0); --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxSel : in dpMuxInputs; --! Select inputs from dataPath(Memory,Imediate,RegisterFile,Alu)
muxRegFile : in STD_LOGIC_VECTOR(1 downto 0); --! Select Alu InputA (Memory,Imediate,RegFileA)
regFileWriteAddr : in generalRegisters; --! General register write address
regFileWriteEn : in STD_LOGIC; --! RegisterFile write enable signal
46,7 → 46,7
signal clk : std_logic := '0'; --! Wire to connect Test signal to component
signal outEn : typeEnDis := disable; --! Wire to connect Test signal to component
signal aluOp : aluOps := alu_pass; --! Wire to connect Test signal to component
signal muxSel : std_logic_vector(2 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
signal muxSel : dpMuxInputs := fromMemory; --! Wire to connect Test signal to component
signal muxRegFile : std_logic_vector(1 downto 0) := (others => 'U'); --! Wire to connect Test signal to component
signal regFileWriteAddr : generalRegisters := r0; --! Wire to connect Test signal to component
signal regFileWriteEn : std_logic := '0'; --! Wire to connect Test signal to component
100,7 → 100,7
inputImm <= conv_std_logic_vector(10, nBits);
regFileWriteAddr <= r0;
aluOp <= alu_pass;
muxSel <= muxPos(fromImediate);
muxSel <= fromImediate;
muxRegFile <= muxRegPos(fromRegFileA);
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
107,7 → 107,7
-- Read value in r0 to verify if is equal to 20
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileA);
muxSel <= fromRegFileA;
regFileReadAddrA <= r0; -- Read data from r0 and verify if it's 10
regFileEnA <= '1';
outEn <= enable;
114,7 → 114,7
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(10, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
muxSel <= fromMemory;
regFileEnA <= '0';
outEn <= disable;
124,7 → 124,7
inputImm <= conv_std_logic_vector(20, nBits);
regFileWriteAddr <= r1;
aluOp <= alu_pass;
muxSel <= muxPos(fromImediate);
muxSel <= fromImediate;
muxRegFile <= muxRegPos(fromRegFileA);
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to latch some data to the register file
131,7 → 131,7
-- Read value in r1 to verify if is equal to 20
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileA);
muxSel <= fromRegFileA;
regFileReadAddrA <= r1; -- Read data from r0 and verify if it's 10
regFileEnA <= '1';
outEn <= enable;
138,7 → 138,7
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
muxSel <= fromMemory;
regFileEnA <= '0';
outEn <= disable;
148,7 → 148,7
regFileReadAddrB <= r1; -- Read data from r1
regFileEnB <= '1';
regFileWriteAddr <= r2; -- Write data in r2
muxSel <= muxPos(fromRegFileB); -- Select the PortB output from regFile
muxSel <= fromRegFileB; -- Select the PortB output from regFile
muxRegFile <= muxRegPos(fromRegFileA);
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to write into r2
155,7 → 155,7
-- Read value in r2 to verify if is equal to r1(20)
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileA);
muxSel <= fromRegFileA;
regFileReadAddrA <= r2; -- Read data from r0 and verify if it's 10
regFileEnA <= '1';
outEn <= enable;
162,7 → 162,7
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(20, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
muxSel <= fromMemory;
regFileEnA <= '0';
outEn <= disable;
wait for 1 ns; -- Finish test case
175,7 → 175,7
regFileEnB <= '1';
aluOp <= alu_sum;
regFileWriteAddr <= r2; -- Write data in r2
muxSel <= muxPos(fromAlu); -- Select the Alu output
muxSel <= fromAlu; -- Select the Alu output
muxRegFile <= muxRegPos(fromRegFileA);
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to write into r2
182,7 → 182,7
-- Read value in r2 to verify if is equal to 30(10+20)
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileB); -- Must access from other Port otherwise you will need an extra cycle to change it's address
muxSel <= fromRegFileB; -- Must access from other Port otherwise you will need an extra cycle to change it's address
regFileReadAddrB <= r2; -- Read data from r0 and verify if it's 10
regFileEnB <= '1';
outEn <= enable;
189,7 → 189,7
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(30, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
muxSel <= fromMemory;
regFileEnA <= '0';
regFileEnB <= '0';
outEn <= disable;
203,7 → 203,7
regFileEnB <= '1';
aluOp <= alu_sum;
regFileWriteAddr <= r3; -- Write data in r2
muxSel <= muxPos(fromAlu); -- Select the Alu output
muxSel <= fromAlu; -- Select the Alu output
muxRegFile <= muxRegPos(fromRegFileA);
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to write into r2
210,7 → 210,7
-- Read value in r2 to verify if is equal to 30(10+20)
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileB); -- Must access from other Port otherwise you will need an extra cycle to change it's address
muxSel <= fromRegFileB; -- Must access from other Port otherwise you will need an extra cycle to change it's address
regFileReadAddrB <= r3; -- Read data from r0 and verify if it's 10
regFileEnB <= '1';
outEn <= enable;
217,7 → 217,7
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(40, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
muxSel <= fromMemory;
regFileEnA <= '0';
regFileEnB <= '0';
outEn <= disable;
230,13 → 230,13
regFileWriteAddr <= r3;
muxRegFile <= muxRegPos(fromImediate);
aluOp <= alu_sum;
muxSel <= muxPos(fromAlu); -- Select the Alu output
muxSel <= fromAlu; -- Select the Alu output
regFileWriteEn <= '1';
wait for CLK_period; -- Wait for clock cycle to write into r2
-- Read value in r2 to verify if is equal to 42(40+2)
regFileWriteEn <= '0';
inputImm <= (others => 'U');
muxSel <= muxPos(fromRegFileA); -- Must access from other Port otherwise you will need an extra cycle to change it's address
muxSel <= fromRegFileA; -- Must access from other Port otherwise you will need an extra cycle to change it's address
regFileReadAddrA <= r3; -- Read data from r0 and verify if it's 10
regFileEnA <= '1';
outEn <= enable;
243,7 → 243,7
wait for 1 ns; -- Wait for data to settle
assert outputDp = conv_std_logic_vector(42, nBits) report "Invalid value" severity FAILURE;
wait for 1 ns; -- Finish test case
muxSel <= (others => 'U');
muxSel <= fromMemory;
regFileEnA <= '0';
regFileEnB <= '0';
outEn <= disable;
/trunk/hdl/opencpu32/testCode/testCodeBin.dat
1,5 → 1,5
00000100000000000000000000001010
00000100010000000000000000010100
00000000100001000000000000000000
01101100100000000000000000000000
01110000100000000000000000000010
00000100000000000000000000001010
00000100010000000000000000010100
00000000100001000000000000000000
01101100100000000000000000000000
01110000100000000000000000000010

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