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URL https://opencores.org/ocsvn/opencpu32/opencpu32/trunk

Subversion Repositories opencpu32

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  • This comparison shows the changes necessary to convert path 
    /opencpu32
    from Rev 44 to Rev 45
    ↔ Reverse comparison
  •

Rev 44 → Rev 45

/trunk/hdl/opencpu32/testOpenCpu.vhd
97,58 → 97,20
end if;
rst <= '1';
wait for 2 ns;
wait for 15 ns;
rst <= '0';
wait for 2 ns;
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
wait for 15 ns;
 
while not endfile( cmdfile ) loop
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
 
wait until mem_rd = '0';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
 
wait until mem_rd = '0';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
wait until mem_rd = '0';
end loop;
wait until mem_rd = '0';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
wait until mem_rd = '0';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
wait until mem_rd = '0';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
wait until mem_rd = '0';
readline(cmdfile,line_in); -- Read a line from the file
read(line_in,instructionCode,good); -- Read the CI input
assert good report "Could not parse the line" severity ERROR;
mem_data_in <= instructionCode;
wait for CLK_period;
wait until mem_rd = '0';
 
-- Finish simulation
assert false report "NONE. End of simulation." severity failure;
/trunk/hdl/opencpu32/opencpu32.gise
234,7 → 234,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334673019" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334673019">
<transform xil_pn:end_ts="1334674245" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1334674245">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
254,11 → 254,11
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334672343" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334672343">
<transform xil_pn:end_ts="1334674301" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8309380896524256912" xil_pn:start_ts="1334674301">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334672343" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334672343">
<transform xil_pn:end_ts="1334674301" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7964109342171924334" xil_pn:start_ts="1334674301">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
266,7 → 266,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1334673019" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334673019">
<transform xil_pn:end_ts="1334674245" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1334674245">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Alu.vhd"/>
286,7 → 286,7
<outfile xil_pn:name="testRegisterFile.vhd"/>
<outfile xil_pn:name="testTriStateBuffer.vhd"/>
</transform>
<transform xil_pn:end_ts="1334673021" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334673019">
<transform xil_pn:end_ts="1334674303" xil_pn:in_ck="1718853035096696259" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="6846524775138479362" xil_pn:start_ts="1334674301">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
298,7 → 298,7
<outfile xil_pn:name="testOpenCpu_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1334673021" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334673021">
<transform xil_pn:end_ts="1334674303" xil_pn:in_ck="-3218109590739612736" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1487094935924008414" xil_pn:start_ts="1334674303">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
/trunk/hdl/opencpu32/testCode/testCodeBin.dat
3,5 → 3,4
00000000100001000000000000000000
01101100100000000000000000000000
01110000100000000000000000000010
01110000100000000000000000000010
01110000100000000000000000000010
00001100100000000000000000110010

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