OpenCores
URL https://opencores.org/ocsvn/opengfx430/opengfx430/trunk

Subversion Repositories opengfx430

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /opengfx430/trunk/core/rtl
    from Rev 3 to Rev 6
    ↔ Reverse comparison
  •

Rev 3 → Rev 6

/verilog/ogfx_gpu_reg.v
183,33 → 183,33
//
// SRC_PX_ADDR - Set source address
// {4'b1111, 2'b10, 10'b0000000000}
// {addr[15:0] }
// {addr[31:16] }
// {addr[15:0] }
//
// DST_PX_ADDR - Set destination address
// {4'b1111, 2'b10, 10'b0000000001}
// {addr[15:0] }
// {addr[31:16] }
// {addr[15:0] }
//
// OF0_ADDR - Set address offset 0
// {4'b1111, 2'b10, 10'b0000010000}
// {addr[15:0] }
// {addr[31:16] }
// {addr[15:0] }
//
// OF1_ADDR - Set address offset 1
// {4'b1111, 2'b10, 10'b0000010001}
// {addr[15:0] }
// {addr[31:16] }
// {addr[15:0] }
//
// OF2_ADDR - Set address offset 2
// {4'b1111, 2'b10, 10'b0000010010}
// {addr[15:0] }
// {addr[31:16] }
// {addr[15:0] }
//
// OF3_ADDR - Set address offset 3
// {4'b1111, 2'b10, 10'b0000010011}
// {addr[15:0] }
// {addr[31:16] }
// {addr[15:0] }
//
// SET_FILL - Set fill color
// {4'b1111, 2'b01, 10'b0000100000}
467,7 → 467,7
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] src_px_addr_hi;
 
wire src_px_addr_hi_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B1_READ);
wire src_px_addr_hi_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B2_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) src_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
479,7 → 479,7
//------------------------------------------------
reg [`APIX_LO_MSB:0] src_px_addr_lo;
 
wire src_px_addr_lo_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B2_READ);
wire src_px_addr_lo_wr = (reg_access==REG_SRC_PX_ADDR) & (gpu_state==DATA2B1_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) src_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
488,7 → 488,7
`ifdef VRAM_BIGGER_4_KW
assign src_px_addr = {src_px_addr_hi[`APIX_HI_MSB:0], src_px_addr_lo};
`else
assign src_px_addr = {src_px_addr_lo[`APIX_LO_MS:0]};
assign src_px_addr = {src_px_addr_lo[`APIX_LO_MSB:0]};
`endif
 
assign src_px_addr_align = src_px_addr + src_offset_addr;
504,7 → 504,7
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] dst_px_addr_hi;
 
wire dst_px_addr_hi_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B1_READ);
wire dst_px_addr_hi_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B2_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) dst_px_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
516,7 → 516,7
//------------------------------------------------
reg [`APIX_LO_MSB:0] dst_px_addr_lo;
 
wire dst_px_addr_lo_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B2_READ);
wire dst_px_addr_lo_wr = (reg_access==REG_DST_PX_ADDR) & (gpu_state==DATA2B1_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) dst_px_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
525,7 → 525,7
`ifdef VRAM_BIGGER_4_KW
assign dst_px_addr = {dst_px_addr_hi[`APIX_HI_MSB:0], dst_px_addr_lo};
`else
assign dst_px_addr = {dst_px_addr_lo[`APIX_LO_MS:0]};
assign dst_px_addr = {dst_px_addr_lo[`APIX_LO_MSB:0]};
`endif
 
assign dst_px_addr_align = dst_px_addr + dst_offset_addr;
541,7 → 541,7
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] of0_addr_hi;
 
wire of0_addr_hi_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B1_READ);
wire of0_addr_hi_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B2_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) of0_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
553,7 → 553,7
//------------------------------------------------
reg [`APIX_LO_MSB:0] of0_addr_lo;
 
wire of0_addr_lo_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B2_READ);
wire of0_addr_lo_wr = (reg_access==REG_OF0_ADDR) & (gpu_state==DATA2B1_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) of0_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
562,7 → 562,7
`ifdef VRAM_BIGGER_4_KW
assign of0_addr = {of0_addr_hi[`APIX_HI_MSB:0], of0_addr_lo};
`else
assign of0_addr = {of0_addr_lo[`APIX_LO_MS:0]};
assign of0_addr = {of0_addr_lo[`APIX_LO_MSB:0]};
`endif
 
//------------------------------------------------
571,7 → 571,7
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] of1_addr_hi;
 
wire of1_addr_hi_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B1_READ);
wire of1_addr_hi_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B2_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) of1_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
583,7 → 583,7
//------------------------------------------------
reg [`APIX_LO_MSB:0] of1_addr_lo;
 
wire of1_addr_lo_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B2_READ);
wire of1_addr_lo_wr = (reg_access==REG_OF1_ADDR) & (gpu_state==DATA2B1_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) of1_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
592,7 → 592,7
`ifdef VRAM_BIGGER_4_KW
assign of1_addr = {of1_addr_hi[`APIX_HI_MSB:0], of1_addr_lo};
`else
assign of1_addr = {of1_addr_lo[`APIX_LO_MS:0]};
assign of1_addr = {of1_addr_lo[`APIX_LO_MSB:0]};
`endif
 
//------------------------------------------------
601,7 → 601,7
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] of2_addr_hi;
 
wire of2_addr_hi_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B1_READ);
wire of2_addr_hi_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B2_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) of2_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
613,7 → 613,7
//------------------------------------------------
reg [`APIX_LO_MSB:0] of2_addr_lo;
 
wire of2_addr_lo_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B2_READ);
wire of2_addr_lo_wr = (reg_access==REG_OF2_ADDR) & (gpu_state==DATA2B1_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) of2_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
622,7 → 622,7
`ifdef VRAM_BIGGER_4_KW
assign of2_addr = {of2_addr_hi[`APIX_HI_MSB:0], of2_addr_lo};
`else
assign of2_addr = {of2_addr_lo[`APIX_LO_MS:0]};
assign of2_addr = {of2_addr_lo[`APIX_LO_MSB:0]};
`endif
 
//------------------------------------------------
631,7 → 631,7
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] of3_addr_hi;
 
wire of3_addr_hi_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B1_READ);
wire of3_addr_hi_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B2_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) of3_addr_hi <= {`APIX_HI_MSB+1{1'b0}};
643,7 → 643,7
//------------------------------------------------
reg [`APIX_LO_MSB:0] of3_addr_lo;
 
wire of3_addr_lo_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B2_READ);
wire of3_addr_lo_wr = (reg_access==REG_OF3_ADDR) & (gpu_state==DATA2B1_READ);
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) of3_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
652,7 → 652,7
`ifdef VRAM_BIGGER_4_KW
assign of3_addr = {of3_addr_hi[`APIX_HI_MSB:0], of3_addr_lo};
`else
assign of3_addr = {of3_addr_lo[`APIX_LO_MS:0]};
assign of3_addr = {of3_addr_lo[`APIX_LO_MSB:0]};
`endif
 
// Offset address selection
/verilog/ogfx_gpu.v
50,6 → 50,7
// OUTPUTs
gpu_cmd_done_evt_o, // GPU command done event
gpu_cmd_error_evt_o, // GPU command error event
gpu_dma_busy_o, // GPU DMA execution on going
gpu_get_data_o, // GPU get next data
 
vid_ram_addr_o, // Video-RAM address
77,6 → 78,7
//=========
output gpu_cmd_done_evt_o; // GPU command done event
output gpu_cmd_error_evt_o; // GPU command error event
output gpu_dma_busy_o; // GPU DMA execution on going
output gpu_get_data_o; // GPU get next data
 
output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
178,6 → 180,7
 
// OUTPUTs
.gpu_exec_done_o (gpu_exec_done ), // GPU execution done
.gpu_dma_busy_o (gpu_dma_busy_o ), // GPU DMA execution on going
 
.vid_ram_addr_o (vid_ram_addr_o ), // Video-RAM address
.vid_ram_din_o (vid_ram_din_o ), // Video-RAM data
/verilog/ogfx_if_lt24.v
376,30 → 376,30
reg [15:0] lt24_d_nxt;
always @(lt24_state_nxt or cmd_generic_cmd_val_i or cmd_generic_param_val_i or lt24_d_o or cmd_dfill_i or refresh_data_i)
case(lt24_state_nxt)
STATE_IDLE : lt24_d_nxt <= 16'h0000;
STATE_IDLE : lt24_d_nxt = 16'h0000;
 
STATE_CMD_LO,
STATE_CMD_HI : lt24_d_nxt <= {8'h00, cmd_generic_cmd_val_i};
STATE_CMD_HI : lt24_d_nxt = {8'h00, cmd_generic_cmd_val_i};
STATE_CMD_PARAM_LO,
STATE_CMD_PARAM_HI : lt24_d_nxt <= cmd_generic_param_val_i;
STATE_CMD_PARAM_WAIT : lt24_d_nxt <= lt24_d_o;
STATE_CMD_PARAM_HI : lt24_d_nxt = cmd_generic_param_val_i;
STATE_CMD_PARAM_WAIT : lt24_d_nxt = lt24_d_o;
 
STATE_RAMWR_INIT_CMD_LO,
STATE_RAMWR_INIT_CMD_HI : lt24_d_nxt <= 16'h002C;
STATE_RAMWR_INIT_CMD_HI : lt24_d_nxt = 16'h002C;
STATE_RAMWR_INIT_DATA_LO,
STATE_RAMWR_INIT_DATA_HI : lt24_d_nxt <= cmd_dfill_i;
STATE_RAMWR_INIT_DATA_HI : lt24_d_nxt = cmd_dfill_i;
 
STATE_SCANLINE_CMD_LO,
STATE_SCANLINE_CMD_HI : lt24_d_nxt <= 16'h0045;
STATE_SCANLINE_CMD_HI : lt24_d_nxt = 16'h0045;
 
STATE_RAMWR_REFR_CMD_LO,
STATE_RAMWR_REFR_CMD_HI : lt24_d_nxt <= 16'h002C;
STATE_RAMWR_REFR_DATA_LO : lt24_d_nxt <= refresh_data_i;
STATE_RAMWR_REFR_DATA_HI : lt24_d_nxt <= lt24_d_o;
STATE_RAMWR_REFR_WAIT : lt24_d_nxt <= lt24_d_o;
STATE_RAMWR_REFR_CMD_HI : lt24_d_nxt = 16'h002C;
STATE_RAMWR_REFR_DATA_LO : lt24_d_nxt = refresh_data_i;
STATE_RAMWR_REFR_DATA_HI : lt24_d_nxt = lt24_d_o;
STATE_RAMWR_REFR_WAIT : lt24_d_nxt = lt24_d_o;
 
// pragma coverage off
default : lt24_d_nxt <= 16'h0000;
default : lt24_d_nxt = 16'h0000;
// pragma coverage on
endcase
 
424,20 → 424,21
//============================================================================
 
reg [1:0] status_gts_msb;
wire status_gts_msb_wr = ((lt24_state == STATE_SCANLINE_GTS1_LO) & (lt24_state_nxt == STATE_SCANLINE_GTS1_HI));
wire status_gts_msb_wr = ((lt24_state == STATE_SCANLINE_GTS1_LO) & (lt24_state_nxt == STATE_SCANLINE_GTS1_HI));
always @(posedge mclk or posedge puc_rst)
if (puc_rst) status_gts_msb <= 2'h0;
else if (status_gts_msb_wr) status_gts_msb <= lt24_d_i[1:0];
 
reg [7:0] status_gts_lsb;
wire status_gts_lsb_wr = ((lt24_state == STATE_SCANLINE_GTS2_LO) & (lt24_state_nxt == STATE_SCANLINE_GTS2_HI));
wire status_gts_lsb_wr = ((lt24_state == STATE_SCANLINE_GTS2_LO) & (lt24_state_nxt == STATE_SCANLINE_GTS2_HI));
always @(posedge mclk or posedge puc_rst)
if (puc_rst) status_gts_lsb <= 8'h00;
else if (status_gts_lsb_wr) status_gts_lsb <= lt24_d_i[7:0];
 
wire [9:0] status_gts = {status_gts_msb, status_gts_lsb};
wire [7:0] unused_lt24_d_15_8 = lt24_d_i[15:8];
wire [9:0] status_gts = {status_gts_msb, status_gts_lsb};
 
assign status_gts_match = (status_gts == cfg_lt24_refresh_sync_val_i);
assign status_gts_match = (status_gts == cfg_lt24_refresh_sync_val_i);
 
//============================================================================
// 8) REFRESH TIMER & TRIGGER
/verilog/ogfx_backend_frame_fifo.v
212,18 → 212,18
else if (vid_ram_pixel_done) vid_ram_column_count <= vid_ram_column_count + {{`LPIX_MSB{1'b0}}, 1'b1};
 
// Depending on the color mode, format the address for doing the RAM accesses.
assign vid_ram_addr_o = ({`VRAM_MSB+1{gfx_mode_1_bpp }} & vid_ram_pixel_addr[`VRAM_MSB+4:4]) |
({`VRAM_MSB+1{gfx_mode_2_bpp }} & vid_ram_pixel_addr[`VRAM_MSB+3:3]) |
({`VRAM_MSB+1{gfx_mode_4_bpp }} & vid_ram_pixel_addr[`VRAM_MSB+2:2]) |
({`VRAM_MSB+1{gfx_mode_8_bpp }} & vid_ram_pixel_addr[`VRAM_MSB+1:1]) |
({`VRAM_MSB+1{gfx_mode_16_bpp}} & vid_ram_pixel_addr[`VRAM_MSB+0:0]) ;
assign vid_ram_addr_o = ({`VRAM_MSB+1{gfx_mode_1_bpp }} & vid_ram_pixel_addr[`VRAM_MSB+4:4]) |
({`VRAM_MSB+1{gfx_mode_2_bpp }} & vid_ram_pixel_addr[`VRAM_MSB+3:3]) |
({`VRAM_MSB+1{gfx_mode_4_bpp }} & vid_ram_pixel_addr[`VRAM_MSB+2:2]) |
({`VRAM_MSB+1{gfx_mode_8_bpp }} & vid_ram_pixel_addr[`VRAM_MSB+1:1]) |
({`VRAM_MSB+1{gfx_mode_16_bpp}} & vid_ram_pixel_addr[`VRAM_MSB+0:0]) ;
 
// Compute the next RAM address to detect when a new address is generated
wire [16:0] vid_ram_addr_nxt = ({`VRAM_MSB+1{gfx_mode_1_bpp }} & vid_ram_pixel_addr_nxt[`VRAM_MSB+4:4]) |
({`VRAM_MSB+1{gfx_mode_2_bpp }} & vid_ram_pixel_addr_nxt[`VRAM_MSB+3:3]) |
({`VRAM_MSB+1{gfx_mode_4_bpp }} & vid_ram_pixel_addr_nxt[`VRAM_MSB+2:2]) |
({`VRAM_MSB+1{gfx_mode_8_bpp }} & vid_ram_pixel_addr_nxt[`VRAM_MSB+1:1]) |
({`VRAM_MSB+1{gfx_mode_16_bpp}} & vid_ram_pixel_addr_nxt[`VRAM_MSB+0:0]) ;
wire [`VRAM_MSB:0] vid_ram_addr_nxt = ({`VRAM_MSB+1{gfx_mode_1_bpp }} & vid_ram_pixel_addr_nxt[`VRAM_MSB+4:4]) |
({`VRAM_MSB+1{gfx_mode_2_bpp }} & vid_ram_pixel_addr_nxt[`VRAM_MSB+3:3]) |
({`VRAM_MSB+1{gfx_mode_4_bpp }} & vid_ram_pixel_addr_nxt[`VRAM_MSB+2:2]) |
({`VRAM_MSB+1{gfx_mode_8_bpp }} & vid_ram_pixel_addr_nxt[`VRAM_MSB+1:1]) |
({`VRAM_MSB+1{gfx_mode_16_bpp}} & vid_ram_pixel_addr_nxt[`VRAM_MSB+0:0]) ;
 
// Detect when a new word needs to be fetched from the memory
// (i.e. detect when the RAM address is updated)
/verilog/openGFX430.v
197,6 → 197,7
 
wire gpu_cmd_done_evt;
wire gpu_cmd_error_evt;
wire gpu_dma_busy;
wire gpu_get_data;
wire [15:0] gpu_data;
wire gpu_data_avail;
260,6 → 261,7
.dbg_freeze_i ( dbg_freeze_i ), // Freeze address auto-incr on read
.gpu_cmd_done_evt_i ( gpu_cmd_done_evt ), // GPU command done event
.gpu_cmd_error_evt_i ( gpu_cmd_error_evt ), // GPU command error event
.gpu_dma_busy_i ( gpu_dma_busy ), // GPU DMA execution on going
.gpu_get_data_i ( gpu_get_data ), // GPU get next data
.lt24_status_i ( lt24_status ), // LT24 FSM Status
.lt24_start_evt_i ( lt24_start_evt ), // LT24 FSM start event
287,6 → 289,7
// OUTPUTs
.gpu_cmd_done_evt_o ( gpu_cmd_done_evt ), // GPU command done event
.gpu_cmd_error_evt_o ( gpu_cmd_error_evt ), // GPU command error event
.gpu_dma_busy_o ( gpu_dma_busy ), // GPU DMA execution on going
.gpu_get_data_o ( gpu_get_data ), // GPU get next data
 
.vid_ram_addr_o ( vid_ram_gpu_addr ), // Video-RAM address
/verilog/ogfx_gpu_dma.v
44,6 → 44,7
 
// OUTPUTs
gpu_exec_done_o, // GPU execution done
gpu_dma_busy_o, // GPU DMA execution on going
 
vid_ram_addr_o, // Video-RAM address
vid_ram_din_o, // Video-RAM data
86,6 → 87,7
// OUTPUTs
//=========
output gpu_exec_done_o; // GPU execution done
output gpu_dma_busy_o; // GPU DMA execution on going
 
output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
output [15:0] vid_ram_din_o; // Video-RAM data
237,6 → 239,7
wire dma_pixel_done = (dma_state==SKIP) | ((dma_state==DST_READ) & pixel_is_transparent) |
((dma_state==DST_WRITE) & data_ready_nxt ) ;
assign gpu_exec_done_o = (dma_state==IDLE) & ~trig_exec_i;
assign gpu_dma_busy_o = (dma_state!=IDLE);
 
 
//=============================================================================
/verilog/ogfx_reg.v
92,6 → 92,7
dbg_freeze_i, // Freeze address auto-incr on read
gpu_cmd_done_evt_i, // GPU command done event
gpu_cmd_error_evt_i, // GPU command error event
gpu_dma_busy_i, // GPU DMA execution on going
gpu_get_data_i, // GPU get next data
lt24_status_i, // LT24 FSM Status
lt24_start_evt_i, // LT24 FSM is starting
160,6 → 161,7
input dbg_freeze_i; // Freeze address auto-incr on read
input gpu_cmd_done_evt_i; // GPU command done event
input gpu_cmd_error_evt_i; // GPU command error event
input gpu_dma_busy_i; // GPU DMA execution on going
input gpu_get_data_i; // GPU get next data
input [4:0] lt24_status_i; // LT24 FSM Status
input lt24_start_evt_i; // LT24 FSM is starting
193,8 → 195,8
 
DISPLAY_WIDTH = 'h10, // Display configuration
DISPLAY_HEIGHT = 'h12,
DISPLAY_SIZE_HI = 'h14,
DISPLAY_SIZE_LO = 'h16,
DISPLAY_SIZE_LO = 'h14,
DISPLAY_SIZE_HI = 'h16,
DISPLAY_CFG = 'h18,
 
LT24_CFG = 'h20, // LT24 configuration and Generic command sending
209,29 → 211,30
LUT_RAM_DATA = 'h32,
 
FRAME_SELECT = 'h3E, // Frame pointers and selection
FRAME0_PTR_HI = 'h40,
FRAME0_PTR_LO = 'h42,
FRAME1_PTR_HI = 'h44,
FRAME1_PTR_LO = 'h46,
FRAME2_PTR_HI = 'h48,
FRAME2_PTR_LO = 'h4A,
FRAME3_PTR_HI = 'h4C,
FRAME3_PTR_LO = 'h4E,
FRAME0_PTR_LO = 'h40,
FRAME0_PTR_HI = 'h42,
FRAME1_PTR_LO = 'h44,
FRAME1_PTR_HI = 'h46,
FRAME2_PTR_LO = 'h48,
FRAME2_PTR_HI = 'h4A,
FRAME3_PTR_LO = 'h4C,
FRAME3_PTR_HI = 'h4E,
 
VID_RAM0_CFG = 'h50, // First Video Memory Access Gate
VID_RAM0_WIDTH = 'h52,
VID_RAM0_ADDR_HI = 'h54,
VID_RAM0_ADDR_LO = 'h56,
VID_RAM0_ADDR_LO = 'h54,
VID_RAM0_ADDR_HI = 'h56,
VID_RAM0_DATA = 'h58,
 
VID_RAM1_CFG = 'h60, // Second Video Memory Access Gate
VID_RAM1_WIDTH = 'h62,
VID_RAM1_ADDR_HI = 'h64,
VID_RAM1_ADDR_LO = 'h66,
VID_RAM1_ADDR_LO = 'h64,
VID_RAM1_ADDR_HI = 'h66,
VID_RAM1_DATA = 'h68,
 
GPU_CMD = 'h70, // Graphic Processing Unit
GPU_STAT = 'h72;
GPU_CMD_LO = 'h70, // Graphic Processing Unit
GPU_CMD_HI = 'h72,
GPU_STAT = 'h74;
 
 
// Register one-hot decoder utilities
245,8 → 248,8
 
DISPLAY_WIDTH_D = (BASE_REG << DISPLAY_WIDTH ),
DISPLAY_HEIGHT_D = (BASE_REG << DISPLAY_HEIGHT ),
DISPLAY_SIZE_LO_D = (BASE_REG << DISPLAY_SIZE_LO ),
DISPLAY_SIZE_HI_D = (BASE_REG << DISPLAY_SIZE_HI ),
DISPLAY_SIZE_LO_D = (BASE_REG << DISPLAY_SIZE_LO ),
DISPLAY_CFG_D = (BASE_REG << DISPLAY_CFG ),
 
LT24_CFG_D = (BASE_REG << LT24_CFG ),
261,28 → 264,29
LUT_RAM_DATA_D = (BASE_REG << LUT_RAM_DATA ),
 
FRAME_SELECT_D = (BASE_REG << FRAME_SELECT ),
FRAME0_PTR_LO_D = (BASE_REG << FRAME0_PTR_LO ),
FRAME0_PTR_HI_D = (BASE_REG << FRAME0_PTR_HI ),
FRAME0_PTR_LO_D = (BASE_REG << FRAME0_PTR_LO ),
FRAME1_PTR_LO_D = (BASE_REG << FRAME1_PTR_LO ),
FRAME1_PTR_HI_D = (BASE_REG << FRAME1_PTR_HI ),
FRAME1_PTR_LO_D = (BASE_REG << FRAME1_PTR_LO ),
FRAME2_PTR_LO_D = (BASE_REG << FRAME2_PTR_LO ),
FRAME2_PTR_HI_D = (BASE_REG << FRAME2_PTR_HI ),
FRAME2_PTR_LO_D = (BASE_REG << FRAME2_PTR_LO ),
FRAME3_PTR_LO_D = (BASE_REG << FRAME3_PTR_LO ),
FRAME3_PTR_HI_D = (BASE_REG << FRAME3_PTR_HI ),
FRAME3_PTR_LO_D = (BASE_REG << FRAME3_PTR_LO ),
 
VID_RAM0_CFG_D = (BASE_REG << VID_RAM0_CFG ),
VID_RAM0_WIDTH_D = (BASE_REG << VID_RAM0_WIDTH ),
VID_RAM0_ADDR_LO_D = (BASE_REG << VID_RAM0_ADDR_LO ),
VID_RAM0_ADDR_HI_D = (BASE_REG << VID_RAM0_ADDR_HI ),
VID_RAM0_ADDR_LO_D = (BASE_REG << VID_RAM0_ADDR_LO ),
VID_RAM0_DATA_D = (BASE_REG << VID_RAM0_DATA ),
 
VID_RAM1_CFG_D = (BASE_REG << VID_RAM1_CFG ),
VID_RAM1_WIDTH_D = (BASE_REG << VID_RAM1_WIDTH ),
VID_RAM1_ADDR_LO_D = (BASE_REG << VID_RAM1_ADDR_LO ),
VID_RAM1_ADDR_HI_D = (BASE_REG << VID_RAM1_ADDR_HI ),
VID_RAM1_ADDR_LO_D = (BASE_REG << VID_RAM1_ADDR_LO ),
VID_RAM1_DATA_D = (BASE_REG << VID_RAM1_DATA ),
 
GPU_CMD_D = (BASE_REG << GPU_CMD ),
GPU_CMD_LO_D = (BASE_REG << GPU_CMD_LO ),
GPU_CMD_HI_D = (BASE_REG << GPU_CMD_HI ),
GPU_STAT_D = (BASE_REG << GPU_STAT );
 
 
303,8 → 307,8
 
(DISPLAY_WIDTH_D & {DEC_SZ{(reg_addr == DISPLAY_WIDTH )}}) |
(DISPLAY_HEIGHT_D & {DEC_SZ{(reg_addr == DISPLAY_HEIGHT )}}) |
(DISPLAY_SIZE_LO_D & {DEC_SZ{(reg_addr == DISPLAY_SIZE_LO )}}) |
(DISPLAY_SIZE_HI_D & {DEC_SZ{(reg_addr == DISPLAY_SIZE_HI )}}) |
(DISPLAY_SIZE_LO_D & {DEC_SZ{(reg_addr == DISPLAY_SIZE_LO )}}) |
(DISPLAY_CFG_D & {DEC_SZ{(reg_addr == DISPLAY_CFG )}}) |
 
(LT24_CFG_D & {DEC_SZ{(reg_addr == LT24_CFG )}}) |
319,28 → 323,29
(LUT_RAM_DATA_D & {DEC_SZ{(reg_addr == LUT_RAM_DATA )}}) |
 
(FRAME_SELECT_D & {DEC_SZ{(reg_addr == FRAME_SELECT )}}) |
(FRAME0_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME0_PTR_LO )}}) |
(FRAME0_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME0_PTR_HI )}}) |
(FRAME0_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME0_PTR_LO )}}) |
(FRAME1_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME1_PTR_LO )}}) |
(FRAME1_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME1_PTR_HI )}}) |
(FRAME1_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME1_PTR_LO )}}) |
(FRAME2_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME2_PTR_LO )}}) |
(FRAME2_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME2_PTR_HI )}}) |
(FRAME2_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME2_PTR_LO )}}) |
(FRAME3_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME3_PTR_LO )}}) |
(FRAME3_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME3_PTR_HI )}}) |
(FRAME3_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME3_PTR_LO )}}) |
 
(VID_RAM0_CFG_D & {DEC_SZ{(reg_addr == VID_RAM0_CFG )}}) |
(VID_RAM0_WIDTH_D & {DEC_SZ{(reg_addr == VID_RAM0_WIDTH )}}) |
(VID_RAM0_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM0_ADDR_LO )}}) |
(VID_RAM0_ADDR_HI_D & {DEC_SZ{(reg_addr == VID_RAM0_ADDR_HI )}}) |
(VID_RAM0_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM0_ADDR_LO )}}) |
(VID_RAM0_DATA_D & {DEC_SZ{(reg_addr == VID_RAM0_DATA )}}) |
 
(VID_RAM1_CFG_D & {DEC_SZ{(reg_addr == VID_RAM1_CFG )}}) |
(VID_RAM1_WIDTH_D & {DEC_SZ{(reg_addr == VID_RAM1_WIDTH )}}) |
(VID_RAM1_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM1_ADDR_LO )}}) |
(VID_RAM1_ADDR_HI_D & {DEC_SZ{(reg_addr == VID_RAM1_ADDR_HI )}}) |
(VID_RAM1_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM1_ADDR_LO )}}) |
(VID_RAM1_DATA_D & {DEC_SZ{(reg_addr == VID_RAM1_DATA )}}) |
 
(GPU_CMD_D & {DEC_SZ{(reg_addr == GPU_CMD )}}) |
(GPU_CMD_LO_D & {DEC_SZ{(reg_addr == GPU_CMD_LO )}}) |
(GPU_CMD_HI_D & {DEC_SZ{(reg_addr == GPU_CMD_HI )}}) |
(GPU_STAT_D & {DEC_SZ{(reg_addr == GPU_STAT )}});
 
// Read/Write probes
367,8 → 372,6
`ifdef WITH_EXTRA_LUT_BANK
reg lut_bank_select;
`endif
reg vid_ram0_addr_lo_wr_dly;
reg vid_ram1_addr_lo_wr_dly;
wire gpu_fifo_done_evt;
wire gpu_fifo_ovfl_evt;
 
1088,9 → 1091,7
 
.vid_ram_cfg_wr_i ( reg_wr[VID_RAM0_CFG] ), // VID_RAM0_CFG Write strobe
.vid_ram_width_wr_i ( reg_wr[VID_RAM0_WIDTH] ), // VID_RAM0_WIDTH Write strobe
`ifdef VRAM_BIGGER_4_KW
.vid_ram_addr_hi_wr_i ( reg_wr[VID_RAM0_ADDR_HI] ), // VID_RAM0_ADDR_HI Write strobe
`endif
.vid_ram_addr_lo_wr_i ( reg_wr[VID_RAM0_ADDR_LO] ), // VID_RAM0_ADDR_LO Write strobe
.vid_ram_data_wr_i ( reg_wr[VID_RAM0_DATA] ), // VID_RAM0_DATA Write strobe
.vid_ram_data_rd_i ( reg_rd[VID_RAM0_DATA] ), // VID_RAM0_DATA Read strobe
1148,9 → 1149,7
 
.vid_ram_cfg_wr_i ( reg_wr[VID_RAM1_CFG] ), // VID_RAM1_CFG Write strobe
.vid_ram_width_wr_i ( reg_wr[VID_RAM1_WIDTH] ), // VID_RAM1_WIDTH Write strobe
`ifdef VRAM_BIGGER_4_KW
.vid_ram_addr_hi_wr_i ( reg_wr[VID_RAM1_ADDR_HI] ), // VID_RAM1_ADDR_HI Write strobe
`endif
.vid_ram_addr_lo_wr_i ( reg_wr[VID_RAM1_ADDR_LO] ), // VID_RAM1_ADDR_LO Write strobe
.vid_ram_data_wr_i ( reg_wr[VID_RAM1_DATA] ), // VID_RAM1_DATA Write strobe
.vid_ram_data_rd_i ( reg_rd[VID_RAM1_DATA] ), // VID_RAM1_DATA Read strobe
1173,8 → 1172,11
//------------------------------------------------
 
wire [3:0] gpu_stat_fifo_cnt;
wire [3:0] gpu_stat_fifo_cnt_empty;
wire gpu_stat_fifo_empty;
wire gpu_stat_fifo_full;
wire gpu_stat_fifo_full_less_2;
wire gpu_stat_fifo_full_less_3;
 
ogfx_reg_fifo ogfx_reg_fifo_gpu_inst (
 
1183,6 → 1185,7
.fifo_data_o ( gpu_data_o ), // Read data output
.fifo_done_evt_o ( gpu_fifo_done_evt ), // Fifo has been emptied
.fifo_empty_o ( gpu_stat_fifo_empty ), // Fifo is currentely empty
.fifo_empty_cnt_o ( gpu_stat_fifo_cnt_empty ), // Fifo empty words counter
.fifo_full_o ( gpu_stat_fifo_full ), // Fifo is currentely full
.fifo_ovfl_evt_o ( gpu_fifo_ovfl_evt ), // Fifo overflow event
 
1193,14 → 1196,19
.fifo_data_i ( per_din_i ), // Read data input
.fifo_enable_i ( gpu_enable_o ), // Enable fifo (flushed when disabled)
.fifo_pop_i ( gpu_get_data_i ), // Pop data from the fifo
.fifo_push_i ( reg_wr[GPU_CMD] ) // Push new data to the fifo
.fifo_push_i ( reg_wr[GPU_CMD_LO] |
reg_wr[GPU_CMD_HI] ) // Push new data to the fifo
);
 
assign gpu_data_avail_o = ~gpu_stat_fifo_empty;
 
wire [15:0] gpu_stat = {10'h000, gpu_stat_fifo_full, gpu_stat_fifo_empty, gpu_stat_fifo_cnt};
wire gpu_busy = ~gpu_stat_fifo_empty | gpu_dma_busy_i;
 
wire [15:0] gpu_stat = {gpu_busy, 2'b00, gpu_dma_busy_i,
2'b00 , gpu_stat_fifo_full, gpu_stat_fifo_empty,
gpu_stat_fifo_cnt, gpu_stat_fifo_cnt_empty};
 
 
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
1212,10 → 1220,10
 
wire [15:0] display_width_read = display_width_rd & {16{reg_rd[DISPLAY_WIDTH ]}};
wire [15:0] display_height_read = display_height_rd & {16{reg_rd[DISPLAY_HEIGHT ]}};
wire [15:0] display_size_lo_read = display_size_lo_rd & {16{reg_rd[DISPLAY_SIZE_LO ]}};
`ifdef WITH_DISPLAY_SIZE_HI
wire [15:0] display_size_hi_read = display_size_hi_rd & {16{reg_rd[DISPLAY_SIZE_HI ]}};
`endif
wire [15:0] display_size_lo_read = display_size_lo_rd & {16{reg_rd[DISPLAY_SIZE_LO ]}};
wire [15:0] display_cfg_read = display_cfg & {16{reg_rd[DISPLAY_CFG ]}};
 
wire [15:0] lt24_cfg_read = lt24_cfg & {16{reg_rd[LT24_CFG ]}};
1230,44 → 1238,45
wire [15:0] lut_ram_data_read = lut_ram_data & {16{reg_rd[LUT_RAM_DATA ]}};
 
wire [15:0] frame_select_read = frame_select & {16{reg_rd[FRAME_SELECT ]}};
wire [15:0] frame0_ptr_lo_read = frame0_ptr_lo_rd & {16{reg_rd[FRAME0_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame0_ptr_hi_read = frame0_ptr_hi_rd & {16{reg_rd[FRAME0_PTR_HI ]}};
`endif
wire [15:0] frame0_ptr_lo_read = frame0_ptr_lo_rd & {16{reg_rd[FRAME0_PTR_LO ]}};
`ifdef WITH_FRAME1_POINTER
wire [15:0] frame1_ptr_lo_read = frame1_ptr_lo_rd & {16{reg_rd[FRAME1_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame1_ptr_hi_read = frame1_ptr_hi_rd & {16{reg_rd[FRAME1_PTR_HI ]}};
`endif
wire [15:0] frame1_ptr_lo_read = frame1_ptr_lo_rd & {16{reg_rd[FRAME1_PTR_LO ]}};
`endif
`ifdef WITH_FRAME2_POINTER
wire [15:0] frame2_ptr_lo_read = frame2_ptr_lo_rd & {16{reg_rd[FRAME2_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame2_ptr_hi_read = frame2_ptr_hi_rd & {16{reg_rd[FRAME2_PTR_HI ]}};
`endif
wire [15:0] frame2_ptr_lo_read = frame2_ptr_lo_rd & {16{reg_rd[FRAME2_PTR_LO ]}};
`endif
`ifdef WITH_FRAME3_POINTER
wire [15:0] frame3_ptr_lo_read = frame3_ptr_lo_rd & {16{reg_rd[FRAME3_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame3_ptr_hi_read = frame3_ptr_hi_rd & {16{reg_rd[FRAME3_PTR_HI ]}};
`endif
wire [15:0] frame3_ptr_lo_read = frame3_ptr_lo_rd & {16{reg_rd[FRAME3_PTR_LO ]}};
`endif
wire [15:0] vid_ram0_cfg_read = vid_ram0_cfg & {16{reg_rd[VID_RAM0_CFG ]}};
wire [15:0] vid_ram0_width_read = vid_ram0_width & {16{reg_rd[VID_RAM0_WIDTH ]}};
wire [15:0] vid_ram0_addr_lo_read = vid_ram0_addr_lo & {16{reg_rd[VID_RAM0_ADDR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram0_addr_hi_read = vid_ram0_addr_hi & {16{reg_rd[VID_RAM0_ADDR_HI ]}};
`endif
wire [15:0] vid_ram0_addr_lo_read = vid_ram0_addr_lo & {16{reg_rd[VID_RAM0_ADDR_LO ]}};
wire [15:0] vid_ram0_data_read = vid_ram0_data & {16{reg_rd[VID_RAM0_DATA ]}};
 
wire [15:0] vid_ram1_cfg_read = vid_ram1_cfg & {16{reg_rd[VID_RAM1_CFG ]}};
wire [15:0] vid_ram1_width_read = vid_ram1_width & {16{reg_rd[VID_RAM1_WIDTH ]}};
wire [15:0] vid_ram1_addr_lo_read = vid_ram1_addr_lo & {16{reg_rd[VID_RAM1_ADDR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram1_addr_hi_read = vid_ram1_addr_hi & {16{reg_rd[VID_RAM1_ADDR_HI ]}};
`endif
wire [15:0] vid_ram1_addr_lo_read = vid_ram1_addr_lo & {16{reg_rd[VID_RAM1_ADDR_LO ]}};
wire [15:0] vid_ram1_data_read = vid_ram1_data & {16{reg_rd[VID_RAM1_DATA ]}};
wire [15:0] gpu_cmd_read = 16'h0000 & {16{reg_rd[GPU_CMD ]}};
wire [15:0] gpu_cmd_lo_read = 16'h0000 & {16{reg_rd[GPU_CMD_LO ]}};
wire [15:0] gpu_cmd_hi_read = 16'h0000 & {16{reg_rd[GPU_CMD_HI ]}};
wire [15:0] gpu_stat_read = gpu_stat & {16{reg_rd[GPU_STAT ]}};
 
 
1277,10 → 1286,10
 
display_width_read |
display_height_read |
display_size_lo_read |
`ifdef WITH_DISPLAY_SIZE_HI
display_size_hi_read |
`endif
display_size_lo_read |
display_cfg_read |
 
lt24_cfg_read |
1295,44 → 1304,45
lut_ram_data_read |
 
frame_select_read |
frame0_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame0_ptr_hi_read |
`endif
frame0_ptr_lo_read |
`ifdef WITH_FRAME1_POINTER
frame1_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame1_ptr_hi_read |
`endif
frame1_ptr_lo_read |
`endif
`ifdef WITH_FRAME2_POINTER
frame2_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame2_ptr_hi_read |
`endif
frame2_ptr_lo_read |
`endif
`ifdef WITH_FRAME3_POINTER
frame3_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame3_ptr_hi_read |
`endif
frame3_ptr_lo_read |
`endif
vid_ram0_cfg_read |
vid_ram0_width_read |
vid_ram0_addr_lo_read |
`ifdef VRAM_BIGGER_4_KW
vid_ram0_addr_hi_read |
`endif
vid_ram0_addr_lo_read |
vid_ram0_data_read |
 
vid_ram1_cfg_read |
vid_ram1_width_read |
vid_ram1_addr_lo_read |
`ifdef VRAM_BIGGER_4_KW
vid_ram1_addr_hi_read |
`endif
vid_ram1_addr_lo_read |
vid_ram1_data_read |
gpu_cmd_read |
gpu_cmd_lo_read |
gpu_cmd_hi_read |
gpu_stat_read;
 
 
1341,16 → 1351,16
//============================================================================
 
// Write access strobe
assign vid_ram_wen_o = ~(vid_ram0_we | vid_ram1_we);
assign vid_ram_wen_o = ~(vid_ram0_we | vid_ram1_we );
 
// Chip enable.
assign vid_ram_cen_o = ~(vid_ram0_ce | vid_ram1_ce);
assign vid_ram_cen_o = ~(vid_ram0_ce | vid_ram1_ce );
 
// Data to be written
assign vid_ram_din_o = (vid_ram0_din | vid_ram1_din);
assign vid_ram_din_o = (vid_ram0_din | vid_ram1_din );
 
// Detect memory accesses for ADDR update
wire vid_ram_access = (vid_ram0_access | vid_ram1_access);
wire vid_ram_access = (vid_ram0_access | vid_ram1_access );
 
// Next Address
wire [`APIX_MSB:0] vid_ram_addr_nxt = (vid_ram0_addr_nxt | vid_ram1_addr_nxt);
/verilog/ogfx_backend_lut_fifo.v
142,10 → 142,10
wire [15:0] lut_hw_data_1_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[0] ==1'b0 }}) | // 1 bpp: Black
({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[0] ==1'b1 }}) ; // White
 
wire [15:0] lut_hw_data_2_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[0] ==2'b00 }}) | // 2 bpp: Black
({5'b01000, 6'b010000, 5'b01000} & {16{frame_data_i[0] ==2'b01 }}) | // Dark Gray
({5'b11000, 6'b110000, 5'b11000} & {16{frame_data_i[0] ==2'b10 }}) | // Light Gray
({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[0] ==2'b11 }}) ; // White
wire [15:0] lut_hw_data_2_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[1:0]==2'b00 }}) | // 2 bpp: Black
({5'b01000, 6'b010000, 5'b01000} & {16{frame_data_i[1:0]==2'b01 }}) | // Dark Gray
({5'b11000, 6'b110000, 5'b11000} & {16{frame_data_i[1:0]==2'b10 }}) | // Light Gray
({5'b11111, 6'b111111, 5'b11111} & {16{frame_data_i[1:0]==2'b11 }}) ; // White
 
wire [15:0] lut_hw_data_4_bpp = ({5'b00000, 6'b000000, 5'b00000} & {16{frame_data_i[3:0]==4'b0000}}) | // 4 bpp: Black
({5'b00000, 6'b000000, 5'b10000} & {16{frame_data_i[3:0]==4'b0001}}) | // Dark Blue
/verilog/ogfx_reg_fifo.v
43,41 → 43,43
module ogfx_reg_fifo (
 
// OUTPUTs
fifo_cnt_o, // Fifo counter
fifo_data_o, // Read data output
fifo_done_evt_o, // Fifo has been emptied
fifo_empty_o, // Fifo is currentely empty
fifo_full_o, // Fifo is currentely full
fifo_ovfl_evt_o, // Fifo overflow event
fifo_cnt_o, // Fifo counter
fifo_empty_cnt_o, // Fifo empty words counter
fifo_data_o, // Read data output
fifo_done_evt_o, // Fifo has been emptied
fifo_empty_o, // Fifo is currentely empty
fifo_full_o, // Fifo is currentely full
fifo_ovfl_evt_o, // Fifo overflow event
 
// INPUTs
mclk, // Main system clock
puc_rst, // Main system reset
mclk, // Main system clock
puc_rst, // Main system reset
 
fifo_data_i, // Read data input
fifo_enable_i, // Enable fifo (flushed when disabled)
fifo_pop_i, // Pop data from the fifo
fifo_push_i // Push new data to the fifo
fifo_data_i, // Read data input
fifo_enable_i, // Enable fifo (flushed when disabled)
fifo_pop_i, // Pop data from the fifo
fifo_push_i // Push new data to the fifo
);
 
// OUTPUTs
//=========
output [3:0] fifo_cnt_o; // Fifo counter
output [15:0] fifo_data_o; // Read data output
output fifo_done_evt_o; // Fifo has been emptied
output fifo_empty_o; // Fifo is currentely empty
output fifo_full_o; // Fifo is currentely full
output fifo_ovfl_evt_o; // Fifo overflow event
output [3:0] fifo_cnt_o; // Fifo counter
output [3:0] fifo_empty_cnt_o; // Fifo empty word counter
output [15:0] fifo_data_o; // Read data output
output fifo_done_evt_o; // Fifo has been emptied
output fifo_empty_o; // Fifo is currentely empty
output fifo_full_o; // Fifo is currentely full
output fifo_ovfl_evt_o; // Fifo overflow event
 
// INPUTs
//=========
input mclk; // Main system clock
input puc_rst; // Main system reset
input mclk; // Main system clock
input puc_rst; // Main system reset
 
input [15:0] fifo_data_i; // Read data input
input fifo_enable_i; // Enable fifo (flushed when disabled)
input fifo_pop_i; // Pop data from the fifo
input fifo_push_i; // Push new data to the fifo
input [15:0] fifo_data_i; // Read data input
input fifo_enable_i; // Enable fifo (flushed when disabled)
input fifo_pop_i; // Pop data from the fifo
input fifo_push_i; // Push new data to the fifo
 
 
//=============================================================================
98,10 → 100,11
//============================================================================
 
// Control signals
wire fifo_full_o = (fifo_cnt_o == FIFO_FULL);
wire fifo_empty_o = (fifo_cnt_o == FIFO_EMPTY);
wire fifo_push_int = fifo_push_i & !fifo_full_o;
wire fifo_pop_int = fifo_pop_i & !fifo_empty_o;
assign fifo_full_o = (fifo_cnt_o == FIFO_FULL);
assign fifo_empty_o = (fifo_cnt_o == FIFO_EMPTY);
assign fifo_empty_cnt_o = (FIFO_FULL-fifo_cnt_o);
wire fifo_push_int = fifo_push_i & !fifo_full_o;
wire fifo_pop_int = fifo_pop_i & !fifo_empty_o;
 
// Events
assign fifo_done_evt_o = ~fifo_empty_o & (fifo_cnt_nxt == FIFO_EMPTY);
/verilog/ogfx_reg_vram_if.v
63,9 → 63,7
 
vid_ram_cfg_wr_i, // VID_RAMx_CFG Write strobe
vid_ram_width_wr_i, // VID_RAMx_WIDTH Write strobe
`ifdef VRAM_BIGGER_4_KW
vid_ram_addr_hi_wr_i, // VID_RAMx_ADDR_HI Write strobe
`endif
vid_ram_addr_lo_wr_i, // VID_RAMx_ADDR_LO Write strobe
vid_ram_data_wr_i, // VID_RAMx_DATA Write strobe
vid_ram_data_rd_i, // VID_RAMx_DATA Read strobe
106,9 → 104,7
 
input vid_ram_cfg_wr_i; // VID_RAMx_CFG Write strobe
input vid_ram_width_wr_i; // VID_RAMx_WIDTH Write strobe
`ifdef VRAM_BIGGER_4_KW
input vid_ram_addr_hi_wr_i; // VID_RAMx_ADDR_HI Write strobe
`endif
input vid_ram_addr_lo_wr_i; // VID_RAMx_ADDR_LO Write strobe
input vid_ram_data_wr_i; // VID_RAMx_DATA Write strobe
input vid_ram_data_rd_i; // VID_RAMx_DATA Read strobe
200,6 → 196,7
wire [`APIX_MSB:0] vid_ram_addr;
wire [`APIX_MSB:0] vid_ram_addr_inc;
wire vid_ram_addr_inc_wr;
reg vid_ram_addr_hi_wr_dly;
 
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] vid_ram_addr_hi;
217,7 → 214,6
// VID_RAMx_ADDR_LO Register
//------------------------------------------------
reg [`APIX_LO_MSB:0] vid_ram_addr_lo;
reg vid_ram_addr_lo_wr_dly;
 
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) vid_ram_addr_lo <= {`APIX_LO_MSB+1{1'b0}};
249,7 → 245,7
.gfx_mode_8_bpp_i ( gfx_mode_8_bpp_i ), // Graphic mode 8 bpp resolution
.gfx_mode_16_bpp_i ( gfx_mode_16_bpp_i ), // Graphic mode 16 bpp resolution
.vid_ram_addr_i ( vid_ram_addr ), // Video-RAM address
.vid_ram_addr_init_i ( vid_ram_addr_lo_wr_dly ), // Video-RAM address initialization
.vid_ram_addr_init_i ( vid_ram_addr_hi_wr_dly ), // Video-RAM address initialization
.vid_ram_addr_step_i ( vid_ram_addr_inc_wr ), // Video-RAM address step
.vid_ram_width_i ( vid_ram_width ), // Video-RAM width
.vid_ram_msk_mode_i ( vid_ram_msk_mode ), // Video-RAM Mask mode enable
332,8 → 328,8
 
// Strobe writing to VID_RAMx_ADDR_LO register
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) vid_ram_addr_lo_wr_dly <= 1'b0;
else vid_ram_addr_lo_wr_dly <= vid_ram_addr_lo_wr_i;
if (puc_rst) vid_ram_addr_hi_wr_dly <= 1'b0;
else vid_ram_addr_hi_wr_dly <= vid_ram_addr_hi_wr_i;
 
// Strobe reading from VID_RAMx_DATA register
reg vid_ram_data_rd_dly;
348,7 → 344,7
else vid_ram_data_wr_dly <= vid_ram_data_wr_i;
 
// Trigger read access after a write in MSK mode
wire vid_ram_data_rd_msk = ((vid_ram_data_wr_dly | vid_ram_data_rd_dly | vid_ram_addr_lo_wr_i) & vid_ram_msk_mode & ~gfx_mode_16_bpp_i);
wire vid_ram_data_rd_msk = ((vid_ram_data_wr_dly | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i) & vid_ram_msk_mode & ~gfx_mode_16_bpp_i);
 
 
//------------------------------------------------
363,7 → 359,7
// Note: we perform a data read access:
// - one cycle after a VID_RAM_DATA register read access (so that the address has been incremented)
// - one cycle after a VID_RAM_ADDR_LO register write
wire vid_ram_ce_early = (vid_ram_addr_lo_wr_i | vid_ram_data_rd_dly | vid_ram_data_rd_msk | // Read access
wire vid_ram_ce_early = (vid_ram_addr_hi_wr_i | vid_ram_data_rd_dly | vid_ram_data_rd_msk | // Read access
vid_ram_data_wr_i); // Write access
 
reg [1:0] vid_ram_ce;
386,11 → 382,11
 
// Mux ram address for early read access when ADDR_LO is updated
`ifdef VRAM_BIGGER_4_KW
wire [`APIX_MSB:0] vid_ram_addr_mux = vid_ram_addr_lo_wr_i ? {vid_ram_addr[`APIX_MSB:16], per_din_i} :
vid_ram_data_rd_msk ? vid_ram_addr_inc : vid_ram_addr;
wire [`APIX_MSB:0] vid_ram_addr_mux = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_HI_MSB:0], vid_ram_addr[15:0]} :
vid_ram_data_rd_msk ? vid_ram_addr_inc : vid_ram_addr;
`else
wire [`APIX_MSB:0] vid_ram_addr_mux = vid_ram_addr_lo_wr_i ? {per_din_i[`APIX_LO_MSB:0]} :
vid_ram_data_rd_msk ? vid_ram_addr_inc : vid_ram_addr;
wire [`APIX_MSB:0] vid_ram_addr_mux = vid_ram_addr_hi_wr_i ? {per_din_i[`APIX_LO_MSB:0]} :
vid_ram_data_rd_msk ? vid_ram_addr_inc : vid_ram_addr;
`endif
 
// Add frame pointer offset
397,7 → 393,7
wire [`APIX_MSB:0] vid_ram_addr_offset = vid_ram_base_addr_i + vid_ram_addr_mux;
 
// Detect memory accesses for ADDR update
wire vid_ram_access_o = vid_ram_data_wr_i | vid_ram_data_rd_dly | vid_ram_addr_lo_wr_i | vid_ram_data_rd_msk;
wire vid_ram_access_o = vid_ram_data_wr_i | vid_ram_data_rd_dly | vid_ram_addr_hi_wr_i | vid_ram_data_rd_msk;
 
// Mux Address between the two interfaces
wire [`APIX_MSB:0] vid_ram_addr_nxt_o = {`APIX_MSB+1{vid_ram_access_o}} & vid_ram_addr_offset;
405,7 → 401,7
// Increment the address when accessing the VID_RAMx_DATA register:
// - one clock cycle after a write access
// - with the read access (if not in read-modify-write mode)
assign vid_ram_addr_inc_wr = vid_ram_addr_lo_wr_dly | vid_ram_data_wr_dly | (vid_ram_data_rd_i & ~dbg_freeze_i & ~vid_ram_rmw_mode);
assign vid_ram_addr_inc_wr = vid_ram_addr_hi_wr_dly | vid_ram_data_wr_dly | (vid_ram_data_rd_i & ~dbg_freeze_i & ~vid_ram_rmw_mode);
 
// Compute mask for the address LSBs depending on BPP resolution
wire [3:0] gfx_mode_addr_msk = ( {4{gfx_mode_1_bpp_i}} | // Take 4 address LSBs in 1bpp mode

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.