URL
https://opencores.org/ocsvn/opengfx430/opengfx430/trunk
Subversion Repositories opengfx430
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- This comparison shows the changes necessary to convert path
/opengfx430/trunk
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/core/rtl/verilog/ogfx_reg.v
742,6 → 742,11
if (puc_rst) sw_lut_enable_o <= 1'b0; |
else if (lut_cfg_wr) sw_lut_enable_o <= per_din_i[0]; // Enable software color LUT |
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reg sw_lut_ram_rmw_mode; |
always @ (posedge mclk or posedge puc_rst) |
if (puc_rst) sw_lut_ram_rmw_mode <= 1'b0; |
else if (lut_cfg_wr) sw_lut_ram_rmw_mode <= per_din_i[1]; |
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`ifdef WITH_EXTRA_LUT_BANK |
reg sw_lut_bank_select_o; |
always @ (posedge mclk or posedge puc_rst) |
753,6 → 758,7
`else |
assign sw_lut_bank_select_o = 1'b0; |
assign sw_lut_enable_o = 1'b0; |
wire sw_lut_ram_rmw_mode = 1'b0; |
`endif |
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reg [2:0] hw_lut_palette_sel_o; |
770,9 → 776,10
if (puc_rst) hw_lut_fgcolor_o <= 4'hf; |
else if (lut_cfg_wr) hw_lut_fgcolor_o <= per_din_i[15:12]; |
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wire [15:0] lut_cfg_rd = {hw_lut_fgcolor_o, hw_lut_bgcolor_o, |
1'b0, hw_lut_palette_sel_o, |
1'b0, sw_lut_bank_select_o, 1'b0, sw_lut_enable_o}; |
wire [15:0] lut_cfg_rd = {hw_lut_fgcolor_o, hw_lut_bgcolor_o, |
1'b0, hw_lut_palette_sel_o, |
1'b0, sw_lut_bank_select_o, |
sw_lut_ram_rmw_mode, sw_lut_enable_o}; |
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//------------------------------------------------ |
// LUT_RAM_ADDR Register |
831,7 → 838,9
else if (lut_ram_dout_rdy) lut_ram_data <= lut_ram_dout_i; |
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// Increment the address after a write or read access to the LUT_RAM_DATA register |
assign lut_ram_addr_inc_wr = lut_ram_data_wr | lut_ram_data_rd; |
// - one clock cycle after a write access |
// - with the read access (if not in read-modify-write mode) |
assign lut_ram_addr_inc_wr = lut_ram_data_wr | (lut_ram_data_rd & ~dbg_freeze_i & ~sw_lut_ram_rmw_mode); |
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// Apply peripheral data bus % write strobe during VID_RAMx_DATA write access |
assign lut_ram_din_o = per_din_i & {16{lut_ram_data_wr}}; |