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URL https://opencores.org/ocsvn/openhmc/openhmc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openhmc/trunk/openHMC/sim/UVC/axi4_stream/sv
    from Rev 12 to Rev 15
    ↔ Reverse comparison
  •

Rev 12 → Rev 15

/axi4_stream_slave_agent.sv
64,7 → 64,10
end
if (!uvm_config_db#(axi4_stream_config)::get(this, "", "axi4_stream_cfg", axi4_stream_cfg)) begin
uvm_report_fatal(get_type_name(), $psprintf("axi4_stream_cfg not set via config_db"));
end else begin
uvm_config_db#(axi4_stream_config)::set(this, "driver" , "axi4_stream_cfg", axi4_stream_cfg); //distributing axi4_stream_cfg to master driver
end
if(axi4_stream_cfg.slave_active == UVM_ACTIVE)begin
uvm_config_db#(axi4_stream_config)::set(this, "driver", "axi4_stream_cfg", axi4_stream_cfg); // distribute axi4_stream_cfg to driver
driver = axi4_stream_slave_driver#(.DATA_BYTES(DATA_BYTES), .TUSER_WIDTH(TUSER_WIDTH))::type_id::create("driver", this);
/axi4_stream_master_agent.sv
69,6 → 69,8
 
if (!uvm_config_db#(axi4_stream_config)::get(this, "", "axi4_stream_cfg", axi4_stream_cfg)) begin
uvm_report_fatal(get_type_name(), $psprintf("axi4_stream_cfg not set via config_db"));
end else begin
uvm_config_db#(axi4_stream_config)::set(this, "driver" , "axi4_stream_cfg", axi4_stream_cfg); //distributing axi4_stream_cfg to master driver
end
 
if(axi4_stream_cfg.master_active == UVM_ACTIVE)begin //-- distribute axi4_stream_cfg to driver
/axi4_stream_hmc_monitor.sv
154,11 → 154,11
end
 
end
if(|vc.tuser)
`uvm_info(get_type_name(),$psprintf("%d header and %d tails available", headers_seen, tails_seen) ,UVM_HIGH)
 
`uvm_info(get_type_name(),$psprintf("%d header and %d tails available", headers_seen, tails_seen) ,UVM_HIGH)
 
 
 
endfunction : collect_flits
 
//-- Use FLITs to form packets
174,6 → 174,8
current_flit = flit_queue.pop_front();
no_length_mismatches_allowed : assert (current_flit[14:11] == current_flit[10:7]); //--check internal hmc_packet length
current_packet_length = current_flit[10:7];
`uvm_info(get_type_name(),$psprintf("packet length %0d ", current_packet_length), UVM_HIGH)
`uvm_info(get_type_name(),$psprintf("queue size %0d ", flit_queue.size()), UVM_HIGH)
flit_queue_underflow2 : assert (flit_queue.size() >= current_packet_length - 1); //--check check hmc_packet complete received
 
 
227,15 → 229,10
 
hmc_packet packet;
 
 
`uvm_info(get_type_name(),$psprintf("got valid cycle"), UVM_HIGH)
 
collect_flits(vc);
 
//`uvm_info(get_type_name(),$psprintf("got %0d tails and %0d flits",tails_seen, flit_queue.size() ), UVM_HIGH)
 
`uvm_info(get_type_name(),$psprintf("got %0d tails and %0d flits",tails_seen, flit_queue.size() ), UVM_HIGH)
 
 
//-- Convert flit_queue to hmc_packets
while (tails_seen >0) begin
collect_packet();
/axi4_stream_if.sv
46,15 → 46,15
`ifndef AXI4_STREAM_IF_SV
`define AXI4_STREAM_IF_SV
 
interface axi4_stream_if #(parameter DATA_BYTES = 16, parameter TUSER_WIDTH = 16) (
input logic ACLK, //-- Clock (All signals sampled on the rising edge)
input logic ARESET_N //-- Global Reset
);
interface axi4_stream_if #(parameter DATA_BYTES = 16, parameter TUSER_WIDTH = 16) ();
//--
//-- Interface signals
//--
 
logic ACLK; //-- Clock (All signals sampled on the rising edge)
logic ARESET_N; //-- Global Reset
 
logic TVALID; // Master valid
logic TREADY; // Slave ready
logic [8*DATA_BYTES-1:0] TDATA; //-- Master data
69,12 → 69,12
logic [DATA_BYTES/16-1:0] DEBUG_HEADERS; //-- contains the HMC-HEADER Flags
logic [DATA_BYTES/16-1:0] DEBUG_TAILS; //-- contains the HMC-TAIL Flags
//-- assigning the debug signals to TUSER
assign DEBUG_VALIDS = TUSER[1*(DATA_BYTES /16)-1: (0* DATA_BYTES /16)];
assign DEBUG_HEADERS = TUSER[2*(DATA_BYTES /16)-1: (1* DATA_BYTES /16)];
assign DEBUG_TAILS = TUSER[3*(DATA_BYTES /16)-1: (2* DATA_BYTES /16)];
//--
//-- Interface Coverage
//--
166,11 → 166,11
//
//endproperty
 
chk_reset_tvalid : assert property (
//-- TVALID must be inactive during Reset
@(posedge ACLK)
!ARESET_N |-> TVALID == 1'b0
);
// chk_reset_tvalid : assert property (
// //-- TVALID must be inactive during Reset
// @(posedge ACLK)
// !ARESET_N |-> TVALID == 1'b0
// );
 
 
chk_valid_hold : assert property (
205,9 → 205,24
|=> (TVALID == 1) throughout ( $countones(DEBUG_HEADERS) < $countones(DEBUG_TAILS) )[->1]
);
 
time clk_rise;
time reset_rise;
 
always @(posedge ACLK) begin
if(ARESET_N == 0)
clk_rise <= $time();
end
always @(posedge ARESET_N) begin
reset_rise <= $time();
end
//TODO TODO ADD
// check_sync_reset : assert property (
// @(posedge ACLK)
// $rose(ARESET_N) |=> (reset_rise == clk_rise)
// );
 
 
property data_hold_p;
//-- if TVALID is set TDATA must not be changed until TREADY
logic [8*DATA_BYTES-1:0] m_data;
/axi4_stream_valid_cycle.sv
47,7 → 47,7
class axi4_stream_valid_cycle #(parameter DATA_BYTES = 16, parameter TUSER_WIDTH = 16) extends uvm_sequence_item;
 
rand bit [DATA_BYTES*8-1:0] tdata;
rand bit [TUSER_WIDTH-1:0] tuser;
rand bit [TUSER_WIDTH-1:0] tuser;
rand int unsigned delay = 0;
constraint c_packet_delay {
/axi4_stream_config.sv
44,10 → 44,12
 
uvm_active_passive_enum master_active = UVM_PASSIVE;
uvm_active_passive_enum slave_active = UVM_PASSIVE;
uvm_active_passive_enum open_rsp_mode = UVM_PASSIVE;
 
`uvm_object_utils_begin(axi4_stream_config)
`uvm_field_enum(uvm_active_passive_enum, master_active, UVM_DEFAULT)
`uvm_field_enum(uvm_active_passive_enum, slave_active, UVM_DEFAULT)
`uvm_field_enum(uvm_active_passive_enum, open_rsp_mode, UVM_DEFAULT)
`uvm_object_utils_end
 
function new(string name = "axi4_stream_config");
/axi4_stream_slave_driver.sv
44,6 → 44,12
class axi4_stream_slave_driver #(parameter DATA_BYTES = 16, parameter TUSER_WIDTH = 16) extends uvm_driver #(hmc_packet);
 
axi4_stream_config axi4_stream_cfg;
rand int block_cycles;
constraint c_block_cycles {
soft block_cycles dist{0:/30,[1:5]:/41, [6:15]:/25, [16:10000]:/4};
}
 
virtual interface axi4_stream_if #(.DATA_BYTES(DATA_BYTES), .TUSER_WIDTH(TUSER_WIDTH)) vif;
66,13 → 72,15
end else begin
`uvm_fatal(get_type_name(),"vif is not set")
end
if (!uvm_config_db#(axi4_stream_config)::get(this, "", "axi4_stream_cfg", axi4_stream_cfg)) begin
uvm_report_fatal(get_type_name(), $psprintf("axi4_stream_cfg not set via config_db"));
end
endfunction : build_phase
 
task run_phase(uvm_phase phase);
bit ready_asserted = 0;
bit last_valid = 0;
int set_probability;
 
 
super.run_phase(phase);
 
forever begin
84,23 → 92,34
fork
forever begin
//-- Accept packets
@(negedge vif.ACLK);
@(posedge vif.ACLK);
 
set_probability_randomization : assert (std::randomize(set_probability) with {set_probability >= 0 && set_probability < 10;});
 
//-- Higher probability to be ready when the master has something to send
if (ready_asserted == 0 && vif.TVALID == 1 && set_probability > 3) begin
ready_asserted = 1;
//-- Can be ready when the master has nothing to send
end else if (ready_asserted == 0 && vif.TVALID == 0 && set_probability > 8) begin
ready_asserted = 1;
//-- Only become not ready after accepting something
end else if (ready_asserted == 1 && vif.TVALID == 1 && set_probability > 3) begin
ready_asserted = 0;
if(axi4_stream_cfg.open_rsp_mode==UVM_ACTIVE) begin
vif.TREADY <= 1'b1;
end else begin
if (vif.TVALID)
randcase
3 : vif.TREADY <= 1;
1 : vif.TREADY <= 0;
endcase
else
randcase
1 : vif.TREADY <= 1;
1 : vif.TREADY <= 0;
1 : begin //-- hold tready at least until tvalid is set
vif.TREADY <= 0;
void'(this.randomize());
while (vif.TVALID == 0)
@(posedge vif.ACLK);
repeat(block_cycles) @(posedge vif.ACLK); //-- wait 2 additional cycles
end
endcase
end
vif.TREADY <= ready_asserted;
last_valid = vif.TVALID == 1'b1;
end
begin //-- Asynchronous reset
@(negedge vif.ARESET_N);

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