OpenCores
URL https://opencores.org/ocsvn/openhmc/openhmc/trunk

Subversion Repositories openhmc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openhmc/trunk/openHMC/sim/tb/bfm/testlib
    from Rev 12 to Rev 15
    ↔ Reverse comparison
  •

Rev 12 → Rev 15

/seq_lib/hmc_small_pkts_zdelay_seq.sv File deleted \ No newline at end of file
/seq_lib/hmc_big_pkts_seq.sv File deleted
/seq_lib/hmc_complex_pkt_seq.sv File deleted \ No newline at end of file
/seq_lib/hmc_hdelay_seq.sv File deleted \ No newline at end of file
/seq_lib/hmc_seq_lib.sv File deleted \ No newline at end of file
/seq_lib/hmc_base_pkt_seq.sv File deleted \ No newline at end of file
/seq_lib/hmc_big_pkts_hdelay_seq.sv File deleted \ No newline at end of file
/seq_lib/hmc_zdelay_seq.sv File deleted \ No newline at end of file
/seq_lib/hmc_small_pkts_seq.sv File deleted \ No newline at end of file
/seq_lib/hmc_big_pkts_zdelay_seq.sv File deleted
/seq_lib/hmc_single_pkt_cycle_seq.sv File deleted \ No newline at end of file
/seq_lib/hmc_small_pkts_hdelay_seq.sv File deleted \ No newline at end of file
/init_test/init_test_seq.sv File deleted
/init_test/init_test.sv File deleted \ No newline at end of file
/high_delay_pkt_test/high_delay_pkt_test_seq.sv File deleted \ No newline at end of file
/high_delay_pkt_test/high_delay_pkt_test.sv File deleted \ No newline at end of file
/posted_pkt_test/posted_pkt_test_seq.sv File deleted \ No newline at end of file
/posted_pkt_test/posted_pkt_test.sv File deleted \ No newline at end of file
/big_pkt_zdelay_test/big_pkt_zdelay_test_seq.sv File deleted \ No newline at end of file
/big_pkt_zdelay_test/big_pkt_zdelay_test.sv File deleted \ No newline at end of file
/non_posted_pkt_test/non_posted_pkt_test.sv File deleted \ No newline at end of file
/non_posted_pkt_test/non_posted_pkt_test_seq.sv File deleted \ No newline at end of file
/small_pkt_hdelay_test/small_pkt_hdelay_test.sv File deleted \ No newline at end of file
/small_pkt_hdelay_test/small_pkt_hdelay_test_seq.sv File deleted \ No newline at end of file
/big_pkt_test/big_pkt_test.sv File deleted \ No newline at end of file
/big_pkt_test/big_pkt_test_seq.sv File deleted \ No newline at end of file
/simple_test/simple_test_seq.sv File deleted
/simple_test/simple_test.sv File deleted \ No newline at end of file
/small_pkt_zdelay_test/small_pkt_zdelay_test_seq.sv File deleted \ No newline at end of file
/small_pkt_zdelay_test/small_pkt_zdelay_test.sv File deleted \ No newline at end of file
/sleep_mode/sleep_mode_seq.sv File deleted
/sleep_mode/sleep_mode.sv File deleted \ No newline at end of file
/big_pkt_hdelay_test/big_pkt_hdelay_test.sv File deleted \ No newline at end of file
/big_pkt_hdelay_test/big_pkt_hdelay_test_seq.sv File deleted \ No newline at end of file
/atomic_pkt_test/atomic_pkt_test.sv File deleted \ No newline at end of file
/atomic_pkt_test/atomic_pkt_test_seq.sv File deleted \ No newline at end of file
/test_lib.sv File deleted
/zero_delay_pkt_test/zero_delay_pkt_test.sv File deleted \ No newline at end of file
/zero_delay_pkt_test/zero_delay_pkt_test_seq.sv File deleted \ No newline at end of file
/hmc_check_seq.sv File deleted
/small_pkt_test/small_pkt_test_seq.sv File deleted \ No newline at end of file
/small_pkt_test/small_pkt_test.sv File deleted \ No newline at end of file
/bfm_init_seq.sv File deleted
/hmc_init_seq.sv File deleted
/hmc_base_test.sv
62,7 → 62,8
//-- AXI4 request config
axi4_req_config = axi4_stream_config::type_id::create("axi4_req_config", this);
axi4_req_config.master_active = UVM_ACTIVE;
axi4_req_config.slave_active = UVM_PASSIVE;
axi4_req_config.slave_active = UVM_PASSIVE;
axi4_req_config.open_rsp_mode = UVM_PASSIVE;
 
uvm_report_info(get_type_name(), $psprintf("Setting the axi4_req config:\n"), UVM_LOW);
uvm_config_db#(axi4_stream_config)::set(this, "hmc_tb0", "axi4_req_config", axi4_req_config);
71,6 → 72,7
axi4_rsp_config = axi4_stream_config::type_id::create("axi4_rsp_config", this);
axi4_rsp_config.master_active = UVM_PASSIVE;
axi4_rsp_config.slave_active = UVM_ACTIVE;
axi4_rsp_config.open_rsp_mode = `OPEN_RSP_MODE==1 ? UVM_ACTIVE : UVM_PASSIVE;
 
uvm_report_info(get_type_name(), $psprintf("Setting the axi4_rsp config:\n"), UVM_LOW);
uvm_config_db#(axi4_stream_config)::set(this, "hmc_tb0", "axi4_rsp_config", axi4_rsp_config);
77,6 → 79,7
//-- HMC link config
link_cfg = hmc_link_config::type_id::create("link_cfg",this);
link_cfg.cfg_rsp_open_loop = `OPEN_RSP_MODE==1 ? UVM_ACTIVE : UVM_PASSIVE;
void'(link_cfg.randomize());
uvm_config_db#(hmc_link_config)::set(this, "hmc_tb0", "link_cfg", link_cfg);
104,10 → 107,6
phase.phase_done.set_drain_time(this, 10us);
endtask : run_phase
 
//function void report_phase(uvm_phase phase);
// report_summarize();
//endfunction : report_phase
 
endclass : hmc_base_test
 
 
118,7 → 117,7
endfunction : new
 
`uvm_object_utils(hmc_base_seq)
`uvm_declare_p_sequencer(hmc_vseqr)
`uvm_declare_p_sequencer(vseqr)
 
virtual task pre_body();
if(starting_phase != null)
/hmc_model_init_seq.sv
0,0 → 1,135
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: openhmc@ziti.uni-heidelberg.de
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
*/
 
`ifndef BFM_INIT_SEQ
`define BFM_INIT_SEQ
 
class hmc_model_init_seq extends hmc_base_seq;
 
reg_openhmc_rf_status_general_c status;
reg_openhmc_rf_control_c control;
reg_openhmc_rf_sent_np_c sent_np;
reg_openhmc_rf_rcvd_rsp_c rcvd_rsp;
 
function new(string name="hmc_model_init_seq");
super.new(name);
endfunction : new
 
`uvm_object_utils(hmc_model_init_seq)
`uvm_declare_p_sequencer(vseqr)
 
task body();
// init register
//initiate all the registers (used for sleep mode)
$cast(status,p_sequencer.rf_seqr_hmc.get_by_name("status_general"));
status.set_check_on_read(1'b0);
 
$cast(control,p_sequencer.rf_seqr_hmc.get_by_name("control"));
control.set_check_on_read(1'b0);
 
$cast(sent_np,p_sequencer.rf_seqr_hmc.get_by_name("sent_np"));
sent_np.set_check_on_read(1'b0);
 
$cast(rcvd_rsp,p_sequencer.rf_seqr_hmc.get_by_name("rcvd_rsp"));
rcvd_rsp.set_check_on_read(1'b0);
 
`uvm_info(get_type_name(), $psprintf("Configure BFM"), UVM_NONE)
`uvm_info(get_type_name(), $psprintf("HMC_Token Count is: %d", p_sequencer.link_cfg.hmc_tokens), UVM_NONE)
p_sequencer.hmc_link_cfg.cfg_cid = p_sequencer.link_cfg.cube_id;
p_sequencer.hmc_link_cfg.cfg_lane_auto_correct = p_sequencer.link_cfg.cfg_lane_auto_correct;
p_sequencer.hmc_link_cfg.cfg_rsp_open_loop = p_sequencer.link_cfg.cfg_rsp_open_loop;
 
// These are set to match the design
p_sequencer.hmc_link_cfg.cfg_rx_clk_ratio = p_sequencer.link_cfg.cfg_rx_clk_ratio;
p_sequencer.hmc_link_cfg.cfg_half_link_mode_rx = p_sequencer.link_cfg.cfg_half_link_mode_rx;
p_sequencer.hmc_link_cfg.cfg_tx_lane_reverse = p_sequencer.link_cfg.cfg_tx_lane_reverse;
p_sequencer.hmc_link_cfg.cfg_tx_lane_delay = p_sequencer.link_cfg.cfg_tx_lane_delay;
p_sequencer.hmc_link_cfg.cfg_hsstx_inv = p_sequencer.link_cfg.cfg_hsstx_inv;
 
p_sequencer.hmc_link_cfg.cfg_tx_clk_ratio = p_sequencer.link_cfg.cfg_tx_clk_ratio;
p_sequencer.hmc_link_cfg.cfg_half_link_mode_tx = p_sequencer.link_cfg.cfg_half_link_mode_tx;
 
p_sequencer.hmc_link_cfg.cfg_descram_enb = p_sequencer.link_cfg.cfg_scram_enb;
p_sequencer.hmc_link_cfg.cfg_scram_enb = p_sequencer.link_cfg.cfg_scram_enb;
p_sequencer.hmc_link_cfg.cfg_tokens = p_sequencer.link_cfg.hmc_tokens;
p_sequencer.hmc_link_cfg.cfg_tokens_expected = p_sequencer.link_cfg.rx_tokens;
 
p_sequencer.hmc_link_cfg.cfg_init_retry_rxcnt = p_sequencer.link_cfg.cfg_init_retry_rxcnt;
p_sequencer.hmc_link_cfg.cfg_init_retry_txcnt = p_sequencer.link_cfg.cfg_init_retry_txcnt;
//***Enable Errors - Dont touch
p_sequencer.hmc_link_cfg.cfg_rsp_dln = p_sequencer.link_cfg.cfg_rsp_dln;
p_sequencer.hmc_link_cfg.cfg_rsp_lng = p_sequencer.link_cfg.cfg_rsp_lng;
p_sequencer.hmc_link_cfg.cfg_rsp_crc = p_sequencer.link_cfg.cfg_rsp_crc;
p_sequencer.hmc_link_cfg.cfg_rsp_seq = p_sequencer.link_cfg.cfg_rsp_seq;
p_sequencer.hmc_link_cfg.cfg_rsp_poison = p_sequencer.link_cfg.cfg_rsp_poison;
p_sequencer.hmc_link_cfg.cfg_req_dln = p_sequencer.link_cfg.cfg_req_dln;
p_sequencer.hmc_link_cfg.cfg_req_lng = p_sequencer.link_cfg.cfg_req_lng;
p_sequencer.hmc_link_cfg.cfg_req_crc = p_sequencer.link_cfg.cfg_req_crc;
p_sequencer.hmc_link_cfg.cfg_req_seq = p_sequencer.link_cfg.cfg_req_seq;
 
//Reduce timings for simulation
p_sequencer.hmc_link_cfg.cfg_tsref = p_sequencer.link_cfg.cfg_tsref;
p_sequencer.hmc_link_cfg.cfg_top = p_sequencer.link_cfg.cfg_top;
 
p_sequencer.hmc_link_cfg.cfg_retry_timeout = p_sequencer.link_cfg.cfg_retry_timeout;
p_sequencer.hmc_link_cfg.cfg_retry_limit = p_sequencer.link_cfg.cfg_retry_limit; //8
 
//Enable retry
p_sequencer.hmc_link_cfg.cfg_retry_enb = p_sequencer.link_cfg.cfg_retry_enb;
 
if(p_sequencer.hmc_link_cfg.cfg_scram_enb)
p_sequencer.hmc_link_cfg.cfg_tx_rl_lim = p_sequencer.link_cfg.cfg_tx_rl_lim;
 
p_sequencer.hmc_link_cfg.display(); //uncomment for full link configuration output
 
tb_top.dut_I.hmc_bfm0.set_config(p_sequencer.hmc_link_cfg,0);
`uvm_info(get_type_name(), $psprintf("HMC BFM CONFIGURATION IS COMPLETE"), UVM_NONE)
 
endtask : body
 
endclass : hmc_model_init_seq
 
`endif // HMC_INIT_SEQ
/openhmc_init_seq.sv
0,0 → 1,140
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: openhmc@ziti.uni-heidelberg.de
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
*/
 
`ifndef HMC_INIT_SEQ
`define HMC_INIT_SEQ
 
class openhmc_init_seq extends hmc_base_seq;
 
function new(string name="openhmc_init_seq");
super.new(name);
endfunction : new
 
`uvm_object_utils(openhmc_init_seq)
`uvm_declare_p_sequencer(vseqr)
 
bit phy_tx_ready = 1'b0;
bit phy_rx_ready = 1'b0;
bit link_up = 1'b0;
int timeout = 0;
 
task body();
 
//------------------------------------------------------- configure the openHMC controller
reg_openhmc_rf_control_c control;
reg_openhmc_rf_status_general_c status;
reg_openhmc_rf_status_init_c status_init;
reg_openhmc_rf_counter_reset_c cnt_reset;
 
`uvm_info(get_type_name(), "Running init sequence", UVM_NONE)
 
$cast(control,p_sequencer.rf_seqr_hmc.get_by_name("control"));
control.set_check_on_read(1'b0);
p_sequencer.rf_seqr_hmc.read_reg(control);
 
control.fields.rx_token_count_ = p_sequencer.link_cfg.rx_tokens;
control.fields.scrambler_disable_ = ~p_sequencer.link_cfg.cfg_scram_enb;
control.fields.bit_slip_time_ = p_sequencer.link_cfg.bit_slip_time;
control.fields.set_hmc_sleep_ = 0;
control.fields.run_length_enable_ = ~p_sequencer.link_cfg.cfg_scram_enb;
control.fields.irtry_to_send_ = p_sequencer.link_cfg.cfg_init_retry_txcnt*4;
control.fields.irtry_received_threshold_ = p_sequencer.link_cfg.cfg_init_retry_rxcnt;
 
p_sequencer.rf_seqr_hmc.write_reg(control);
 
//Dummy Read to status init
$cast(status_init,p_sequencer.rf_seqr_hmc.get_by_name("status_init"));
status_init.set_check_on_read(1'b0);
p_sequencer.rf_seqr_hmc.read_reg(status_init);
 
//Dummy counter reset
$cast(cnt_reset,p_sequencer.rf_seqr_hmc.get_by_name("counter_reset"));
cnt_reset.fields.rreinit_ = 1;
p_sequencer.rf_seqr_hmc.write_reg(cnt_reset);
 
//-- Wait until the PHY is out of reset
$cast(status,p_sequencer.rf_seqr_hmc.get_by_name("status_general"));
status.set_check_on_read(1'b0);
while (phy_tx_ready == 1'b0)
begin
#1us;
p_sequencer.rf_seqr_hmc.read_reg(status);
phy_tx_ready = status.fields.phy_tx_ready_;
`uvm_info(get_type_name(), "Waiting for the PHY TX to get ready", UVM_NONE)
end
`uvm_info(get_type_name(), "Phy TX ready", UVM_NONE)
 
//------------------------------------------------------- Set Reset and Init Continue
control.fields.p_rst_n_ = 1;
p_sequencer.rf_seqr_hmc.write_reg(control);
#1us;
 
control.fields.hmc_init_cont_set_ = 1;
p_sequencer.rf_seqr_hmc.write_reg(control);
`uvm_info(get_type_name(), "Init cont in RF set", UVM_NONE)
 
//------------------------------------------------------- Wait for the PHY to get ready
while (phy_rx_ready == 1'b0)
begin
#1us;
p_sequencer.rf_seqr_hmc.read_reg(status);
phy_rx_ready = status.fields.phy_rx_ready_;
`uvm_info(get_type_name(), "Waiting for PHY RX to get ready", UVM_NONE)
end
`uvm_info(get_type_name(), "Phy RX is ready", UVM_NONE)
 
//-- Poll on link_up to make sure that it comes up.
while (link_up == 1'b0)
begin
if (timeout == 8000) //-- Try Resetting it.
begin
`uvm_fatal(get_type_name(), "The link didn't come up...")
end
#4ns;
p_sequencer.rf_seqr_hmc.read_reg(status);
link_up = status.fields.link_up_;
timeout = timeout + 1;
end
`uvm_info(get_type_name(), "Link is UP !", UVM_NONE)
 
endtask : body
 
endclass : openhmc_init_seq
 
`endif // HMC_INIT_SEQ

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.