URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core/bench/verilog
- from Rev 106 to Rev 111
- ↔ Reverse comparison
Rev 106 → Rev 111
/tb_openMSP430.v
62,7 → 62,7
wire [15:0] pmem_dout; |
|
// Peripherals interface |
wire [7:0] per_addr; |
wire [13:0] per_addr; |
wire [15:0] per_din; |
wire [15:0] per_dout; |
wire [1:0] per_we; |
127,7 → 127,7
wire aclk_en; |
wire smclk_en; |
reg reset_n; |
wire puc; |
wire puc_rst; |
reg nmi; |
reg [13:0] irq; |
wire [13:0] irq_acc; |
287,7 → 287,7
.pmem_cen (pmem_cen), // Program Memory chip enable (low active) |
.pmem_din (pmem_din), // Program Memory data input (optional) |
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional) |
.puc (puc), // Main system reset |
.puc_rst (puc_rst), // Main system reset |
.smclk_en (smclk_en), // SMCLK enable |
|
// INPUTs |
359,7 → 359,7
.per_din (per_din), // Peripheral data input |
.per_en (per_en), // Peripheral enable (high active) |
.per_we (per_we), // Peripheral write enable (high active) |
.puc (puc) // Main system reset |
.puc_rst (puc_rst) // Main system reset |
); |
|
// |
389,7 → 389,7
.per_din (per_din), // Peripheral data input |
.per_en (per_en), // Peripheral enable (high active) |
.per_we (per_we), // Peripheral write enable (high active) |
.puc (puc), // Main system reset |
.puc_rst (puc_rst), // Main system reset |
.smclk_en (smclk_en), // SMCLK enable (from CPU) |
.ta_cci0a (ta_cci0a), // Timer A compare 0 input A |
.ta_cci0b (ta_cci0b), // Timer A compare 0 input B |
415,11 → 415,14
.per_din (per_din), // Peripheral data input |
.per_en (per_en), // Peripheral enable (high active) |
.per_we (per_we), // Peripheral write enable (high active) |
.puc (puc) // Main system reset |
.puc_rst (puc_rst) // Main system reset |
); |
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template_periph_16b template_periph_16b_0 ( |
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`ifdef CVER |
template_periph_16b #(15'h0190) template_periph_16b_0 ( |
`else |
template_periph_16b #(.BASE_ADDR(15'd`PER_SIZE-15'h0070)) template_periph_16b_0 ( |
`endif |
// OUTPUTs |
.per_dout (per_dout_temp_16b), // Peripheral data output |
|
429,7 → 432,7
.per_din (per_din), // Peripheral data input |
.per_en (per_en), // Peripheral enable (high active) |
.per_we (per_we), // Peripheral write enable (high active) |
.puc (puc) // Main system reset |
.puc_rst (puc_rst) // Main system reset |
); |
|
|
479,7 → 482,7
|
// INPUTs |
.mclk (mclk), // Main system clock |
.puc (puc) // Main system reset |
.puc_rst (puc_rst) // Main system reset |
); |
|
|
/msp_debug.v
53,7 → 53,7
|
// INPUTs |
mclk, // Main system clock |
puc // Main system reset |
puc_rst // Main system reset |
); |
|
// OUTPUTs |
69,7 → 69,7
// INPUTs |
//============ |
input mclk; // Main system clock |
input puc; // Main system reset |
input puc_rst; // Main system reset |
|
|
//============================================================================= |
171,13 → 171,13
//==================================== |
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reg [31:0] inst_number; |
always @(posedge mclk or posedge puc) |
if (puc) inst_number <= 0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_number <= 0; |
else if (decode) inst_number <= inst_number+1; |
|
reg [31:0] inst_cycle; |
always @(posedge mclk or posedge puc) |
if (puc) inst_cycle <= 0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_cycle <= 0; |
else if (decode) inst_cycle <= 0; |
else inst_cycle <= inst_cycle+1; |
|
187,14 → 187,14
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// Buffer opcode |
reg [15:0] opcode; |
always @(posedge mclk or posedge puc) |
if (puc) opcode <= 0; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) opcode <= 0; |
else if (decode) opcode <= ir; |
|
// Interrupts |
reg irq; |
always @(posedge mclk or posedge puc) |
if (puc) irq <= 1'b1; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) irq <= 1'b1; |
else if (decode) irq <= irq_detect; |
|
// Instruction type |
438,8 → 438,8
//================================ |
|
reg [15:0] inst_pc; |
always @(posedge mclk or posedge puc) |
if (puc) inst_pc <= 16'h0000; |
always @(posedge mclk or posedge puc_rst) |
if (puc_rst) inst_pc <= 16'h0000; |
else if (decode) inst_pc <= pc; |
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