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Rev 23 → Rev 33

/tb_openMSP430.v
45,110 → 45,110
// Wire & Register definition
//------------------------------
 
// RAM interface
wire [`RAM_MSB:0] ram_addr;
wire ram_cen;
wire [15:0] ram_din;
wire [1:0] ram_wen;
wire [15:0] ram_dout;
// Data Memory interface
wire [`DMEM_MSB:0] dmem_addr;
wire dmem_cen;
wire [15:0] dmem_din;
wire [1:0] dmem_wen;
wire [15:0] dmem_dout;
 
// ROM interface
wire [`ROM_MSB:0] rom_addr;
wire rom_cen;
wire [15:0] rom_din_dbg;
wire [1:0] rom_wen_dbg;
wire [15:0] rom_dout;
// Program Memory interface
wire [`PMEM_MSB:0] pmem_addr;
wire pmem_cen;
wire [15:0] pmem_din;
wire [1:0] pmem_wen;
wire [15:0] pmem_dout;
 
// Peripherals interface
wire [7:0] per_addr;
wire [15:0] per_din;
wire [15:0] per_dout;
wire [1:0] per_wen;
wire per_en;
wire [7:0] per_addr;
wire [15:0] per_din;
wire [15:0] per_dout;
wire [1:0] per_wen;
wire per_en;
 
// Digital I/O
wire irq_port1;
wire irq_port2;
wire [15:0] per_dout_dio;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p3_sel;
wire [7:0] p4_dout;
wire [7:0] p4_dout_en;
wire [7:0] p4_sel;
wire [7:0] p5_dout;
wire [7:0] p5_dout_en;
wire [7:0] p5_sel;
wire [7:0] p6_dout;
wire [7:0] p6_dout_en;
wire [7:0] p6_sel;
reg [7:0] p1_din;
reg [7:0] p2_din;
reg [7:0] p3_din;
reg [7:0] p4_din;
reg [7:0] p5_din;
reg [7:0] p6_din;
wire irq_port1;
wire irq_port2;
wire [15:0] per_dout_dio;
wire [7:0] p1_dout;
wire [7:0] p1_dout_en;
wire [7:0] p1_sel;
wire [7:0] p2_dout;
wire [7:0] p2_dout_en;
wire [7:0] p2_sel;
wire [7:0] p3_dout;
wire [7:0] p3_dout_en;
wire [7:0] p3_sel;
wire [7:0] p4_dout;
wire [7:0] p4_dout_en;
wire [7:0] p4_sel;
wire [7:0] p5_dout;
wire [7:0] p5_dout_en;
wire [7:0] p5_sel;
wire [7:0] p6_dout;
wire [7:0] p6_dout_en;
wire [7:0] p6_sel;
reg [7:0] p1_din;
reg [7:0] p2_din;
reg [7:0] p3_din;
reg [7:0] p4_din;
reg [7:0] p5_din;
reg [7:0] p6_din;
 
// Peripheral templates
wire [15:0] per_dout_temp_8b;
wire [15:0] per_dout_temp_16b;
wire [15:0] per_dout_temp_8b;
wire [15:0] per_dout_temp_16b;
 
// Timer A
wire irq_ta0;
wire irq_ta1;
wire [15:0] per_dout_timerA;
reg inclk;
reg taclk;
reg ta_cci0a;
reg ta_cci0b;
reg ta_cci1a;
reg ta_cci1b;
reg ta_cci2a;
reg ta_cci2b;
wire ta_out0;
wire ta_out0_en;
wire ta_out1;
wire ta_out1_en;
wire ta_out2;
wire ta_out2_en;
wire irq_ta0;
wire irq_ta1;
wire [15:0] per_dout_timerA;
reg inclk;
reg taclk;
reg ta_cci0a;
reg ta_cci0b;
reg ta_cci1a;
reg ta_cci1b;
reg ta_cci2a;
reg ta_cci2b;
wire ta_out0;
wire ta_out0_en;
wire ta_out1;
wire ta_out1_en;
wire ta_out2;
wire ta_out2_en;
// Clock / Reset & Interrupts
reg dco_clk;
reg lfxt_clk;
wire mclk;
wire aclk_en;
wire smclk_en;
reg reset_n;
wire puc;
reg nmi;
reg [13:0] irq;
wire [13:0] irq_acc;
wire [13:0] irq_in;
reg dco_clk;
reg lfxt_clk;
wire mclk;
wire aclk_en;
wire smclk_en;
reg reset_n;
wire puc;
reg nmi;
reg [13:0] irq;
wire [13:0] irq_acc;
wire [13:0] irq_in;
 
// Debug interface
wire dbg_freeze;
wire dbg_uart_txd;
reg dbg_uart_rxd;
reg [15:0] dbg_uart_buf;
wire dbg_freeze;
wire dbg_uart_txd;
reg dbg_uart_rxd;
reg [15:0] dbg_uart_buf;
 
// Core testbench debuging signals
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
// Testbench variables
integer error;
reg stimulus_done;
integer error;
reg stimulus_done;
 
 
//
170,7 → 170,7
//------------------------------
initial
begin
$readmemh("./rom.mem", rom_0.mem);
$readmemh("./pmem.mem", pmem_0.mem);
end
 
//
222,38 → 222,38
 
//
// ROM
// Program Memory
//----------------------------------
 
ram #(`ROM_MSB) rom_0 (
ram #(`PMEM_MSB) pmem_0 (
 
// OUTPUTs
.ram_dout (rom_dout), // ROM data output
.ram_dout (pmem_dout), // Program Memory data output
 
// INPUTs
.ram_addr (rom_addr), // ROM address
.ram_cen (rom_cen), // ROM chip enable (low active)
.ram_clk (mclk), // ROM clock
.ram_din (rom_din_dbg), // ROM data input
.ram_wen (rom_wen_dbg) // ROM write enable (low active)
.ram_addr (pmem_addr), // Program Memory address
.ram_cen (pmem_cen), // Program Memory chip enable (low active)
.ram_clk (mclk), // Program Memory clock
.ram_din (pmem_din), // Program Memory data input
.ram_wen (pmem_wen) // Program Memory write enable (low active)
);
 
 
//
// RAM
// Data Memory
//----------------------------------
 
ram #(`RAM_MSB) ram_0 (
ram #(`DMEM_MSB) dmem_0 (
 
// OUTPUTs
.ram_dout (ram_dout), // RAM data output
.ram_dout (dmem_dout), // Data Memory data output
 
// INPUTs
.ram_addr (ram_addr), // RAM address
.ram_cen (ram_cen), // RAM chip enable (low active)
.ram_clk (mclk), // RAM clock
.ram_din (ram_din), // RAM data input
.ram_wen (ram_wen) // RAM write enable (low active)
.ram_addr (dmem_addr), // Data Memory address
.ram_cen (dmem_cen), // Data Memory chip enable (low active)
.ram_clk (mclk), // Data Memory clock
.ram_din (dmem_din), // Data Memory data input
.ram_wen (dmem_wen) // Data Memory write enable (low active)
);
 
 
267,6 → 267,10
.aclk_en (aclk_en), // ACLK enable
.dbg_freeze (dbg_freeze), // Freeze peripherals
.dbg_uart_txd (dbg_uart_txd), // Debug interface: UART TXD
.dmem_addr (dmem_addr), // Data Memory address
.dmem_cen (dmem_cen), // Data Memory chip enable (low active)
.dmem_din (dmem_din), // Data Memory data input
.dmem_wen (dmem_wen), // Data Memory write enable (low active)
.irq_acc (irq_acc), // Interrupt request accepted (one-hot signal)
.mclk (mclk), // Main system clock
.per_addr (per_addr), // Peripheral address
273,27 → 277,23
.per_din (per_din), // Peripheral data input
.per_wen (per_wen), // Peripheral write enable (high active)
.per_en (per_en), // Peripheral enable (high active)
.pmem_addr (pmem_addr), // Program Memory address
.pmem_cen (pmem_cen), // Program Memory chip enable (low active)
.pmem_din (pmem_din), // Program Memory data input (optional)
.pmem_wen (pmem_wen), // Program Memory write enable (low active) (optional)
.puc (puc), // Main system reset
.ram_addr (ram_addr), // RAM address
.ram_cen (ram_cen), // RAM chip enable (low active)
.ram_din (ram_din), // RAM data input
.ram_wen (ram_wen), // RAM write enable (low active)
.rom_addr (rom_addr), // ROM address
.rom_cen (rom_cen), // ROM chip enable (low active)
.rom_din_dbg (rom_din_dbg), // ROM data input --FOR DEBUG INTERFACE--
.rom_wen_dbg (rom_wen_dbg), // ROM write enable (low active) --FOR DBG IF--
.smclk_en (smclk_en), // SMCLK enable
 
// INPUTs
.dbg_uart_rxd (dbg_uart_rxd), // Debug interface: UART RXD
.dco_clk (dco_clk), // Fast oscillator (fast clock)
.dmem_dout (dmem_dout), // Data Memory data output
.irq (irq_in), // Maskable interrupts
.lfxt_clk (lfxt_clk), // Low frequency oscillator (typ 32kHz)
.nmi (nmi), // Non-maskable interrupt (asynchronous)
.per_dout (per_dout), // Peripheral data output
.ram_dout (ram_dout), // RAM data output
.reset_n (reset_n), // Reset Pin (low active)
.rom_dout (rom_dout) // ROM data output
.pmem_dout (pmem_dout), // Program Memory data output
.reset_n (reset_n) // Reset Pin (low active)
);
 
//
/registers.v
61,89 → 61,89
// RAM cells
//======================
 
wire [15:0] mem200 = ram_0.mem[0];
wire [15:0] mem202 = ram_0.mem[1];
wire [15:0] mem204 = ram_0.mem[2];
wire [15:0] mem206 = ram_0.mem[3];
wire [15:0] mem208 = ram_0.mem[4];
wire [15:0] mem20A = ram_0.mem[5];
wire [15:0] mem20C = ram_0.mem[6];
wire [15:0] mem20E = ram_0.mem[7];
wire [15:0] mem210 = ram_0.mem[8];
wire [15:0] mem212 = ram_0.mem[9];
wire [15:0] mem214 = ram_0.mem[10];
wire [15:0] mem216 = ram_0.mem[11];
wire [15:0] mem218 = ram_0.mem[12];
wire [15:0] mem21A = ram_0.mem[13];
wire [15:0] mem21C = ram_0.mem[14];
wire [15:0] mem21E = ram_0.mem[15];
wire [15:0] mem220 = ram_0.mem[16];
wire [15:0] mem222 = ram_0.mem[17];
wire [15:0] mem224 = ram_0.mem[18];
wire [15:0] mem226 = ram_0.mem[19];
wire [15:0] mem228 = ram_0.mem[20];
wire [15:0] mem22A = ram_0.mem[21];
wire [15:0] mem22C = ram_0.mem[22];
wire [15:0] mem22E = ram_0.mem[23];
wire [15:0] mem230 = ram_0.mem[24];
wire [15:0] mem232 = ram_0.mem[25];
wire [15:0] mem234 = ram_0.mem[26];
wire [15:0] mem236 = ram_0.mem[27];
wire [15:0] mem238 = ram_0.mem[28];
wire [15:0] mem23A = ram_0.mem[29];
wire [15:0] mem23C = ram_0.mem[30];
wire [15:0] mem23E = ram_0.mem[31];
wire [15:0] mem240 = ram_0.mem[32];
wire [15:0] mem242 = ram_0.mem[33];
wire [15:0] mem244 = ram_0.mem[34];
wire [15:0] mem246 = ram_0.mem[35];
wire [15:0] mem248 = ram_0.mem[36];
wire [15:0] mem24A = ram_0.mem[37];
wire [15:0] mem24C = ram_0.mem[38];
wire [15:0] mem24E = ram_0.mem[39];
wire [15:0] mem250 = ram_0.mem[40];
wire [15:0] mem252 = ram_0.mem[41];
wire [15:0] mem254 = ram_0.mem[42];
wire [15:0] mem256 = ram_0.mem[43];
wire [15:0] mem258 = ram_0.mem[44];
wire [15:0] mem25A = ram_0.mem[45];
wire [15:0] mem25C = ram_0.mem[46];
wire [15:0] mem25E = ram_0.mem[47];
wire [15:0] mem260 = ram_0.mem[48];
wire [15:0] mem262 = ram_0.mem[49];
wire [15:0] mem264 = ram_0.mem[50];
wire [15:0] mem266 = ram_0.mem[51];
wire [15:0] mem268 = ram_0.mem[52];
wire [15:0] mem26A = ram_0.mem[53];
wire [15:0] mem26C = ram_0.mem[54];
wire [15:0] mem26E = ram_0.mem[55];
wire [15:0] mem270 = ram_0.mem[56];
wire [15:0] mem272 = ram_0.mem[57];
wire [15:0] mem274 = ram_0.mem[58];
wire [15:0] mem276 = ram_0.mem[59];
wire [15:0] mem278 = ram_0.mem[60];
wire [15:0] mem27A = ram_0.mem[61];
wire [15:0] mem27C = ram_0.mem[62];
wire [15:0] mem27E = ram_0.mem[63];
wire [15:0] mem280 = ram_0.mem[64];
wire [15:0] mem200 = dmem_0.mem[0];
wire [15:0] mem202 = dmem_0.mem[1];
wire [15:0] mem204 = dmem_0.mem[2];
wire [15:0] mem206 = dmem_0.mem[3];
wire [15:0] mem208 = dmem_0.mem[4];
wire [15:0] mem20A = dmem_0.mem[5];
wire [15:0] mem20C = dmem_0.mem[6];
wire [15:0] mem20E = dmem_0.mem[7];
wire [15:0] mem210 = dmem_0.mem[8];
wire [15:0] mem212 = dmem_0.mem[9];
wire [15:0] mem214 = dmem_0.mem[10];
wire [15:0] mem216 = dmem_0.mem[11];
wire [15:0] mem218 = dmem_0.mem[12];
wire [15:0] mem21A = dmem_0.mem[13];
wire [15:0] mem21C = dmem_0.mem[14];
wire [15:0] mem21E = dmem_0.mem[15];
wire [15:0] mem220 = dmem_0.mem[16];
wire [15:0] mem222 = dmem_0.mem[17];
wire [15:0] mem224 = dmem_0.mem[18];
wire [15:0] mem226 = dmem_0.mem[19];
wire [15:0] mem228 = dmem_0.mem[20];
wire [15:0] mem22A = dmem_0.mem[21];
wire [15:0] mem22C = dmem_0.mem[22];
wire [15:0] mem22E = dmem_0.mem[23];
wire [15:0] mem230 = dmem_0.mem[24];
wire [15:0] mem232 = dmem_0.mem[25];
wire [15:0] mem234 = dmem_0.mem[26];
wire [15:0] mem236 = dmem_0.mem[27];
wire [15:0] mem238 = dmem_0.mem[28];
wire [15:0] mem23A = dmem_0.mem[29];
wire [15:0] mem23C = dmem_0.mem[30];
wire [15:0] mem23E = dmem_0.mem[31];
wire [15:0] mem240 = dmem_0.mem[32];
wire [15:0] mem242 = dmem_0.mem[33];
wire [15:0] mem244 = dmem_0.mem[34];
wire [15:0] mem246 = dmem_0.mem[35];
wire [15:0] mem248 = dmem_0.mem[36];
wire [15:0] mem24A = dmem_0.mem[37];
wire [15:0] mem24C = dmem_0.mem[38];
wire [15:0] mem24E = dmem_0.mem[39];
wire [15:0] mem250 = dmem_0.mem[40];
wire [15:0] mem252 = dmem_0.mem[41];
wire [15:0] mem254 = dmem_0.mem[42];
wire [15:0] mem256 = dmem_0.mem[43];
wire [15:0] mem258 = dmem_0.mem[44];
wire [15:0] mem25A = dmem_0.mem[45];
wire [15:0] mem25C = dmem_0.mem[46];
wire [15:0] mem25E = dmem_0.mem[47];
wire [15:0] mem260 = dmem_0.mem[48];
wire [15:0] mem262 = dmem_0.mem[49];
wire [15:0] mem264 = dmem_0.mem[50];
wire [15:0] mem266 = dmem_0.mem[51];
wire [15:0] mem268 = dmem_0.mem[52];
wire [15:0] mem26A = dmem_0.mem[53];
wire [15:0] mem26C = dmem_0.mem[54];
wire [15:0] mem26E = dmem_0.mem[55];
wire [15:0] mem270 = dmem_0.mem[56];
wire [15:0] mem272 = dmem_0.mem[57];
wire [15:0] mem274 = dmem_0.mem[58];
wire [15:0] mem276 = dmem_0.mem[59];
wire [15:0] mem278 = dmem_0.mem[60];
wire [15:0] mem27A = dmem_0.mem[61];
wire [15:0] mem27C = dmem_0.mem[62];
wire [15:0] mem27E = dmem_0.mem[63];
wire [15:0] mem280 = dmem_0.mem[64];
 
 
// Interrupt vectors
//======================
 
wire [15:0] irq_vect_15 = rom_0.mem[(1<<(`ROM_MSB+1))-1]; // RESET Vector
wire [15:0] irq_vect_14 = rom_0.mem[(1<<(`ROM_MSB+1))-2]; // NMI
wire [15:0] irq_vect_13 = rom_0.mem[(1<<(`ROM_MSB+1))-3]; // IRQ 13
wire [15:0] irq_vect_12 = rom_0.mem[(1<<(`ROM_MSB+1))-4]; // IRQ 12
wire [15:0] irq_vect_11 = rom_0.mem[(1<<(`ROM_MSB+1))-5]; // IRQ 11
wire [15:0] irq_vect_10 = rom_0.mem[(1<<(`ROM_MSB+1))-6]; // IRQ 10
wire [15:0] irq_vect_09 = rom_0.mem[(1<<(`ROM_MSB+1))-7]; // IRQ 9
wire [15:0] irq_vect_08 = rom_0.mem[(1<<(`ROM_MSB+1))-8]; // IRQ 8
wire [15:0] irq_vect_07 = rom_0.mem[(1<<(`ROM_MSB+1))-9]; // IRQ 7
wire [15:0] irq_vect_06 = rom_0.mem[(1<<(`ROM_MSB+1))-10]; // IRQ 6
wire [15:0] irq_vect_05 = rom_0.mem[(1<<(`ROM_MSB+1))-11]; // IRQ 5
wire [15:0] irq_vect_04 = rom_0.mem[(1<<(`ROM_MSB+1))-12]; // IRQ 4
wire [15:0] irq_vect_03 = rom_0.mem[(1<<(`ROM_MSB+1))-13]; // IRQ 3
wire [15:0] irq_vect_02 = rom_0.mem[(1<<(`ROM_MSB+1))-14]; // IRQ 2
wire [15:0] irq_vect_01 = rom_0.mem[(1<<(`ROM_MSB+1))-15]; // IRQ 1
wire [15:0] irq_vect_00 = rom_0.mem[(1<<(`ROM_MSB+1))-16]; // IRQ 0
wire [15:0] irq_vect_15 = pmem_0.mem[(1<<(`PMEM_MSB+1))-1]; // RESET Vector
wire [15:0] irq_vect_14 = pmem_0.mem[(1<<(`PMEM_MSB+1))-2]; // NMI
wire [15:0] irq_vect_13 = pmem_0.mem[(1<<(`PMEM_MSB+1))-3]; // IRQ 13
wire [15:0] irq_vect_12 = pmem_0.mem[(1<<(`PMEM_MSB+1))-4]; // IRQ 12
wire [15:0] irq_vect_11 = pmem_0.mem[(1<<(`PMEM_MSB+1))-5]; // IRQ 11
wire [15:0] irq_vect_10 = pmem_0.mem[(1<<(`PMEM_MSB+1))-6]; // IRQ 10
wire [15:0] irq_vect_09 = pmem_0.mem[(1<<(`PMEM_MSB+1))-7]; // IRQ 9
wire [15:0] irq_vect_08 = pmem_0.mem[(1<<(`PMEM_MSB+1))-8]; // IRQ 8
wire [15:0] irq_vect_07 = pmem_0.mem[(1<<(`PMEM_MSB+1))-9]; // IRQ 7
wire [15:0] irq_vect_06 = pmem_0.mem[(1<<(`PMEM_MSB+1))-10]; // IRQ 6
wire [15:0] irq_vect_05 = pmem_0.mem[(1<<(`PMEM_MSB+1))-11]; // IRQ 5
wire [15:0] irq_vect_04 = pmem_0.mem[(1<<(`PMEM_MSB+1))-12]; // IRQ 4
wire [15:0] irq_vect_03 = pmem_0.mem[(1<<(`PMEM_MSB+1))-13]; // IRQ 3
wire [15:0] irq_vect_02 = pmem_0.mem[(1<<(`PMEM_MSB+1))-14]; // IRQ 2
wire [15:0] irq_vect_01 = pmem_0.mem[(1<<(`PMEM_MSB+1))-15]; // IRQ 1
wire [15:0] irq_vect_00 = pmem_0.mem[(1<<(`PMEM_MSB+1))-16]; // IRQ 0

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