URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
Compare Revisions
- This comparison shows the changes necessary to convert path
/openmsp430/trunk/core/rtl/verilog
- from Rev 117 to Rev 128
- ↔ Reverse comparison
Rev 117 → Rev 128
/omsp_execution_unit.v
154,11 → 154,9
inst_type[`INST_JMP])) | dbg_reg_wr; |
|
wire reg_sp_wr = (((e_state==`E_IRQ_1) | (e_state==`E_IRQ_3)) & ~inst_irq_rst) | |
((e_state==`E_DST_RD) & ((inst_so[`PUSH] & ~inst_as[`IDX] & |
~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1])) | |
inst_so[`CALL])) | |
((e_state==`E_SRC_AD) & (inst_so[`PUSH] & inst_as[`IDX])) | |
((e_state==`E_SRC_RD) & (inst_so[`PUSH] & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))); |
((e_state==`E_DST_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ~inst_as[`IDX] & ~((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))) | |
((e_state==`E_SRC_AD) & ((inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX])) | |
((e_state==`E_SRC_RD) & ((inst_so[`PUSH] | inst_so[`CALL]) & ((inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]))); |
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wire reg_sr_wr = (e_state==`E_DST_RD) & inst_so[`RETI]; |
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228,7 → 226,7
wire src_reg_dest_sel = (e_state==`E_IRQ_1) | |
(e_state==`E_IRQ_3) | |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL])) | |
((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]); |
((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]); |
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wire src_mdb_in_val_sel = ((e_state==`E_DST_RD) & inst_so[`RETI]) | |
((e_state==`E_EXEC) & (inst_as[`INDIR] | inst_as[`INDIR_I] | |
272,8 → 270,8
(e_state==`E_IRQ_1) | |
(e_state==`E_IRQ_3) | |
((e_state==`E_DST_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & ~inst_so[`RETI]) | |
((e_state==`E_SRC_AD) & inst_so[`PUSH] & inst_as[`IDX]) | |
((e_state==`E_SRC_RD) & inst_so[`PUSH] & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]); |
((e_state==`E_SRC_AD) & (inst_so[`PUSH] | inst_so[`CALL]) & inst_as[`IDX]) | |
((e_state==`E_SRC_RD) & (inst_so[`PUSH] | inst_so[`CALL]) & (inst_as[`INDIR] | inst_as[`INDIR_I]) & inst_src[1]); |
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wire dst_reg_dest_sel = ((e_state==`E_DST_RD) & ~(inst_so[`PUSH] | inst_so[`CALL] | inst_ad[`ABS] | inst_so[`RETI])) | |
((e_state==`E_DST_WR) & ~inst_ad[`ABS]) | |